Loop Id: 2964 | Module: exec | Source: par_csr_matop.c:127-242 [...] | Coverage: 0.1% |
---|
Loop Id: 2964 | Module: exec | Source: par_csr_matop.c:127-242 [...] | Coverage: 0.1% |
---|
0x4c58cc LDR X4, [SP, #128] |
0x4c58d0 ORR X3, XZR, X20 |
0x4c58d4 ORR X12, XZR, X15 |
0x4c58d8 CBNZ X4, 4c59a8 |
0x4c58dc LDR X18, [X28, X17,LSL #3] |
0x4c58e0 ORR X4, XZR, X25 |
0x4c58e4 LDR X30, [X28, X16] |
0x4c58e8 CMP X18, X30 |
0x4c58ec B.GE 4c5964 |
(2968) 0x4c58f0 LDR X30, [X6, X18,LSL #3] |
(2968) 0x4c58f4 UBFM X25, X30, #61, #60 |
(2968) 0x4c58f8 LDR X0, [X23, X30,LSL #3] |
(2968) 0x4c58fc ADD X13, X25, #8 |
(2968) 0x4c5900 LDR X10, [X23, X13] |
(2968) 0x4c5904 ADD X25, X23, X13 |
(2968) 0x4c5908 CMP X0, X10 |
(2968) 0x4c590c B.GE 4c594c |
(2968) 0x4c5910 STR X2, [SP, #104] |
(2968) 0x4c5914 HINT #0 |
(2968) 0x4c5918 HINT #0 |
(2968) 0x4c591c HINT #0 |
(2971) 0x4c5920 LDR X1, [X21, X0,LSL #3] |
(2971) 0x4c5924 LDR X2, [X19, X1,LSL #3] |
(2971) 0x4c5928 CMP X20, X2 |
(2971) 0x4c592c B.LE 4c5a68 |
(2971) 0x4c5930 STR X3, [X19, X1,LSL #3] |
(2971) 0x4c5934 ADD X0, X0, #1 |
(2971) 0x4c5938 ADD X3, X3, #1 |
(2971) 0x4c593c LDR X10, [X25] |
(2971) 0x4c5940 CMP X10, X0 |
(2971) 0x4c5944 B.GT 4c5920 |
(2968) 0x4c5948 LDR X2, [SP, #104] |
(2968) 0x4c594c CBNZ X5, 4c5a7c |
(2968) 0x4c5950 LDR X30, [X28, X16] |
(2968) 0x4c5954 ADD X18, X18, #1 |
(2968) 0x4c5958 CMP X30, X18 |
(2968) 0x4c595c B.GT 4c58f0 |
0x4c5960 ORR X25, XZR, X4 |
0x4c5964 LDR X4, [SP, #136] |
0x4c5968 ADD X16, X16, #8 |
0x4c596c STR X20, [X4, X17,LSL #3] |
0x4c5970 LDR X20, [SP, #112] |
0x4c5974 STR X15, [X2, X17,LSL #3] |
0x4c5978 ADD X17, X17, #1 |
0x4c597c CMP X20, X17 |
0x4c5980 B.EQ 4c5b18 |
0x4c5984 ORR X20, XZR, X3 |
0x4c5988 LDR X3, [SP, #120] |
0x4c598c ORR X15, XZR, X12 |
0x4c5990 CBZ X3, 4c58cc |
0x4c59a8 LDR X18, [X11, X17,LSL #3] |
0x4c59ac LDR X10, [X11, X16] |
0x4c59b0 CMP X18, X10 |
0x4c59b4 B.GE 4c58dc |
0x4c59b8 ORR X4, XZR, X5 |
0x4c59bc HINT #0 |
(2965) 0x4c59c0 LDR X30, [X14, X18,LSL #3] |
(2965) 0x4c59c4 UBFM X5, X30, #61, #60 |
(2965) 0x4c59c8 LDR X1, [X7, X30,LSL #3] |
(2965) 0x4c59cc ADD X10, X5, #8 |
(2965) 0x4c59d0 LDR X5, [X7, X10] |
(2965) 0x4c59d4 ADD X13, X7, X10 |
(2965) 0x4c59d8 CMP X1, X5 |
(2965) 0x4c59dc B.GE 4c5a14 |
(2965) 0x4c59e0 STR X2, [SP, #104] |
(2967) 0x4c59e4 LDR X0, [X25, X1,LSL #3] |
(2967) 0x4c59e8 ADD X0, X22, X0 |
(2967) 0x4c59ec LDR X2, [X19, X0,LSL #3] |
(2967) 0x4c59f0 CMP X15, X2 |
(2967) 0x4c59f4 B.LE 4c5b08 |
(2967) 0x4c59f8 STR X12, [X19, X0,LSL #3] |
(2967) 0x4c59fc ADD X1, X1, #1 |
(2967) 0x4c5a00 ADD X12, X12, #1 |
(2967) 0x4c5a04 LDR X5, [X13] |
(2967) 0x4c5a08 CMP X5, X1 |
(2967) 0x4c5a0c B.GT 4c59e4 |
(2965) 0x4c5a10 LDR X2, [SP, #104] |
(2965) 0x4c5a14 LDR X0, [X8, X30,LSL #3] |
(2965) 0x4c5a18 ADD X30, X8, X10 |
(2965) 0x4c5a1c LDR X1, [X8, X10] |
(2965) 0x4c5a20 CMP X0, X1 |
(2965) 0x4c5a24 B.GE 4c5a50 |
(2966) 0x4c5a28 LDR X13, [X26, X0,LSL #3] |
(2966) 0x4c5a2c LDR X10, [X19, X13,LSL #3] |
(2966) 0x4c5a30 CMP X20, X10 |
(2966) 0x4c5a34 B.LE 4c5ae8 |
(2966) 0x4c5a38 STR X3, [X19, X13,LSL #3] |
(2966) 0x4c5a3c ADD X0, X0, #1 |
(2966) 0x4c5a40 ADD X3, X3, #1 |
(2966) 0x4c5a44 LDR X1, [X30] |
(2966) 0x4c5a48 CMP X0, X1 |
(2966) 0x4c5a4c B.LT 4c5a28 |
(2965) 0x4c5a50 LDR X5, [X11, X16] |
(2965) 0x4c5a54 ADD X18, X18, #1 |
(2965) 0x4c5a58 CMP X5, X18 |
(2965) 0x4c5a5c B.GT 4c59c0 |
0x4c5a60 ORR X5, XZR, X4 |
0x4c5a64 B 4c58dc |
(2971) 0x4c5a68 ADD X0, X0, #1 |
(2971) 0x4c5a6c CMP X0, X10 |
(2971) 0x4c5a70 B.LT 4c5920 |
(2968) 0x4c5a74 LDR X2, [SP, #104] |
(2968) 0x4c5a78 B 4c594c |
(2968) 0x4c5a7c LDR X1, [X9, X30,LSL #3] |
(2968) 0x4c5a80 ADD X30, X9, X13 |
(2968) 0x4c5a84 LDR X13, [X9, X13] |
(2968) 0x4c5a88 CMP X1, X13 |
(2968) 0x4c5a8c B.GE 4c5950 |
(2969) 0x4c5a90 LDR X25, [X27, X1,LSL #3] |
(2969) 0x4c5a94 LDR X0, [X24, X25,LSL #3] |
(2969) 0x4c5a98 ADD X10, X22, X0 |
(2969) 0x4c5a9c LDR X25, [X19, X10,LSL #3] |
(2969) 0x4c5aa0 CMP X15, X25 |
(2969) 0x4c5aa4 B.LE 4c5ad8 |
(2970) 0x4c5aa8 STR X12, [X19, X10,LSL #3] |
(2970) 0x4c5aac ADD X1, X1, #1 |
(2970) 0x4c5ab0 ADD X12, X12, #1 |
(2970) 0x4c5ab4 LDR X13, [X30] |
(2970) 0x4c5ab8 CMP X13, X1 |
(2970) 0x4c5abc B.LE 4c5950 |
(2970) 0x4c5ac0 LDR X25, [X27, X1,LSL #3] |
(2970) 0x4c5ac4 LDR X0, [X24, X25,LSL #3] |
(2970) 0x4c5ac8 ADD X10, X22, X0 |
(2970) 0x4c5acc LDR X25, [X19, X10,LSL #3] |
(2970) 0x4c5ad0 CMP X15, X25 |
(2970) 0x4c5ad4 B.GT 4c5aa8 |
(2969) 0x4c5ad8 ADD X1, X1, #1 |
(2969) 0x4c5adc CMP X13, X1 |
(2969) 0x4c5ae0 B.GT 4c5a90 |
(2968) 0x4c5ae4 B 4c5950 |
(2966) 0x4c5ae8 ADD X0, X0, #1 |
(2966) 0x4c5aec CMP X0, X1 |
(2966) 0x4c5af0 B.LT 4c5a28 |
(2965) 0x4c5af4 LDR X5, [X11, X16] |
(2965) 0x4c5af8 ADD X18, X18, #1 |
(2965) 0x4c5afc CMP X5, X18 |
(2965) 0x4c5b00 B.GT 4c59c0 |
0x4c5b04 B 4c5a60 |
(2967) 0x4c5b08 ADD X1, X1, #1 |
(2967) 0x4c5b0c CMP X1, X5 |
(2967) 0x4c5b10 B.LT 4c59e4 |
(2965) 0x4c5b14 B 4c5a10 |
/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 127 - 242 |
-------------------------------------------------------------------------------- |
127: for (i1 = ns; i1 < ne; i1++) |
[...] |
135: if ( allsquare ) { |
[...] |
144: if (num_cols_offd_A) |
145: { |
146: for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++) |
[...] |
154: for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++) |
155: { |
156: i3 = num_cols_diag_B+B_ext_offd_j[jj3]; |
[...] |
164: if (B_marker[i3] < jj_row_begin_offd) |
165: { |
166: B_marker[i3] = jj_count_offd; |
167: jj_count_offd++; |
168: } |
169: } |
170: for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++) |
171: { |
172: i3 = B_ext_diag_j[jj3]; |
173: |
174: if (B_marker[i3] < jj_row_begin_diag) |
175: { |
176: B_marker[i3] = jj_count_diag; |
177: jj_count_diag++; |
[...] |
187: for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++) |
[...] |
195: for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++) |
[...] |
205: if (B_marker[i3] < jj_row_begin_diag) |
206: { |
207: B_marker[i3] = jj_count_diag; |
208: jj_count_diag++; |
[...] |
216: if (num_cols_offd_B) |
217: { |
218: for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++) |
219: { |
220: i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]]; |
[...] |
228: if (B_marker[i3] < jj_row_begin_offd) |
229: { |
230: B_marker[i3] = jj_count_offd; |
231: jj_count_offd++; |
[...] |
241: (*C_diag_i)[i1] = jj_row_begin_diag; |
242: (*C_offd_i)[i1] = jj_row_begin_offd; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | GOMP_parallel | libomp.so | |
○ | hypre_ParMatmul_RowSizes | par_csr_matop.c:286 | exec |
○ | hypre_ParMatmul | par_csr_matop.c:812 | exec |
○ | hypre_BoomerAMGSetup | par_amg_setup.c:1227 | exec |
○ | hypre_PCGSetup | pcg.c:234 | exec |
○ | main | amg.c:398 | exec |
○ | __libc_start_main | libc-2.31.so | |
○ | _start | amg.c:599 | exec |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.07 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParMatmul_RowSizes._omp_fn.0 |
Source | par_csr_matop.c:127-127,par_csr_matop.c:135-135,par_csr_matop.c:144-146,par_csr_matop.c:187-187,par_csr_matop.c:241-242 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 3.75 |
CQA cycles if no scalar integer | 3.75 |
CQA cycles if FP arith vectorized | 3.75 |
CQA cycles if fully vectorized | 0.94 |
Front-end cycles | 3.75 |
DIV/SQRT cycles | 3.50 |
P0 cycles | 3.50 |
P1 cycles | 3.25 |
P2 cycles | 3.25 |
P3 cycles | 3.25 |
P4 cycles | 3.25 |
P5 cycles | 0.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 3.33 |
P10 cycles | 3.33 |
P11 cycles | 3.33 |
P12 cycles | 1.00 |
P13 cycles | 1.00 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 31.00 |
Nb uops | 30.00 |
Nb loads | NA |
Nb stores | 2.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 21.33 |
Bytes prefetched | 0.00 |
Bytes loaded | 64.00 |
Bytes stored | 16.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 25.00 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 25.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.07 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParMatmul_RowSizes._omp_fn.0 |
Source | par_csr_matop.c:127-127,par_csr_matop.c:135-135,par_csr_matop.c:144-146,par_csr_matop.c:187-187,par_csr_matop.c:241-242 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 3.75 |
CQA cycles if no scalar integer | 3.75 |
CQA cycles if FP arith vectorized | 3.75 |
CQA cycles if fully vectorized | 0.94 |
Front-end cycles | 3.75 |
DIV/SQRT cycles | 3.50 |
P0 cycles | 3.50 |
P1 cycles | 3.25 |
P2 cycles | 3.25 |
P3 cycles | 3.25 |
P4 cycles | 3.25 |
P5 cycles | 0.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 3.33 |
P10 cycles | 3.33 |
P11 cycles | 3.33 |
P12 cycles | 1.00 |
P13 cycles | 1.00 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 31.00 |
Nb uops | 30.00 |
Nb loads | NA |
Nb stores | 2.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 21.33 |
Bytes prefetched | 0.00 |
Bytes loaded | 64.00 |
Bytes stored | 16.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 25.00 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 25.00 |
Path / |
Function | hypre_ParMatmul_RowSizes._omp_fn.0 |
Source file and lines | par_csr_matop.c:127-242 |
Module | exec |
nb instructions | 31 |
loop length | 124 |
nb stack references | 0 |
front end | 3.75 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.50 | 3.50 | 3.25 | 3.25 | 3.25 | 3.25 | 0.00 | 0.00 | 0.00 | 0.00 | 3.33 | 3.33 | 3.33 | 1.00 | 1.00 |
cycles | 3.50 | 3.50 | 3.25 | 3.25 | 3.25 | 3.25 | 0.00 | 0.00 | 0.00 | 0.00 | 3.33 | 3.33 | 3.33 | 1.00 | 1.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 3.75 |
Overall L1 | 3.75 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LDR X4, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ORR X3, XZR, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X12, XZR, X15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CBNZ X4, 4c59a8 <hypre_ParMatmul_RowSizes._omp_fn.0+0x208> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X18, [X28, X17,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ORR X4, XZR, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X30, [X28, X16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X18, X30 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 4c5964 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1c4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR X25, XZR, X4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X4, [SP, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X16, X16, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X20, [X4, X17,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X20, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STR X15, [X2, X17,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X17, X17, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X20, X17 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4c5b18 <hypre_ParMatmul_RowSizes._omp_fn.0+0x378> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR X20, XZR, X3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X3, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ORR X15, XZR, X12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CBZ X3, 4c58cc <hypre_ParMatmul_RowSizes._omp_fn.0+0x12c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X18, [X11, X17,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X10, [X11, X16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X18, X10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 4c58dc <hypre_ParMatmul_RowSizes._omp_fn.0+0x13c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR X4, XZR, X5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
HINT #0 | ||||||||||||||||||
ORR X5, XZR, X4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
B 4c58dc <hypre_ParMatmul_RowSizes._omp_fn.0+0x13c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
B 4c5a60 <hypre_ParMatmul_RowSizes._omp_fn.0+0x2c0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Function | hypre_ParMatmul_RowSizes._omp_fn.0 |
Source file and lines | par_csr_matop.c:127-242 |
Module | exec |
nb instructions | 31 |
loop length | 124 |
nb stack references | 0 |
front end | 3.75 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.50 | 3.50 | 3.25 | 3.25 | 3.25 | 3.25 | 0.00 | 0.00 | 0.00 | 0.00 | 3.33 | 3.33 | 3.33 | 1.00 | 1.00 |
cycles | 3.50 | 3.50 | 3.25 | 3.25 | 3.25 | 3.25 | 0.00 | 0.00 | 0.00 | 0.00 | 3.33 | 3.33 | 3.33 | 1.00 | 1.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 3.75 |
Overall L1 | 3.75 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LDR X4, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ORR X3, XZR, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X12, XZR, X15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CBNZ X4, 4c59a8 <hypre_ParMatmul_RowSizes._omp_fn.0+0x208> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X18, [X28, X17,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ORR X4, XZR, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X30, [X28, X16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X18, X30 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 4c5964 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1c4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR X25, XZR, X4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X4, [SP, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X16, X16, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X20, [X4, X17,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X20, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STR X15, [X2, X17,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X17, X17, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X20, X17 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4c5b18 <hypre_ParMatmul_RowSizes._omp_fn.0+0x378> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR X20, XZR, X3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X3, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ORR X15, XZR, X12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CBZ X3, 4c58cc <hypre_ParMatmul_RowSizes._omp_fn.0+0x12c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X18, [X11, X17,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X10, [X11, X16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X18, X10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 4c58dc <hypre_ParMatmul_RowSizes._omp_fn.0+0x13c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR X4, XZR, X5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
HINT #0 | ||||||||||||||||||
ORR X5, XZR, X4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
B 4c58dc <hypre_ParMatmul_RowSizes._omp_fn.0+0x13c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
B 4c5a60 <hypre_ParMatmul_RowSizes._omp_fn.0+0x2c0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |