Loop Id: 1713 | Module: exec | Source: par_multi_interp.c:488-514 | Coverage: 0.1% |
---|
Loop Id: 1713 | Module: exec | Source: par_multi_interp.c:488-514 | Coverage: 0.1% |
---|
0x43298c LDR X0, [SP, #560] |
0x432990 SUB X18, X0, #1 |
0x432994 CMP X0, X23 |
0x432998 STR X18, [SP, #560] |
0x43299c B.LE 432a98 |
0x4329a0 LDR X18, [X9, X18,LSL #3] |
0x4329a4 ADD X0, X18, #1 |
0x4329a8 LDR X1, [X10, X18,LSL #3] |
0x4329ac LDR X3, [X10, X0,LSL #3] |
0x4329b0 CMP X1, X3 |
0x4329b4 B.GE 432a00 |
0x4329b8 LDUR X2, [X29, #368] |
0x4329bc LDR X4, [SP, #584] |
0x4329c0 B 4329d0 |
(1715) 0x4329c4 ADD X1, X1, #1 |
(1715) 0x4329c8 CMP X1, X3 |
(1715) 0x4329cc B.GE 432a00 |
(1715) 0x4329d0 LDR X5, [X11, X1,LSL #3] |
(1715) 0x4329d4 LDR X5, [X12, X5,LSL #3] |
(1715) 0x4329d8 CMP X5, #1 |
(1715) 0x4329dc B.NE 4329c4 |
(1715) 0x4329e0 LDR X3, [X2, X0,LSL #3] |
(1715) 0x4329e4 ADD X20, X20, #1 |
(1715) 0x4329e8 ADD X3, X3, #1 |
(1715) 0x4329ec STR X3, [X2, X0,LSL #3] |
(1715) 0x4329f0 STR X16, [X4, X18,LSL #3] |
(1715) 0x4329f4 LDR X3, [X10, X0,LSL #3] |
(1715) 0x4329f8 B 4329c4 |
0x432a00 LDR X1, [X13, X18,LSL #3] |
0x432a04 LDR X4, [X13, X0,LSL #3] |
0x432a08 CMP X1, X4 |
0x432a0c B.GE 432a60 |
0x432a10 LDUR X2, [X29, #344] |
0x432a14 LDR X3, [SP, #584] |
0x432a18 B 432a2c |
(1714) 0x432a20 ADD X1, X1, #1 |
(1714) 0x432a24 CMP X1, X4 |
(1714) 0x432a28 B.GE 432a60 |
(1714) 0x432a2c LDR X5, [X14, X1,LSL #3] |
(1714) 0x432a30 LDR X5, [X15, X5,LSL #3] |
(1714) 0x432a34 CMP X5, #1 |
(1714) 0x432a38 B.NE 432a20 |
(1714) 0x432a3c LDR X4, [X2, X0,LSL #3] |
(1714) 0x432a40 ADD X19, X19, #1 |
(1714) 0x432a44 ADD X4, X4, #1 |
(1714) 0x432a48 STR X4, [X2, X0,LSL #3] |
(1714) 0x432a4c STR X16, [X3, X18,LSL #3] |
(1714) 0x432a50 LDR X4, [X13, X0,LSL #3] |
(1714) 0x432a54 B 432a20 |
0x432a60 LDR X0, [X17, X18,LSL #3] |
0x432a64 CMP X0, #1 |
0x432a68 B.NE 43298c |
0x432a6c LDR X1, [SP, #560] |
0x432a70 LDR X0, [X9, X23,LSL #3] |
0x432a74 ADD X2, X1, #1 |
0x432a78 STR X2, [SP, #560] |
0x432a7c STR X0, [X9, X1,LSL #3] |
0x432a80 STR X18, [X9, X23,LSL #3] |
0x432a84 ADD X23, X23, #1 |
0x432a88 B 43298c |
/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 488 - 514 |
-------------------------------------------------------------------------------- |
488: for (i = pass_array_size-1; i > cnt-1; i--) |
489: { |
490: i1 = pass_array[i]; |
491: for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++) |
492: { |
493: j1 = S_diag_j[j]; |
494: if (CF_marker[j1] == 1) |
495: { |
496: P_diag_i[i1+1]++; |
497: cnt_nz++; |
498: assigned[i1] = 1; |
499: } |
500: } |
501: for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++) |
502: { |
503: j1 = S_offd_j[j]; |
504: if (CF_marker_offd[j1] == 1) |
505: { |
506: P_offd_i[i1+1]++; |
507: cnt_nz_offd++; |
508: assigned[i1] = 1; |
509: } |
510: } |
511: if (assigned[i1] == 1) |
512: { |
513: pass_array[i++] = pass_array[cnt]; |
514: pass_array[cnt++] = i1; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | hypre_BoomerAMGSetup | par_amg_setup.c:785 | exec |
○ | hypre_PCGSetup | pcg.c:234 | exec |
○ | main | amg.c:398 | exec |
○ | __libc_start_main | libc-2.31.so | |
○ | _start | exec |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.42 |
Bottlenecks | P10, P11, P12, |
Function | hypre_BoomerAMGBuildMultipass |
Source | par_multi_interp.c:488-491,par_multi_interp.c:501-501,par_multi_interp.c:511-514 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 5.67 |
CQA cycles if no scalar integer | 5.67 |
CQA cycles if FP arith vectorized | 5.67 |
CQA cycles if fully vectorized | 1.42 |
Front-end cycles | 4.00 |
DIV/SQRT cycles | 3.50 |
P0 cycles | 3.50 |
P1 cycles | 2.00 |
P2 cycles | 2.00 |
P3 cycles | 2.00 |
P4 cycles | 2.00 |
P5 cycles | 0.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 5.67 |
P10 cycles | 5.67 |
P11 cycles | 5.67 |
P12 cycles | 2.00 |
P13 cycles | 2.00 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 32.00 |
Nb uops | 32.00 |
Nb loads | NA |
Nb stores | 4.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 104.00 |
Bytes stored | 32.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 25.00 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 25.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 25.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.42 |
Bottlenecks | P10, P11, P12, |
Function | hypre_BoomerAMGBuildMultipass |
Source | par_multi_interp.c:488-491,par_multi_interp.c:501-501,par_multi_interp.c:511-514 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 5.67 |
CQA cycles if no scalar integer | 5.67 |
CQA cycles if FP arith vectorized | 5.67 |
CQA cycles if fully vectorized | 1.42 |
Front-end cycles | 4.00 |
DIV/SQRT cycles | 3.50 |
P0 cycles | 3.50 |
P1 cycles | 2.00 |
P2 cycles | 2.00 |
P3 cycles | 2.00 |
P4 cycles | 2.00 |
P5 cycles | 0.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 5.67 |
P10 cycles | 5.67 |
P11 cycles | 5.67 |
P12 cycles | 2.00 |
P13 cycles | 2.00 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 32.00 |
Nb uops | 32.00 |
Nb loads | NA |
Nb stores | 4.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 104.00 |
Bytes stored | 32.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 25.00 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 25.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 25.00 |
Path / |
Function | hypre_BoomerAMGBuildMultipass |
Source file and lines | par_multi_interp.c:488-514 |
Module | exec |
nb instructions | 32 |
loop length | 128 |
nb stack references | 0 |
front end | 4.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.50 | 3.50 | 2.00 | 2.00 | 2.00 | 2.00 | 0.00 | 0.00 | 0.00 | 0.00 | 5.67 | 5.67 | 5.67 | 2.00 | 2.00 |
cycles | 3.50 | 3.50 | 2.00 | 2.00 | 2.00 | 2.00 | 0.00 | 0.00 | 0.00 | 0.00 | 5.67 | 5.67 | 5.67 | 2.00 | 2.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 4.00 |
Overall L1 | 5.67 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LDR X0, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUB X18, X0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X0, X23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
STR X18, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
B.LE 432a98 <hypre_BoomerAMGBuildMultipass+0xa38> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X18, [X9, X18,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X0, X18, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X1, [X10, X18,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X3, [X10, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X1, X3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 432a00 <hypre_BoomerAMGBuildMultipass+0x9a0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDUR X2, [X29, #368] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X4, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
B 4329d0 <hypre_BoomerAMGBuildMultipass+0x970> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X1, [X13, X18,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X4, [X13, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X1, X4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 432a60 <hypre_BoomerAMGBuildMultipass+0xa00> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDUR X2, [X29, #344] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X3, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
B 432a2c <hypre_BoomerAMGBuildMultipass+0x9cc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X0, [X17, X18,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.NE 43298c <hypre_BoomerAMGBuildMultipass+0x92c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X1, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X0, [X9, X23,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X2, X1, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X2, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X0, [X9, X1,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X18, [X9, X23,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X23, X23, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
B 43298c <hypre_BoomerAMGBuildMultipass+0x92c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Function | hypre_BoomerAMGBuildMultipass |
Source file and lines | par_multi_interp.c:488-514 |
Module | exec |
nb instructions | 32 |
loop length | 128 |
nb stack references | 0 |
front end | 4.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.50 | 3.50 | 2.00 | 2.00 | 2.00 | 2.00 | 0.00 | 0.00 | 0.00 | 0.00 | 5.67 | 5.67 | 5.67 | 2.00 | 2.00 |
cycles | 3.50 | 3.50 | 2.00 | 2.00 | 2.00 | 2.00 | 0.00 | 0.00 | 0.00 | 0.00 | 5.67 | 5.67 | 5.67 | 2.00 | 2.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 4.00 |
Overall L1 | 5.67 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LDR X0, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUB X18, X0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X0, X23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
STR X18, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
B.LE 432a98 <hypre_BoomerAMGBuildMultipass+0xa38> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X18, [X9, X18,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X0, X18, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X1, [X10, X18,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X3, [X10, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X1, X3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 432a00 <hypre_BoomerAMGBuildMultipass+0x9a0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDUR X2, [X29, #368] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X4, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
B 4329d0 <hypre_BoomerAMGBuildMultipass+0x970> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X1, [X13, X18,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X4, [X13, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X1, X4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 432a60 <hypre_BoomerAMGBuildMultipass+0xa00> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDUR X2, [X29, #344] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X3, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
B 432a2c <hypre_BoomerAMGBuildMultipass+0x9cc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X0, [X17, X18,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.NE 43298c <hypre_BoomerAMGBuildMultipass+0x92c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X1, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X0, [X9, X23,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X2, X1, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X2, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X0, [X9, X1,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X18, [X9, X23,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X23, X23, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
B 43298c <hypre_BoomerAMGBuildMultipass+0x92c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |