Loop Id: 2308 | Module: exec | Source: par_strength.c:1714-1797 [...] | Coverage: 0.06% |
---|
Loop Id: 2308 | Module: exec | Source: par_strength.c:1714-1797 [...] | Coverage: 0.06% |
---|
0x499f94 LDR X20, [SP, #128] |
0x499f98 LDR X22, [SP, #144] |
0x499f9c LDR X17, [SP, #160] |
0x499fa0 LDR X30, [X20, X9,LSL #3] |
0x499fa4 STR X11, [X22, X9,LSL #3] |
0x499fa8 LDR X4, [X17] |
0x499fac CBZ X4, 499fb8 |
0x499fb8 UBFM X10, X30, #61, #60 |
0x499fbc LDR X13, [X18, X30,LSL #3] |
0x499fc0 ORR X4, XZR, X11 |
0x499fc4 ADD X20, X10, #8 |
0x499fc8 ORR X3, XZR, X6 |
0x499fcc LDR X2, [X18, X20] |
0x499fd0 ADD X22, X18, X20 |
0x499fd4 CMP X13, X2 |
0x499fd8 B.GE 49a0c8 |
0x499fdc HINT #0 |
(2312) 0x499fe0 LDR X12, [X26, X13,LSL #3] |
(2312) 0x499fe4 LDR X5, [X23, X12,LSL #3] |
(2312) 0x499fe8 UBFM X17, X12, #61, #60 |
(2312) 0x499fec CMP X5, #0 |
(2312) 0x499ff0 B.LE 49a00c |
(2312) 0x499ff4 LDR X0, [X8, X12,LSL #3] |
(2312) 0x499ff8 LDR X1, [X21, X0,LSL #3] |
(2312) 0x499ffc CMP X11, X1 |
(2312) 0x49a000 B.LE 49a00c |
(2312) 0x49a004 STR X4, [X21, X0,LSL #3] |
(2312) 0x49a008 ADD X4, X4, #1 |
(2312) 0x49a00c ADD X10, X17, #8 |
(2312) 0x49a010 LDR X0, [X18, X12,LSL #3] |
(2312) 0x49a014 ADD X17, X18, X10 |
(2312) 0x49a018 LDR X5, [X18, X10] |
(2312) 0x49a01c CMP X0, X5 |
(2312) 0x49a020 B.GE 49a06c |
(2314) 0x49a024 LDR X1, [X26, X0,LSL #3] |
(2314) 0x49a028 LDR X2, [X23, X1,LSL #3] |
(2314) 0x49a02c CMP X2, #0 |
(2314) 0x49a030 B.LE 49a060 |
(2314) 0x49a034 LDR X1, [X8, X1,LSL #3] |
(2314) 0x49a038 CMP X9, X1 |
(2314) 0x49a03c B.EQ 49a060 |
(2314) 0x49a040 LDR X2, [X21, X1,LSL #3] |
(2314) 0x49a044 CMP X11, X2 |
(2314) 0x49a048 B.LE 49a060 |
(2314) 0x49a04c STR X4, [X21, X1,LSL #3] |
(2314) 0x49a050 ADD X4, X4, #1 |
(2314) 0x49a054 LDR X5, [X17] |
(2314) 0x49a058 HINT #0 |
(2314) 0x49a05c HINT #0 |
(2314) 0x49a060 ADD X0, X0, #1 |
(2314) 0x49a064 CMP X0, X5 |
(2314) 0x49a068 B.LT 49a024 |
(2312) 0x49a06c LDR X0, [X14, X12,LSL #3] |
(2312) 0x49a070 ADD X12, X14, X10 |
(2312) 0x49a074 LDR X5, [X14, X10] |
(2312) 0x49a078 CMP X0, X5 |
(2312) 0x49a07c B.GE 49a0b8 |
(2313) 0x49a080 LDR X10, [X25, X0,LSL #3] |
(2313) 0x49a084 LDR X17, [X24, X10,LSL #3] |
(2313) 0x49a088 CMP X17, #0 |
(2313) 0x49a08c B.LE 49a0ac |
(2313) 0x49a090 LDR X1, [X7, X10,LSL #3] |
(2313) 0x49a094 LDR X2, [X19, X1,LSL #3] |
(2313) 0x49a098 CMP X6, X2 |
(2313) 0x49a09c B.LE 49a0ac |
(2313) 0x49a0a0 STR X3, [X19, X1,LSL #3] |
(2313) 0x49a0a4 ADD X3, X3, #1 |
(2313) 0x49a0a8 LDR X5, [X12] |
(2313) 0x49a0ac ADD X0, X0, #1 |
(2313) 0x49a0b0 CMP X0, X5 |
(2313) 0x49a0b4 B.LT 49a080 |
(2312) 0x49a0b8 LDR X12, [X22] |
(2312) 0x49a0bc ADD X13, X13, #1 |
(2312) 0x49a0c0 CMP X12, X13 |
(2312) 0x49a0c4 B.GT 499fe0 |
0x49a0c8 LDR X13, [X14, X30,LSL #3] |
0x49a0cc ADD X30, X14, X20 |
0x49a0d0 LDR X20, [X14, X20] |
0x49a0d4 CMP X13, X20 |
0x49a0d8 B.GE 49a1a0 |
0x49a0dc HINT #0 |
(2309) 0x49a0e0 LDR X22, [X25, X13,LSL #3] |
(2309) 0x49a0e4 LDR X17, [X24, X22,LSL #3] |
(2309) 0x49a0e8 UBFM X10, X22, #61, #60 |
(2309) 0x49a0ec CMP X17, #0 |
(2309) 0x49a0f0 B.LE 49a10c |
(2309) 0x49a0f4 LDR X2, [X7, X22,LSL #3] |
(2309) 0x49a0f8 LDR X1, [X19, X2,LSL #3] |
(2309) 0x49a0fc CMP X1, X6 |
(2309) 0x49a100 B.GE 49a10c |
(2309) 0x49a104 STR X3, [X19, X2,LSL #3] |
(2309) 0x49a108 ADD X3, X3, #1 |
(2309) 0x49a10c ADD X17, X10, #8 |
(2309) 0x49a110 LDR X0, [X16, X22,LSL #3] |
(2309) 0x49a114 ADD X12, X16, X17 |
(2309) 0x49a118 LDR X10, [X16, X17] |
(2309) 0x49a11c CMP X0, X10 |
(2309) 0x49a120 B.GE 49a154 |
(2311) 0x49a124 LDR X20, [X28, X0,LSL #3] |
(2311) 0x49a128 CMP X9, X20 |
(2311) 0x49a12c B.EQ 49a148 |
(2311) 0x49a130 LDR X5, [X21, X20,LSL #3] |
(2311) 0x49a134 CMP X11, X5 |
(2311) 0x49a138 B.LE 49a148 |
(2311) 0x49a13c STR X4, [X21, X20,LSL #3] |
(2311) 0x49a140 ADD X4, X4, #1 |
(2311) 0x49a144 LDR X10, [X12] |
(2311) 0x49a148 ADD X0, X0, #1 |
(2311) 0x49a14c CMP X0, X10 |
(2311) 0x49a150 B.LT 49a124 |
(2309) 0x49a154 LDR X12, [X15, X22,LSL #3] |
(2309) 0x49a158 ADD X22, X15, X17 |
(2309) 0x49a15c LDR X17, [X15, X17] |
(2309) 0x49a160 CMP X12, X17 |
(2309) 0x49a164 B.GE 49a190 |
(2310) 0x49a168 LDR X1, [X27, X12,LSL #3] |
(2310) 0x49a16c LDR X2, [X19, X1,LSL #3] |
(2310) 0x49a170 CMP X6, X2 |
(2310) 0x49a174 B.LE 49a1bc |
(2310) 0x49a178 STR X3, [X19, X1,LSL #3] |
(2310) 0x49a17c ADD X12, X12, #1 |
(2310) 0x49a180 ADD X3, X3, #1 |
(2310) 0x49a184 LDR X17, [X22] |
(2310) 0x49a188 CMP X12, X17 |
(2310) 0x49a18c B.LT 49a168 |
(2309) 0x49a190 LDR X20, [X30] |
(2309) 0x49a194 ADD X13, X13, #1 |
(2309) 0x49a198 CMP X20, X13 |
(2309) 0x49a19c B.GT 49a0e0 |
0x49a1a0 LDR X6, [SP, #136] |
0x49a1a4 ADD X9, X9, #1 |
0x49a1a8 CMP X6, X9 |
0x49a1ac B.EQ 49a1dc |
0x49a1b0 ORR X11, XZR, X4 |
0x49a1b4 ORR X6, XZR, X3 |
0x49a1b8 B 499f94 |
(2310) 0x49a1bc ADD X12, X12, #1 |
(2310) 0x49a1c0 CMP X12, X17 |
(2310) 0x49a1c4 B.LT 49a168 |
(2309) 0x49a1c8 LDR X20, [X30] |
(2309) 0x49a1cc ADD X13, X13, #1 |
(2309) 0x49a1d0 CMP X20, X13 |
(2309) 0x49a1d4 B.GT 49a0e0 |
0x49a1d8 B 49a1a0 |
/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 1714 - 1797 |
-------------------------------------------------------------------------------- |
1714: for (ic = ic_begin; ic < ic_end; ic++) |
[...] |
1720: HYPRE_Int i1 = coarse_to_fine[ic]; |
1721: |
1722: HYPRE_Int jj_row_begin_diag = num_nonzeros_diag; |
1723: HYPRE_Int jj_row_begin_offd = num_nonzeros_offd; |
1724: |
1725: C_diag_i[ic] = num_nonzeros_diag; |
1726: if (num_cols_offd_C) |
1727: { |
1728: C_offd_i[ic] = num_nonzeros_offd; |
1729: } |
1730: |
1731: for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++) |
1732: { |
1733: i2 = S_diag_j[jj1]; |
1734: if (CF_marker[i2] > 0) |
1735: { |
1736: index = fine_to_coarse[i2]; |
1737: if (S_marker[index] < jj_row_begin_diag) |
1738: { |
1739: S_marker[index] = num_nonzeros_diag; |
1740: num_nonzeros_diag++; |
1741: } |
1742: } |
1743: for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++) |
1744: { |
1745: i3 = S_diag_j[jj2]; |
1746: if (CF_marker[i3] > 0) |
1747: { |
1748: index = fine_to_coarse[i3]; |
1749: if (index != ic && S_marker[index] < jj_row_begin_diag) |
1750: { |
1751: S_marker[index] = num_nonzeros_diag; |
1752: num_nonzeros_diag++; |
1753: } |
1754: } |
1755: } |
1756: for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++) |
1757: { |
1758: i3 = S_offd_j[jj2]; |
1759: if (CF_marker_offd[i3] > 0) |
1760: { |
1761: index = map_S_to_C[i3]; |
1762: if (S_marker_offd[index] < jj_row_begin_offd) |
1763: { |
1764: S_marker_offd[index] = num_nonzeros_offd; |
1765: num_nonzeros_offd++; |
1766: } |
1767: } |
1768: } |
1769: } |
1770: for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++) |
1771: { |
1772: i2 = S_offd_j[jj1]; |
1773: if (CF_marker_offd[i2] > 0) |
1774: { |
1775: index = map_S_to_C[i2]; |
1776: if (S_marker_offd[index] < jj_row_begin_offd) |
1777: { |
1778: S_marker_offd[index] = num_nonzeros_offd; |
1779: num_nonzeros_offd++; |
1780: } |
1781: } |
1782: for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++) |
1783: { |
1784: i3 = S_ext_diag_j[jj2]; |
1785: if (i3 != ic && S_marker[i3] < jj_row_begin_diag) |
1786: { |
1787: S_marker[i3] = num_nonzeros_diag; |
1788: num_nonzeros_diag++; |
1789: } |
1790: } |
1791: for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++) |
1792: { |
1793: i3 = S_ext_offd_j[jj2]; |
1794: if (S_marker_offd[i3] < jj_row_begin_offd) |
1795: { |
1796: S_marker_offd[i3] = num_nonzeros_offd; |
1797: num_nonzeros_offd++; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | GOMP_parallel | libomp.so | |
○ | hypre_BoomerAMGCreate2ndS | par_strength.c:1668 | exec |
○ | hypre_BoomerAMGSetup | par_amg_setup.c:623 | exec |
○ | hypre_PCGSetup | pcg.c:234 | exec |
○ | main | amg.c:398 | exec |
○ | __libc_start_main | libc-2.31.so | |
○ | _start | amg.c:599 | exec |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.05 |
Bottlenecks | P10, |
Function | hypre_BoomerAMGCreate2ndS._omp_fn.7 |
Source | par_strength.c:1714-1714,par_strength.c:1720-1720,par_strength.c:1725-1726,par_strength.c:1731-1731,par_strength.c:1770-1770 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 3.83 |
CQA cycles if no scalar integer | 3.83 |
CQA cycles if FP arith vectorized | 3.83 |
CQA cycles if fully vectorized | 0.96 |
Front-end cycles | 3.63 |
DIV/SQRT cycles | 3.00 |
P0 cycles | 3.00 |
P1 cycles | 3.00 |
P2 cycles | 3.00 |
P3 cycles | 3.00 |
P4 cycles | 3.00 |
P5 cycles | 0.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 3.83 |
P10 cycles | 3.50 |
P11 cycles | 3.67 |
P12 cycles | 0.50 |
P13 cycles | 0.50 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 31.00 |
Nb uops | 29.00 |
Nb loads | NA |
Nb stores | 1.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 22.96 |
Bytes prefetched | 0.00 |
Bytes loaded | 80.00 |
Bytes stored | 8.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 25.00 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 25.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.05 |
Bottlenecks | P10, |
Function | hypre_BoomerAMGCreate2ndS._omp_fn.7 |
Source | par_strength.c:1714-1714,par_strength.c:1720-1720,par_strength.c:1725-1726,par_strength.c:1731-1731,par_strength.c:1770-1770 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 3.83 |
CQA cycles if no scalar integer | 3.83 |
CQA cycles if FP arith vectorized | 3.83 |
CQA cycles if fully vectorized | 0.96 |
Front-end cycles | 3.63 |
DIV/SQRT cycles | 3.00 |
P0 cycles | 3.00 |
P1 cycles | 3.00 |
P2 cycles | 3.00 |
P3 cycles | 3.00 |
P4 cycles | 3.00 |
P5 cycles | 0.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 3.83 |
P10 cycles | 3.50 |
P11 cycles | 3.67 |
P12 cycles | 0.50 |
P13 cycles | 0.50 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 31.00 |
Nb uops | 29.00 |
Nb loads | NA |
Nb stores | 1.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 22.96 |
Bytes prefetched | 0.00 |
Bytes loaded | 80.00 |
Bytes stored | 8.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 25.00 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 25.00 |
Path / |
Function | hypre_BoomerAMGCreate2ndS._omp_fn.7 |
Source file and lines | par_strength.c:1714-1797 |
Module | exec |
nb instructions | 31 |
loop length | 124 |
nb stack references | 0 |
front end | 3.63 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.00 | 3.00 | 3.00 | 3.00 | 3.00 | 3.00 | 0.00 | 0.00 | 0.00 | 0.00 | 3.83 | 3.50 | 3.67 | 0.50 | 0.50 |
cycles | 3.00 | 3.00 | 3.00 | 3.00 | 3.00 | 3.00 | 0.00 | 0.00 | 0.00 | 0.00 | 3.83 | 3.50 | 3.67 | 0.50 | 0.50 |
Cycles executing div or sqrt instructions | NA |
Front-end | 3.63 |
Overall L1 | 3.83 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LDR X20, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X22, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X17, [SP, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X30, [X20, X9,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STR X11, [X22, X9,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X4, [X17] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CBZ X4, 499fb8 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1418> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
UBFM X10, X30, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X13, [X18, X30,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ORR X4, XZR, X11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X20, X10, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X3, XZR, X6 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X2, [X18, X20] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X22, X18, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X13, X2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 49a0c8 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1528> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
LDR X13, [X14, X30,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X30, X14, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X20, [X14, X20] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X13, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 49a1a0 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1600> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
LDR X6, [SP, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X9, X9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X6, X9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 49a1dc <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x163c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR X11, XZR, X4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X6, XZR, X3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
B 499f94 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x13f4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
B 49a1a0 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1600> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Function | hypre_BoomerAMGCreate2ndS._omp_fn.7 |
Source file and lines | par_strength.c:1714-1797 |
Module | exec |
nb instructions | 31 |
loop length | 124 |
nb stack references | 0 |
front end | 3.63 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.00 | 3.00 | 3.00 | 3.00 | 3.00 | 3.00 | 0.00 | 0.00 | 0.00 | 0.00 | 3.83 | 3.50 | 3.67 | 0.50 | 0.50 |
cycles | 3.00 | 3.00 | 3.00 | 3.00 | 3.00 | 3.00 | 0.00 | 0.00 | 0.00 | 0.00 | 3.83 | 3.50 | 3.67 | 0.50 | 0.50 |
Cycles executing div or sqrt instructions | NA |
Front-end | 3.63 |
Overall L1 | 3.83 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LDR X20, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X22, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X17, [SP, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X30, [X20, X9,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STR X11, [X22, X9,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X4, [X17] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CBZ X4, 499fb8 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1418> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
UBFM X10, X30, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X13, [X18, X30,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ORR X4, XZR, X11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X20, X10, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X3, XZR, X6 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X2, [X18, X20] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X22, X18, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X13, X2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 49a0c8 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1528> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
LDR X13, [X14, X30,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X30, X14, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X20, [X14, X20] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X13, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 49a1a0 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1600> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
LDR X6, [SP, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X9, X9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X6, X9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 49a1dc <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x163c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR X11, XZR, X4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X6, XZR, X3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
B 499f94 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x13f4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
B 49a1a0 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1600> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |