Loop Id: 24 | Module: exec | Source: csr_matop.c:272-298 [...] | Coverage: 0.25% |
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Loop Id: 24 | Module: exec | Source: csr_matop.c:272-298 [...] | Coverage: 0.25% |
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(22) 0x4a1ec0 CMP X21, X28 |
(22) 0x4a1ec4 B.GE 4a1f98 |
(22) 0x4a1ec8 LDR X17, [X8, X21,LSL #3] |
(22) 0x4a1ecc LDR X18, [X19] |
(22) 0x4a1ed0 CBZ X18, 4a1ee4 |
(22) 0x4a1ee4 LDR X18, [X12, X21,LSL #3] |
(22) 0x4a1ee8 ADD X21, X21, #1 |
(22) 0x4a1eec LDR X4, [X12, X21,LSL #3] |
(22) 0x4a1ef0 CMP X18, X4 |
(22) 0x4a1ef4 B.GE 4a1ec0 |
(23) 0x4a1ef8 LDR X0, [X27] |
(23) 0x4a1efc LDR X1, [X26] |
(23) 0x4a1f00 B 4a1f14 |
(26) 0x4a1f04 LDR X4, [X12, X21,LSL #3] |
(23) 0x4a1f08 ADD X18, X18, #1 |
(23) 0x4a1f0c CMP X18, X4 |
(23) 0x4a1f10 B.GE 4a1ec0 |
(23) 0x4a1f14 LDR X2, [X13, X18,LSL #3] |
(23) 0x4a1f18 LDR X3, [X15, X2,LSL #3] |
(23) 0x4a1f1c LDR X5, [X16, X2,LSL #3] |
(23) 0x4a1f20 CMP X3, X5 |
(23) 0x4a1f24 B.GE 4a1f08 |
0x4a1f28 LDR D0, [X14, X18,LSL #3] |
0x4a1f2c LDR X4, [X22] |
0x4a1f30 LDR X6, [X23] |
0x4a1f34 B 4a1f58 |
0x4a1f40 LDR D2, [X4, X24,LSL #3] |
0x4a1f44 FMADD D1, D0, D1, D2 |
0x4a1f48 STR D1, [X4, X24,LSL #3] |
0x4a1f4c ADD X3, X3, #1 |
0x4a1f50 CMP X3, X5 |
0x4a1f54 B.GE 4a1f04 |
(25) 0x4a1f58 LDR X7, [X0, X3,LSL #3] |
(25) 0x4a1f5c LDR D1, [X1, X3,LSL #3] |
(25) 0x4a1f60 LDR X24, [X20, X7,LSL #3] |
(25) 0x4a1f64 CMP X24, X17 |
(25) 0x4a1f68 B.GE 4a1f40 |
(25) 0x4a1f6c STR X9, [X20, X7,LSL #3] |
(25) 0x4a1f70 STR X7, [X6, X9,LSL #3] |
(25) 0x4a1f74 FMUL D1, D0, D1 |
(25) 0x4a1f78 ADD X9, X9, #1 |
(25) 0x4a1f7c LDR X5, [X20, X7,LSL #3] |
(25) 0x4a1f80 STR D1, [X4, X5,LSL #3] |
(25) 0x4a1f84 LDR X5, [X16, X2,LSL #3] |
(25) 0x4a1f88 ADD X3, X3, #1 |
(25) 0x4a1f8c CMP X3, X5 |
(25) 0x4a1f90 B.LT 4a1f58 |
(26) 0x4a1f94 B 4a1f04 |
/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c: 272 - 298 |
-------------------------------------------------------------------------------- |
272: for (ic = ns; ic < ne; ic++) |
273: { |
274: row_start = C_i[ic]; |
275: if (allsquare) |
[...] |
282: for (ia = A_i[ic]; ia < A_i[ic+1]; ia++) |
283: { |
284: ja = A_j[ia]; |
285: a_entry = A_data[ia]; |
286: for (ib = B_i[ja]; ib < B_i[ja+1]; ib++) |
287: { |
288: jb = B_j[ib]; |
289: b_entry = B_data[ib]; |
290: if (B_marker[jb] < row_start) |
291: { |
292: B_marker[jb] = counter; |
293: C_j[B_marker[jb]] = jb; |
294: C_data[B_marker[jb]] = a_entry*b_entry; |
295: counter++; |
296: } |
297: else |
298: C_data[B_marker[jb]] += a_entry*b_entry; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○100.00 | __kmp_invoke_microtask | libomp.so |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.57 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.10 |
Bottlenecks | P10, |
Function | .omp_outlined.#0x4a1a00 |
Source | csr_matop.c:286-286,csr_matop.c:298-298 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 1.83 |
CQA cycles if no scalar integer | 1.17 |
CQA cycles if FP arith vectorized | 1.83 |
CQA cycles if fully vectorized | 0.46 |
Front-end cycles | 1.25 |
DIV/SQRT cycles | 1.00 |
P0 cycles | 1.00 |
P1 cycles | 0.50 |
P2 cycles | 0.50 |
P3 cycles | 0.50 |
P4 cycles | 0.50 |
P5 cycles | 0.50 |
P6 cycles | 0.50 |
P7 cycles | 0.50 |
P8 cycles | 0.50 |
P9 cycles | 1.83 |
P10 cycles | 1.50 |
P11 cycles | 1.67 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 10.00 |
Nb uops | 10.00 |
Nb loads | NA |
Nb stores | 1.00 |
Nb stack references | 0.00 |
FLOP/cycle | 1.09 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 1.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 21.82 |
Bytes prefetched | 0.00 |
Bytes loaded | 32.00 |
Bytes stored | 8.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 25.00 |
Vector-efficiency ratio load | 25.00 |
Vector-efficiency ratio store | 25.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.57 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.10 |
Bottlenecks | P10, |
Function | .omp_outlined.#0x4a1a00 |
Source | csr_matop.c:286-286,csr_matop.c:298-298 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 1.83 |
CQA cycles if no scalar integer | 1.17 |
CQA cycles if FP arith vectorized | 1.83 |
CQA cycles if fully vectorized | 0.46 |
Front-end cycles | 1.25 |
DIV/SQRT cycles | 1.00 |
P0 cycles | 1.00 |
P1 cycles | 0.50 |
P2 cycles | 0.50 |
P3 cycles | 0.50 |
P4 cycles | 0.50 |
P5 cycles | 0.50 |
P6 cycles | 0.50 |
P7 cycles | 0.50 |
P8 cycles | 0.50 |
P9 cycles | 1.83 |
P10 cycles | 1.50 |
P11 cycles | 1.67 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 10.00 |
Nb uops | 10.00 |
Nb loads | NA |
Nb stores | 1.00 |
Nb stack references | 0.00 |
FLOP/cycle | 1.09 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 1.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 21.82 |
Bytes prefetched | 0.00 |
Bytes loaded | 32.00 |
Bytes stored | 8.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 25.00 |
Vector-efficiency ratio load | 25.00 |
Vector-efficiency ratio store | 25.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Path / |
Function | .omp_outlined.#0x4a1a00 |
Source file and lines | csr_matop.c:272-298 |
Module | exec |
nb instructions | 10 |
loop length | 40 |
nb stack references | 0 |
front end | 1.25 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.00 | 1.00 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 | 1.83 | 1.50 | 1.67 | 0.00 | 0.00 |
cycles | 1.00 | 1.00 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 | 1.83 | 1.50 | 1.67 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 1.25 |
Overall L1 | 1.83 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LDR D0, [X14, X18,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDR X4, [X22] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X6, [X23] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
B 4a1f58 <.omp_outlined.+0x558> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR D2, [X4, X24,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
FMADD D1, D0, D1, D2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
STR D1, [X4, X24,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
ADD X3, X3, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X3, X5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 4a1f04 <.omp_outlined.+0x504> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Function | .omp_outlined.#0x4a1a00 |
Source file and lines | csr_matop.c:272-298 |
Module | exec |
nb instructions | 10 |
loop length | 40 |
nb stack references | 0 |
front end | 1.25 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.00 | 1.00 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 | 1.83 | 1.50 | 1.67 | 0.00 | 0.00 |
cycles | 1.00 | 1.00 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 | 0.50 | 1.83 | 1.50 | 1.67 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 1.25 |
Overall L1 | 1.83 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LDR D0, [X14, X18,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDR X4, [X22] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X6, [X23] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
B 4a1f58 <.omp_outlined.+0x558> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR D2, [X4, X24,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
FMADD D1, D0, D1, D2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
STR D1, [X4, X24,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
ADD X3, X3, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X3, X5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 4a1f04 <.omp_outlined.+0x504> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |