Loop Id: 1462 | Module: exec | Source: par_interp.c:3180-3191 | Coverage: 0.06% |
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Loop Id: 1462 | Module: exec | Source: par_interp.c:3180-3191 | Coverage: 0.06% |
---|
(1461) 0x42de88 ORR X0, XZR, X21 |
(1461) 0x42de8c ORR X1, XZR, X20 |
(1461) 0x42de90 ORR X2, XZR, X22 |
(1461) 0x42de94 ORR X3, XZR, X23 |
(1461) 0x42de98 BL 4ae6e0 |
(1461) 0x42de9c ORR X0, XZR, X21 |
(1461) 0x42dea0 ORR X1, XZR, X20 |
(1461) 0x42dea4 SUB X3, X23, #1 |
(1461) 0x42dea8 ORR X2, XZR, X22 |
(1461) 0x42deac BL 42de50 |
(1461) 0x42deb0 ADD X22, X23, #1 |
(1461) 0x42deb4 CMP X22, X19 |
(1461) 0x42deb8 B.GE 42df44 |
(1461) 0x42debc ADD X8, X22, X19 |
(1461) 0x42dec0 ORR X0, XZR, X21 |
(1461) 0x42dec4 CMP X8, #0 |
(1461) 0x42dec8 ORR X1, XZR, X20 |
(1461) 0x42decc ORR X2, XZR, X22 |
(1461) 0x42ded0 CSINC X8, X8, X8, #10 |
(1461) 0x42ded4 SBFM X3, X8, #1, #63 |
(1461) 0x42ded8 BL 4ae6e0 |
(1461) 0x42dedc ORR X23, XZR, X22 |
(1461) 0x42dee0 CMP X22, X19 |
(1461) 0x42dee4 B.GE 42de88 |
0x42dee8 ORR X23, XZR, X22 |
0x42deec ADD X24, X22, #1 |
0x42def0 B 42df10 |
0x42df00 ADD X24, X24, #1 |
0x42df04 ADD X8, X25, X24 |
0x42df08 CMP X8, #1 |
0x42df0c B.EQ 42de88 |
0x42df10 LDR D0, [X20, X24,LSL #3] |
0x42df14 LDR D1, [X20, X22,LSL #3] |
0x42df18 FABS D0, D0 |
0x42df1c FABS D1, D1 |
0x42df20 FCMP D0, D1 |
0x42df24 B.LE 42df00 |
0x42df28 ADD X23, X23, #1 |
0x42df2c ORR X0, XZR, X21 |
0x42df30 ORR X1, XZR, X20 |
0x42df34 ORR X3, XZR, X24 |
0x42df38 ORR X2, XZR, X23 |
0x42df3c BL 4ae6e0 |
0x42df40 B 42df00 |
/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_interp.c: 3180 - 3191 |
-------------------------------------------------------------------------------- |
3180: if (left >= right) |
3181: return; |
3182: hypre_swap2( v, w, left, (left+right)/2); |
3183: last = left; |
3184: for (i = left+1; i <= right; i++) |
3185: if (fabs(w[i]) > fabs(w[left])) |
3186: { |
3187: hypre_swap2(v, w, ++last, i); |
3188: } |
3189: hypre_swap2(v, w, left, last); |
3190: hypre_qsort2abs(v, w, left, last-1); |
3191: hypre_qsort2abs(v, w, last+1, right); |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►50.00+ | hypre_qsort2abs | par_interp.c:3191 | exec |
○ | hypre_qsort2abs | par_interp.c:3191 | exec |
○ | .omp_outlined..46 | par_interp.c:2912 | exec |
○ | __kmp_invoke_microtask | libomp.so | |
►50.00+ | .omp_outlined..46 | par_interp.c:2912 | exec |
○ | __kmp_invoke_microtask | libomp.so |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 4.12 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.10 |
Bottlenecks | P2, P3, P4, P5, |
Function | hypre_qsort2abs |
Source | par_interp.c:3184-3187 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 2.75 |
CQA cycles if no scalar integer | 0.67 |
CQA cycles if FP arith vectorized | 2.75 |
CQA cycles if fully vectorized | 0.69 |
Front-end cycles | 2.50 |
DIV/SQRT cycles | 2.50 |
P0 cycles | 2.50 |
P1 cycles | 2.75 |
P2 cycles | 2.75 |
P3 cycles | 2.75 |
P4 cycles | 2.75 |
P5 cycles | 1.00 |
P6 cycles | 0.75 |
P7 cycles | 0.75 |
P8 cycles | 0.50 |
P9 cycles | 0.67 |
P10 cycles | 0.67 |
P11 cycles | 0.67 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 20.00 |
Nb uops | 20.00 |
Nb loads | NA |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 5.82 |
Bytes prefetched | 0.00 |
Bytes loaded | 16.00 |
Bytes stored | 0.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 25.00 |
Vector-efficiency ratio load | 25.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 25.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 25.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 4.12 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.10 |
Bottlenecks | P2, P3, P4, P5, |
Function | hypre_qsort2abs |
Source | par_interp.c:3184-3187 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 2.75 |
CQA cycles if no scalar integer | 0.67 |
CQA cycles if FP arith vectorized | 2.75 |
CQA cycles if fully vectorized | 0.69 |
Front-end cycles | 2.50 |
DIV/SQRT cycles | 2.50 |
P0 cycles | 2.50 |
P1 cycles | 2.75 |
P2 cycles | 2.75 |
P3 cycles | 2.75 |
P4 cycles | 2.75 |
P5 cycles | 1.00 |
P6 cycles | 0.75 |
P7 cycles | 0.75 |
P8 cycles | 0.50 |
P9 cycles | 0.67 |
P10 cycles | 0.67 |
P11 cycles | 0.67 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 20.00 |
Nb uops | 20.00 |
Nb loads | NA |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 5.82 |
Bytes prefetched | 0.00 |
Bytes loaded | 16.00 |
Bytes stored | 0.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 25.00 |
Vector-efficiency ratio load | 25.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 25.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 25.00 |
Path / |
Function | hypre_qsort2abs |
Source file and lines | par_interp.c:3180-3191 |
Module | exec |
nb instructions | 20 |
loop length | 80 |
nb stack references | 0 |
front end | 2.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 2.50 | 2.75 | 2.75 | 2.75 | 2.75 | 1.00 | 0.75 | 0.75 | 0.50 | 0.67 | 0.67 | 0.67 | 0.00 | 0.00 |
cycles | 2.50 | 2.50 | 2.75 | 2.75 | 2.75 | 2.75 | 1.00 | 0.75 | 0.75 | 0.50 | 0.67 | 0.67 | 0.67 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 2.50 |
Overall L1 | 2.75 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ORR X23, XZR, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X24, X22, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
B 42df10 <hypre_qsort2abs+0xc0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD X24, X24, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X8, X25, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 42de88 <hypre_qsort2abs+0x38> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR D0, [X20, X24,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDR D1, [X20, X22,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
FABS D0, D0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
FABS D1, D1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
FCMP D0, D1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
B.LE 42df00 <hypre_qsort2abs+0xb0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD X23, X23, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X0, XZR, X21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X1, XZR, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X3, XZR, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X2, XZR, X23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 4ae6e0 <hypre_swap2> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
B 42df00 <hypre_qsort2abs+0xb0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Function | hypre_qsort2abs |
Source file and lines | par_interp.c:3180-3191 |
Module | exec |
nb instructions | 20 |
loop length | 80 |
nb stack references | 0 |
front end | 2.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 2.50 | 2.75 | 2.75 | 2.75 | 2.75 | 1.00 | 0.75 | 0.75 | 0.50 | 0.67 | 0.67 | 0.67 | 0.00 | 0.00 |
cycles | 2.50 | 2.50 | 2.75 | 2.75 | 2.75 | 2.75 | 1.00 | 0.75 | 0.75 | 0.50 | 0.67 | 0.67 | 0.67 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 2.50 |
Overall L1 | 2.75 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ORR X23, XZR, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X24, X22, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
B 42df10 <hypre_qsort2abs+0xc0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD X24, X24, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X8, X25, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 42de88 <hypre_qsort2abs+0x38> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR D0, [X20, X24,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDR D1, [X20, X22,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
FABS D0, D0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
FABS D1, D1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
FCMP D0, D1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
B.LE 42df00 <hypre_qsort2abs+0xb0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD X23, X23, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X0, XZR, X21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X1, XZR, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X3, XZR, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X2, XZR, X23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 4ae6e0 <hypre_swap2> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
B 42df00 <hypre_qsort2abs+0xb0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |