Function: hypre_qsort2abs | Module: exec | Source: par_interp.c:3180-3192 | Coverage: 0.06% |
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Function: hypre_qsort2abs | Module: exec | Source: par_interp.c:3180-3192 | Coverage: 0.06% |
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/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_interp.c: 3180 - 3192 |
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3180: if (left >= right) |
3181: return; |
3182: hypre_swap2( v, w, left, (left+right)/2); |
3183: last = left; |
3184: for (i = left+1; i <= right; i++) |
3185: if (fabs(w[i]) > fabs(w[left])) |
3186: { |
3187: hypre_swap2(v, w, ++last, i); |
3188: } |
3189: hypre_swap2(v, w, left, last); |
3190: hypre_qsort2abs(v, w, left, last-1); |
3191: hypre_qsort2abs(v, w, last+1, right); |
3192: } |
0x42dd10 CMP X2, X3 |
0x42dd14 B.GE 42de18 |
0x42dd18 STP X29, X30, [SP, #944]! |
0x42dd1c STR X25, [SP, #16] |
0x42dd20 STP X24, X23, [SP, #32] |
0x42dd24 STP X22, X21, [SP, #48] |
0x42dd28 STP X20, X19, [SP, #64] |
0x42dd2c ADD X29, SP, #0 |
0x42dd30 ORR X19, XZR, X3 |
0x42dd34 ORR X22, XZR, X2 |
0x42dd38 ORR X20, XZR, X1 |
0x42dd3c ORR X21, XZR, X0 |
0x42dd40 SUB X25, XZR, X3 |
0x42dd44 B 42dd7c |
(1493) 0x42dd48 ORR X0, XZR, X21 |
(1493) 0x42dd4c ORR X1, XZR, X20 |
(1493) 0x42dd50 ORR X2, XZR, X22 |
(1493) 0x42dd54 ORR X3, XZR, X23 |
(1493) 0x42dd58 BL 4b29c0 |
(1493) 0x42dd5c ORR X0, XZR, X21 |
(1493) 0x42dd60 ORR X1, XZR, X20 |
(1493) 0x42dd64 SUB X3, X23, #1 |
(1493) 0x42dd68 ORR X2, XZR, X22 |
(1493) 0x42dd6c BL 42dd10 |
(1493) 0x42dd70 ADD X22, X23, #1 |
(1493) 0x42dd74 CMP X22, X19 |
(1493) 0x42dd78 B.GE 42de04 |
(1493) 0x42dd7c ADD X8, X22, X19 |
(1493) 0x42dd80 ORR X0, XZR, X21 |
(1493) 0x42dd84 CMP X8, #0 |
(1493) 0x42dd88 ORR X1, XZR, X20 |
(1493) 0x42dd8c ORR X2, XZR, X22 |
(1493) 0x42dd90 CSINC X8, X8, X8, #10 |
(1493) 0x42dd94 SBFM X3, X8, #1, #63 |
(1493) 0x42dd98 BL 4b29c0 |
(1493) 0x42dd9c ORR X23, XZR, X22 |
(1493) 0x42dda0 CMP X22, X19 |
(1493) 0x42dda4 B.GE 42dd48 |
(1494) 0x42dda8 ORR X23, XZR, X22 |
(1494) 0x42ddac ADD X24, X22, #1 |
(1494) 0x42ddb0 B 42ddd0 |
0x42ddb4 HINT #0 |
0x42ddb8 HINT #0 |
0x42ddbc HINT #0 |
(1494) 0x42ddc0 ADD X24, X24, #1 |
(1494) 0x42ddc4 ADD X8, X25, X24 |
(1494) 0x42ddc8 CMP X8, #1 |
(1494) 0x42ddcc B.EQ 42dd48 |
(1494) 0x42ddd0 LDR D0, [X20, X24,LSL #3] |
(1494) 0x42ddd4 LDR D1, [X20, X22,LSL #3] |
(1494) 0x42ddd8 FABS D0, D0 |
(1494) 0x42dddc FABS D1, D1 |
(1494) 0x42dde0 FCMP D0, D1 |
(1494) 0x42dde4 B.LE 42ddc0 |
(1494) 0x42dde8 ADD X23, X23, #1 |
(1494) 0x42ddec ORR X0, XZR, X21 |
(1494) 0x42ddf0 ORR X1, XZR, X20 |
(1494) 0x42ddf4 ORR X3, XZR, X24 |
(1494) 0x42ddf8 ORR X2, XZR, X23 |
(1494) 0x42ddfc BL 4b29c0 |
(1494) 0x42de00 B 42ddc0 |
0x42de04 LDP X20, X19, [SP, #64] |
0x42de08 LDP X22, X21, [SP, #48] |
0x42de0c LDP X24, X23, [SP, #32] |
0x42de10 LDR X25, [SP, #16] |
0x42de14 LDP X29, X30, [SP], #80 |
0x42de18 RET |
0x42de1c HINT #0 |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►50.00+ | .omp_outlined..46 | par_interp.c:2912 | exec |
○ | __kmp_invoke_microtask | libomp.so | |
►50.00+ | hypre_qsort2abs | par_interp.c:3191 | exec |
○ | .omp_outlined..46 | par_interp.c:2912 | exec |
○ | __kmp_invoke_microtask | libomp.so |
Path / |
Source file and lines | par_interp.c:3180-3192 |
Module | exec |
nb instructions | 24 |
loop length | 96 |
nb stack references | 0 |
front end | 2.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.50 | 1.50 | 2.00 | 2.00 | 2.00 | 2.00 | 0.00 | 0.00 | 0.00 | 0.00 | 3.50 | 3.17 | 3.33 | 2.50 | 2.50 |
cycles | 1.50 | 1.50 | 2.00 | 2.00 | 2.00 | 2.00 | 0.00 | 0.00 | 0.00 | 0.00 | 3.50 | 3.17 | 3.33 | 2.50 | 2.50 |
Cycles executing div or sqrt instructions | NA |
Front-end | 2.50 |
Overall L1 | 3.50 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CMP X2, X3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 42de18 <hypre_qsort2abs+0x108> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
STP X29, X30, [SP, #944]! | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X25, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X24, X23, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X22, X21, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X20, X19, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X19, XZR, X3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X22, XZR, X2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X20, XZR, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X21, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X25, XZR, X3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
B 42dd7c <hypre_qsort2abs+0x6c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
LDP X20, X19, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X22, X21, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X24, X23, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDR X25, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDP X29, X30, [SP], #80 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
RET | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 |
Source file and lines | par_interp.c:3180-3192 |
Module | exec |
nb instructions | 24 |
loop length | 96 |
nb stack references | 0 |
front end | 2.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.50 | 1.50 | 2.00 | 2.00 | 2.00 | 2.00 | 0.00 | 0.00 | 0.00 | 0.00 | 3.50 | 3.17 | 3.33 | 2.50 | 2.50 |
cycles | 1.50 | 1.50 | 2.00 | 2.00 | 2.00 | 2.00 | 0.00 | 0.00 | 0.00 | 0.00 | 3.50 | 3.17 | 3.33 | 2.50 | 2.50 |
Cycles executing div or sqrt instructions | NA |
Front-end | 2.50 |
Overall L1 | 3.50 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CMP X2, X3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 42de18 <hypre_qsort2abs+0x108> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
STP X29, X30, [SP, #944]! | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X25, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X24, X23, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X22, X21, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X20, X19, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X19, XZR, X3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X22, XZR, X2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X20, XZR, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X21, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X25, XZR, X3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
B 42dd7c <hypre_qsort2abs+0x6c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
LDP X20, X19, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X22, X21, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X24, X23, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDR X25, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDP X29, X30, [SP], #80 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
RET | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_qsort2abs– | 0.06 | 0.01 |
▼Loop 1494 - par_interp.c:3180-3191 - exec– | 0.03 | 0 |
○Loop 1493 - par_interp.c:3180-3191 - exec | 0 | 0 |