Loop Id: 1737 | Module: exec | Source: csr_matop.c:540-548 | Coverage: 0.06% |
---|
Loop Id: 1737 | Module: exec | Source: csr_matop.c:540-548 | Coverage: 0.06% |
---|
(1738) 0x4a6ba0 ORR X14, XZR, X15 |
(1738) 0x4a6ba4 CMP X22, X21 |
(1738) 0x4a6ba8 B.LE 4a6c9c |
(1738) 0x4a6bac SUB X22, X22, #1 |
(1738) 0x4a6bb0 LDR X15, [X8, X22,LSL #3] |
(1738) 0x4a6bb4 CMP X14, X15 |
(1738) 0x4a6bb8 B.LE 4a6ba0 |
0x4a6bbc HINT #0 |
0x4a6bc0 LDR X15, [X13, X14,LSL #3] |
0x4a6bc4 LDR X16, [X19] |
0x4a6bc8 LDR D0, [X12, X14,LSL #3] |
0x4a6bcc SUB X14, X14, #1 |
0x4a6bd0 MADD X16, X20, X16, X15 |
0x4a6bd4 LDR X17, [X9, X16,LSL #3] |
0x4a6bd8 SUB X17, X17, #1 |
0x4a6bdc STR X17, [X9, X16,LSL #3] |
0x4a6be0 LDR X16, [X19] |
0x4a6be4 MADD X15, X20, X16, X15 |
0x4a6be8 LDR X15, [X9, X15,LSL #3] |
0x4a6bec STR D0, [X10, X15,LSL #3] |
0x4a6bf0 STR X22, [X11, X15,LSL #3] |
0x4a6bf4 LDR X15, [X8, X22,LSL #3] |
0x4a6bf8 CMP X14, X15 |
0x4a6bfc B.GT 4a6bc0 |
0x4a6c00 B 4a6ba0 |
/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c: 540 - 548 |
-------------------------------------------------------------------------------- |
540: for (i = iEnd - 1; i >= iBegin; --i) { |
541: for (j = A_i[i + 1] - 1; j >= A_i[i]; --j) { |
542: HYPRE_Int idx = A_j[j]; |
543: --bucket[my_thread_num*num_colsA + idx]; |
544: |
545: HYPRE_Int offset = bucket[my_thread_num*num_colsA + idx]; |
546: |
547: AT_data[offset] = A_data[j]; |
548: AT_j[offset] = i; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○100.00 | __kmp_invoke_microtask | libomp.so |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.91 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.05 |
Bottlenecks | P10, |
Function | .omp_outlined..7#0x4a67e0 |
Source | csr_matop.c:541-548 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 3.50 |
CQA cycles if no scalar integer | 1.83 |
CQA cycles if FP arith vectorized | 3.50 |
CQA cycles if fully vectorized | 0.88 |
Front-end cycles | 2.13 |
DIV/SQRT cycles | 1.00 |
P0 cycles | 1.00 |
P1 cycles | 1.00 |
P2 cycles | 1.00 |
P3 cycles | 2.00 |
P4 cycles | 1.00 |
P5 cycles | 0.50 |
P6 cycles | 0.50 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 3.50 |
P10 cycles | 3.17 |
P11 cycles | 3.33 |
P12 cycles | 1.00 |
P13 cycles | 1.00 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 18.00 |
Nb uops | 17.00 |
Nb loads | NA |
Nb stores | 3.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 22.86 |
Bytes prefetched | 0.00 |
Bytes loaded | 56.00 |
Bytes stored | 24.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 25.00 |
Vector-efficiency ratio load | 25.00 |
Vector-efficiency ratio store | 25.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 25.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.91 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.05 |
Bottlenecks | P10, |
Function | .omp_outlined..7#0x4a67e0 |
Source | csr_matop.c:541-548 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 3.50 |
CQA cycles if no scalar integer | 1.83 |
CQA cycles if FP arith vectorized | 3.50 |
CQA cycles if fully vectorized | 0.88 |
Front-end cycles | 2.13 |
DIV/SQRT cycles | 1.00 |
P0 cycles | 1.00 |
P1 cycles | 1.00 |
P2 cycles | 1.00 |
P3 cycles | 2.00 |
P4 cycles | 1.00 |
P5 cycles | 0.50 |
P6 cycles | 0.50 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 3.50 |
P10 cycles | 3.17 |
P11 cycles | 3.33 |
P12 cycles | 1.00 |
P13 cycles | 1.00 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 18.00 |
Nb uops | 17.00 |
Nb loads | NA |
Nb stores | 3.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 22.86 |
Bytes prefetched | 0.00 |
Bytes loaded | 56.00 |
Bytes stored | 24.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 25.00 |
Vector-efficiency ratio load | 25.00 |
Vector-efficiency ratio store | 25.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 25.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Path / |
Function | .omp_outlined..7#0x4a67e0 |
Source file and lines | csr_matop.c:540-548 |
Module | exec |
nb instructions | 18 |
loop length | 72 |
nb stack references | 0 |
front end | 2.13 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.00 | 1.00 | 1.00 | 1.00 | 2.00 | 1.00 | 0.50 | 0.50 | 0.00 | 0.00 | 3.50 | 3.17 | 3.33 | 1.00 | 1.00 |
cycles | 1.00 | 1.00 | 1.00 | 1.00 | 2.00 | 1.00 | 0.50 | 0.50 | 0.00 | 0.00 | 3.50 | 3.17 | 3.33 | 1.00 | 1.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 2.13 |
Overall L1 | 3.50 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HINT #0 | ||||||||||||||||||
LDR X15, [X13, X14,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X16, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR D0, [X12, X14,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
SUB X14, X14, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MADD X16, X20, X16, X15 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
LDR X17, [X9, X16,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUB X17, X17, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X17, [X9, X16,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X16, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
MADD X15, X20, X16, X15 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
LDR X15, [X9, X15,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STR D0, [X10, X15,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STR X22, [X11, X15,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X15, [X8, X22,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X14, X15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GT 4a6bc0 <.omp_outlined..7+0x3e0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
B 4a6ba0 <.omp_outlined..7+0x3c0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Function | .omp_outlined..7#0x4a67e0 |
Source file and lines | csr_matop.c:540-548 |
Module | exec |
nb instructions | 18 |
loop length | 72 |
nb stack references | 0 |
front end | 2.13 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.00 | 1.00 | 1.00 | 1.00 | 2.00 | 1.00 | 0.50 | 0.50 | 0.00 | 0.00 | 3.50 | 3.17 | 3.33 | 1.00 | 1.00 |
cycles | 1.00 | 1.00 | 1.00 | 1.00 | 2.00 | 1.00 | 0.50 | 0.50 | 0.00 | 0.00 | 3.50 | 3.17 | 3.33 | 1.00 | 1.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 2.13 |
Overall L1 | 3.50 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HINT #0 | ||||||||||||||||||
LDR X15, [X13, X14,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X16, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR D0, [X12, X14,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
SUB X14, X14, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MADD X16, X20, X16, X15 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
LDR X17, [X9, X16,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUB X17, X17, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X17, [X9, X16,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X16, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
MADD X15, X20, X16, X15 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
LDR X15, [X9, X15,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STR D0, [X10, X15,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STR X22, [X11, X15,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X15, [X8, X22,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X14, X15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GT 4a6bc0 <.omp_outlined..7+0x3e0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
B 4a6ba0 <.omp_outlined..7+0x3c0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |