Loop Id: 2978 | Module: exec | Source: par_csr_matop.c:937-989 [...] | Coverage: 1.52% |
---|
Loop Id: 2978 | Module: exec | Source: par_csr_matop.c:937-989 [...] | Coverage: 1.52% |
---|
0x4c6350 LDR X17, [X28, X15,LSL #3] |
0x4c6354 LDR D17, [X30, X15,LSL #3] |
0x4c6358 UBFM X8, X17, #61, #60 |
0x4c635c LDR X2, [X27, X17,LSL #3] |
0x4c6360 ADD X7, X8, #8 |
0x4c6364 LDR X6, [X27, X7] |
0x4c6368 ADD X8, X27, X7 |
0x4c636c CMP X2, X6 |
0x4c6370 B.GE 4c63b0 |
0x4c6374 HINT #0 |
0x4c6378 HINT #0 |
0x4c637c HINT #0 |
(2981) 0x4c6380 LDR X4, [X21, X2,LSL #3] |
(2981) 0x4c6384 LDR D18, [X22, X2,LSL #3] |
(2981) 0x4c6388 LDR X5, [X0, X4,LSL #3] |
(2981) 0x4c638c FMUL D19, D17, D18 |
(2981) 0x4c6390 CMP X20, X5 |
(2981) 0x4c6394 B.GT 4c64fc |
(2981) 0x4c6398 LDR D20, [X19, X5,LSL #3] |
(2981) 0x4c639c ADD X2, X2, #1 |
(2981) 0x4c63a0 FADD D21, D20, D19 |
(2981) 0x4c63a4 STR D21, [X19, X5,LSL #3] |
(2981) 0x4c63a8 CMP X6, X2 |
(2981) 0x4c63ac B.GT 4c6380 |
0x4c63b0 CBNZ X18, 4c6520 |
0x4c63b4 LDR X17, [X16, #8] |
0x4c63b8 ADD X15, X15, #1 |
0x4c63bc CMP X17, X15 |
0x4c63c0 B.GT 4c6350 |
(2981) 0x4c64fc STR X1, [X0, X4,LSL #3] |
(2981) 0x4c6500 ADD X2, X2, #1 |
(2981) 0x4c6504 STR D19, [X19, X1,LSL #3] |
(2981) 0x4c6508 STR X4, [X24, X1,LSL #3] |
(2981) 0x4c650c ADD X1, X1, #1 |
(2981) 0x4c6510 LDR X6, [X8] |
(2981) 0x4c6514 CMP X2, X6 |
(2981) 0x4c6518 B.LT 4c6380 |
0x4c651c CBZ X18, 4c63b4 |
0x4c6520 LDR X2, [X9, X17,LSL #3] |
0x4c6524 ADD X17, X9, X7 |
0x4c6528 LDR X7, [X9, X7] |
0x4c652c CMP X2, X7 |
0x4c6530 B.GE 4c63b4 |
0x4c6534 HINT #0 |
0x4c6538 HINT #0 |
0x4c653c HINT #0 |
(2979) 0x4c6540 LDR X8, [X13, X2,LSL #3] |
(2979) 0x4c6544 LDR D22, [X14, X2,LSL #3] |
(2979) 0x4c6548 LDR X5, [X12, X8,LSL #3] |
(2979) 0x4c654c FMUL D23, D17, D22 |
(2979) 0x4c6550 ADD X6, X26, X5 |
(2979) 0x4c6554 LDR X4, [X0, X6,LSL #3] |
(2979) 0x4c6558 CMP X25, X4 |
(2979) 0x4c655c B.GT 4c6598 |
(2980) 0x4c6560 LDR D24, [X23, X4,LSL #3] |
(2980) 0x4c6564 ADD X2, X2, #1 |
(2980) 0x4c6568 FADD D25, D24, D23 |
(2980) 0x4c656c STR D25, [X23, X4,LSL #3] |
(2980) 0x4c6570 CMP X7, X2 |
(2980) 0x4c6574 B.LE 4c63b4 |
(2980) 0x4c6578 LDR X8, [X13, X2,LSL #3] |
(2980) 0x4c657c LDR D22, [X14, X2,LSL #3] |
(2980) 0x4c6580 LDR X5, [X12, X8,LSL #3] |
(2980) 0x4c6584 FMUL D23, D17, D22 |
(2980) 0x4c6588 ADD X6, X26, X5 |
(2980) 0x4c658c LDR X4, [X0, X6,LSL #3] |
(2980) 0x4c6590 CMP X25, X4 |
(2980) 0x4c6594 B.LE 4c6560 |
(2979) 0x4c6598 STR X3, [X0, X6,LSL #3] |
(2979) 0x4c659c ADD X2, X2, #1 |
(2979) 0x4c65a0 STR D23, [X23, X3,LSL #3] |
(2979) 0x4c65a4 STR X5, [X11, X3,LSL #3] |
(2979) 0x4c65a8 ADD X3, X3, #1 |
(2979) 0x4c65ac LDR X7, [X17] |
(2979) 0x4c65b0 CMP X2, X7 |
(2979) 0x4c65b4 B.LT 4c6540 |
0x4c65b8 B 4c63b4 |
/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 937 - 989 |
-------------------------------------------------------------------------------- |
937: for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++) |
938: { |
939: i2 = A_diag_j[jj2]; |
940: a_entry = A_diag_data[jj2]; |
[...] |
946: for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++) |
947: { |
948: i3 = B_diag_j[jj3]; |
[...] |
956: if (B_marker[i3] < jj_row_begin_diag) |
957: { |
958: B_marker[i3] = jj_count_diag; |
959: C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3]; |
960: C_diag_j[jj_count_diag] = i3; |
961: jj_count_diag++; |
962: } |
963: else |
964: { |
965: C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3]; |
966: } |
967: } |
968: if (num_cols_offd_B) |
969: { |
970: for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++) |
971: { |
972: i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]]; |
[...] |
980: if (B_marker[i3] < jj_row_begin_offd) |
981: { |
982: B_marker[i3] = jj_count_offd; |
983: C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3]; |
984: C_offd_j[jj_count_offd] = i3-num_cols_diag_B; |
985: jj_count_offd++; |
986: } |
987: else |
988: { |
989: C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3]; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | GOMP_parallel | libomp.so | |
○ | hypre_ParMatmul | par_csr_matop.c:998 | exec |
○ | hypre_BoomerAMGSetup | par_amg_setup.c:1227 | exec |
○ | hypre_PCGSetup | pcg.c:234 | exec |
○ | main | amg.c:398 | exec |
○ | __libc_start_main | libc-2.31.so | |
○ | _start | amg.c:599 | exec |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.25 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.14 |
Bottlenecks | P0, P1, |
Function | hypre_ParMatmul._omp_fn.3 |
Source | par_csr_matop.c:937-937,par_csr_matop.c:940-940,par_csr_matop.c:946-946,par_csr_matop.c:968-970 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 3.00 |
CQA cycles if no scalar integer | 1.33 |
CQA cycles if FP arith vectorized | 3.00 |
CQA cycles if fully vectorized | 0.75 |
Front-end cycles | 2.63 |
DIV/SQRT cycles | 3.00 |
P0 cycles | 3.00 |
P1 cycles | 2.00 |
P2 cycles | 2.00 |
P3 cycles | 2.00 |
P4 cycles | 2.00 |
P5 cycles | 0.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 2.33 |
P10 cycles | 2.33 |
P11 cycles | 2.33 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 27.00 |
Nb uops | 21.00 |
Nb loads | NA |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 18.67 |
Bytes prefetched | 0.00 |
Bytes loaded | 56.00 |
Bytes stored | 0.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 25.00 |
Vector-efficiency ratio load | 25.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 25.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 25.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.25 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.14 |
Bottlenecks | P0, P1, |
Function | hypre_ParMatmul._omp_fn.3 |
Source | par_csr_matop.c:937-937,par_csr_matop.c:940-940,par_csr_matop.c:946-946,par_csr_matop.c:968-970 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 3.00 |
CQA cycles if no scalar integer | 1.33 |
CQA cycles if FP arith vectorized | 3.00 |
CQA cycles if fully vectorized | 0.75 |
Front-end cycles | 2.63 |
DIV/SQRT cycles | 3.00 |
P0 cycles | 3.00 |
P1 cycles | 2.00 |
P2 cycles | 2.00 |
P3 cycles | 2.00 |
P4 cycles | 2.00 |
P5 cycles | 0.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 2.33 |
P10 cycles | 2.33 |
P11 cycles | 2.33 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 27.00 |
Nb uops | 21.00 |
Nb loads | NA |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 18.67 |
Bytes prefetched | 0.00 |
Bytes loaded | 56.00 |
Bytes stored | 0.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 25.00 |
Vector-efficiency ratio load | 25.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 25.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 25.00 |
Path / |
Function | hypre_ParMatmul._omp_fn.3 |
Source file and lines | par_csr_matop.c:937-989 |
Module | exec |
nb instructions | 27 |
loop length | 108 |
nb stack references | 0 |
front end | 2.63 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.00 | 3.00 | 2.00 | 2.00 | 2.00 | 2.00 | 0.00 | 0.00 | 0.00 | 0.00 | 2.33 | 2.33 | 2.33 | 0.00 | 0.00 |
cycles | 3.00 | 3.00 | 2.00 | 2.00 | 2.00 | 2.00 | 0.00 | 0.00 | 0.00 | 0.00 | 2.33 | 2.33 | 2.33 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 2.63 |
Overall L1 | 3.00 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LDR X17, [X28, X15,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR D17, [X30, X15,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
UBFM X8, X17, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X2, [X27, X17,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X7, X8, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X6, [X27, X7] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X8, X27, X7 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X2, X6 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 4c63b0 <hypre_ParMatmul._omp_fn.3+0x200> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
CBNZ X18, 4c6520 <hypre_ParMatmul._omp_fn.3+0x370> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X17, [X16, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X15, X15, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X17, X15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GT 4c6350 <hypre_ParMatmul._omp_fn.3+0x1a0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CBZ X18, 4c63b4 <hypre_ParMatmul._omp_fn.3+0x204> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X2, [X9, X17,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X17, X9, X7 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X7, [X9, X7] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X2, X7 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 4c63b4 <hypre_ParMatmul._omp_fn.3+0x204> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
B 4c63b4 <hypre_ParMatmul._omp_fn.3+0x204> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Function | hypre_ParMatmul._omp_fn.3 |
Source file and lines | par_csr_matop.c:937-989 |
Module | exec |
nb instructions | 27 |
loop length | 108 |
nb stack references | 0 |
front end | 2.63 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.00 | 3.00 | 2.00 | 2.00 | 2.00 | 2.00 | 0.00 | 0.00 | 0.00 | 0.00 | 2.33 | 2.33 | 2.33 | 0.00 | 0.00 |
cycles | 3.00 | 3.00 | 2.00 | 2.00 | 2.00 | 2.00 | 0.00 | 0.00 | 0.00 | 0.00 | 2.33 | 2.33 | 2.33 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 2.63 |
Overall L1 | 3.00 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LDR X17, [X28, X15,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR D17, [X30, X15,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
UBFM X8, X17, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X2, [X27, X17,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X7, X8, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X6, [X27, X7] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X8, X27, X7 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X2, X6 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 4c63b0 <hypre_ParMatmul._omp_fn.3+0x200> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
CBNZ X18, 4c6520 <hypre_ParMatmul._omp_fn.3+0x370> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X17, [X16, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X15, X15, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X17, X15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GT 4c6350 <hypre_ParMatmul._omp_fn.3+0x1a0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CBZ X18, 4c63b4 <hypre_ParMatmul._omp_fn.3+0x204> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X2, [X9, X17,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X17, X9, X7 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X7, [X9, X7] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X2, X7 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 4c63b4 <hypre_ParMatmul._omp_fn.3+0x204> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
B 4c63b4 <hypre_ParMatmul._omp_fn.3+0x204> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |