Loop Id: 1122 | Module: exec | Source: par_strength.c:2011-2048 | Coverage: 0.35% |
---|
Loop Id: 1122 | Module: exec | Source: par_strength.c:2011-2048 | Coverage: 0.35% |
---|
0x46b0a4 LDR X7, [X9, X0,LSL #3] |
0x46b0a8 ADD X2, X2, #1 |
0x46b0ac CMP X2, X7 |
0x46b0b0 B.GE 46b200 |
0x46b0b4 LDR X19, [X10, X2,LSL #3] |
0x46b0b8 LDR X7, [X11, X19,LSL #3] |
0x46b0bc CMP X7, #1 |
0x46b0c0 B.LT 46b0f0 |
0x46b0c4 LDR X7, [X3, X19,LSL #3] |
0x46b0c8 LDR X20, [X24, X7,LSL #3] |
0x46b0cc CMP X20, X17 |
0x46b0d0 B.GE 46b0f0 |
0x46b0d4 LDUR X20, [X29, #480] |
0x46b0d8 STR X20, [X24, X7,LSL #3] |
0x46b0dc LDUR X20, [X29, #480] |
0x46b0e0 STR X7, [X4, X20,LSL #3] |
0x46b0e4 LDUR X7, [X29, #480] |
0x46b0e8 ADD X7, X7, #1 |
0x46b0ec STUR X7, [X29, #480] |
0x46b0f0 ADD X7, X19, #1 |
0x46b0f4 LDR X20, [X9, X19,LSL #3] |
0x46b0f8 LDR X23, [X9, X7,LSL #3] |
0x46b0fc CMP X20, X23 |
0x46b100 B.GE 46b184 |
0x46b104 LDP X26, X21, [X29, #960] |
0x46b108 LDR X21, [X21] |
0x46b10c LDR X26, [X26] |
0x46b110 B 46b12c |
(1124) 0x46b120 ADD X20, X20, #1 |
(1124) 0x46b124 CMP X20, X23 |
(1124) 0x46b128 B.GE 46b180 |
(1124) 0x46b12c LDR X27, [X10, X20,LSL #3] |
(1124) 0x46b130 LDR X28, [X11, X27,LSL #3] |
(1124) 0x46b134 CMP X28, #1 |
(1124) 0x46b138 B.LT 46b120 |
(1124) 0x46b13c LDR X27, [X21, X27,LSL #3] |
(1124) 0x46b140 CMP X27, X22 |
(1124) 0x46b144 B.EQ 46b120 |
(1124) 0x46b148 LDR X28, [X24, X27,LSL #3] |
(1124) 0x46b14c CMP X28, X17 |
(1124) 0x46b150 B.GE 46b120 |
(1124) 0x46b154 LDUR X23, [X29, #480] |
(1124) 0x46b158 STR X23, [X24, X27,LSL #3] |
(1124) 0x46b15c LDUR X23, [X29, #480] |
(1124) 0x46b160 STR X27, [X26, X23,LSL #3] |
(1124) 0x46b164 LDUR X23, [X29, #480] |
(1124) 0x46b168 ADD X23, X23, #1 |
(1124) 0x46b16c STUR X23, [X29, #480] |
(1124) 0x46b170 LDR X23, [X9, X7,LSL #3] |
(1124) 0x46b174 B 46b120 |
0x46b180 LDUR X28, [X29, #432] |
0x46b184 LDR X19, [X12, X19,LSL #3] |
0x46b188 LDR X23, [X12, X7,LSL #3] |
0x46b18c CMP X19, X23 |
0x46b190 B.GE 46b0a4 |
0x46b194 LDUR X20, [X29, #464] |
0x46b198 LDR X21, [X28] |
0x46b19c LDR X20, [X20] |
0x46b1a0 B 46b1b0 |
(1123) 0x46b1a4 ADD X19, X19, #1 |
(1123) 0x46b1a8 CMP X19, X23 |
(1123) 0x46b1ac B.GE 46b0a4 |
(1123) 0x46b1b0 LDR X26, [X5, X19,LSL #3] |
(1123) 0x46b1b4 LDR X27, [X6, X26,LSL #3] |
(1123) 0x46b1b8 CMP X27, #1 |
(1123) 0x46b1bc B.LT 46b1a4 |
(1123) 0x46b1c0 LDR X26, [X20, X26,LSL #3] |
(1123) 0x46b1c4 LDR X27, [X25, X26,LSL #3] |
(1123) 0x46b1c8 CMP X27, X18 |
(1123) 0x46b1cc B.GE 46b1a4 |
(1123) 0x46b1d0 LDUR X23, [X29, #472] |
(1123) 0x46b1d4 STR X23, [X25, X26,LSL #3] |
(1123) 0x46b1d8 LDUR X23, [X29, #472] |
(1123) 0x46b1dc STR X26, [X21, X23,LSL #3] |
(1123) 0x46b1e0 LDUR X23, [X29, #472] |
(1123) 0x46b1e4 ADD X23, X23, #1 |
(1123) 0x46b1e8 STUR X23, [X29, #472] |
(1123) 0x46b1ec LDR X23, [X12, X7,LSL #3] |
(1123) 0x46b1f0 B 46b1a4 |
/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 2011 - 2048 |
-------------------------------------------------------------------------------- |
2011: for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++) |
2012: { |
2013: i2 = S_diag_j[jj1]; |
2014: if (CF_marker[i2] > 0) |
2015: { |
2016: index = fine_to_coarse[i2]; |
2017: if (S_marker[index] < jj_row_begin_diag) |
2018: { |
2019: S_marker[index] = num_nonzeros_diag; |
2020: C_diag_j[num_nonzeros_diag] = index; |
2021: num_nonzeros_diag++; |
2022: } |
2023: } |
2024: for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++) |
2025: { |
2026: i3 = S_diag_j[jj2]; |
2027: if (CF_marker[i3] > 0) |
2028: { |
2029: index = fine_to_coarse[i3]; |
2030: if (index != ic && S_marker[index] < jj_row_begin_diag) |
2031: { |
2032: S_marker[index] = num_nonzeros_diag; |
2033: C_diag_j[num_nonzeros_diag] = index; |
2034: num_nonzeros_diag++; |
2035: } |
2036: } |
2037: } |
2038: for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++) |
2039: { |
2040: i3 = S_offd_j[jj2]; |
2041: if (CF_marker_offd[i3] > 0) |
2042: { |
2043: index = map_S_to_C[i3]; |
2044: if (S_marker_offd[index] < jj_row_begin_offd) |
2045: { |
2046: S_marker_offd[index] = num_nonzeros_offd; |
2047: C_offd_j[num_nonzeros_offd] = index; |
2048: num_nonzeros_offd++; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○100.00 | __kmp_invoke_microtask | libomp.so |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.02 |
Bottlenecks | P10, |
Function | .omp_outlined..20#0x46a2b0 |
Source | par_strength.c:2011-2021,par_strength.c:2024-2024,par_strength.c:2038-2038 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 7.50 |
CQA cycles if no scalar integer | 7.50 |
CQA cycles if FP arith vectorized | 7.50 |
CQA cycles if fully vectorized | 1.88 |
Front-end cycles | 4.63 |
DIV/SQRT cycles | 3.50 |
P0 cycles | 3.50 |
P1 cycles | 2.00 |
P2 cycles | 2.00 |
P3 cycles | 2.00 |
P4 cycles | 2.00 |
P5 cycles | 0.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 7.50 |
P10 cycles | 7.17 |
P11 cycles | 7.33 |
P12 cycles | 1.50 |
P13 cycles | 1.50 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 37.00 |
Nb uops | 37.00 |
Nb loads | NA |
Nb stores | 3.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.53 |
Bytes prefetched | 0.00 |
Bytes loaded | 160.00 |
Bytes stored | 24.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 25.00 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 25.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.02 |
Bottlenecks | P10, |
Function | .omp_outlined..20#0x46a2b0 |
Source | par_strength.c:2011-2021,par_strength.c:2024-2024,par_strength.c:2038-2038 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 7.50 |
CQA cycles if no scalar integer | 7.50 |
CQA cycles if FP arith vectorized | 7.50 |
CQA cycles if fully vectorized | 1.88 |
Front-end cycles | 4.63 |
DIV/SQRT cycles | 3.50 |
P0 cycles | 3.50 |
P1 cycles | 2.00 |
P2 cycles | 2.00 |
P3 cycles | 2.00 |
P4 cycles | 2.00 |
P5 cycles | 0.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 7.50 |
P10 cycles | 7.17 |
P11 cycles | 7.33 |
P12 cycles | 1.50 |
P13 cycles | 1.50 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 37.00 |
Nb uops | 37.00 |
Nb loads | NA |
Nb stores | 3.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.53 |
Bytes prefetched | 0.00 |
Bytes loaded | 160.00 |
Bytes stored | 24.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 25.00 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 25.00 |
Path / |
Function | .omp_outlined..20#0x46a2b0 |
Source file and lines | par_strength.c:2011-2048 |
Module | exec |
nb instructions | 37 |
loop length | 148 |
nb stack references | 0 |
front end | 4.63 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.50 | 3.50 | 2.00 | 2.00 | 2.00 | 2.00 | 0.00 | 0.00 | 0.00 | 0.00 | 7.50 | 7.17 | 7.33 | 1.50 | 1.50 |
cycles | 3.50 | 3.50 | 2.00 | 2.00 | 2.00 | 2.00 | 0.00 | 0.00 | 0.00 | 0.00 | 7.50 | 7.17 | 7.33 | 1.50 | 1.50 |
Cycles executing div or sqrt instructions | NA |
Front-end | 4.63 |
Overall L1 | 7.50 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LDR X7, [X9, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X2, X2, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X2, X7 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 46b200 <.omp_outlined..20+0xf50> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X19, [X10, X2,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X7, [X11, X19,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LT 46b0f0 <.omp_outlined..20+0xe40> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X7, [X3, X19,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X20, [X24, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X20, X17 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 46b0f0 <.omp_outlined..20+0xe40> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDUR X20, [X29, #480] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STR X20, [X24, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDUR X20, [X29, #480] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STR X7, [X4, X20,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDUR X7, [X29, #480] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X7, X7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STUR X7, [X29, #480] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X7, X19, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X20, [X9, X19,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X23, [X9, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X20, X23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 46b184 <.omp_outlined..20+0xed4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDP X26, X21, [X29, #960] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDR X21, [X21] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X26, [X26] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
B 46b12c <.omp_outlined..20+0xe7c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDUR X28, [X29, #432] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X19, [X12, X19,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X23, [X12, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X19, X23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 46b0a4 <.omp_outlined..20+0xdf4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDUR X20, [X29, #464] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X21, [X28] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X20, [X20] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
B 46b1b0 <.omp_outlined..20+0xf00> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Function | .omp_outlined..20#0x46a2b0 |
Source file and lines | par_strength.c:2011-2048 |
Module | exec |
nb instructions | 37 |
loop length | 148 |
nb stack references | 0 |
front end | 4.63 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.50 | 3.50 | 2.00 | 2.00 | 2.00 | 2.00 | 0.00 | 0.00 | 0.00 | 0.00 | 7.50 | 7.17 | 7.33 | 1.50 | 1.50 |
cycles | 3.50 | 3.50 | 2.00 | 2.00 | 2.00 | 2.00 | 0.00 | 0.00 | 0.00 | 0.00 | 7.50 | 7.17 | 7.33 | 1.50 | 1.50 |
Cycles executing div or sqrt instructions | NA |
Front-end | 4.63 |
Overall L1 | 7.50 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LDR X7, [X9, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X2, X2, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X2, X7 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 46b200 <.omp_outlined..20+0xf50> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X19, [X10, X2,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X7, [X11, X19,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LT 46b0f0 <.omp_outlined..20+0xe40> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X7, [X3, X19,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X20, [X24, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X20, X17 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 46b0f0 <.omp_outlined..20+0xe40> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDUR X20, [X29, #480] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STR X20, [X24, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDUR X20, [X29, #480] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STR X7, [X4, X20,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDUR X7, [X29, #480] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X7, X7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STUR X7, [X29, #480] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X7, X19, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X20, [X9, X19,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X23, [X9, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X20, X23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 46b184 <.omp_outlined..20+0xed4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDP X26, X21, [X29, #960] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDR X21, [X21] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X26, [X26] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
B 46b12c <.omp_outlined..20+0xe7c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDUR X28, [X29, #432] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X19, [X12, X19,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X23, [X12, X7,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X19, X23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 46b0a4 <.omp_outlined..20+0xdf4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDUR X20, [X29, #464] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X21, [X28] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X20, [X20] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
B 46b1b0 <.omp_outlined..20+0xf00> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |