Loop Id: 1028 | Module: exec | Source: csr_matvec.c:334-341 | Coverage: 0.8% |
---|
Loop Id: 1028 | Module: exec | Source: csr_matvec.c:334-341 | Coverage: 0.8% |
---|
0x4aa5e0 STR D0, [X13, X20,LSL #3] |
0x4aa5e4 ORR X20, XZR, X0 |
0x4aa5e8 CMP X0, X19 |
0x4aa5ec B.EQ 4ab304 |
0x4aa5f0 ADD X0, X20, #1 |
0x4aa5f4 ORR X4, XZR, X16 |
0x4aa5f8 LDR D0, [X8, X20,LSL #3] |
0x4aa5fc LDR X16, [X9, X0,LSL #3] |
0x4aa600 SUBS X2, X16, X4 |
0x4aa604 B.LE 4aa5e0 |
0x4aa608 CMP X2, #2 |
0x4aa60c B.CS 4aa620 |
0x4aa610 ORR X1, XZR, X4 |
0x4aa614 B 4aa674 |
0x4aa674 SUB W2, W16, W1 |
0x4aa678 ANDS X3, X2, #4160 |
0x4aa67c B.EQ 4aa6b4 |
0x4aa680 ORR X2, XZR, X1 |
(1031) 0x4aa684 LDR X4, [X12, X2,LSL #3] |
(1031) 0x4aa688 LDR D1, [X10, X2,LSL #3] |
(1031) 0x4aa68c ADD X2, X2, #1 |
(1031) 0x4aa690 SUBS X3, X3, #1 |
(1031) 0x4aa694 LDR D2, [X11, X4,LSL #3] |
(1031) 0x4aa698 FMADD D0, D2, D1, D0 |
(1031) 0x4aa69c B.NE 4aa684 |
0x4aa6a0 ORN X1, XZR, X1 |
0x4aa6a4 ADD X1, X16, X1 |
0x4aa6a8 CMP X1, #3 |
0x4aa6ac B.CC 4aa5e0 |
0x4aa6b0 B 4aa6c8 |
0x4aa6b4 ORR X2, XZR, X1 |
0x4aa6b8 ORN X1, XZR, X1 |
0x4aa6bc ADD X1, X16, X1 |
0x4aa6c0 CMP X1, #3 |
0x4aa6c4 B.CC 4aa5e0 |
0x4aa6c8 UBFM X3, X2, #61, #60 |
0x4aa6cc SUB X1, X16, X2 |
0x4aa6d0 ADD X2, X17, X3 |
0x4aa6d4 ADD X3, X18, X3 |
0x4aa6d8 HINT #0 |
0x4aa6dc HINT #0 |
(1030) 0x4aa6e0 LDP X4, X5, [X3, #1008] |
(1030) 0x4aa6e4 LDP D2, D3, [X2, #1008] |
(1030) 0x4aa6e8 SUBS X1, X1, #4 |
(1030) 0x4aa6ec LDR D1, [X11, X4,LSL #3] |
(1030) 0x4aa6f0 FMADD D0, D1, D2, D0 |
(1030) 0x4aa6f4 LDR D1, [X11, X5,LSL #3] |
(1030) 0x4aa6f8 FMADD D0, D1, D3, D0 |
(1030) 0x4aa6fc LDP X4, X5, [X3], #32 |
(1030) 0x4aa700 LDR D2, [X11, X4,LSL #3] |
(1030) 0x4aa704 LDP D1, D3, [X2], #32 |
(1030) 0x4aa708 FMADD D0, D2, D1, D0 |
(1030) 0x4aa70c LDR D1, [X11, X5,LSL #3] |
(1030) 0x4aa710 FMADD D0, D1, D3, D0 |
(1030) 0x4aa714 B.NE 4aa6e0 |
0x4aa718 B 4aa5e0 |
/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 334 - 341 |
-------------------------------------------------------------------------------- |
334: for (i = iBegin; i < iEnd; i++) |
335: { |
336: tempx = b_data[i]; |
337: for (jj = A_i[i]; jj < A_i[i+1]; jj++) |
338: { |
339: tempx += A_data[jj] * x_data[A_j[jj]]; |
340: } |
341: y_data[i] = tempx; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○100.00 | __kmp_invoke_microtask | libomp.so |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 6.30 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.67 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.17 |
Bottlenecks | P2, P3, P4, P5, |
Function | .omp_outlined..18#0x4a9fb0 |
Source | csr_matvec.c:334-337,csr_matvec.c:341-341 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 5.25 |
CQA cycles if no scalar integer | 0.83 |
CQA cycles if FP arith vectorized | 5.25 |
CQA cycles if fully vectorized | 1.13 |
Front-end cycles | 4.13 |
DIV/SQRT cycles | 4.50 |
P0 cycles | 4.50 |
P1 cycles | 5.25 |
P2 cycles | 5.25 |
P3 cycles | 5.25 |
P4 cycles | 5.25 |
P5 cycles | 0.50 |
P6 cycles | 0.50 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 1.17 |
P10 cycles | 0.83 |
P11 cycles | 1.00 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 35.00 |
Nb uops | 33.00 |
Nb loads | NA |
Nb stores | 1.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 4.57 |
Bytes prefetched | 0.00 |
Bytes loaded | 16.00 |
Bytes stored | 8.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 24.31 |
Vector-efficiency ratio load | 25.00 |
Vector-efficiency ratio store | 25.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 22.92 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 25.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 6.30 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.67 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.17 |
Bottlenecks | P2, P3, P4, P5, |
Function | .omp_outlined..18#0x4a9fb0 |
Source | csr_matvec.c:334-337,csr_matvec.c:341-341 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 5.25 |
CQA cycles if no scalar integer | 0.83 |
CQA cycles if FP arith vectorized | 5.25 |
CQA cycles if fully vectorized | 1.13 |
Front-end cycles | 4.13 |
DIV/SQRT cycles | 4.50 |
P0 cycles | 4.50 |
P1 cycles | 5.25 |
P2 cycles | 5.25 |
P3 cycles | 5.25 |
P4 cycles | 5.25 |
P5 cycles | 0.50 |
P6 cycles | 0.50 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 1.17 |
P10 cycles | 0.83 |
P11 cycles | 1.00 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 35.00 |
Nb uops | 33.00 |
Nb loads | NA |
Nb stores | 1.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 4.57 |
Bytes prefetched | 0.00 |
Bytes loaded | 16.00 |
Bytes stored | 8.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 24.31 |
Vector-efficiency ratio load | 25.00 |
Vector-efficiency ratio store | 25.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 22.92 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 25.00 |
Path / |
Function | .omp_outlined..18#0x4a9fb0 |
Source file and lines | csr_matvec.c:334-341 |
Module | exec |
nb instructions | 35 |
loop length | 140 |
nb stack references | 0 |
front end | 4.13 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.50 | 4.50 | 5.25 | 5.25 | 5.25 | 5.25 | 0.50 | 0.50 | 0.00 | 0.00 | 1.17 | 0.83 | 1.00 | 0.00 | 0.00 |
cycles | 4.50 | 4.50 | 5.25 | 5.25 | 5.25 | 5.25 | 0.50 | 0.50 | 0.00 | 0.00 | 1.17 | 0.83 | 1.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 4.13 |
Overall L1 | 5.25 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STR D0, [X13, X20,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
ORR X20, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X0, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4ab304 <.omp_outlined..18+0x1354> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD X0, X20, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X4, XZR, X16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR D0, [X8, X20,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDR X16, [X9, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUBS X2, X16, X4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LE 4aa5e0 <.omp_outlined..18+0x630> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP X2, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.CS 4aa620 <.omp_outlined..18+0x670> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR X1, XZR, X4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
B 4aa674 <.omp_outlined..18+0x6c4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB W2, W16, W1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ANDS X3, X2, #4160 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4aa6b4 <.omp_outlined..18+0x704> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR X2, XZR, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORN X1, XZR, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X1, X16, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X1, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.CC 4aa5e0 <.omp_outlined..18+0x630> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
B 4aa6c8 <.omp_outlined..18+0x718> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR X2, XZR, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORN X1, XZR, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X1, X16, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X1, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.CC 4aa5e0 <.omp_outlined..18+0x630> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
UBFM X3, X2, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X1, X16, X2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X2, X17, X3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X3, X18, X3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
B 4aa5e0 <.omp_outlined..18+0x630> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Function | .omp_outlined..18#0x4a9fb0 |
Source file and lines | csr_matvec.c:334-341 |
Module | exec |
nb instructions | 35 |
loop length | 140 |
nb stack references | 0 |
front end | 4.13 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.50 | 4.50 | 5.25 | 5.25 | 5.25 | 5.25 | 0.50 | 0.50 | 0.00 | 0.00 | 1.17 | 0.83 | 1.00 | 0.00 | 0.00 |
cycles | 4.50 | 4.50 | 5.25 | 5.25 | 5.25 | 5.25 | 0.50 | 0.50 | 0.00 | 0.00 | 1.17 | 0.83 | 1.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 4.13 |
Overall L1 | 5.25 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STR D0, [X13, X20,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
ORR X20, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X0, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4ab304 <.omp_outlined..18+0x1354> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD X0, X20, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X4, XZR, X16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR D0, [X8, X20,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDR X16, [X9, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUBS X2, X16, X4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LE 4aa5e0 <.omp_outlined..18+0x630> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP X2, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.CS 4aa620 <.omp_outlined..18+0x670> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR X1, XZR, X4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
B 4aa674 <.omp_outlined..18+0x6c4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB W2, W16, W1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ANDS X3, X2, #4160 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4aa6b4 <.omp_outlined..18+0x704> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR X2, XZR, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORN X1, XZR, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X1, X16, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X1, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.CC 4aa5e0 <.omp_outlined..18+0x630> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
B 4aa6c8 <.omp_outlined..18+0x718> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR X2, XZR, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORN X1, XZR, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X1, X16, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X1, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.CC 4aa5e0 <.omp_outlined..18+0x630> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
UBFM X3, X2, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X1, X16, X2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X2, X17, X3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X3, X18, X3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
B 4aa5e0 <.omp_outlined..18+0x630> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |