Loop Id: 2974 | Module: exec | Source: par_csr_matop.c:865-989 [...] | Coverage: 0.16% |
---|
Loop Id: 2974 | Module: exec | Source: par_csr_matop.c:865-989 [...] | Coverage: 0.16% |
---|
0x4c632c LDR X9, [SP, #152] |
0x4c6330 ORR X1, XZR, X20 |
0x4c6334 ORR X3, XZR, X25 |
0x4c6338 CBNZ X9, 4c6414 |
0x4c633c LDP X15, X30, [X16] |
0x4c6340 CMP X15, X30 |
0x4c6344 B.GE 4c63c4 |
0x4c6348 LDP X18, X9, [SP, #160] |
0x4c634c LDP X28, X30, [SP, #176] |
(2978) 0x4c6350 LDR X17, [X28, X15,LSL #3] |
(2978) 0x4c6354 LDR D17, [X30, X15,LSL #3] |
(2978) 0x4c6358 UBFM X8, X17, #61, #60 |
(2978) 0x4c635c LDR X2, [X27, X17,LSL #3] |
(2978) 0x4c6360 ADD X7, X8, #8 |
(2978) 0x4c6364 LDR X6, [X27, X7] |
(2978) 0x4c6368 ADD X8, X27, X7 |
(2978) 0x4c636c CMP X2, X6 |
(2978) 0x4c6370 B.GE 4c63b0 |
(2978) 0x4c6374 HINT #0 |
(2978) 0x4c6378 HINT #0 |
(2978) 0x4c637c HINT #0 |
(2981) 0x4c6380 LDR X4, [X21, X2,LSL #3] |
(2981) 0x4c6384 LDR D18, [X22, X2,LSL #3] |
(2981) 0x4c6388 LDR X5, [X0, X4,LSL #3] |
(2981) 0x4c638c FMUL D19, D17, D18 |
(2981) 0x4c6390 CMP X20, X5 |
(2981) 0x4c6394 B.GT 4c64fc |
(2981) 0x4c6398 LDR D20, [X19, X5,LSL #3] |
(2981) 0x4c639c ADD X2, X2, #1 |
(2981) 0x4c63a0 FADD D21, D20, D19 |
(2981) 0x4c63a4 STR D21, [X19, X5,LSL #3] |
(2981) 0x4c63a8 CMP X6, X2 |
(2981) 0x4c63ac B.GT 4c6380 |
(2978) 0x4c63b0 CBNZ X18, 4c6520 |
(2978) 0x4c63b4 LDR X17, [X16, #8] |
(2978) 0x4c63b8 ADD X15, X15, #1 |
(2978) 0x4c63bc CMP X17, X15 |
(2978) 0x4c63c0 B.GT 4c6350 |
0x4c63c4 LDP X20, X25, [SP, #120] |
0x4c63c8 ADD X16, X16, #8 |
0x4c63cc LDR X28, [SP, #136] |
0x4c63d0 ADD X18, X20, #1 |
0x4c63d4 ADD X9, X25, #8 |
0x4c63d8 STP X18, X9, [SP, #120] |
0x4c63dc CMP X28, X18 |
0x4c63e0 B.EQ 4c6614 |
0x4c63e4 LDR X28, [SP, #144] |
0x4c63e8 ORR X25, XZR, X3 |
0x4c63ec ORR X20, XZR, X1 |
0x4c63f0 CBZ X28, 4c632c |
0x4c6414 LDR X30, [SP, #128] |
0x4c6418 LDP X17, X6, [X30] |
0x4c641c CMP X17, X6 |
0x4c6420 B.GE 4c633c |
0x4c6424 STP X14, X21, [SP, #208] |
0x4c6428 STR X27, [SP, #224] |
0x4c642c LDP X15, X18, [SP, #232] |
0x4c6430 LDP X21, X27, [SP, #248] |
0x4c6434 LDP X28, X8, [SP, #264] |
0x4c6438 STP X12, X13, [SP, #192] |
0x4c643c LDR X9, [SP, #280] |
(2975) 0x4c6440 LDR X14, [X21, X17,LSL #3] |
(2975) 0x4c6444 LDR D1, [X27, X17,LSL #3] |
(2975) 0x4c6448 UBFM X12, X14, #61, #60 |
(2975) 0x4c644c LDR X2, [X15, X14,LSL #3] |
(2975) 0x4c6450 ADD X12, X12, #8 |
(2975) 0x4c6454 LDR X7, [X15, X12] |
(2975) 0x4c6458 ADD X13, X15, X12 |
(2975) 0x4c645c CMP X2, X7 |
(2975) 0x4c6460 B.GE 4c6498 |
(2977) 0x4c6464 LDR X5, [X28, X2,LSL #3] |
(2977) 0x4c6468 LDR D0, [X8, X2,LSL #3] |
(2977) 0x4c646c ADD X6, X26, X5 |
(2977) 0x4c6470 LDR X4, [X0, X6,LSL #3] |
(2977) 0x4c6474 FMUL D3, D1, D0 |
(2977) 0x4c6478 CMP X25, X4 |
(2977) 0x4c647c B.GT 4c65f0 |
(2977) 0x4c6480 LDR D2, [X23, X4,LSL #3] |
(2977) 0x4c6484 ADD X2, X2, #1 |
(2977) 0x4c6488 FADD D4, D2, D3 |
(2977) 0x4c648c STR D4, [X23, X4,LSL #3] |
(2977) 0x4c6490 CMP X7, X2 |
(2977) 0x4c6494 B.GT 4c6464 |
(2975) 0x4c6498 LDR X5, [X18, X14,LSL #3] |
(2975) 0x4c649c ADD X14, X18, X12 |
(2975) 0x4c64a0 LDR X6, [X18, X12] |
(2975) 0x4c64a4 CMP X5, X6 |
(2975) 0x4c64a8 B.GE 4c64dc |
(2976) 0x4c64ac LDR X12, [X9, X5,LSL #3] |
(2976) 0x4c64b0 LDR D5, [X10, X5,LSL #3] |
(2976) 0x4c64b4 LDR X13, [X0, X12,LSL #3] |
(2976) 0x4c64b8 FMUL D6, D1, D5 |
(2976) 0x4c64bc CMP X20, X13 |
(2976) 0x4c64c0 B.GT 4c65bc |
(2976) 0x4c64c4 LDR D7, [X19, X13,LSL #3] |
(2976) 0x4c64c8 ADD X5, X5, #1 |
(2976) 0x4c64cc FADD D16, D7, D6 |
(2976) 0x4c64d0 STR D16, [X19, X13,LSL #3] |
(2976) 0x4c64d4 CMP X6, X5 |
(2976) 0x4c64d8 B.GT 4c64ac |
(2975) 0x4c64dc LDR X4, [X30, #8] |
(2975) 0x4c64e0 ADD X17, X17, #1 |
(2975) 0x4c64e4 CMP X4, X17 |
(2975) 0x4c64e8 B.GT 4c6440 |
0x4c64ec LDP X12, X13, [SP, #192] |
0x4c64f0 LDP X14, X21, [SP, #208] |
0x4c64f4 LDR X27, [SP, #224] |
0x4c64f8 B 4c633c |
(2981) 0x4c64fc STR X1, [X0, X4,LSL #3] |
(2981) 0x4c6500 ADD X2, X2, #1 |
(2981) 0x4c6504 STR D19, [X19, X1,LSL #3] |
(2981) 0x4c6508 STR X4, [X24, X1,LSL #3] |
(2981) 0x4c650c ADD X1, X1, #1 |
(2981) 0x4c6510 LDR X6, [X8] |
(2981) 0x4c6514 CMP X2, X6 |
(2981) 0x4c6518 B.LT 4c6380 |
(2978) 0x4c651c CBZ X18, 4c63b4 |
(2978) 0x4c6520 LDR X2, [X9, X17,LSL #3] |
(2978) 0x4c6524 ADD X17, X9, X7 |
(2978) 0x4c6528 LDR X7, [X9, X7] |
(2978) 0x4c652c CMP X2, X7 |
(2978) 0x4c6530 B.GE 4c63b4 |
(2978) 0x4c6534 HINT #0 |
(2978) 0x4c6538 HINT #0 |
(2978) 0x4c653c HINT #0 |
(2979) 0x4c6540 LDR X8, [X13, X2,LSL #3] |
(2979) 0x4c6544 LDR D22, [X14, X2,LSL #3] |
(2979) 0x4c6548 LDR X5, [X12, X8,LSL #3] |
(2979) 0x4c654c FMUL D23, D17, D22 |
(2979) 0x4c6550 ADD X6, X26, X5 |
(2979) 0x4c6554 LDR X4, [X0, X6,LSL #3] |
(2979) 0x4c6558 CMP X25, X4 |
(2979) 0x4c655c B.GT 4c6598 |
(2980) 0x4c6560 LDR D24, [X23, X4,LSL #3] |
(2980) 0x4c6564 ADD X2, X2, #1 |
(2980) 0x4c6568 FADD D25, D24, D23 |
(2980) 0x4c656c STR D25, [X23, X4,LSL #3] |
(2980) 0x4c6570 CMP X7, X2 |
(2980) 0x4c6574 B.LE 4c63b4 |
(2980) 0x4c6578 LDR X8, [X13, X2,LSL #3] |
(2980) 0x4c657c LDR D22, [X14, X2,LSL #3] |
(2980) 0x4c6580 LDR X5, [X12, X8,LSL #3] |
(2980) 0x4c6584 FMUL D23, D17, D22 |
(2980) 0x4c6588 ADD X6, X26, X5 |
(2980) 0x4c658c LDR X4, [X0, X6,LSL #3] |
(2980) 0x4c6590 CMP X25, X4 |
(2980) 0x4c6594 B.LE 4c6560 |
(2979) 0x4c6598 STR X3, [X0, X6,LSL #3] |
(2979) 0x4c659c ADD X2, X2, #1 |
(2979) 0x4c65a0 STR D23, [X23, X3,LSL #3] |
(2979) 0x4c65a4 STR X5, [X11, X3,LSL #3] |
(2979) 0x4c65a8 ADD X3, X3, #1 |
(2979) 0x4c65ac LDR X7, [X17] |
(2979) 0x4c65b0 CMP X2, X7 |
(2979) 0x4c65b4 B.LT 4c6540 |
(2978) 0x4c65b8 B 4c63b4 |
(2976) 0x4c65bc STR X1, [X0, X12,LSL #3] |
(2976) 0x4c65c0 ADD X5, X5, #1 |
(2976) 0x4c65c4 STR D6, [X19, X1,LSL #3] |
(2976) 0x4c65c8 STR X12, [X24, X1,LSL #3] |
(2976) 0x4c65cc ADD X1, X1, #1 |
(2976) 0x4c65d0 LDR X6, [X14] |
(2976) 0x4c65d4 CMP X5, X6 |
(2976) 0x4c65d8 B.LT 4c64ac |
(2975) 0x4c65dc LDR X4, [X30, #8] |
(2975) 0x4c65e0 ADD X17, X17, #1 |
(2975) 0x4c65e4 CMP X4, X17 |
(2975) 0x4c65e8 B.GT 4c6440 |
0x4c65ec B 4c64ec |
(2977) 0x4c65f0 STR X3, [X0, X6,LSL #3] |
(2977) 0x4c65f4 ADD X2, X2, #1 |
(2977) 0x4c65f8 STR D3, [X23, X3,LSL #3] |
(2977) 0x4c65fc STR X5, [X11, X3,LSL #3] |
(2977) 0x4c6600 ADD X3, X3, #1 |
(2977) 0x4c6604 LDR X7, [X13] |
(2977) 0x4c6608 CMP X2, X7 |
(2977) 0x4c660c B.LT 4c6464 |
(2975) 0x4c6610 B 4c6498 |
/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 865 - 989 |
-------------------------------------------------------------------------------- |
865: for (i1 = ns; i1 < ne; i1++) |
[...] |
874: if ( allsquare ) |
[...] |
886: if (num_cols_offd_A) |
887: { |
888: for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++) |
889: { |
890: i2 = A_offd_j[jj2]; |
891: a_entry = A_offd_data[jj2]; |
[...] |
897: for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++) |
898: { |
899: i3 = num_cols_diag_B+B_ext_offd_j[jj3]; |
[...] |
907: if (B_marker[i3] < jj_row_begin_offd) |
908: { |
909: B_marker[i3] = jj_count_offd; |
910: C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3]; |
911: C_offd_j[jj_count_offd] = i3-num_cols_diag_B; |
912: jj_count_offd++; |
913: } |
914: else |
915: C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3]; |
916: } |
917: for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++) |
918: { |
919: i3 = B_ext_diag_j[jj3]; |
920: if (B_marker[i3] < jj_row_begin_diag) |
921: { |
922: B_marker[i3] = jj_count_diag; |
923: C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3]; |
924: C_diag_j[jj_count_diag] = i3; |
925: jj_count_diag++; |
926: } |
927: else |
928: C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3]; |
[...] |
937: for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++) |
938: { |
939: i2 = A_diag_j[jj2]; |
940: a_entry = A_diag_data[jj2]; |
[...] |
946: for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++) |
947: { |
948: i3 = B_diag_j[jj3]; |
[...] |
956: if (B_marker[i3] < jj_row_begin_diag) |
957: { |
958: B_marker[i3] = jj_count_diag; |
959: C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3]; |
960: C_diag_j[jj_count_diag] = i3; |
961: jj_count_diag++; |
962: } |
963: else |
964: { |
965: C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3]; |
966: } |
967: } |
968: if (num_cols_offd_B) |
969: { |
970: for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++) |
971: { |
972: i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]]; |
[...] |
980: if (B_marker[i3] < jj_row_begin_offd) |
981: { |
982: B_marker[i3] = jj_count_offd; |
983: C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3]; |
984: C_offd_j[jj_count_offd] = i3-num_cols_diag_B; |
985: jj_count_offd++; |
986: } |
987: else |
988: { |
989: C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3]; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | GOMP_parallel | libomp.so | |
○ | hypre_ParMatmul | par_csr_matop.c:998 | exec |
○ | hypre_BoomerAMGSetup | par_amg_setup.c:1227 | exec |
○ | hypre_PCGSetup | pcg.c:234 | exec |
○ | main | amg.c:398 | exec |
○ | __libc_start_main | libc-2.31.so | |
○ | _start | amg.c:599 | exec |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.44 |
Bottlenecks | P10, P11, P12, |
Function | hypre_ParMatmul._omp_fn.3 |
Source | par_csr_matop.c:865-865,par_csr_matop.c:874-874,par_csr_matop.c:886-888,par_csr_matop.c:937-937 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 6.67 |
CQA cycles if no scalar integer | 6.67 |
CQA cycles if FP arith vectorized | 6.67 |
CQA cycles if fully vectorized | 1.67 |
Front-end cycles | 4.63 |
DIV/SQRT cycles | 3.50 |
P0 cycles | 3.50 |
P1 cycles | 2.50 |
P2 cycles | 2.50 |
P3 cycles | 2.50 |
P4 cycles | 2.50 |
P5 cycles | 0.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 6.67 |
P10 cycles | 6.67 |
P11 cycles | 6.67 |
P12 cycles | 2.00 |
P13 cycles | 2.00 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 37.00 |
Nb uops | 37.00 |
Nb loads | NA |
Nb stores | 4.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 39.60 |
Bytes prefetched | 0.00 |
Bytes loaded | 208.00 |
Bytes stored | 56.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 25.00 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 25.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 25.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.44 |
Bottlenecks | P10, P11, P12, |
Function | hypre_ParMatmul._omp_fn.3 |
Source | par_csr_matop.c:865-865,par_csr_matop.c:874-874,par_csr_matop.c:886-888,par_csr_matop.c:937-937 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 6.67 |
CQA cycles if no scalar integer | 6.67 |
CQA cycles if FP arith vectorized | 6.67 |
CQA cycles if fully vectorized | 1.67 |
Front-end cycles | 4.63 |
DIV/SQRT cycles | 3.50 |
P0 cycles | 3.50 |
P1 cycles | 2.50 |
P2 cycles | 2.50 |
P3 cycles | 2.50 |
P4 cycles | 2.50 |
P5 cycles | 0.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 6.67 |
P10 cycles | 6.67 |
P11 cycles | 6.67 |
P12 cycles | 2.00 |
P13 cycles | 2.00 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 37.00 |
Nb uops | 37.00 |
Nb loads | NA |
Nb stores | 4.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 39.60 |
Bytes prefetched | 0.00 |
Bytes loaded | 208.00 |
Bytes stored | 56.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 25.00 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 25.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 25.00 |
Path / |
Function | hypre_ParMatmul._omp_fn.3 |
Source file and lines | par_csr_matop.c:865-989 |
Module | exec |
nb instructions | 37 |
loop length | 148 |
nb stack references | 0 |
front end | 4.63 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.50 | 3.50 | 2.50 | 2.50 | 2.50 | 2.50 | 0.00 | 0.00 | 0.00 | 0.00 | 6.67 | 6.67 | 6.67 | 2.00 | 2.00 |
cycles | 3.50 | 3.50 | 2.50 | 2.50 | 2.50 | 2.50 | 0.00 | 0.00 | 0.00 | 0.00 | 6.67 | 6.67 | 6.67 | 2.00 | 2.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 4.63 |
Overall L1 | 6.67 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LDR X9, [SP, #152] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ORR X1, XZR, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X3, XZR, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CBNZ X9, 4c6414 <hypre_ParMatmul._omp_fn.3+0x264> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDP X15, X30, [X16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
CMP X15, X30 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 4c63c4 <hypre_ParMatmul._omp_fn.3+0x214> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDP X18, X9, [SP, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X28, X30, [SP, #176] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X20, X25, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
ADD X16, X16, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X28, [SP, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X18, X20, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X9, X25, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X18, X9, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
CMP X28, X18 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4c6614 <hypre_ParMatmul._omp_fn.3+0x464> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X28, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ORR X25, XZR, X3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X20, XZR, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CBZ X28, 4c632c <hypre_ParMatmul._omp_fn.3+0x17c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X30, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDP X17, X6, [X30] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
CMP X17, X6 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 4c633c <hypre_ParMatmul._omp_fn.3+0x18c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
STP X14, X21, [SP, #208] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X27, [SP, #224] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDP X15, X18, [SP, #232] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X21, X27, [SP, #248] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X28, X8, [SP, #264] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
STP X12, X13, [SP, #192] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X9, [SP, #280] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDP X12, X13, [SP, #192] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X14, X21, [SP, #208] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDR X27, [SP, #224] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
B 4c633c <hypre_ParMatmul._omp_fn.3+0x18c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
B 4c64ec <hypre_ParMatmul._omp_fn.3+0x33c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Function | hypre_ParMatmul._omp_fn.3 |
Source file and lines | par_csr_matop.c:865-989 |
Module | exec |
nb instructions | 37 |
loop length | 148 |
nb stack references | 0 |
front end | 4.63 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.50 | 3.50 | 2.50 | 2.50 | 2.50 | 2.50 | 0.00 | 0.00 | 0.00 | 0.00 | 6.67 | 6.67 | 6.67 | 2.00 | 2.00 |
cycles | 3.50 | 3.50 | 2.50 | 2.50 | 2.50 | 2.50 | 0.00 | 0.00 | 0.00 | 0.00 | 6.67 | 6.67 | 6.67 | 2.00 | 2.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 4.63 |
Overall L1 | 6.67 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LDR X9, [SP, #152] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ORR X1, XZR, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X3, XZR, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CBNZ X9, 4c6414 <hypre_ParMatmul._omp_fn.3+0x264> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDP X15, X30, [X16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
CMP X15, X30 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 4c63c4 <hypre_ParMatmul._omp_fn.3+0x214> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDP X18, X9, [SP, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X28, X30, [SP, #176] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X20, X25, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
ADD X16, X16, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X28, [SP, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X18, X20, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X9, X25, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X18, X9, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
CMP X28, X18 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4c6614 <hypre_ParMatmul._omp_fn.3+0x464> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X28, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ORR X25, XZR, X3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X20, XZR, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CBZ X28, 4c632c <hypre_ParMatmul._omp_fn.3+0x17c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X30, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDP X17, X6, [X30] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
CMP X17, X6 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 4c633c <hypre_ParMatmul._omp_fn.3+0x18c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
STP X14, X21, [SP, #208] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X27, [SP, #224] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDP X15, X18, [SP, #232] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X21, X27, [SP, #248] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X28, X8, [SP, #264] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
STP X12, X13, [SP, #192] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X9, [SP, #280] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDP X12, X13, [SP, #192] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X14, X21, [SP, #208] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDR X27, [SP, #224] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
B 4c633c <hypre_ParMatmul._omp_fn.3+0x18c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
B 4c64ec <hypre_ParMatmul._omp_fn.3+0x33c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |