Loop Id: 1156 | Module: exec | Source: par_strength.c:1714-1770 [...] | Coverage: 0.03% |
---|
Loop Id: 1156 | Module: exec | Source: par_strength.c:1714-1770 [...] | Coverage: 0.03% |
---|
0x46db84 ADD X18, X18, #1 |
0x46db88 CMP X18, X30 |
0x46db8c B.EQ 46e3f0 |
0x46db90 LDUR X8, [X29, #448] |
0x46db94 LDP X2, X1, [X29, #984] |
0x46db98 LDR X10, [X8, X18,LSL #3] |
0x46db9c LDUR X8, [X29, #440] |
0x46dba0 STR X1, [X8, X18,LSL #3] |
0x46dba4 LDUR X8, [X29, #432] |
0x46dba8 LDR X8, [X8] |
0x46dbac CBZ X8, 46dbbc |
0x46dbbc ADD X3, X10, #1 |
0x46dbc0 LDR X5, [X11, X10,LSL #3] |
0x46dbc4 LDR X8, [X11, X3,LSL #3] |
0x46dbc8 CMP X5, X8 |
0x46dbcc B.GE 46dd30 |
0x46dbd0 LDUR X8, [X29, #456] |
0x46dbd4 STUR X10, [X29, #376] |
0x46dbd8 LDR X6, [X8] |
0x46dbdc LDUR X8, [X29, #400] |
0x46dbe0 LDR X7, [X8] |
0x46dbe4 LDUR X8, [X29, #408] |
0x46dbe8 LDR X30, [X8] |
0x46dbec B 46dc10 |
(1158) 0x46dc00 LDR X8, [X11, X3,LSL #3] |
(1158) 0x46dc04 ADD X5, X5, #1 |
(1158) 0x46dc08 CMP X5, X8 |
(1158) 0x46dc0c B.GE 46dd28 |
(1158) 0x46dc10 LDR X27, [X12, X5,LSL #3] |
(1158) 0x46dc14 LDR X8, [X13, X27,LSL #3] |
(1158) 0x46dc18 CMP X8, #1 |
(1158) 0x46dc1c B.LT 46dc44 |
(1158) 0x46dc20 LDR X8, [X6, X27,LSL #3] |
(1158) 0x46dc24 LDR X9, [X24, X8,LSL #3] |
(1158) 0x46dc28 CMP X9, X1 |
(1158) 0x46dc2c B.GE 46dc44 |
(1158) 0x46dc30 LDUR X9, [X29, #480] |
(1158) 0x46dc34 STR X9, [X24, X8,LSL #3] |
(1158) 0x46dc38 LDUR X8, [X29, #480] |
(1158) 0x46dc3c ADD X8, X8, #1 |
(1158) 0x46dc40 STUR X8, [X29, #480] |
(1158) 0x46dc44 ADD X28, X27, #1 |
(1158) 0x46dc48 LDR X10, [X11, X27,LSL #3] |
(1158) 0x46dc4c LDR X8, [X11, X28,LSL #3] |
(1158) 0x46dc50 CMP X10, X8 |
(1158) 0x46dc54 B.GE 46dcc0 |
(1158) 0x46dc58 LDUR X9, [X29, #456] |
(1158) 0x46dc5c LDR X9, [X9] |
(1158) 0x46dc60 B 46dc70 |
(1160) 0x46dc64 ADD X10, X10, #1 |
(1160) 0x46dc68 CMP X10, X8 |
(1160) 0x46dc6c B.GE 46dcc0 |
(1160) 0x46dc70 LDR X4, [X12, X10,LSL #3] |
(1160) 0x46dc74 LDR X19, [X13, X4,LSL #3] |
(1160) 0x46dc78 CMP X19, #1 |
(1160) 0x46dc7c B.LT 46dc64 |
(1160) 0x46dc80 LDR X4, [X9, X4,LSL #3] |
(1160) 0x46dc84 CMP X4, X18 |
(1160) 0x46dc88 B.EQ 46dc64 |
(1160) 0x46dc8c LDR X19, [X24, X4,LSL #3] |
(1160) 0x46dc90 CMP X19, X1 |
(1160) 0x46dc94 B.GE 46dc64 |
(1160) 0x46dc98 LDUR X8, [X29, #480] |
(1160) 0x46dc9c STR X8, [X24, X4,LSL #3] |
(1160) 0x46dca0 LDUR X8, [X29, #480] |
(1160) 0x46dca4 ADD X8, X8, #1 |
(1160) 0x46dca8 STUR X8, [X29, #480] |
(1160) 0x46dcac LDR X8, [X11, X28,LSL #3] |
(1160) 0x46dcb0 B 46dc64 |
(1158) 0x46dcc0 LDR X10, [X14, X27,LSL #3] |
(1158) 0x46dcc4 LDR X9, [X14, X28,LSL #3] |
(1158) 0x46dcc8 CMP X10, X9 |
(1158) 0x46dccc B.GE 46dc00 |
(1158) 0x46dcd0 LDUR X8, [X29, #464] |
(1158) 0x46dcd4 LDR X8, [X8] |
(1158) 0x46dcd8 B 46dcec |
(1159) 0x46dce0 ADD X10, X10, #1 |
(1159) 0x46dce4 CMP X10, X9 |
(1159) 0x46dce8 B.GE 46dc00 |
(1159) 0x46dcec LDR X4, [X7, X10,LSL #3] |
(1159) 0x46dcf0 LDR X19, [X30, X4,LSL #3] |
(1159) 0x46dcf4 CMP X19, #1 |
(1159) 0x46dcf8 B.LT 46dce0 |
(1159) 0x46dcfc LDR X4, [X8, X4,LSL #3] |
(1159) 0x46dd00 LDR X19, [X25, X4,LSL #3] |
(1159) 0x46dd04 CMP X19, X2 |
(1159) 0x46dd08 B.GE 46dce0 |
(1159) 0x46dd0c LDUR X9, [X29, #472] |
(1159) 0x46dd10 STR X9, [X25, X4,LSL #3] |
(1159) 0x46dd14 LDUR X9, [X29, #472] |
(1159) 0x46dd18 ADD X9, X9, #1 |
(1159) 0x46dd1c STUR X9, [X29, #472] |
(1159) 0x46dd20 LDR X9, [X14, X28,LSL #3] |
(1159) 0x46dd24 B 46dce0 |
0x46dd28 LDUR X30, [X29, #416] |
0x46dd2c LDUR X10, [X29, #376] |
0x46dd30 LDR X4, [X14, X10,LSL #3] |
0x46dd34 LDR X8, [X14, X3,LSL #3] |
0x46dd38 CMP X4, X8 |
0x46dd3c B.GE 46db84 |
/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 1714 - 1770 |
-------------------------------------------------------------------------------- |
1714: for (ic = ic_begin; ic < ic_end; ic++) |
[...] |
1720: HYPRE_Int i1 = coarse_to_fine[ic]; |
1721: |
1722: HYPRE_Int jj_row_begin_diag = num_nonzeros_diag; |
1723: HYPRE_Int jj_row_begin_offd = num_nonzeros_offd; |
1724: |
1725: C_diag_i[ic] = num_nonzeros_diag; |
1726: if (num_cols_offd_C) |
1727: { |
1728: C_offd_i[ic] = num_nonzeros_offd; |
1729: } |
1730: |
1731: for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++) |
1732: { |
1733: i2 = S_diag_j[jj1]; |
1734: if (CF_marker[i2] > 0) |
1735: { |
1736: index = fine_to_coarse[i2]; |
1737: if (S_marker[index] < jj_row_begin_diag) |
1738: { |
1739: S_marker[index] = num_nonzeros_diag; |
1740: num_nonzeros_diag++; |
1741: } |
1742: } |
1743: for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++) |
1744: { |
1745: i3 = S_diag_j[jj2]; |
1746: if (CF_marker[i3] > 0) |
1747: { |
1748: index = fine_to_coarse[i3]; |
1749: if (index != ic && S_marker[index] < jj_row_begin_diag) |
1750: { |
1751: S_marker[index] = num_nonzeros_diag; |
1752: num_nonzeros_diag++; |
1753: } |
1754: } |
1755: } |
1756: for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++) |
1757: { |
1758: i3 = S_offd_j[jj2]; |
1759: if (CF_marker_offd[i3] > 0) |
1760: { |
1761: index = map_S_to_C[i3]; |
1762: if (S_marker_offd[index] < jj_row_begin_offd) |
1763: { |
1764: S_marker_offd[index] = num_nonzeros_offd; |
1765: num_nonzeros_offd++; |
1766: } |
1767: } |
1768: } |
1769: } |
1770: for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○100.00 | __kmp_invoke_microtask | libomp.so |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.78 |
Bottlenecks | P10, P11, P12, |
Function | .omp_outlined..20#0x46d910 |
Source | par_strength.c:1714-1714,par_strength.c:1720-1722,par_strength.c:1725-1728,par_strength.c:1731-1731,par_strength.c:1756-1756,par_strength.c:1770-1770 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 6.67 |
CQA cycles if no scalar integer | 6.67 |
CQA cycles if FP arith vectorized | 6.67 |
CQA cycles if fully vectorized | 1.67 |
Front-end cycles | 3.75 |
DIV/SQRT cycles | 2.50 |
P0 cycles | 2.50 |
P1 cycles | 1.25 |
P2 cycles | 1.25 |
P3 cycles | 1.25 |
P4 cycles | 1.25 |
P5 cycles | 0.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 6.67 |
P10 cycles | 6.67 |
P11 cycles | 6.67 |
P12 cycles | 1.00 |
P13 cycles | 1.00 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 30.00 |
Nb uops | 30.00 |
Nb loads | NA |
Nb stores | 2.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 25.20 |
Bytes prefetched | 0.00 |
Bytes loaded | 152.00 |
Bytes stored | 16.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 25.00 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 25.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.78 |
Bottlenecks | P10, P11, P12, |
Function | .omp_outlined..20#0x46d910 |
Source | par_strength.c:1714-1714,par_strength.c:1720-1722,par_strength.c:1725-1728,par_strength.c:1731-1731,par_strength.c:1756-1756,par_strength.c:1770-1770 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 6.67 |
CQA cycles if no scalar integer | 6.67 |
CQA cycles if FP arith vectorized | 6.67 |
CQA cycles if fully vectorized | 1.67 |
Front-end cycles | 3.75 |
DIV/SQRT cycles | 2.50 |
P0 cycles | 2.50 |
P1 cycles | 1.25 |
P2 cycles | 1.25 |
P3 cycles | 1.25 |
P4 cycles | 1.25 |
P5 cycles | 0.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 6.67 |
P10 cycles | 6.67 |
P11 cycles | 6.67 |
P12 cycles | 1.00 |
P13 cycles | 1.00 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 30.00 |
Nb uops | 30.00 |
Nb loads | NA |
Nb stores | 2.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 25.20 |
Bytes prefetched | 0.00 |
Bytes loaded | 152.00 |
Bytes stored | 16.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 25.00 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 25.00 |
Path / |
Function | .omp_outlined..20#0x46d910 |
Source file and lines | par_strength.c:1714-1770 |
Module | exec |
nb instructions | 30 |
loop length | 120 |
nb stack references | 0 |
front end | 3.75 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 2.50 | 1.25 | 1.25 | 1.25 | 1.25 | 0.00 | 0.00 | 0.00 | 0.00 | 6.67 | 6.67 | 6.67 | 1.00 | 1.00 |
cycles | 2.50 | 2.50 | 1.25 | 1.25 | 1.25 | 1.25 | 0.00 | 0.00 | 0.00 | 0.00 | 6.67 | 6.67 | 6.67 | 1.00 | 1.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 3.75 |
Overall L1 | 6.67 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADD X18, X18, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X18, X30 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 46e3f0 <.omp_outlined..20+0xae0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDUR X8, [X29, #448] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDP X2, X1, [X29, #984] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDR X10, [X8, X18,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDUR X8, [X29, #440] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STR X1, [X8, X18,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDUR X8, [X29, #432] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CBZ X8, 46dbbc <.omp_outlined..20+0x2ac> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD X3, X10, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X5, [X11, X10,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X8, [X11, X3,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X5, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 46dd30 <.omp_outlined..20+0x420> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDUR X8, [X29, #456] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STUR X10, [X29, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X6, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDUR X8, [X29, #400] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X7, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDUR X8, [X29, #408] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X30, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
B 46dc10 <.omp_outlined..20+0x300> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDUR X30, [X29, #416] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDUR X10, [X29, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X4, [X14, X10,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X8, [X14, X3,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X4, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 46db84 <.omp_outlined..20+0x274> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Function | .omp_outlined..20#0x46d910 |
Source file and lines | par_strength.c:1714-1770 |
Module | exec |
nb instructions | 30 |
loop length | 120 |
nb stack references | 0 |
front end | 3.75 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 2.50 | 1.25 | 1.25 | 1.25 | 1.25 | 0.00 | 0.00 | 0.00 | 0.00 | 6.67 | 6.67 | 6.67 | 1.00 | 1.00 |
cycles | 2.50 | 2.50 | 1.25 | 1.25 | 1.25 | 1.25 | 0.00 | 0.00 | 0.00 | 0.00 | 6.67 | 6.67 | 6.67 | 1.00 | 1.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 3.75 |
Overall L1 | 6.67 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADD X18, X18, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X18, X30 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 46e3f0 <.omp_outlined..20+0xae0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDUR X8, [X29, #448] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDP X2, X1, [X29, #984] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDR X10, [X8, X18,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDUR X8, [X29, #440] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STR X1, [X8, X18,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDUR X8, [X29, #432] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CBZ X8, 46dbbc <.omp_outlined..20+0x2ac> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD X3, X10, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X5, [X11, X10,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X8, [X11, X3,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X5, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 46dd30 <.omp_outlined..20+0x420> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDUR X8, [X29, #456] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STUR X10, [X29, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X6, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDUR X8, [X29, #400] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X7, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDUR X8, [X29, #408] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X30, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
B 46dc10 <.omp_outlined..20+0x300> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDUR X30, [X29, #416] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDUR X10, [X29, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X4, [X14, X10,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X8, [X14, X3,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X4, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 46db84 <.omp_outlined..20+0x274> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |