Loop Id: 3434 | Module: exec | Source: IJMatrix_parcsr.c:3383-3454 [...] | Coverage: 0.84% |
---|
Loop Id: 3434 | Module: exec | Source: IJMatrix_parcsr.c:3383-3454 [...] | Coverage: 0.84% |
---|
(3436) 0x4e316c LDR X1, [X27, X21,LSL #3] |
(3436) 0x4e3170 CMP X8, X1 |
(3436) 0x4e3174 CCMP X9, X1, #0, #10 |
(3436) 0x4e3178 B.LE 4e3370 |
(3436) 0x4e317c LDR X0, [X18, X6] |
(3436) 0x4e3180 CMP X3, X0 |
(3436) 0x4e3184 B.LE 4e3300 |
(3436) 0x4e3188 SUB X30, X3, X0 |
(3436) 0x4e318c ANDS X4, X30, #4224 |
(3436) 0x4e3190 B.EQ 4e3258 |
(3436) 0x4e3194 CMP X4, #1 |
(3436) 0x4e3198 B.EQ 4e323c |
(3436) 0x4e319c CMP X4, #2 |
(3436) 0x4e31a0 B.EQ 4e3228 |
(3436) 0x4e31a4 CMP X4, #3 |
(3436) 0x4e31a8 B.EQ 4e3214 |
(3436) 0x4e31ac CMP X4, #4 |
(3436) 0x4e31b0 B.EQ 4e3200 |
(3436) 0x4e31b4 CMP X4, #5 |
(3436) 0x4e31b8 B.EQ 4e31ec |
(3436) 0x4e31bc CMP X4, #6 |
(3436) 0x4e31c0 B.EQ 4e31d8 |
(3436) 0x4e31c4 LDR X11, [X23, X0,LSL #3] |
(3436) 0x4e31c8 UBFM X2, X0, #61, #60 |
(3436) 0x4e31cc CMP X1, X11 |
(3436) 0x4e31d0 B.EQ 4e3808 |
(3436) 0x4e31d4 ADD X0, X0, #1 |
(3436) 0x4e31d8 LDR X12, [X23, X0,LSL #3] |
(3436) 0x4e31dc UBFM X2, X0, #61, #60 |
(3436) 0x4e31e0 CMP X1, X12 |
(3436) 0x4e31e4 B.EQ 4e3808 |
(3436) 0x4e31e8 ADD X0, X0, #1 |
(3436) 0x4e31ec LDR X13, [X23, X0,LSL #3] |
(3436) 0x4e31f0 UBFM X2, X0, #61, #60 |
(3436) 0x4e31f4 CMP X1, X13 |
(3436) 0x4e31f8 B.EQ 4e3808 |
(3436) 0x4e31fc ADD X0, X0, #1 |
(3436) 0x4e3200 LDR X14, [X23, X0,LSL #3] |
(3436) 0x4e3204 UBFM X2, X0, #61, #60 |
(3436) 0x4e3208 CMP X1, X14 |
(3436) 0x4e320c B.EQ 4e3808 |
(3436) 0x4e3210 ADD X0, X0, #1 |
(3436) 0x4e3214 LDR X15, [X23, X0,LSL #3] |
(3436) 0x4e3218 UBFM X2, X0, #61, #60 |
(3436) 0x4e321c CMP X1, X15 |
(3436) 0x4e3220 B.EQ 4e3808 |
(3436) 0x4e3224 ADD X0, X0, #1 |
(3436) 0x4e3228 LDR X25, [X23, X0,LSL #3] |
(3436) 0x4e322c UBFM X2, X0, #61, #60 |
(3436) 0x4e3230 CMP X1, X25 |
(3436) 0x4e3234 B.EQ 4e3808 |
(3436) 0x4e3238 ADD X0, X0, #1 |
(3436) 0x4e323c LDR X30, [X23, X0,LSL #3] |
(3436) 0x4e3240 UBFM X2, X0, #61, #60 |
(3436) 0x4e3244 CMP X1, X30 |
(3436) 0x4e3248 B.EQ 4e3808 |
(3436) 0x4e324c ADD X0, X0, #1 |
(3436) 0x4e3250 CMP X3, X0 |
(3436) 0x4e3254 B.EQ 4e3300 |
(3437) 0x4e3258 LDR X30, [X23, X0,LSL #3] |
(3437) 0x4e325c ADD X4, X0, #1 |
(3437) 0x4e3260 ADD X12, X0, #3 |
(3437) 0x4e3264 ADD X11, X0, #2 |
(3437) 0x4e3268 ADD X13, X0, #4 |
(3437) 0x4e326c ADD X14, X0, #5 |
(3437) 0x4e3270 ADD X15, X0, #6 |
(3437) 0x4e3274 ADD X25, X0, #7 |
(3437) 0x4e3278 UBFM X2, X0, #61, #60 |
(3437) 0x4e327c ADD X0, X0, #8 |
(3437) 0x4e3280 CMP X1, X30 |
(3437) 0x4e3284 B.EQ 4e3808 |
(3437) 0x4e3288 LDR X30, [X23, X4,LSL #3] |
(3437) 0x4e328c UBFM X2, X4, #61, #60 |
(3437) 0x4e3290 CMP X1, X30 |
(3437) 0x4e3294 B.EQ 4e3808 |
(3437) 0x4e3298 LDR X4, [X23, X11,LSL #3] |
(3437) 0x4e329c UBFM X2, X11, #61, #60 |
(3437) 0x4e32a0 CMP X1, X4 |
(3437) 0x4e32a4 B.EQ 4e3808 |
(3437) 0x4e32a8 LDR X11, [X23, X12,LSL #3] |
(3437) 0x4e32ac UBFM X2, X12, #61, #60 |
(3437) 0x4e32b0 CMP X1, X11 |
(3437) 0x4e32b4 B.EQ 4e3808 |
(3437) 0x4e32b8 LDR X12, [X23, X13,LSL #3] |
(3437) 0x4e32bc UBFM X2, X13, #61, #60 |
(3437) 0x4e32c0 CMP X1, X12 |
(3437) 0x4e32c4 B.EQ 4e3808 |
(3437) 0x4e32c8 LDR X13, [X23, X14,LSL #3] |
(3437) 0x4e32cc UBFM X2, X14, #61, #60 |
(3437) 0x4e32d0 CMP X1, X13 |
(3437) 0x4e32d4 B.EQ 4e3808 |
(3437) 0x4e32d8 LDR X14, [X23, X15,LSL #3] |
(3437) 0x4e32dc UBFM X2, X15, #61, #60 |
(3437) 0x4e32e0 CMP X1, X14 |
(3437) 0x4e32e4 B.EQ 4e3808 |
(3437) 0x4e32e8 LDR X15, [X23, X25,LSL #3] |
(3437) 0x4e32ec UBFM X2, X25, #61, #60 |
(3437) 0x4e32f0 CMP X1, X15 |
(3437) 0x4e32f4 B.EQ 4e3808 |
(3437) 0x4e32f8 CMP X3, X0 |
(3437) 0x4e32fc B.NE 4e3258 |
(3436) 0x4e3300 CMP X20, X28 |
(3436) 0x4e3304 B.LE 4e3c0c |
(3436) 0x4e3308 LDR D2, [X5, X21,LSL #3] |
(3436) 0x4e330c UBFM X2, X28, #61, #60 |
(3436) 0x4e3310 STR X1, [X23, X28,LSL #3] |
(3436) 0x4e3314 ADD X28, X28, #1 |
(3436) 0x4e3318 STR D2, [X19, X2] |
(3436) 0x4e331c ADD X21, X21, #1 |
(3436) 0x4e3320 CMP X21, X17 |
(3436) 0x4e3324 B.NE 4e316c |
0x4e3370 LDR X0, [X26, X6] |
0x4e3374 CMP X16, X0 |
0x4e3378 B.LE 4e34f4 |
0x4e337c SUB X2, X16, X0 |
0x4e3380 ANDS X14, X2, #4224 |
0x4e3384 B.EQ 4e344c |
0x4e3388 CMP X14, #1 |
0x4e338c B.EQ 4e3430 |
0x4e3390 CMP X14, #2 |
0x4e3394 B.EQ 4e341c |
0x4e3398 CMP X14, #3 |
0x4e339c B.EQ 4e3408 |
0x4e33a0 CMP X14, #4 |
0x4e33a4 B.EQ 4e33f4 |
0x4e33a8 CMP X14, #5 |
0x4e33ac B.EQ 4e33e0 |
0x4e33b0 CMP X14, #6 |
0x4e33b4 B.EQ 4e33cc |
0x4e33b8 LDR X25, [X24, X0,LSL #3] |
0x4e33bc UBFM X2, X0, #61, #60 |
0x4e33c0 CMP X1, X25 |
0x4e33c4 B.EQ 4e3814 |
0x4e33c8 ADD X0, X0, #1 |
0x4e33cc LDR X13, [X24, X0,LSL #3] |
0x4e33d0 UBFM X2, X0, #61, #60 |
0x4e33d4 CMP X1, X13 |
0x4e33d8 B.EQ 4e3814 |
0x4e33dc ADD X0, X0, #1 |
0x4e33e0 LDR X15, [X24, X0,LSL #3] |
0x4e33e4 UBFM X2, X0, #61, #60 |
0x4e33e8 CMP X1, X15 |
0x4e33ec B.EQ 4e3814 |
0x4e33f0 ADD X0, X0, #1 |
0x4e33f4 LDR X30, [X24, X0,LSL #3] |
0x4e33f8 UBFM X2, X0, #61, #60 |
0x4e33fc CMP X1, X30 |
0x4e3400 B.EQ 4e3814 |
0x4e3404 ADD X0, X0, #1 |
0x4e3408 LDR X4, [X24, X0,LSL #3] |
0x4e340c UBFM X2, X0, #61, #60 |
0x4e3410 CMP X1, X4 |
0x4e3414 B.EQ 4e3814 |
0x4e3418 ADD X0, X0, #1 |
0x4e341c LDR X11, [X24, X0,LSL #3] |
0x4e3420 UBFM X2, X0, #61, #60 |
0x4e3424 CMP X1, X11 |
0x4e3428 B.EQ 4e3814 |
0x4e342c ADD X0, X0, #1 |
0x4e3430 LDR X12, [X24, X0,LSL #3] |
0x4e3434 UBFM X2, X0, #61, #60 |
0x4e3438 CMP X1, X12 |
0x4e343c B.EQ 4e3814 |
0x4e3440 ADD X0, X0, #1 |
0x4e3444 CMP X16, X0 |
0x4e3448 B.EQ 4e34f4 |
(3438) 0x4e344c LDR X30, [X24, X0,LSL #3] |
(3438) 0x4e3450 ADD X4, X0, #1 |
(3438) 0x4e3454 ADD X12, X0, #3 |
(3438) 0x4e3458 ADD X11, X0, #2 |
(3438) 0x4e345c ADD X13, X0, #4 |
(3438) 0x4e3460 ADD X14, X0, #5 |
(3438) 0x4e3464 ADD X15, X0, #6 |
(3438) 0x4e3468 ADD X25, X0, #7 |
(3438) 0x4e346c UBFM X2, X0, #61, #60 |
(3438) 0x4e3470 ADD X0, X0, #8 |
(3438) 0x4e3474 CMP X1, X30 |
(3438) 0x4e3478 B.EQ 4e3814 |
(3438) 0x4e347c LDR X30, [X24, X4,LSL #3] |
(3438) 0x4e3480 UBFM X2, X4, #61, #60 |
(3438) 0x4e3484 CMP X1, X30 |
(3438) 0x4e3488 B.EQ 4e3814 |
(3438) 0x4e348c LDR X4, [X24, X11,LSL #3] |
(3438) 0x4e3490 UBFM X2, X11, #61, #60 |
(3438) 0x4e3494 CMP X1, X4 |
(3438) 0x4e3498 B.EQ 4e3814 |
(3438) 0x4e349c LDR X11, [X24, X12,LSL #3] |
(3438) 0x4e34a0 UBFM X2, X12, #61, #60 |
(3438) 0x4e34a4 CMP X1, X11 |
(3438) 0x4e34a8 B.EQ 4e3814 |
(3438) 0x4e34ac LDR X12, [X24, X13,LSL #3] |
(3438) 0x4e34b0 UBFM X2, X13, #61, #60 |
(3438) 0x4e34b4 CMP X1, X12 |
(3438) 0x4e34b8 B.EQ 4e3814 |
(3438) 0x4e34bc LDR X13, [X24, X14,LSL #3] |
(3438) 0x4e34c0 UBFM X2, X14, #61, #60 |
(3438) 0x4e34c4 CMP X1, X13 |
(3438) 0x4e34c8 B.EQ 4e3814 |
(3438) 0x4e34cc LDR X14, [X24, X15,LSL #3] |
(3438) 0x4e34d0 UBFM X2, X15, #61, #60 |
(3438) 0x4e34d4 CMP X1, X14 |
(3438) 0x4e34d8 B.EQ 4e3814 |
(3438) 0x4e34dc LDR X15, [X24, X25,LSL #3] |
(3438) 0x4e34e0 UBFM X2, X25, #61, #60 |
(3438) 0x4e34e4 CMP X1, X15 |
(3438) 0x4e34e8 B.EQ 4e3814 |
(3438) 0x4e34ec CMP X16, X0 |
(3438) 0x4e34f0 B.NE 4e344c |
0x4e34f4 LDR X25, [SP, #176] |
0x4e34f8 CMP X25, X10 |
0x4e34fc B.LE 4e3e78 |
0x4e3500 LDR D0, [X5, X21,LSL #3] |
0x4e3504 UBFM X0, X10, #61, #60 |
0x4e3508 STR X1, [X24, X10,LSL #3] |
0x4e350c ADD X10, X10, #1 |
0x4e3510 STR D0, [X7, X0] |
0x4e3514 B 4e331c |
(3436) 0x4e3808 LDR D3, [X5, X21,LSL #3] |
(3436) 0x4e380c STR D3, [X19, X2] |
(3436) 0x4e3810 B 4e331c |
0x4e3814 LDR D1, [X5, X21,LSL #3] |
0x4e3818 STR D1, [X7, X2] |
0x4e381c B 4e331c |
/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 3383 - 3454 |
-------------------------------------------------------------------------------- |
3383: for (i=0; i < n; i++) |
3384: { |
3385: if (cols[indx] < col_0 || cols[indx] > col_n) |
3386: /* insert into offd */ |
3387: { |
3388: for (j=offd_i[row_local]; j < offd_indx; j++) |
3389: { |
3390: if (offd_j[j] == cols[indx]) |
3391: { |
3392: offd_data[j] = values[indx]; |
3393: not_found = 0; |
3394: break; |
3395: } |
3396: } |
3397: if (not_found) |
3398: { |
3399: if (cnt_offd < offd_space) |
3400: { |
3401: offd_j[cnt_offd] = cols[indx]; |
3402: offd_data[cnt_offd++] = values[indx]; |
[...] |
3422: for (j=diag_i[row_local]; j < diag_indx; j++) |
3423: { |
3424: if (diag_j[j] == cols[indx]) |
3425: { |
3426: diag_data[j] = values[indx]; |
3427: not_found = 0; |
3428: break; |
3429: } |
3430: } |
3431: if (not_found) |
3432: { |
3433: if (cnt_diag < diag_space) |
3434: { |
3435: diag_j[cnt_diag] = cols[indx]; |
3436: diag_data[cnt_diag++] = values[indx]; |
[...] |
3454: indx++; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | GOMP_parallel | libomp.so | |
○ | hypre_IJMatrixSetValuesOMPParC[...] | IJMatrix_parcsr.c:3509 | exec |
○ | BuildIJLaplacian27pt | amg.c:2267 | exec |
○ | main | amg.c:274 | exec |
○ | __libc_start_main | libc-2.31.so | |
○ | _start | amg.c:599 | exec |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 7.13 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.12 |
Bottlenecks | P0, P1, |
Function | hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1 |
Source | IJMatrix_parcsr.c:3422-3426,IJMatrix_parcsr.c:3431-3436 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 9.50 |
CQA cycles if no scalar integer | 1.33 |
CQA cycles if FP arith vectorized | 9.50 |
CQA cycles if fully vectorized | 2.38 |
Front-end cycles | 8.38 |
DIV/SQRT cycles | 9.50 |
P0 cycles | 9.50 |
P1 cycles | 8.50 |
P2 cycles | 8.50 |
P3 cycles | 8.50 |
P4 cycles | 8.50 |
P5 cycles | 1.00 |
P6 cycles | 1.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 4.83 |
P10 cycles | 4.50 |
P11 cycles | 4.67 |
P12 cycles | 0.50 |
P13 cycles | 0.50 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 67.00 |
Nb uops | 67.00 |
Nb loads | NA |
Nb stores | 3.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 11.79 |
Bytes prefetched | 0.00 |
Bytes loaded | 88.00 |
Bytes stored | 24.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 25.00 |
Vector-efficiency ratio load | 25.00 |
Vector-efficiency ratio store | 25.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 25.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 7.13 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.12 |
Bottlenecks | P0, P1, |
Function | hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1 |
Source | IJMatrix_parcsr.c:3422-3426,IJMatrix_parcsr.c:3431-3436 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 9.50 |
CQA cycles if no scalar integer | 1.33 |
CQA cycles if FP arith vectorized | 9.50 |
CQA cycles if fully vectorized | 2.38 |
Front-end cycles | 8.38 |
DIV/SQRT cycles | 9.50 |
P0 cycles | 9.50 |
P1 cycles | 8.50 |
P2 cycles | 8.50 |
P3 cycles | 8.50 |
P4 cycles | 8.50 |
P5 cycles | 1.00 |
P6 cycles | 1.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 4.83 |
P10 cycles | 4.50 |
P11 cycles | 4.67 |
P12 cycles | 0.50 |
P13 cycles | 0.50 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 67.00 |
Nb uops | 67.00 |
Nb loads | NA |
Nb stores | 3.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 11.79 |
Bytes prefetched | 0.00 |
Bytes loaded | 88.00 |
Bytes stored | 24.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 25.00 |
Vector-efficiency ratio load | 25.00 |
Vector-efficiency ratio store | 25.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 25.00 |
Path / |
Function | hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1 |
Source file and lines | IJMatrix_parcsr.c:3383-3454 |
Module | exec |
nb instructions | 67 |
loop length | 268 |
nb stack references | 0 |
front end | 8.38 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 9.50 | 9.50 | 8.50 | 8.50 | 8.50 | 8.50 | 1.00 | 1.00 | 0.00 | 0.00 | 4.83 | 4.50 | 4.67 | 0.50 | 0.50 |
cycles | 9.50 | 9.50 | 8.50 | 8.50 | 8.50 | 8.50 | 1.00 | 1.00 | 0.00 | 0.00 | 4.83 | 4.50 | 4.67 | 0.50 | 0.50 |
Cycles executing div or sqrt instructions | NA |
Front-end | 8.38 |
Overall L1 | 9.50 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LDR X0, [X26, X6] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X16, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LE 4e34f4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x80c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB X2, X16, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ANDS X14, X2, #4224 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e344c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x764> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP X14, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e3430 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x748> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP X14, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e341c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x734> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP X14, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e3408 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x720> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP X14, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e33f4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x70c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP X14, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e33e0 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x6f8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP X14, #6 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e33cc <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x6e4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X25, [X24, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
UBFM X2, X0, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X1, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e3814 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb2c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD X0, X0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X13, [X24, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
UBFM X2, X0, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X1, X13 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e3814 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb2c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD X0, X0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X15, [X24, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
UBFM X2, X0, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X1, X15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e3814 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb2c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD X0, X0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X30, [X24, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
UBFM X2, X0, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X1, X30 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e3814 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb2c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD X0, X0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X4, [X24, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
UBFM X2, X0, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X1, X4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e3814 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb2c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD X0, X0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X11, [X24, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
UBFM X2, X0, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X1, X11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e3814 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb2c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD X0, X0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X12, [X24, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
UBFM X2, X0, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X1, X12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e3814 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb2c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD X0, X0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X16, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e34f4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x80c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X25, [SP, #176] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X25, X10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LE 4e3e78 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1190> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR D0, [X5, X21,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
UBFM X0, X10, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X1, [X24, X10,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X10, X10, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR D0, [X7, X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
B 4e331c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x634> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR D1, [X5, X21,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
STR D1, [X7, X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
B 4e331c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x634> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Function | hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1 |
Source file and lines | IJMatrix_parcsr.c:3383-3454 |
Module | exec |
nb instructions | 67 |
loop length | 268 |
nb stack references | 0 |
front end | 8.38 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 9.50 | 9.50 | 8.50 | 8.50 | 8.50 | 8.50 | 1.00 | 1.00 | 0.00 | 0.00 | 4.83 | 4.50 | 4.67 | 0.50 | 0.50 |
cycles | 9.50 | 9.50 | 8.50 | 8.50 | 8.50 | 8.50 | 1.00 | 1.00 | 0.00 | 0.00 | 4.83 | 4.50 | 4.67 | 0.50 | 0.50 |
Cycles executing div or sqrt instructions | NA |
Front-end | 8.38 |
Overall L1 | 9.50 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LDR X0, [X26, X6] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X16, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LE 4e34f4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x80c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB X2, X16, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ANDS X14, X2, #4224 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e344c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x764> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP X14, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e3430 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x748> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP X14, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e341c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x734> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP X14, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e3408 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x720> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP X14, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e33f4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x70c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP X14, #5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e33e0 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x6f8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP X14, #6 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e33cc <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x6e4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X25, [X24, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
UBFM X2, X0, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X1, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e3814 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb2c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD X0, X0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X13, [X24, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
UBFM X2, X0, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X1, X13 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e3814 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb2c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD X0, X0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X15, [X24, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
UBFM X2, X0, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X1, X15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e3814 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb2c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD X0, X0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X30, [X24, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
UBFM X2, X0, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X1, X30 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e3814 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb2c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD X0, X0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X4, [X24, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
UBFM X2, X0, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X1, X4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e3814 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb2c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD X0, X0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X11, [X24, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
UBFM X2, X0, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X1, X11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e3814 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb2c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD X0, X0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X12, [X24, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
UBFM X2, X0, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X1, X12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e3814 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb2c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD X0, X0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X16, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.EQ 4e34f4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x80c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X25, [SP, #176] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X25, X10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LE 4e3e78 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1190> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR D0, [X5, X21,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
UBFM X0, X10, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X1, [X24, X10,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X10, X10, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR D0, [X7, X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
B 4e331c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x634> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR D1, [X5, X21,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
STR D1, [X7, X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
B 4e331c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x634> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |