Function: updateLinkCells | Module: exec | Source: linkCells.c:288-385 [...] | Coverage: 0.17% |
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Function: updateLinkCells | Module: exec | Source: linkCells.c:288-385 [...] | Coverage: 0.17% |
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/scratch_na/users/xoserete/qaas_runs/171-322-9862/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 288 - 385 |
-------------------------------------------------------------------------------- |
288: { |
289: emptyHaloCells(boxes); |
290: |
291: for (int iBox=0; iBox<boxes->nLocalBoxes; ++iBox) |
292: { |
293: int iOff = iBox*MAXATOMS; |
294: int ii=0; |
295: while (ii < boxes->nAtoms[iBox]) |
296: { |
297: int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]); |
298: if (jBox != iBox) |
299: moveAtom(boxes, atoms, ii, iBox, jBox); |
300: else |
301: ++ii; |
302: } |
303: } |
304: } |
[...] |
352: int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0])); |
353: int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1])); |
354: int iz = (int)(floor((rr[2] - localMin[2])*boxes->invBoxSize[2])); |
355: |
356: |
357: // For each axis, if we are inside the local domain, make sure we get |
358: // a local link cell. Otherwise, make sure we get a halo link cell. |
359: if (rr[0] < localMax[0]) |
360: { |
361: if (ix == gridSize[0]) ix = gridSize[0] - 1; |
362: } |
363: else |
364: ix = gridSize[0]; // assign to halo cell |
365: if (rr[1] < localMax[1]) |
[...] |
371: if (rr[2] < localMax[2]) |
[...] |
378: return getBoxFromTuple(boxes, ix, iy, iz); |
[...] |
384: for (int ii=boxes->nLocalBoxes; ii<boxes->nTotalBoxes; ++ii) |
385: boxes->nAtoms[ii] = 0; |
0x40b2d0 PUSH %RBP |
0x40b2d1 MOV %RSP,%RBP |
0x40b2d4 PUSH %R15 |
0x40b2d6 PUSH %R14 |
0x40b2d8 PUSH %R13 |
0x40b2da PUSH %R12 |
0x40b2dc PUSH %RBX |
0x40b2dd SUB $0x48,%RSP |
0x40b2e1 MOV %RSI,%RBX |
0x40b2e4 MOV %RDI,%R14 |
0x40b2e7 MOVSXD 0xc(%RDI),%R15 |
0x40b2eb MOV 0x14(%RDI),%EAX |
0x40b2ee CMP %EAX,%R15D |
0x40b2f1 JGE 40b315 |
0x40b2f3 LEA (,%R15,4),%RDI |
0x40b2fb ADD 0x78(%R14),%RDI |
0x40b2ff MOV %R15D,%ECX |
0x40b302 NOT %ECX |
0x40b304 ADD %ECX,%EAX |
0x40b306 LEA 0x4(,%RAX,4),%RDX |
0x40b30e XOR %ESI,%ESI |
0x40b310 CALL 414a80 <_intel_fast_memset> |
0x40b315 TEST %R15D,%R15D |
0x40b318 JLE 40b4a9 |
0x40b31e MOV 0x78(%R14),%RAX |
0x40b322 MOV %RAX,-0x30(%RBP) |
0x40b326 MOV %R15D,%EAX |
0x40b329 MOV %RAX,-0x38(%RBP) |
0x40b32d XOR %R15D,%R15D |
0x40b330 JMP 40b34d |
0x40b332 NOPW %CS:(%RAX,%RAX,1) |
(83) 0x40b340 INC %R15 |
(83) 0x40b343 CMP -0x38(%RBP),%R15 |
(83) 0x40b347 JE 40b4a9 |
(83) 0x40b34d MOV -0x30(%RBP),%RAX |
(83) 0x40b351 CMPL $0,(%RAX,%R15,4) |
(83) 0x40b356 JLE 40b340 |
(83) 0x40b358 MOV %R15D,%R13D |
(83) 0x40b35b SAL $0x6,%R13D |
(83) 0x40b35f VMOVSD 0x20(%R14),%XMM0 |
(83) 0x40b365 VMOVSD %XMM0,-0x70(%RBP) |
(83) 0x40b36a VMOVSD 0x28(%R14),%XMM0 |
(83) 0x40b370 VMOVSD %XMM0,-0x68(%RBP) |
(83) 0x40b375 VMOVSD 0x68(%R14),%XMM0 |
(83) 0x40b37b VMOVSD %XMM0,-0x60(%RBP) |
(83) 0x40b380 VMOVSD 0x70(%R14),%XMM0 |
(83) 0x40b386 VMOVSD %XMM0,-0x58(%RBP) |
(83) 0x40b38b VMOVSD 0x30(%R14),%XMM0 |
(83) 0x40b391 VMOVSD %XMM0,-0x50(%RBP) |
(83) 0x40b396 VMOVSD 0x38(%R14),%XMM0 |
(83) 0x40b39c VMOVSD %XMM0,-0x48(%RBP) |
(83) 0x40b3a1 VMOVSD 0x40(%R14),%XMM0 |
(83) 0x40b3a7 VMOVSD %XMM0,-0x40(%RBP) |
(83) 0x40b3ac XOR %R12D,%R12D |
(83) 0x40b3af JMP 40b3d1 |
0x40b3b1 NOPW %CS:(%RAX,%RAX,1) |
(84) 0x40b3c0 INC %R12D |
(84) 0x40b3c3 MOV -0x30(%RBP),%RAX |
(84) 0x40b3c7 CMP (%RAX,%R15,4),%R12D |
(84) 0x40b3cb JGE 40b340 |
(84) 0x40b3d1 MOV 0x18(%RBX),%RAX |
(84) 0x40b3d5 LEA (%R12,%R13,1),%ECX |
(84) 0x40b3d9 MOVSXD %ECX,%RCX |
(84) 0x40b3dc LEA (%RCX,%RCX,2),%RCX |
(84) 0x40b3e0 VMOVSD (%RAX,%RCX,8),%XMM0 |
(84) 0x40b3e5 VMOVSD -0x50(%RBP),%XMM1 |
(84) 0x40b3ea VUCOMISD %XMM0,%XMM1 |
(84) 0x40b3ee JBE 40b420 |
(84) 0x40b3f0 VSUBSD 0x18(%R14),%XMM0,%XMM0 |
(84) 0x40b3f6 VMULSD 0x60(%R14),%XMM0,%XMM0 |
(84) 0x40b3fc VROUNDSD $0x9,%XMM0,%XMM0,%XMM0 |
(84) 0x40b402 VCVTTSD2SI %XMM0,%ESI |
(84) 0x40b406 MOV (%R14),%EDX |
(84) 0x40b409 CMP %ESI,%EDX |
(84) 0x40b40b JNE 40b423 |
(84) 0x40b40d DEC %EDX |
(84) 0x40b40f MOV %EDX,%ESI |
(84) 0x40b411 JMP 40b423 |
0x40b413 NOPW %CS:(%RAX,%RAX,1) |
(84) 0x40b420 MOV (%R14),%ESI |
(84) 0x40b423 VMOVSD 0x8(%RAX,%RCX,8),%XMM0 |
(84) 0x40b429 VSUBSD -0x70(%RBP),%XMM0,%XMM1 |
(84) 0x40b42e VMULSD -0x60(%RBP),%XMM1,%XMM1 |
(84) 0x40b433 VROUNDSD $0x9,%XMM1,%XMM1,%XMM1 |
(84) 0x40b439 VCVTTSD2SI %XMM1,%EDI |
(84) 0x40b43d MOV 0x4(%R14),%EDX |
(84) 0x40b441 CMP %EDI,%EDX |
(84) 0x40b443 JNE 40b448 |
(84) 0x40b445 LEA -0x1(%RDX),%EDI |
(84) 0x40b448 VMOVSD 0x10(%RAX,%RCX,8),%XMM1 |
(84) 0x40b44e VSUBSD -0x68(%RBP),%XMM1,%XMM2 |
(84) 0x40b453 VMULSD -0x58(%RBP),%XMM2,%XMM2 |
(84) 0x40b458 VROUNDSD $0x9,%XMM2,%XMM2,%XMM2 |
(84) 0x40b45e VCVTTSD2SI %XMM2,%EAX |
(84) 0x40b462 MOV 0x8(%R14),%ECX |
(84) 0x40b466 VUCOMISD -0x48(%RBP),%XMM0 |
(84) 0x40b46b CMOVB %EDI,%EDX |
(84) 0x40b46e CMP %EAX,%ECX |
(84) 0x40b470 JNE 40b475 |
(84) 0x40b472 LEA -0x1(%RCX),%EAX |
(84) 0x40b475 VUCOMISD -0x40(%RBP),%XMM1 |
(84) 0x40b47a CMOVB %EAX,%ECX |
(84) 0x40b47d MOV %R14,%RDI |
(84) 0x40b480 CALL 40ae80 <getBoxFromTuple> |
(84) 0x40b485 MOV %EAX,%ECX |
(84) 0x40b487 CMP %RCX,%R15 |
(84) 0x40b48a JE 40b3c0 |
(84) 0x40b490 MOV %R14,%RDI |
(84) 0x40b493 MOV %RBX,%RSI |
(84) 0x40b496 MOV %R12D,%EDX |
(84) 0x40b499 MOV %R15D,%ECX |
(84) 0x40b49c MOV %EAX,%R8D |
(84) 0x40b49f CALL 40b130 <moveAtom> |
(84) 0x40b4a4 JMP 40b3c3 |
0x40b4a9 ADD $0x48,%RSP |
0x40b4ad POP %RBX |
0x40b4ae POP %R12 |
0x40b4b0 POP %R13 |
0x40b4b2 POP %R14 |
0x40b4b4 POP %R15 |
0x40b4b6 POP %RBP |
0x40b4b7 RET |
0x40b4b8 NOPL (%RAX,%RAX,1) |
Path / |
Source file and lines | linkCells.c:288-385 |
Module | exec |
nb instructions | 42 |
nb uops | 43 |
loop length | 163 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 2 |
micro-operation queue | 7.17 cycles |
front end | 7.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.70 | 1.60 | 3.67 | 3.67 | 4.50 | 1.60 | 1.50 | 4.50 | 4.50 | 4.50 | 1.60 | 3.67 |
cycles | 1.70 | 1.60 | 3.67 | 3.67 | 4.50 | 1.60 | 1.50 | 4.50 | 4.50 | 4.50 | 1.60 | 3.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 7.11 |
Stall cycles | 0.00 |
Front-end | 7.17 |
Dispatch | 4.50 |
Overall L1 | 7.17 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 8% |
load | NA (no load vectorizable/vectorized instructions) |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 7% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x48,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOVSXD 0xc(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x14(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %EAX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 40b315 <updateLinkCells+0x45> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (,%R15,4),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD 0x78(%R14),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %R15D,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOT %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %ECX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x4(,%RAX,4),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 414a80 <_intel_fast_memset> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
TEST %R15D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 40b4a9 <updateLinkCells+0x1d9> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x78(%R14),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40b34d <updateLinkCells+0x7d> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x48,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | linkCells.c:288-385 |
Module | exec |
nb instructions | 42 |
nb uops | 43 |
loop length | 163 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 2 |
micro-operation queue | 7.17 cycles |
front end | 7.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.70 | 1.60 | 3.67 | 3.67 | 4.50 | 1.60 | 1.50 | 4.50 | 4.50 | 4.50 | 1.60 | 3.67 |
cycles | 1.70 | 1.60 | 3.67 | 3.67 | 4.50 | 1.60 | 1.50 | 4.50 | 4.50 | 4.50 | 1.60 | 3.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 7.11 |
Stall cycles | 0.00 |
Front-end | 7.17 |
Dispatch | 4.50 |
Overall L1 | 7.17 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 8% |
load | NA (no load vectorizable/vectorized instructions) |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 7% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x48,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOVSXD 0xc(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x14(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %EAX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 40b315 <updateLinkCells+0x45> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (,%R15,4),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD 0x78(%R14),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %R15D,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOT %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %ECX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x4(,%RAX,4),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 414a80 <_intel_fast_memset> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
TEST %R15D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 40b4a9 <updateLinkCells+0x1d9> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x78(%R14),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40b34d <updateLinkCells+0x7d> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x48,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼updateLinkCells– | 0.17 | 0.04 |
▼Loop 83 - linkCells.c:291-378 - exec– | 0 | 0.05 |
○Loop 84 - linkCells.c:295-378 - exec | 0.16 | 2.34 |