Loop Id: 100 | Module: exec | Source: timestep.c:85-96 | Coverage: 0.02% |
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Loop Id: 100 | Module: exec | Source: timestep.c:85-96 | Coverage: 0.02% |
---|
0x40ff00 LEA 0x1(%R13),%RAX |
0x40ff04 ADD $0x40,%ESI |
0x40ff07 CMP -0x58(%RBP),%R13 |
0x40ff0b MOV %RAX,%R13 |
0x40ff0e JE 40feb2 |
0x40ff10 MOV %ESI,%ESI |
0x40ff12 LEA (%RBX,%R13,1),%RCX |
0x40ff16 MOV -0x70(%RBP),%RAX |
0x40ff1a MOV (%RAX,%RCX,4),%R8D |
0x40ff1e TEST %R8D,%R8D |
0x40ff21 JLE 40ff00 |
0x40ff23 LEA (,%RSI,8),%RCX |
0x40ff2b LEA (,%RSI,4),%R12 |
0x40ff33 MOV %R13,-0x40(%RBP) |
0x40ff37 LEA (%RBX,%R13,1),%R14D |
0x40ff3b SAL $0x6,%R14D |
0x40ff3f MOV 0x20(%RDI),%RDX |
0x40ff43 MOV 0x28(%RDI),%R9 |
0x40ff47 MOV 0x10(%RDX),%R15 |
0x40ff4b MOV 0x18(%RDX),%R10 |
0x40ff4f MOV 0x20(%RDX),%R11 |
0x40ff53 LEA -0x1(%R8),%EDX |
0x40ff57 MOVSXD %EDX,%RDX |
0x40ff5a ADD %R14,%RDX |
0x40ff5d SAL $0x3,%RDX |
0x40ff61 LEA (%RDX,%RDX,2),%RDX |
0x40ff65 LEA (%R11,%RDX,1),%R13 |
0x40ff69 ADD $0x10,%R13 |
0x40ff6d SAL $0x3,%R14 |
0x40ff71 LEA (%R14,%R14,2),%R14 |
0x40ff75 LEA (%R10,%R14,1),%RBX |
0x40ff79 CMP %RBX,%R13 |
0x40ff7c JB 410010 |
0x40ff82 ADD %R11,%R14 |
0x40ff85 ADD %R10,%RDX |
0x40ff88 ADD $0x10,%RDX |
0x40ff8c CMP %R14,%RDX |
0x40ff8f JB 410010 |
0x40ff95 LEA (%RCX,%RCX,2),%RCX |
0x40ff99 ADD $0x10,%RCX |
0x40ff9d ADD %R12,%R15 |
0x40ffa0 XOR %EDX,%EDX |
0x40ffa2 MOV -0x38(%RBP),%RBX |
0x40ffa6 MOV -0x40(%RBP),%R13 |
0x40ffaa NOPW (%RAX,%RAX,1) |
(103) 0x40ffb0 MOVSXD (%R15,%RDX,4),%RAX |
(103) 0x40ffb4 SAL $0x4,%RAX |
(103) 0x40ffb8 VDIVSD 0x8(%R9,%RAX,1),%XMM0,%XMM2 |
(103) 0x40ffbf VMOVSD -0x10(%R11,%RCX,1),%XMM3 |
(103) 0x40ffc6 VFMADD213SD -0x10(%R10,%RCX,1),%XMM2,%XMM3 |
(103) 0x40ffcd VMOVSD %XMM3,-0x10(%R10,%RCX,1) |
(103) 0x40ffd4 VMOVSD -0x8(%R11,%RCX,1),%XMM3 |
(103) 0x40ffdb VFMADD213SD -0x8(%R10,%RCX,1),%XMM2,%XMM3 |
(103) 0x40ffe2 VMOVSD %XMM3,-0x8(%R10,%RCX,1) |
(103) 0x40ffe9 VMOVSD (%R11,%RCX,1),%XMM3 |
(103) 0x40ffef VFMADD213SD (%R10,%RCX,1),%XMM2,%XMM3 |
(103) 0x40fff5 VMOVSD %XMM3,(%R10,%RCX,1) |
(103) 0x40fffb ADD $0x18,%RCX |
(103) 0x40ffff INC %RDX |
(103) 0x410002 CMP %EDX,%R8D |
(103) 0x410005 JNE 40ffb0 |
0x410007 JMP 40ff00 |
0x410010 MOV %R8D,%EAX |
0x410013 AND $-0x4,%EAX |
0x410016 JE 410199 |
0x41001c LEA (%RCX,%RCX,2),%R14 |
0x410020 MOV %RAX,-0x68(%RBP) |
0x410024 LEA -0x1(%RAX),%EDX |
0x410027 ADD %R15,%R12 |
0x41002a XOR %ECX,%ECX |
0x41002c NOPL (%RAX) |
(102) 0x410030 MOVSXD (%R12,%RCX,4),%RBX |
(102) 0x410034 MOVSXD 0x4(%R12,%RCX,4),%RAX |
(102) 0x410039 MOVSXD 0x8(%R12,%RCX,4),%R13 |
(102) 0x41003e MOVSXD 0xc(%R12,%RCX,4),%RDI |
(102) 0x410043 SAL $0x4,%RBX |
(102) 0x410047 SAL $0x4,%R13 |
(102) 0x41004b SAL $0x4,%RDI |
(102) 0x41004f VMOVSD 0x8(%R9,%R13,1),%XMM2 |
(102) 0x410056 VMOVHPD 0x8(%R9,%RDI,1),%XMM2,%XMM2 |
(102) 0x41005d SAL $0x4,%RAX |
(102) 0x410061 VMOVSD 0x8(%R9,%RBX,1),%XMM3 |
(102) 0x410068 VMOVHPD 0x8(%R9,%RAX,1),%XMM3,%XMM3 |
(102) 0x41006f VINSERTF128 $0x1,%XMM2,%YMM3,%YMM2 |
(102) 0x410075 VDIVPD %YMM2,%YMM1,%YMM2 |
(102) 0x410079 VMOVUPD 0x20(%R11,%R14,1),%YMM3 |
(102) 0x410080 VBLENDPD $0x3,(%R11,%R14,1),%YMM3,%YMM4 |
(102) 0x410087 VMOVUPD 0x10(%R11,%R14,1),%XMM5 |
(102) 0x41008e VMOVUPD 0x20(%R11,%R14,1),%XMM6 |
(102) 0x410095 VINSERTF128 $0x1,0x40(%R11,%R14,1),%YMM5,%YMM5 |
(102) 0x41009d VBLENDPD $0xa,%YMM5,%YMM4,%YMM7 |
(102) 0x4100a3 VSHUFPD $0x5,%YMM3,%YMM4,%YMM3 |
(102) 0x4100a8 VBROADCASTSD 0x50(%R11,%R14,1),%YMM4 |
(102) 0x4100af VBLENDPD $0xc,0x40(%R11,%R14,1),%YMM6,%YMM6 |
(102) 0x4100b7 VBLENDPD $0x8,%YMM4,%YMM3,%YMM3 |
(102) 0x4100bd VMOVUPD 0x20(%R10,%R14,1),%YMM4 |
(102) 0x4100c4 VBLENDPD $0x3,(%R10,%R14,1),%YMM4,%YMM8 |
(102) 0x4100cb VBLENDPD $0xa,%YMM6,%YMM5,%YMM5 |
(102) 0x4100d1 VMOVUPD 0x10(%R10,%R14,1),%XMM6 |
(102) 0x4100d8 VINSERTF128 $0x1,0x40(%R10,%R14,1),%YMM6,%YMM6 |
(102) 0x4100e0 VMOVUPD 0x20(%R10,%R14,1),%XMM9 |
(102) 0x4100e7 VBLENDPD $0xa,%YMM6,%YMM8,%YMM10 |
(102) 0x4100ed VSHUFPD $0x5,%YMM4,%YMM8,%YMM4 |
(102) 0x4100f2 VBROADCASTSD 0x50(%R10,%R14,1),%YMM8 |
(102) 0x4100f9 VBLENDPD $0x8,%YMM8,%YMM4,%YMM4 |
(102) 0x4100ff VBLENDPD $0xc,0x40(%R10,%R14,1),%YMM9,%YMM8 |
(102) 0x410107 VBLENDPD $0xa,%YMM8,%YMM6,%YMM6 |
(102) 0x41010d VFMADD231PD %YMM7,%YMM2,%YMM10 |
(102) 0x410112 VFMADD231PD %YMM3,%YMM2,%YMM4 |
(102) 0x410117 VFMADD231PD %YMM5,%YMM2,%YMM6 |
(102) 0x41011c VSHUFPD $0x1,%YMM4,%YMM4,%YMM2 |
(102) 0x410121 VBLENDPD $0x4,%YMM10,%YMM2,%YMM2 |
(102) 0x410127 VMOVDDUP %XMM4,%XMM3 |
(102) 0x41012b VPERM2F128 $0x20,%YMM10,%YMM3,%YMM3 |
(102) 0x410131 VSHUFPD $0x4,%YMM4,%YMM4,%YMM4 |
(102) 0x410136 VINSERTF128 $0x1,%XMM6,%YMM10,%YMM5 |
(102) 0x41013c VBLENDPD $0xa,%YMM3,%YMM5,%YMM3 |
(102) 0x410142 VPERM2F128 $0x31,%YMM6,%YMM10,%YMM5 |
(102) 0x410148 VPERM2F128 $0x31,%YMM4,%YMM6,%YMM4 |
(102) 0x41014e VBLENDPD $0xa,%YMM5,%YMM4,%YMM4 |
(102) 0x410154 VBLENDPD $0x2,%YMM6,%YMM2,%YMM2 |
(102) 0x41015a VMOVUPD %YMM2,0x20(%R10,%R14,1) |
(102) 0x410161 VMOVUPD %YMM4,0x40(%R10,%R14,1) |
(102) 0x410168 VMOVUPD %YMM3,(%R10,%R14,1) |
(102) 0x41016e ADD $0x60,%R14 |
(102) 0x410172 ADD $0x4,%RCX |
(102) 0x410176 CMP %EDX,%ECX |
(102) 0x410178 JLE 410030 |
0x41017e MOV -0x68(%RBP),%RAX |
0x410182 CMP %EAX,%R8D |
0x410185 MOV -0x60(%RBP),%RDI |
0x410189 MOV -0x38(%RBP),%RBX |
0x41018d MOV -0x40(%RBP),%R13 |
0x410191 JE 40ff00 |
0x410197 JMP 4101a3 |
0x410199 XOR %EAX,%EAX |
0x41019b MOV -0x38(%RBP),%RBX |
0x41019f MOV -0x40(%RBP),%R13 |
0x4101a3 SUB %EAX,%R8D |
0x4101a6 MOVSXD %EAX,%RDX |
0x4101a9 ADD %RSI,%RDX |
0x4101ac LEA (%RDX,%RDX,2),%RCX |
0x4101b0 LEA 0x10(,%RCX,8),%RCX |
0x4101b8 LEA (%R15,%RDX,4),%RDX |
0x4101bc XOR %R14D,%R14D |
0x4101bf NOP |
(101) 0x4101c0 MOVSXD (%RDX,%R14,4),%RAX |
(101) 0x4101c4 SAL $0x4,%RAX |
(101) 0x4101c8 VDIVSD 0x8(%R9,%RAX,1),%XMM0,%XMM2 |
(101) 0x4101cf VMOVUPD -0x10(%R11,%RCX,1),%XMM3 |
(101) 0x4101d6 VMOVDDUP %XMM2,%XMM4 |
(101) 0x4101da VFMADD213PD -0x10(%R10,%RCX,1),%XMM3,%XMM4 |
(101) 0x4101e1 VMOVUPD %XMM4,-0x10(%R10,%RCX,1) |
(101) 0x4101e8 VMOVSD (%R11,%RCX,1),%XMM3 |
(101) 0x4101ee VFMADD213SD (%R10,%RCX,1),%XMM2,%XMM3 |
(101) 0x4101f4 VMOVSD %XMM3,(%R10,%RCX,1) |
(101) 0x4101fa INC %R14 |
(101) 0x4101fd ADD $0x18,%RCX |
(101) 0x410201 CMP %R14D,%R8D |
(101) 0x410204 JNE 4101c0 |
0x410206 JMP 40ff00 |
/scratch_na/users/xoserete/qaas_runs/171-322-9862/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 85 - 96 |
-------------------------------------------------------------------------------- |
85: #pragma omp parallel for |
86: for (int iBox=0; iBox<nBoxes; iBox++) |
87: { |
88: for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++) |
89: { |
90: int iSpecies = s->atoms->iSpecies[iOff]; |
91: real_t invMass = 1.0/s->species[iSpecies].mass; |
92: s->atoms->r[iOff][0] += dt*s->atoms->p[iOff][0]*invMass; |
93: s->atoms->r[iOff][1] += dt*s->atoms->p[iOff][1]*invMass; |
94: s->atoms->r[iOff][2] += dt*s->atoms->p[iOff][2]*invMass; |
95: } |
96: } |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 14.62 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 2.18 |
Bottlenecks | micro-operation queue, |
Function | advancePosition.extracted |
Source | timestep.c:85-96 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 12.33 |
CQA cycles if no scalar integer | 12.33 |
CQA cycles if FP arith vectorized | 12.33 |
CQA cycles if fully vectorized | 0.84 |
Front-end cycles | 12.33 |
DIV/SQRT cycles | 5.50 |
P0 cycles | 5.67 |
P1 cycles | 5.33 |
P2 cycles | 5.33 |
P3 cycles | 1.00 |
P4 cycles | 5.67 |
P5 cycles | 5.50 |
P6 cycles | 1.00 |
P7 cycles | 1.00 |
P8 cycles | 1.00 |
P9 cycles | 5.67 |
P10 cycles | 5.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 12.46 |
Stall cycles (UFS) | 0.00 |
Nb insns | 74.00 |
Nb uops | 74.00 |
Nb loads | 16.00 |
Nb stores | 2.00 |
Nb stack references | 6.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 11.35 |
Bytes prefetched | 0.00 |
Bytes loaded | 124.00 |
Bytes stored | 16.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 11.11 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 10.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 14.62 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 2.18 |
Bottlenecks | micro-operation queue, |
Function | advancePosition.extracted |
Source | timestep.c:85-96 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 12.33 |
CQA cycles if no scalar integer | 12.33 |
CQA cycles if FP arith vectorized | 12.33 |
CQA cycles if fully vectorized | 0.84 |
Front-end cycles | 12.33 |
DIV/SQRT cycles | 5.50 |
P0 cycles | 5.67 |
P1 cycles | 5.33 |
P2 cycles | 5.33 |
P3 cycles | 1.00 |
P4 cycles | 5.67 |
P5 cycles | 5.50 |
P6 cycles | 1.00 |
P7 cycles | 1.00 |
P8 cycles | 1.00 |
P9 cycles | 5.67 |
P10 cycles | 5.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 12.46 |
Stall cycles (UFS) | 0.00 |
Nb insns | 74.00 |
Nb uops | 74.00 |
Nb loads | 16.00 |
Nb stores | 2.00 |
Nb stack references | 6.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 11.35 |
Bytes prefetched | 0.00 |
Bytes loaded | 124.00 |
Bytes stored | 16.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 11.11 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 10.00 |
Path / |
Function | advancePosition.extracted |
Source file and lines | timestep.c:85-96 |
Module | exec |
nb instructions | 74 |
nb uops | 74 |
loop length | 284 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 12.33 cycles |
front end | 12.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.50 | 5.67 | 5.33 | 5.33 | 1.00 | 5.67 | 5.50 | 1.00 | 1.00 | 1.00 | 5.67 | 5.33 |
cycles | 5.50 | 5.67 | 5.33 | 5.33 | 1.00 | 5.67 | 5.50 | 1.00 | 1.00 | 1.00 | 5.67 | 5.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 12.46 |
Stall cycles | 0.00 |
Front-end | 12.33 |
Dispatch | 5.67 |
Overall L1 | 12.33 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 11% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LEA 0x1(%R13),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x40,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP -0x58(%RBP),%R13 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RAX,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JE 40feb2 <advancePosition.extracted+0x72> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%RBX,%R13,1),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x70(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX,%RCX,4),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R8D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 40ff00 <advancePosition.extracted+0xc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (,%RSI,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (,%RSI,4),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R13,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RBX,%R13,1),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SAL $0x6,%R14D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV 0x20(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RDX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RDX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDX),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x1(%R8),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOVSXD %EDX,%RDX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
ADD %R14,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%RDX,%RDX,2),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R11,%RDX,1),%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x10,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x3,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R14,%R14,2),%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R10,%R14,1),%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %RBX,%R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 410010 <advancePosition.extracted+0x1d0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %R11,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R10,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD $0x10,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R14,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 410010 <advancePosition.extracted+0x1d0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%RCX,%RCX,2),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x10,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD %R12,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x38(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40ff00 <advancePosition.extracted+0xc0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %R8D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 410199 <advancePosition.extracted+0x359> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%RCX,%RCX,2),%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x1(%RAX),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %R15,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x68(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %EAX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x60(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x38(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 40ff00 <advancePosition.extracted+0xc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 4101a3 <advancePosition.extracted+0x363> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x38(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %EAX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RDX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
ADD %RSI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RDX,%RDX,2),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x10(,%RCX,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R15,%RDX,4),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R14D,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40ff00 <advancePosition.extracted+0xc0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Function | advancePosition.extracted |
Source file and lines | timestep.c:85-96 |
Module | exec |
nb instructions | 74 |
nb uops | 74 |
loop length | 284 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 12.33 cycles |
front end | 12.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.50 | 5.67 | 5.33 | 5.33 | 1.00 | 5.67 | 5.50 | 1.00 | 1.00 | 1.00 | 5.67 | 5.33 |
cycles | 5.50 | 5.67 | 5.33 | 5.33 | 1.00 | 5.67 | 5.50 | 1.00 | 1.00 | 1.00 | 5.67 | 5.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 12.46 |
Stall cycles | 0.00 |
Front-end | 12.33 |
Dispatch | 5.67 |
Overall L1 | 12.33 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 11% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LEA 0x1(%R13),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x40,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP -0x58(%RBP),%R13 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RAX,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JE 40feb2 <advancePosition.extracted+0x72> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%RBX,%R13,1),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x70(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX,%RCX,4),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R8D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 40ff00 <advancePosition.extracted+0xc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (,%RSI,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (,%RSI,4),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R13,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RBX,%R13,1),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SAL $0x6,%R14D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV 0x20(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RDX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RDX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDX),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x1(%R8),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOVSXD %EDX,%RDX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
ADD %R14,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%RDX,%RDX,2),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R11,%RDX,1),%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x10,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x3,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R14,%R14,2),%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R10,%R14,1),%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %RBX,%R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 410010 <advancePosition.extracted+0x1d0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %R11,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R10,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD $0x10,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R14,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 410010 <advancePosition.extracted+0x1d0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%RCX,%RCX,2),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x10,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD %R12,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x38(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40ff00 <advancePosition.extracted+0xc0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %R8D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 410199 <advancePosition.extracted+0x359> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%RCX,%RCX,2),%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x1(%RAX),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %R15,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x68(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %EAX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x60(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x38(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 40ff00 <advancePosition.extracted+0xc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 4101a3 <advancePosition.extracted+0x363> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x38(%RBP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %EAX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %EAX,%RDX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
ADD %RSI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RDX,%RDX,2),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x10(,%RCX,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R15,%RDX,4),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R14D,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40ff00 <advancePosition.extracted+0xc0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |