	Loop Id: 242	Module: exec	Source: advec_mom.cpp:186-211 [...]	Coverage: 4.28%

0x435a38 VMOVUPD	(%RSI,%RDX,1),%ZMM7    [2]

0x435a3f VMOVUPD	0x40(%RSI,%RDX,1),%ZMM8    [2]

0x435a47 VCMPPD	$0x1,%ZMM6,%ZMM7,%K3

0x435a4e VCMPPD	$0x1,%ZMM6,%ZMM8,%K2

0x435a55 VMOVDQA32	%ZMM17,%ZMM1

0x435a5b VPBLENDMQ	%ZMM15,%ZMM14,%ZMM4{%K3}

0x435a61 VPMULLQ	%ZMM23,%ZMM4,%ZMM5

0x435a67 VEXTRACTI32X8	$0x1,%ZMM1,%YMM0

0x435a6e VPMOVSXDQ	%YMM1,%ZMM2

0x435a74 KUNPCKBW	%K3,%K2,%K4

0x435a78 VPMOVSXDQ	%YMM0,%ZMM1

0x435a7e VPBLENDMD	%ZMM31,%ZMM24,%ZMM0{%K4}

0x435a84 VPBLENDMQ	%ZMM15,%ZMM14,%ZMM3{%K2}

0x435a8a VPMOVSXDQ	%YMM0,%ZMM26

0x435a90 VEXTRACTI32X8	$0x1,%ZMM0,%YMM0

0x435a97 VPADDQ	%ZMM2,%ZMM5,%ZMM12

0x435a9d VPMULLQ	%ZMM11,%ZMM26,%ZMM27

0x435aa3 VPMULLQ	%ZMM23,%ZMM3,%ZMM5

0x435aa9 VPBLENDMQ	%ZMM14,%ZMM15,%ZMM19{%K3}

0x435aaf VPMULLQ	%ZMM11,%ZMM4,%ZMM4

0x435ab5 VPMULLQ	%ZMM11,%ZMM3,%ZMM3

0x435abb VPMOVSXDQ	%YMM0,%ZMM0

0x435ac1 VPMULLQ	%ZMM11,%ZMM19,%ZMM19

0x435ac7 VPMULLQ	%ZMM11,%ZMM0,%ZMM0

0x435acd VPADDQ	%ZMM2,%ZMM27,%ZMM28

0x435ad3 VPADDQ	%ZMM2,%ZMM4,%ZMM4

0x435ad9 VPADDQ	%ZMM1,%ZMM3,%ZMM3

0x435adf VPBLENDMQ	%ZMM14,%ZMM15,%ZMM18{%K2}

0x435ae5 VPADDQ	%ZMM1,%ZMM0,%ZMM0

0x435aeb VPMULLQ	%ZMM11,%ZMM18,%ZMM18

0x435af1 KMOVB	%K1,%K6

0x435af5 KMOVB	%K1,%K5

0x435af9 VGATHERQPD	(%R10,%ZMM12,8),%ZMM25{%K6}    [3]

0x435b00 KMOVB	%K1,%K3

0x435b04 VPADDQ	%ZMM1,%ZMM5,%ZMM12

0x435b0a KMOVB	%K1,%K2

0x435b0e VGATHERQPD	(%RAX,%ZMM4,8),%ZMM5{%K5}    [4]

0x435b15 VGATHERQPD	(%RAX,%ZMM3,8),%ZMM4{%K3}    [4]

0x435b1c VGATHERQPD	(%RAX,%ZMM28,8),%ZMM3{%K2}    [4]

0x435b23 VPADDQ	%ZMM2,%ZMM19,%ZMM28

0x435b29 VPBLENDMD	%ZMM30,%ZMM24,%ZMM13{%K4}

0x435b2f KMOVB	%K1,%K6

0x435b33 KMOVB	%K1,%K4

0x435b37 VGATHERQPD	(%RAX,%ZMM0,8),%ZMM26{%K4}    [4]

0x435b3e VGATHERQPD	(%RAX,%ZMM28,8),%ZMM0{%K6}    [4]

0x435b45 VSUBPD	%ZMM5,%ZMM0,%ZMM0

0x435b4b VSUBPD	%ZMM3,%ZMM5,%ZMM3

0x435b51 VSUBPD	%ZMM26,%ZMM4,%ZMM27

0x435b57 VPADDQ	%ZMM1,%ZMM18,%ZMM26

0x435b5d VMULPD	%ZMM0,%ZMM3,%ZMM1

0x435b63 KMOVB	%K1,%K7

0x435b67 VGATHERQPD	(%R10,%ZMM12,8),%ZMM20{%K7}    [3]

0x435b6e KMOVB	%K1,%K7

0x435b72 VGATHERQPD	(%RAX,%ZMM26,8),%ZMM2{%K7}    [4]

0x435b79 VSUBPD	%ZMM4,%ZMM2,%ZMM2

0x435b7f VCMPPD	$0xe,%ZMM6,%ZMM1,%K3

0x435b86 VANDPD	%ZMM10,%ZMM0,%ZMM18

0x435b8c VMULPD	%ZMM2,%ZMM27,%ZMM1

0x435b92 VCMPPD	$0xe,%ZMM6,%ZMM0,%K5{%K3}

0x435b99 VANDPD	%ZMM10,%ZMM7,%ZMM0

0x435b9f VMOVAPD	%ZMM6,%ZMM28

0x435ba5 KMOVB	%K3,%K6

0x435ba9 VCMPPD	$0xe,%ZMM6,%ZMM1,%K2

0x435bb0 VANDPD	%ZMM10,%ZMM27,%ZMM1

0x435bb6 VANDPD	%ZMM10,%ZMM2,%ZMM27

0x435bbc VCMPPD	$0xe,%ZMM6,%ZMM2,%K4{%K2}

0x435bc3 VDIVPD	%ZMM25,%ZMM0,%ZMM2

0x435bc9 VANDPD	%ZMM10,%ZMM8,%ZMM25

0x435bcf VDIVPD	%ZMM20,%ZMM25,%ZMM25

0x435bd5 VSUBPD	%ZMM25,%ZMM21,%ZMM0

0x435bdb VMOVAPD	%ZMM6,%ZMM20

0x435be1 VGATHERDPD	(%R9,%YMM13,8),%ZMM20{%K6}    [1]

0x435be8 VSHUFI32X4	$-0x12,%ZMM13,%ZMM13,%ZMM13

0x435bef KMOVB	%K2,%K7

0x435bf3 VGATHERDPD	(%R9,%YMM13,8),%ZMM28{%K7}    [1]

0x435bfa VMULPD	%ZMM27,%ZMM0,%ZMM13

0x435c00 VMOVSD	(%R12),%XMM12    [5]

0x435c06 VANDPD	%ZMM10,%ZMM3,%ZMM3

0x435c0c VBROADCASTSD	%XMM12,%ZMM16

0x435c12 VMULSD	0x39b8e(%RIP),%XMM12,%XMM12    [6]

0x435c1a VDIVPD	%ZMM16,%ZMM13,%ZMM0

0x435c20 VADDPD	%ZMM9,%ZMM25,%ZMM13

0x435c26 VBLENDMPD	%ZMM9,%ZMM22,%ZMM26{%K4}

0x435c2c VBLENDMPD	%ZMM9,%ZMM22,%ZMM19{%K5}

0x435c32 VMULPD	%ZMM1,%ZMM13,%ZMM13

0x435c38 VBROADCASTSD	%XMM12,%ZMM12

0x435c3e VMINPD	%ZMM27,%ZMM1,%ZMM1

0x435c44 VPADDD	%ZMM29,%ZMM17,%ZMM17

0x435c4a VDIVPD	%ZMM28,%ZMM13,%ZMM13

0x435c50 VADDPD	%ZMM13,%ZMM0,%ZMM0

0x435c56 VMULPD	%ZMM12,%ZMM0,%ZMM13

0x435c5c VMINPD	%ZMM1,%ZMM13,%ZMM0

0x435c62 VSUBPD	%ZMM2,%ZMM21,%ZMM1

0x435c68 VSUBPD	%ZMM25,%ZMM9,%ZMM13

0x435c6e VMULPD	%ZMM18,%ZMM1,%ZMM1

0x435c74 VMULPD	%ZMM26,%ZMM13,%ZMM13

0x435c7a VDIVPD	%ZMM16,%ZMM1,%ZMM1

0x435c80 VADDPD	%ZMM9,%ZMM2,%ZMM16

0x435c86 VSUBPD	%ZMM2,%ZMM9,%ZMM2

0x435c8c VFMADD231PD	%ZMM13,%ZMM0,%ZMM4{%K2}

0x435c92 VMULPD	%ZMM3,%ZMM16,%ZMM27

0x435c98 VMINPD	%ZMM18,%ZMM3,%ZMM3

0x435c9e VMULPD	%ZMM8,%ZMM4,%ZMM8

0x435ca4 VDIVPD	%ZMM20,%ZMM27,%ZMM26

0x435caa VADDPD	%ZMM26,%ZMM1,%ZMM1

0x435cb0 VMULPD	%ZMM12,%ZMM1,%ZMM12

0x435cb6 VMOVUPD	%ZMM8,0x40(%RCX,%RDX,1)    [7]

0x435cbe VMINPD	%ZMM3,%ZMM12,%ZMM1

0x435cc4 VMULPD	%ZMM19,%ZMM2,%ZMM12

0x435cca VFMADD231PD	%ZMM12,%ZMM1,%ZMM5{%K3}

0x435cd0 VMULPD	%ZMM5,%ZMM7,%ZMM7

0x435cd6 VMOVUPD	%ZMM7,(%RCX,%RDX,1)    [7]

0x435cdd SUB	$-0x80,%RDX

0x435ce1 CMP	%RDI,%RDX

0x435ce4 JNE	435a38

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 186 - 211

--------------------------------------------------------------------------------

186:           if (node_flux(i, j) < 0.0) {

[...]

197:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(i, donor));

198:           width = celldy[j];

199:           vdiffuw = vel1(i, donor) - vel1(i, upwind);

200:           vdiffdw = vel1(i, downwind) - vel1(i, donor);

201:           limiter = 0.0;

202:           if (vdiffuw * vdiffdw > 0.0) {

203:             auw = std::fabs(vdiffuw);

204:             adw = std::fabs(vdiffdw);

205:             wind = 1.0;

206:             if (vdiffdw <= 0.0) wind = -1.0;

207:             limiter =

208:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldy[dif]) / 6.0, auw), adw);

209:           }

210:           advec_vel_s = vel1(i, donor) + (1.0 - sigma) * limiter;

211:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○97.63	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.37	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.27
Bottlenecks	P0,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.10]
Source	advec_mom.cpp:186-186,advec_mom.cpp:197-211,context.h:69-69
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	96.00
CQA cycles if no scalar integer	96.00
CQA cycles if FP arith vectorized	96.00
CQA cycles if fully vectorized	96.00
Front-end cycles	33.00
P0 cycles	75.50
P1 cycles	13.50
P2 cycles	28.00
P3 cycles	28.00
P4 cycles	1.00
P5 cycles	75.50
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	0.00
P11 cycles	28.00
DIV/SQRT cycles	96.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	115.00
Nb uops	198.00
Nb loads	14.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.84
Nb FLOP add-sub	96.00
Nb FLOP mul	97.00
Nb FLOP fma	16.00
Nb FLOP div	48.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.50
Bytes prefetched	0.00
Bytes loaded	784.00
Bytes stored	128.00
Stride 0	2.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	3.00
Vectorization ratio all	96.04
Vectorization ratio load	85.71
Vectorization ratio store	100.00
Vectorization ratio mul	95.24
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	95.65
Vector-efficiency ratio all	93.07
Vector-efficiency ratio load	87.50
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	95.83
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	88.59

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.27
Bottlenecks	P0,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.10]
Source	advec_mom.cpp:186-186,advec_mom.cpp:197-211,context.h:69-69
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	96.00
CQA cycles if no scalar integer	96.00
CQA cycles if FP arith vectorized	96.00
CQA cycles if fully vectorized	96.00
Front-end cycles	33.00
P0 cycles	75.50
P1 cycles	13.50
P2 cycles	28.00
P3 cycles	28.00
P4 cycles	1.00
P5 cycles	75.50
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	0.00
P11 cycles	28.00
DIV/SQRT cycles	96.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	115.00
Nb uops	198.00
Nb loads	14.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.84
Nb FLOP add-sub	96.00
Nb FLOP mul	97.00
Nb FLOP fma	16.00
Nb FLOP div	48.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.50
Bytes prefetched	0.00
Bytes loaded	784.00
Bytes stored	128.00
Stride 0	2.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	3.00
Vectorization ratio all	96.04
Vectorization ratio load	85.71
Vectorization ratio store	100.00
Vectorization ratio mul	95.24
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	95.65
Vector-efficiency ratio all	93.07
Vector-efficiency ratio load	87.50
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	95.83
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	88.59

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.10]
Source file and lines	advec_mom.cpp:186-211
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:186,197-211
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

It is main loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 93% of vector register length is used (average across all SSE/AVX instructions).

Details

96% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

85% of SSE/AVX loads are used in vector version.
95% of SSE/AVX multiply instructions are used in vector version.
95% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 96.00 to 75.50 cycles (1.27x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 96.00 to 66.50 cycles (1.44x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPD: 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:197
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:197
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:208
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:208
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:208
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:208
VGATHERDPD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:208
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:208
VGATHERQPD: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:197
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:199
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:199
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:199
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:199
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:200
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:197
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:200
VPMULLQ: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:208
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:208
VGATHERQPD: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:197
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:199
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:199
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:199
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:199
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:200
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:197
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:200

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 42 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 273 FP arithmetical operations:

112: addition or subtraction (16 inside FMA instructions)
113: multiply (16 inside FMA instructions)
48: divide

The binary loop is loading 784 bytes (98 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.30 FP operations per loaded or stored byte.

General properties

nb instructions	115
nb uops	198
loop length	690
used x86 registers	8
used mmx registers	0
used xmm registers	1
used ymm registers	3
used zmm registers	32
nb stack references	0
ADD-SUB / MUL ratio	0.92

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	33.00 cycles
front end	33.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	75.50	1.00	28.00	28.00	1.00	75.50	1.00	1.00	1.00	1.00	0.00	28.00
cycles	75.50	13.50	28.00	28.00	1.00	75.50	1.00	1.00	1.00	1.00	0.00	28.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	96.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	33.00
Dispatch	75.50
DIV/SQRT	96.00
Data deps.	1.00
Overall L1	96.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	94%
load	85%
store	100%
mul	92%
add-sub	100%
fma	100%
div/sqrt	100%
other	93%

INT+FP

all	96%
load	85%
store	100%
mul	95%
add-sub	100%
fma	100%
div/sqrt	100%
other	95%

Vector efficiency ratios

INT

all	88%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	75%

all	95%
load	87%
store	100%
mul	93%
add-sub	100%
fma	100%
div/sqrt	100%
other	94%

INT+FP

all	93%
load	87%
store	100%
mul	95%
add-sub	100%
fma	100%
div/sqrt	100%
other	88%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 96.00 cycles. At this rate:

4% of peak load performance is reached (8.17 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 435a38

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD (%RSI,%RDX,1),%ZMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD 0x40(%RSI,%RDX,1),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM6,%ZMM7,%K3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VCMPPD $0x1,%ZMM6,%ZMM8,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VMOVDQA32 %ZMM17,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VPBLENDMQ %ZMM15,%ZMM14,%ZMM4{%K3}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPMULLQ %ZMM23,%ZMM4,%ZMM5	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VEXTRACTI32X8 $0x1,%ZMM1,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM1,%ZMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
KUNPCKBW %K3,%K2,%K4	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
VPMOVSXDQ %YMM0,%ZMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPBLENDMD %ZMM31,%ZMM24,%ZMM0{%K4}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPBLENDMQ %ZMM15,%ZMM14,%ZMM3{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPMOVSXDQ %YMM0,%ZMM26	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VEXTRACTI32X8 $0x1,%ZMM0,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPADDQ %ZMM2,%ZMM5,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPMULLQ %ZMM11,%ZMM26,%ZMM27	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPMULLQ %ZMM23,%ZMM3,%ZMM5	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPBLENDMQ %ZMM14,%ZMM15,%ZMM19{%K3}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPMULLQ %ZMM11,%ZMM4,%ZMM4	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPMULLQ %ZMM11,%ZMM3,%ZMM3	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPMOVSXDQ %YMM0,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMULLQ %ZMM11,%ZMM19,%ZMM19	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPMULLQ %ZMM11,%ZMM0,%ZMM0	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPADDQ %ZMM2,%ZMM27,%ZMM28	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM2,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM1,%ZMM3,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPBLENDMQ %ZMM14,%ZMM15,%ZMM18{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM1,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPMULLQ %ZMM11,%ZMM18,%ZMM18	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%R10,%ZMM12,8),%ZMM25{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
KMOVB %K1,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VPADDQ %ZMM1,%ZMM5,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RAX,%ZMM4,8),%ZMM5{%K5}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RAX,%ZMM3,8),%ZMM4{%K3}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RAX,%ZMM28,8),%ZMM3{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM2,%ZMM19,%ZMM28	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPBLENDMD %ZMM30,%ZMM24,%ZMM13{%K4}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RAX,%ZMM0,8),%ZMM26{%K4}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RAX,%ZMM28,8),%ZMM0{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM5,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM3,%ZMM5,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM26,%ZMM4,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VPADDQ %ZMM1,%ZMM18,%ZMM26	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM0,%ZMM3,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%R10,%ZMM12,8),%ZMM20{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RAX,%ZMM26,8),%ZMM2{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM4,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VCMPPD $0xe,%ZMM6,%ZMM1,%K3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VANDPD %ZMM10,%ZMM0,%ZMM18	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM2,%ZMM27,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0xe,%ZMM6,%ZMM0,%K5{%K3}	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VANDPD %ZMM10,%ZMM7,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVAPD %ZMM6,%ZMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
KMOVB %K3,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VCMPPD $0xe,%ZMM6,%ZMM1,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VANDPD %ZMM10,%ZMM27,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM2,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VCMPPD $0xe,%ZMM6,%ZMM2,%K4{%K2}	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VDIVPD %ZMM25,%ZMM0,%ZMM2	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VANDPD %ZMM10,%ZMM8,%ZMM25	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VDIVPD %ZMM20,%ZMM25,%ZMM25	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VSUBPD %ZMM25,%ZMM21,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM6,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VGATHERDPD (%R9,%YMM13,8),%ZMM20{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSHUFI32X4 $-0x12,%ZMM13,%ZMM13,%ZMM13	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
KMOVB %K2,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERDPD (%R9,%YMM13,8),%ZMM28{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VMULPD %ZMM27,%ZMM0,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVSD (%R12),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VANDPD %ZMM10,%ZMM3,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VBROADCASTSD %XMM12,%ZMM16	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMULSD 0x39b8e(%RIP),%XMM12,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VDIVPD %ZMM16,%ZMM13,%ZMM0	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VADDPD %ZMM9,%ZMM25,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VBLENDMPD %ZMM9,%ZMM22,%ZMM26{%K4}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VBLENDMPD %ZMM9,%ZMM22,%ZMM19{%K5}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM13,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VBROADCASTSD %XMM12,%ZMM12	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMINPD %ZMM27,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPADDD %ZMM29,%ZMM17,%ZMM17	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VDIVPD %ZMM28,%ZMM13,%ZMM13	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VADDPD %ZMM13,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM12,%ZMM0,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM1,%ZMM13,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VSUBPD %ZMM2,%ZMM21,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM25,%ZMM9,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM18,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM26,%ZMM13,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VDIVPD %ZMM16,%ZMM1,%ZMM1	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VADDPD %ZMM9,%ZMM2,%ZMM16	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM2,%ZMM9,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VFMADD231PD %ZMM13,%ZMM0,%ZMM4{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM3,%ZMM16,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMINPD %ZMM18,%ZMM3,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM8,%ZMM4,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VDIVPD %ZMM20,%ZMM27,%ZMM26	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VADDPD %ZMM26,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM12,%ZMM1,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM8,0x40(%RCX,%RDX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMINPD %ZMM3,%ZMM12,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM19,%ZMM2,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM12,%ZMM1,%ZMM5{%K3}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM5,%ZMM7,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM7,(%RCX,%RDX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
SUB $-0x80,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 435a38 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x248>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.10]
Source file and lines	advec_mom.cpp:186-211
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:186,197-211
/home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

It is main loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 93% of vector register length is used (average across all SSE/AVX instructions).

Details

96% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

85% of SSE/AVX loads are used in vector version.
95% of SSE/AVX multiply instructions are used in vector version.
95% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 96.00 to 66.50 cycles (1.44x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPD: 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:197
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:197
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:208
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:208
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:208
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:208
VGATHERDPD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:208
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:208
VGATHERQPD: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:197
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:199
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:199
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:199
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:199
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:200
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:197
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:200
VPMULLQ: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:208
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:208
VGATHERQPD: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:197
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:199
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:199
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:199
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:199
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:200
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:197
- /home/eoseret/qaas_runs_GNR/173-814-2343/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:200

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 273 FP arithmetical operations:

112: addition or subtraction (16 inside FMA instructions)
113: multiply (16 inside FMA instructions)
48: divide

The binary loop is loading 784 bytes (98 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.30 FP operations per loaded or stored byte.

General properties

nb instructions	115
nb uops	198
loop length	690
used x86 registers	8
used mmx registers	0
used xmm registers	1
used ymm registers	3
used zmm registers	32
nb stack references	0
ADD-SUB / MUL ratio	0.92

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	33.00 cycles
front end	33.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	75.50	1.00	28.00	28.00	1.00	75.50	1.00	1.00	1.00	1.00	0.00	28.00
cycles	75.50	13.50	28.00	28.00	1.00	75.50	1.00	1.00	1.00	1.00	0.00	28.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	96.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	33.00
Dispatch	75.50
DIV/SQRT	96.00
Data deps.	1.00
Overall L1	96.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	94%
load	85%
store	100%
mul	92%
add-sub	100%
fma	100%
div/sqrt	100%
other	93%

INT+FP

all	96%
load	85%
store	100%
mul	95%
add-sub	100%
fma	100%
div/sqrt	100%
other	95%

Vector efficiency ratios

INT

all	88%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	75%

all	95%
load	87%
store	100%
mul	93%
add-sub	100%
fma	100%
div/sqrt	100%
other	94%

INT+FP

all	93%
load	87%
store	100%
mul	95%
add-sub	100%
fma	100%
div/sqrt	100%
other	88%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 96.00 cycles. At this rate:

4% of peak load performance is reached (8.17 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 435a38

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD (%RSI,%RDX,1),%ZMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD 0x40(%RSI,%RDX,1),%ZMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VCMPPD $0x1,%ZMM6,%ZMM7,%K3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VCMPPD $0x1,%ZMM6,%ZMM8,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VMOVDQA32 %ZMM17,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VPBLENDMQ %ZMM15,%ZMM14,%ZMM4{%K3}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPMULLQ %ZMM23,%ZMM4,%ZMM5	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VEXTRACTI32X8 $0x1,%ZMM1,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMOVSXDQ %YMM1,%ZMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
KUNPCKBW %K3,%K2,%K4	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
VPMOVSXDQ %YMM0,%ZMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPBLENDMD %ZMM31,%ZMM24,%ZMM0{%K4}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPBLENDMQ %ZMM15,%ZMM14,%ZMM3{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPMOVSXDQ %YMM0,%ZMM26	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VEXTRACTI32X8 $0x1,%ZMM0,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPADDQ %ZMM2,%ZMM5,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPMULLQ %ZMM11,%ZMM26,%ZMM27	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPMULLQ %ZMM23,%ZMM3,%ZMM5	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPBLENDMQ %ZMM14,%ZMM15,%ZMM19{%K3}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPMULLQ %ZMM11,%ZMM4,%ZMM4	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPMULLQ %ZMM11,%ZMM3,%ZMM3	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPMOVSXDQ %YMM0,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VPMULLQ %ZMM11,%ZMM19,%ZMM19	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPMULLQ %ZMM11,%ZMM0,%ZMM0	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPADDQ %ZMM2,%ZMM27,%ZMM28	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM2,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM1,%ZMM3,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPBLENDMQ %ZMM14,%ZMM15,%ZMM18{%K2}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM1,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPMULLQ %ZMM11,%ZMM18,%ZMM18	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K5	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%R10,%ZMM12,8),%ZMM25{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
KMOVB %K1,%K3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VPADDQ %ZMM1,%ZMM5,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RAX,%ZMM4,8),%ZMM5{%K5}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RAX,%ZMM3,8),%ZMM4{%K3}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RAX,%ZMM28,8),%ZMM3{%K2}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VPADDQ %ZMM2,%ZMM19,%ZMM28	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPBLENDMD %ZMM30,%ZMM24,%ZMM13{%K4}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KMOVB %K1,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
KMOVB %K1,%K4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RAX,%ZMM0,8),%ZMM26{%K4}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VGATHERQPD (%RAX,%ZMM28,8),%ZMM0{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM5,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM3,%ZMM5,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPD %ZMM26,%ZMM4,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VPADDQ %ZMM1,%ZMM18,%ZMM26	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM0,%ZMM3,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%R10,%ZMM12,8),%ZMM20{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
KMOVB %K1,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERQPD (%RAX,%ZMM26,8),%ZMM2{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSUBPD %ZMM4,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VCMPPD $0xe,%ZMM6,%ZMM1,%K3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VANDPD %ZMM10,%ZMM0,%ZMM18	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM2,%ZMM27,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VCMPPD $0xe,%ZMM6,%ZMM0,%K5{%K3}	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VANDPD %ZMM10,%ZMM7,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVAPD %ZMM6,%ZMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
KMOVB %K3,%K6	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VCMPPD $0xe,%ZMM6,%ZMM1,%K2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VANDPD %ZMM10,%ZMM27,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VANDPD %ZMM10,%ZMM2,%ZMM27	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VCMPPD $0xe,%ZMM6,%ZMM2,%K4{%K2}	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VDIVPD %ZMM25,%ZMM0,%ZMM2	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VANDPD %ZMM10,%ZMM8,%ZMM25	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VDIVPD %ZMM20,%ZMM25,%ZMM25	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VSUBPD %ZMM25,%ZMM21,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM6,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (100.0%)
VGATHERDPD (%R9,%YMM13,8),%ZMM20{%K6}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VSHUFI32X4 $-0x12,%ZMM13,%ZMM13,%ZMM13	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
KMOVB %K2,%K7	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VGATHERDPD (%R9,%YMM13,8),%ZMM28{%K7}	5	1	0	2.67	2.67	0	2	0	0	0	0	0	2.67	28	3	vect (100.0%)
VMULPD %ZMM27,%ZMM0,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVSD (%R12),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VANDPD %ZMM10,%ZMM3,%ZMM3	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VBROADCASTSD %XMM12,%ZMM16	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMULSD 0x39b8e(%RIP),%XMM12,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VDIVPD %ZMM16,%ZMM13,%ZMM0	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VADDPD %ZMM9,%ZMM25,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VBLENDMPD %ZMM9,%ZMM22,%ZMM26{%K4}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VBLENDMPD %ZMM9,%ZMM22,%ZMM19{%K5}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMULPD %ZMM1,%ZMM13,%ZMM13	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VBROADCASTSD %XMM12,%ZMM12	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMINPD %ZMM27,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VPADDD %ZMM29,%ZMM17,%ZMM17	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VDIVPD %ZMM28,%ZMM13,%ZMM13	3	2.50	0	0	0	0	0.50	0	0	0	0	0	0	22-24	16	vect (100.0%)
VADDPD %ZMM13,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMULPD %ZMM12,%ZMM0,%ZMM13	1	0.50	0	0	0	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMINPD %ZMM3,%ZMM12,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM19,%ZMM2,%ZMM12	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM12,%ZMM1,%ZMM5{%K3}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM5,%ZMM7,%ZMM7	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VMOVUPD %ZMM7,(%RCX,%RDX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
SUB $-0x80,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 435a38 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x248>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code