Function: calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2 ... | Module: exec | Source: calc_dt.cpp:49-75 | Coverage: 4.43% |
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Function: calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2 ... | Module: exec | Source: calc_dt.cpp:49-75 | Coverage: 4.43% |
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/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/calc_dt.cpp: 49 - 75 |
-------------------------------------------------------------------------------- |
49: #pragma omp parallel for simd collapse(2) reduction(min : dt_min_val0) |
50: for (int j = (y_min + 1); j < (y_max + 2); j++) { |
51: for (int i = (x_min + 1); i < (x_max + 2); i++) { |
52: double dsx = celldx[i]; |
53: double dsy = celldy[j]; |
54: double cc = soundspeed(i, j) * soundspeed(i, j); |
55: cc = cc + 2.0 * viscosity_a(i, j) / density0(i, j); |
56: cc = std::fmax(std::sqrt(cc), g_small); |
57: double dtct = dtc_safe * std::fmin(dsx, dsy) / cc; |
58: double div = 0.0; |
59: double dv1 = (xvel0(i, j) + xvel0(i + 0, j + 1)) * xarea(i, j); |
60: double dv2 = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) * xarea(i + 1, j + 0); |
61: div = div + dv2 - dv1; |
62: double dtut = dtu_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j)); |
63: dv1 = (yvel0(i, j) + yvel0(i + 1, j + 0)) * yarea(i, j); |
64: dv2 = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) * yarea(i + 0, j + 1); |
65: div = div + dv2 - dv1; |
66: double dtvt = dtv_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j)); |
67: div = div / (2.0 * volume(i, j)); |
68: double dtdivt; |
69: if (div < -g_small) { |
70: dtdivt = dtdiv_safe * (-1.0 / div); |
71: } else { |
72: dtdivt = g_big; |
73: } |
74: double mins = std::fmin(dtct, std::fmin(dtut, std::fmin(dtvt, std::fmin(dtdivt, g_big)))); |
75: dt_min_val0 = std::fmin(mins, dt_min_val0); |
0x424300 ADRP X1, |
0x424304 STP X29, X30, [SP, #848]! |
0x424308 ADD X29, SP, #0 |
0x42430c LDR X3, [X1, #3864] |
0x424310 STP X19, X20, [SP, #16] |
0x424314 ORR X19, XZR, X0 |
0x424318 STP X23, X24, [SP, #48] |
0x42431c LDP W23, W2, [X0, #128] |
0x424320 STP D8, D9, [SP, #96] |
0x424324 STP D10, D11, [SP, #112] |
0x424328 LDR X0, [X3] |
0x42432c STR X0, [SP, #168] |
0x424330 MOVZ X0, #0 |
0x424334 LDP W5, W0, [X19, #120] |
0x424338 ADD W4, W2, #2 |
0x42433c ADD W23, W23, #1 |
0x424340 LDP D8, D11, [X19] |
0x424344 STR W4, [SP, #152] |
0x424348 ADD W6, W5, #1 |
0x42434c LDP D10, D9, [X19, #16] |
0x424350 STR W6, [SP, #136] |
0x424354 CMP W23, W4 |
0x424358 B.GE 424748 |
0x42435c LDR W8, [SP, #152] |
0x424360 STP X21, X22, [SP, #32] |
0x424364 ADD W21, W0, #2 |
0x424368 LDR W9, [SP, #136] |
0x42436c SUB W24, W8, W23 |
0x424370 CMP W9, W21 |
0x424374 B.GE 424610 |
0x424378 SUB W20, W21, W9 |
0x42437c BL 403530 |
0x424380 MADD W24, W24, W20, WZR |
0x424384 ORR W22, WZR, W0 |
0x424388 BL 4033c0 |
0x42438c UDIV W11, W24, W22 |
0x424390 MSUB W10, W11, W22, W24 |
0x424394 CMP W0, W10 |
0x424398 B.CC 424724 |
0x42439c MADD W13, W11, W0, W10 |
0x4243a0 ADD W12, W11, W13 |
0x4243a4 STR W12, [SP, #156] |
0x4243a8 CMP W13, W12 |
0x4243ac B.CS 424610 |
0x4243b0 UDIV W14, W13, W20 |
0x4243b4 ADRP X18, |
0x4243b8 STP X27, X28, [SP, #80] |
0x4243bc ADRP X17, |
0x4243c0 ADRP X16, |
0x4243c4 FADD D7, D11, D11 |
0x4243c8 MOVN X15, #32784 |
0x4243cc FADD D6, D10, D10 |
0x4243d0 FMOV D18, #0.5000000 |
0x4243d4 LDR W28, [SP, #136] |
0x4243d8 FMOV D19, #-1.0000000 |
0x4243dc STP X25, X26, [SP, #64] |
0x4243e0 LDR D17, [X18, #152] |
0x4243e4 LDP X3, X18, [X19, #48] |
0x4243e8 MSUB W2, W14, W20, W13 |
0x4243ec ADD W23, W14, W23 |
0x4243f0 SBFM X5, X23, #0, #31 |
0x4243f4 FMOV D1, X15 |
0x4243f8 SUB W0, W23, W5 |
0x4243fc LDR D5, [X17, #1976] |
0x424400 ORR X10, XZR, X5 |
0x424404 ADD W12, W2, W28 |
0x424408 STR X3, [SP, #144] |
0x42440c SUB W17, W21, W12 |
0x424410 STR W0, [SP, #140] |
0x424414 CMP W11, W17 |
0x424418 CSEL W6, W11, W17, #9 |
0x42441c ADD W17, W13, W6 |
0x424420 LDR D4, [X16, #256] |
0x424424 ADD X16, X5, #1 |
0x424428 LDP X27, X26, [X19, #32] |
0x42442c LDP X25, X24, [X19, #64] |
0x424430 LDR X23, [X19, #80] |
0x424434 LDR X22, [X19, #88] |
0x424438 LDR X21, [X19, #96] |
0x42443c LDR X30, [X19, #104] |
0x424440 CMP W13, W17 |
0x424444 B.CS 4246d0 |
(297) 0x424448 SBFM X0, X12, #0, #31 |
(297) 0x42444c ADD W1, W12, #1 |
(297) 0x424450 LDR X11, [X22] |
(297) 0x424454 SUB W7, W6, #1 |
(297) 0x424458 ADD X2, X0, #1 |
(297) 0x42445c ADD X6, X7, X2 |
(297) 0x424460 SBFM X1, X1, #0, #31 |
(297) 0x424464 LDR X28, [X23] |
(297) 0x424468 STR X1, [SP, #128] |
(297) 0x42446c LDR X9, [X21] |
(297) 0x424470 MADD X13, X10, X11, XZR |
(297) 0x424474 LDR X5, [X24] |
(297) 0x424478 MADD X4, X10, X28, XZR |
(297) 0x42447c LDR X11, [X25] |
(297) 0x424480 UBFM X15, X9, #61, #60 |
(297) 0x424484 LDR X8, [X18, #8] |
(297) 0x424488 LDR X12, [X22, #16] |
(297) 0x42448c LDR X3, [X23, #16] |
(297) 0x424490 LDR X9, [X21, #16] |
(297) 0x424494 ADD X14, X12, X13,LSL #3 |
(297) 0x424498 LDR X7, [X24, #16] |
(297) 0x42449c ADD X13, X3, X4,LSL #3 |
(297) 0x4244a0 LDR X28, [X25, #16] |
(297) 0x4244a4 MADD X3, X10, X11, XZR |
(297) 0x4244a8 LDR D16, [X8, X10,LSL #3] |
(297) 0x4244ac MADD X8, X10, X5, XZR |
(297) 0x4244b0 LDR X4, [X27] |
(297) 0x4244b4 ADD X12, X7, X8,LSL #3 |
(297) 0x4244b8 ADD X11, X28, X3,LSL #3 |
(297) 0x4244bc LDR X28, [X30] |
(297) 0x4244c0 MADD X8, X10, X15, X9 |
(297) 0x4244c4 MADD X3, X16, X15, X9 |
(297) 0x4244c8 LDR X15, [X26] |
(297) 0x4244cc MADD X7, X10, X4, XZR |
(297) 0x4244d0 LDR X5, [X27, #16] |
(297) 0x4244d4 LDR X1, [X26, #16] |
(297) 0x4244d8 UBFM X9, X15, #61, #60 |
(297) 0x4244dc LDR X15, [X30, #16] |
(297) 0x4244e0 ADD X4, X5, X7,LSL #3 |
(297) 0x4244e4 UBFM X5, X28, #61, #60 |
(297) 0x4244e8 LDR X28, [X26, #16] |
(297) 0x4244ec MADD X7, X10, X5, X15 |
(297) 0x4244f0 MADD X5, X16, X5, X15 |
(297) 0x4244f4 LDR X15, [SP, #144] |
(297) 0x4244f8 MADD X28, X10, X9, X28 |
(297) 0x4244fc MADD X9, X16, X9, X1 |
(297) 0x424500 LDR X1, [SP, #128] |
(297) 0x424504 LDR X15, [X15, #8] |
(297) 0x424508 LDR D0, [X8, X1,LSL #3] |
(297) 0x42450c LDR D2, [X3, X1,LSL #3] |
(297) 0x424510 LDR D21, [X5, X0,LSL #3] |
(297) 0x424514 LDR D3, [X5, X1,LSL #3] |
(297) 0x424518 FADD D23, D0, D2 |
(297) 0x42451c LDR D22, [X4, X1,LSL #3] |
(297) 0x424520 LDR D25, [X9, X0,LSL #3] |
(297) 0x424524 FADD D26, D21, D3 |
(297) 0x424528 LDR D27, [X8, X0,LSL #3] |
(297) 0x42452c LDR D20, [X3, X0,LSL #3] |
(297) 0x424530 FMUL D28, D23, D22 |
(297) 0x424534 LDR D24, [X4, X0,LSL #3] |
(297) 0x424538 FMUL D29, D26, D25 |
(297) 0x42453c LDR D30, [X7, X0,LSL #3] |
(297) 0x424540 FADD D31, D27, D20 |
(297) 0x424544 LDR D11, [X7, X1,LSL #3] |
(297) 0x424548 FABS D10, D28 |
(297) 0x42454c LDR D22, [X28, X0,LSL #3] |
(297) 0x424550 FADD D0, D28, D29 |
(297) 0x424554 LDR D21, [X13, X0,LSL #3] |
(297) 0x424558 FABS D25, D29 |
(297) 0x42455c FMUL D3, D31, D24 |
(297) 0x424560 FADD D2, D30, D11 |
(297) 0x424564 LDR D28, [X12, X0,LSL #3] |
(297) 0x424568 LDR D23, [X11, X0,LSL #3] |
(297) 0x42456c FADD D24, D21, D21 |
(297) 0x424570 LDR D26, [X15, X0,LSL #3] |
(297) 0x424574 FMINNM D27, D16, D26 |
(297) 0x424578 FMUL D20, D27, D8 |
(297) 0x42457c FMUL D31, D2, D22 |
(297) 0x424580 FSUB D30, D0, S3 |
(297) 0x424584 LDR D29, [X14, X0,LSL #3] |
(297) 0x424588 FABS D11, D3 |
(297) 0x42458c FMAXNM D10, D11, D10 |
(297) 0x424590 FMUL D26, D23, D4 |
(297) 0x424594 FMUL D22, D7, D23 |
(297) 0x424598 FMAXNM D3, D10, D26 |
(297) 0x42459c FMUL D21, D6, D23 |
(297) 0x4245a0 FDIV D28, D24, D28 |
(297) 0x4245a4 FSUB D0, D30, S31 |
(297) 0x4245a8 FABS D2, D31 |
(297) 0x4245ac FMAXNM D25, D2, D25 |
(297) 0x4245b0 FMAXNM D24, D25, D26 |
(297) 0x4245b4 FDIV D30, D22, D3 |
(297) 0x4245b8 FMUL D31, D0, D18 |
(297) 0x4245bc FDIV D27, D21, D24 |
(297) 0x4245c0 FMINNM D11, D30, D27 |
(297) 0x4245c4 FMADD D29, D29, D29, D28 |
(297) 0x4245c8 FDIV D23, D31, D23 |
(297) 0x4245cc FSQRT D22, D29 |
(297) 0x4245d0 FMAXNM D21, D22, D4 |
(297) 0x4245d4 FDIV D20, D20, D21 |
(297) 0x4245d8 FMINNM D10, D20, D5 |
(297) 0x4245dc FMINNM D26, D11, D10 |
(297) 0x4245e0 FCMPE D23, D17 |
(297) 0x4245e4 B.GE 424674 |
(297) 0x4245e8 FDIV D3, D19, D23 |
(297) 0x4245ec ADD X1, X1, #1 |
(297) 0x4245f0 ORR X0, XZR, X2 |
(297) 0x4245f4 FMUL D28, D3, D9 |
(297) 0x4245f8 FMINNM D0, D28, D1 |
(297) 0x4245fc FMINNM D1, D0, D26 |
(297) 0x424600 CMP X6, X2 |
(297) 0x424604 B.EQ 42468c |
(299) 0x424608 ADD X2, X2, #1 |
(299) 0x42460c B 424508 |
0x424610 MOVN X13, #32784 |
0x424614 LDP X21, X22, [SP, #32] |
0x424618 FMOV D7, X13 |
(296) 0x42461c ADD X19, X19, #112 |
(296) 0x424620 LDR X1, [X19] |
(293) 0x424624 FMOV D6, X1 |
(293) 0x424628 ORR X30, XZR, X1 |
(293) 0x42462c FMINNM D4, D7, D6 |
(293) 0x424630 FMOV X24, D4 |
(293) 0x424634 CASAL X30, X24, [X19] |
(293) 0x424638 CMP X1, X30 |
(293) 0x42463c B.NE 424730 |
(296) 0x424640 ADRP X23, |
(296) 0x424644 LDR X8, [X23, #3864] |
(296) 0x424648 LDR X2, [SP, #168] |
(296) 0x42464c LDR X1, [X8] |
(296) 0x424650 SUBS X2, X2, X1 |
(296) 0x424654 MOVZ X1, #0 |
(296) 0x424658 B.NE 424738 |
(296) 0x42465c LDP X19, X20, [SP, #16] |
(296) 0x424660 LDP X23, X24, [SP, #48] |
(296) 0x424664 LDP D8, D9, [SP, #96] |
(296) 0x424668 LDP D10, D11, [SP, #112] |
(296) 0x42466c LDP X29, X30, [SP], #176 |
(296) 0x424670 RET |
(295) 0x424674 FMINNM D1, D1, D5 |
(295) 0x424678 ADD X1, X1, #1 |
(295) 0x42467c ORR X0, XZR, X2 |
(295) 0x424680 FMINNM D1, D1, D26 |
(295) 0x424684 CMP X6, X2 |
(295) 0x424688 B.NE 424608 |
(297) 0x42468c LDR W2, [SP, #140] |
(297) 0x424690 ADD X10, X10, #1 |
(297) 0x424694 ADD X16, X16, #1 |
(297) 0x424698 LDR W6, [SP, #152] |
(297) 0x42469c ADD W14, W2, W10 |
(297) 0x4246a0 CMP W6, W14 |
(297) 0x4246a4 B.LE 4246f0 |
(298) 0x4246a8 LDR W11, [SP, #156] |
(298) 0x4246ac ORR W13, WZR, W17 |
(298) 0x4246b0 LDR W12, [SP, #136] |
(298) 0x4246b4 SUB W11, W11, W17 |
(298) 0x4246b8 ORR W17, WZR, W20 |
(298) 0x4246bc CMP W11, W17 |
(298) 0x4246c0 CSEL W6, W11, W17, #9 |
(298) 0x4246c4 ADD W17, W13, W6 |
(298) 0x4246c8 CMP W13, W17 |
(298) 0x4246cc B.CC 424448 |
(298) 0x4246d0 LDR W2, [SP, #140] |
(298) 0x4246d4 ADD X10, X10, #1 |
(298) 0x4246d8 ORR W17, WZR, W13 |
(298) 0x4246dc ADD X16, X16, #1 |
(298) 0x4246e0 LDR W6, [SP, #152] |
(298) 0x4246e4 ADD W14, W2, W10 |
(298) 0x4246e8 CMP W6, W14 |
(298) 0x4246ec B.GT 4246a8 |
(296) 0x4246f0 PTRUE P0.B, VL1 |
(296) 0x4246f4 MOVN X20, #32784 |
(296) 0x4246f8 ADD X18, SP, #160 |
(296) 0x4246fc PTRUE P1.B, ALL |
(296) 0x424700 DUP Z8.D, X20 |
(296) 0x424704 STR D1, [SP, #160] |
(296) 0x424708 LD1D {Z9.D}, P0/Z, [X18, MUL VL] |
(296) 0x42470c FMINNM Z8.D, P0/M, Z8.D, Z9.D |
(296) 0x424710 FMINNMV D7, P1, Z8.D |
(296) 0x424714 LDP X21, X22, [SP, #32] |
(296) 0x424718 LDP X25, X26, [SP, #64] |
(296) 0x42471c LDP X27, X28, [SP, #80] |
(296) 0x424720 B 42461c |
0x424724 ADD W11, W11, #1 |
0x424728 MOVZ W10, #0 |
0x42472c B 42439c |
(293) 0x424730 ORR X1, XZR, X30 |
(293) 0x424734 B 424624 |
(294) 0x424738 STP X21, X22, [SP, #32] |
(294) 0x42473c STP X25, X26, [SP, #64] |
(294) 0x424740 STP X27, X28, [SP, #80] |
(294) 0x424744 BL 403150 |
(294) 0x424748 MOVN X7, #32784 |
(294) 0x42474c FMOV D7, X7 |
(294) 0x424750 B 42461c |
0x424754 HINT #0 |
0x424758 HINT #0 |
0x42475c HINT #0 |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►98.43+ | __kmp_GOMP_microtask_wrapper(i[...] | libomp.so | |
○ | __kmp_invoke_microtask | libomp.so | |
►1.57+ | GOMP_parallel | libomp.so | |
○ | calc_dt_kernel(int, int, int, [...] | calc_dt.cpp:83 | exec |
○ | calc_dt(global_variables&, int[...] | calc_dt.cpp:131 | exec |
○ | timestep(global_variables&, pa[...] | timestep.cpp:80 | exec |
○ | hydro(global_variables&, paral[...] | hydro.cpp:60 | exec |
○ | main | iostream:74 | exec |
○ | __libc_start_main | libc-2.31.so | |
○ | _start | iostream:74 | exec |
Path / |
Source file and lines | calc_dt.cpp:49-75 |
Module | exec |
nb instructions | 91 |
loop length | 364 |
nb stack references | 0 |
front end | 11.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.00 | 4.00 | 10.75 | 10.75 | 10.75 | 10.75 | 2.00 | 2.00 | 2.00 | 2.00 | 11.33 | 11.33 | 11.33 | 6.00 | 6.00 |
cycles | 4.00 | 4.00 | 10.75 | 10.75 | 10.75 | 10.75 | 2.00 | 2.00 | 2.00 | 2.00 | 11.33 | 11.33 | 11.33 | 6.00 | 6.00 |
Cycles executing div or sqrt instructions | 2.00-1.00 |
Front-end | 11.00 |
Overall L1 | 11.33 |
all | 12% |
load | 40% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADRP X1, <462300> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X29, X30, [SP, #848]! | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X3, [X1, #3864] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STP X19, X20, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ORR X19, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X23, X24, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDP W23, W2, [X0, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STP D8, D9, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP D10, D11, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
LDR X0, [X3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STR X0, [SP, #168] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
MOVZ X0, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDP W5, W0, [X19, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD W4, W2, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD W23, W23, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDP D8, D11, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
STR W4, [SP, #152] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD W6, W5, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDP D10, D9, [X19, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
STR W6, [SP, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
CMP W23, W4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 424748 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x448> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR W8, [SP, #152] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STP X21, X22, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD W21, W0, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W9, [SP, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUB W24, W8, W23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP W9, W21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 424610 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x310> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB W20, W21, W9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 403530 <@plt_start@+0x4b0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MADD W24, W24, W20, WZR | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ORR W22, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 4033c0 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
UDIV W11, W24, W22 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5-12 | 1-0.50 |
MSUB W10, W11, W22, W24 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
CMP W0, W10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.CC 424724 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x424> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MADD W13, W11, W0, W10 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ADD W12, W11, W13 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR W12, [SP, #156] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
CMP W13, W12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.CS 424610 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x310> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
UDIV W14, W13, W20 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5-12 | 1-0.50 |
ADRP X18, <44b3b4> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X27, X28, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADRP X17, <44a3bc> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X16, <44a3c0> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
FADD D7, D11, D11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
MOVN X15, #32784 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
FADD D6, D10, D10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
FMOV D18, #0.5000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
LDR W28, [SP, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
FMOV D19, #-1.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
STP X25, X26, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR D17, [X18, #152] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDP X3, X18, [X19, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
MSUB W2, W14, W20, W13 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ADD W23, W14, W23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SBFM X5, X23, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
FMOV D1, X15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
SUB W0, W23, W5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR D5, [X17, #1976] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
ORR X10, XZR, X5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD W12, W2, W28 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X3, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
SUB W17, W21, W12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR W0, [SP, #140] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
CMP W11, W17 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CSEL W6, W11, W17, #9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD W17, W13, W6 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR D4, [X16, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
ADD X16, X5, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDP X27, X26, [X19, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X25, X24, [X19, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDR X23, [X19, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X22, [X19, #88] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X21, [X19, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X30, [X19, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP W13, W17 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.CS 4246d0 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x3d0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOVN X13, #32784 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDP X21, X22, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
FMOV D7, X13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
ADD W11, W11, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W10, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
B 42439c <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x9c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 |
Source file and lines | calc_dt.cpp:49-75 |
Module | exec |
nb instructions | 91 |
loop length | 364 |
nb stack references | 0 |
front end | 11.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.00 | 4.00 | 10.75 | 10.75 | 10.75 | 10.75 | 2.00 | 2.00 | 2.00 | 2.00 | 11.33 | 11.33 | 11.33 | 6.00 | 6.00 |
cycles | 4.00 | 4.00 | 10.75 | 10.75 | 10.75 | 10.75 | 2.00 | 2.00 | 2.00 | 2.00 | 11.33 | 11.33 | 11.33 | 6.00 | 6.00 |
Cycles executing div or sqrt instructions | 2.00-1.00 |
Front-end | 11.00 |
Overall L1 | 11.33 |
all | 12% |
load | 40% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADRP X1, <462300> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X29, X30, [SP, #848]! | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X3, [X1, #3864] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STP X19, X20, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ORR X19, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X23, X24, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDP W23, W2, [X0, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STP D8, D9, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP D10, D11, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
LDR X0, [X3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STR X0, [SP, #168] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
MOVZ X0, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDP W5, W0, [X19, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD W4, W2, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD W23, W23, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDP D8, D11, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
STR W4, [SP, #152] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD W6, W5, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDP D10, D9, [X19, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
STR W6, [SP, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
CMP W23, W4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 424748 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x448> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR W8, [SP, #152] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STP X21, X22, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD W21, W0, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W9, [SP, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUB W24, W8, W23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP W9, W21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 424610 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x310> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB W20, W21, W9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 403530 <@plt_start@+0x4b0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MADD W24, W24, W20, WZR | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ORR W22, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 4033c0 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
UDIV W11, W24, W22 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5-12 | 1-0.50 |
MSUB W10, W11, W22, W24 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
CMP W0, W10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.CC 424724 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x424> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MADD W13, W11, W0, W10 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ADD W12, W11, W13 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR W12, [SP, #156] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
CMP W13, W12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.CS 424610 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x310> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
UDIV W14, W13, W20 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5-12 | 1-0.50 |
ADRP X18, <44b3b4> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X27, X28, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADRP X17, <44a3bc> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X16, <44a3c0> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
FADD D7, D11, D11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
MOVN X15, #32784 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
FADD D6, D10, D10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
FMOV D18, #0.5000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
LDR W28, [SP, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
FMOV D19, #-1.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
STP X25, X26, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR D17, [X18, #152] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDP X3, X18, [X19, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
MSUB W2, W14, W20, W13 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ADD W23, W14, W23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SBFM X5, X23, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
FMOV D1, X15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
SUB W0, W23, W5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR D5, [X17, #1976] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
ORR X10, XZR, X5 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD W12, W2, W28 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X3, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
SUB W17, W21, W12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR W0, [SP, #140] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
CMP W11, W17 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CSEL W6, W11, W17, #9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD W17, W13, W6 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR D4, [X16, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
ADD X16, X5, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDP X27, X26, [X19, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X25, X24, [X19, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDR X23, [X19, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X22, [X19, #88] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X21, [X19, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X30, [X19, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP W13, W17 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.CS 4246d0 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x3d0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOVN X13, #32784 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDP X21, X22, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
FMOV D7, X13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
ADD W11, W11, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W10, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
B 42439c <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x9c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D | 4.43 | 5.89 |
▼Loop 294 - calc_dt.cpp:49-75 - exec– | 0 | 0 |
▼Loop 296 - calc_dt.cpp:49-75 - exec– | 0 | 0 |
▼Loop 297 - calc_dt.cpp:51-75 - exec– | 3.4 | 4.51 |
○Loop 298 - calc_dt.cpp:51-75 - exec | 0 | 0.01 |
○Loop 295 - calc_dt.cpp:75-75 - exec | 1.01 | 1.33 |
○Loop 299 - calc_dt.cpp:75-75 - exec | 0.02 | 0.03 |
○Loop 293 - calc_dt.cpp:49-49 - exec | 0 | 0 |