Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:117-125 [...] | Coverage: 3.71% |
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Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:117-125 [...] | Coverage: 3.71% |
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/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 117 - 125 |
-------------------------------------------------------------------------------- |
117: #pragma omp parallel for simd collapse(2) |
118: for (int j = (y_min + 1); j < (y_max + 2); j++) { |
119: for (int i = (x_min + 1); i < (x_max + 2); i++) { |
120: double pre_mass_s = density1(i, j) * pre_vol(i, j); |
121: double post_mass_s = pre_mass_s + mass_flux_x(i, j) - mass_flux_x(i + 1, j + 0); |
122: double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 1, j + 0)) / post_mass_s; |
123: double advec_vol_s = pre_vol(i, j) + vol_flux_x(i, j) - vol_flux_x(i + 1, j + 0); |
124: density1(i, j) = post_mass_s / advec_vol_s; |
125: energy1(i, j) = post_ener_s; |
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x41f444 STP X29, X30, [SP, #928]! |
0x41f448 ADD X29, SP, #0 |
0x41f44c STP X19, X20, [SP, #16] |
0x41f450 STP X25, X26, [SP, #64] |
0x41f454 LDP W25, W19, [X0, #56] |
0x41f458 STP X23, X24, [SP, #48] |
0x41f45c ORR X23, XZR, X0 |
0x41f460 LDR W20, [X0, #48] |
0x41f464 ADD W25, W25, #1 |
0x41f468 ADD W19, W19, #2 |
0x41f46c LDR W0, [X0, #52] |
0x41f470 CMP W25, W19 |
0x41f474 B.GE 41f650 |
0x41f478 ADD W20, W20, #1 |
0x41f47c STP X21, X22, [SP, #32] |
0x41f480 ADD W22, W0, #2 |
0x41f484 SUB W26, W19, W25 |
0x41f488 CMP W20, W22 |
0x41f48c B.GE 41f664 |
0x41f490 SUB W21, W22, W20 |
0x41f494 BL 403530 |
0x41f498 MADD W26, W26, W21, WZR |
0x41f49c ORR W24, WZR, W0 |
0x41f4a0 BL 4033c0 |
0x41f4a4 ORR W1, WZR, W0 |
0x41f4a8 UDIV W3, W26, W24 |
0x41f4ac MSUB W2, W3, W24, W26 |
0x41f4b0 CMP W0, W2 |
0x41f4b4 B.CC 41f67c |
(185) 0x41f4b8 MADD W26, W3, W1, W2 |
(185) 0x41f4bc ADD W17, W3, W26 |
(185) 0x41f4c0 CMP W26, W17 |
(185) 0x41f4c4 B.CS 41f664 |
(187) 0x41f4c8 UDIV W4, W26, W21 |
(187) 0x41f4cc LDP X16, X15, [X23] |
(187) 0x41f4d0 MOVZ W18, #0 |
(187) 0x41f4d4 CNTD X10, ALL |
(187) 0x41f4d8 PTRUE P1.B, ALL |
(187) 0x41f4dc LDP X14, X13, [X23, #16] |
(187) 0x41f4e0 LDP X12, X11, [X23, #32] |
(187) 0x41f4e4 STR X27, [SP, #80] |
(187) 0x41f4e8 MSUB W6, W4, W21, W26 |
(187) 0x41f4ec ADD W5, W4, W25 |
(187) 0x41f4f0 SBFM X9, X5, #0, #31 |
(187) 0x41f4f4 ADD W7, W6, W20 |
(187) 0x41f4f8 SUB W30, W22, W7 |
(187) 0x41f4fc CMP W3, W30 |
(187) 0x41f500 CSEL X3, X3, X30, #9 |
(187) 0x41f504 ADD W30, W26, W3 |
(187) 0x41f508 CMP W26, W30 |
(187) 0x41f50c B.CS 41f634 |
(188) 0x41f510 SBFM X6, X7, #0, #31 |
(188) 0x41f514 LDR X7, [X11] |
(188) 0x41f518 MOVZ X0, #0 |
(188) 0x41f51c ADD X1, X6, #1 |
(188) 0x41f520 WHILELO P0.D, XZR, X3 |
(188) 0x41f524 LDR X24, [X13] |
(188) 0x41f528 LDR X5, [X14] |
(188) 0x41f52c MADD X27, X9, X7, XZR |
(188) 0x41f530 LDR X8, [X11, #16] |
(188) 0x41f534 MADD X4, X9, X24, XZR |
(188) 0x41f538 LDR X22, [X12] |
(188) 0x41f53c ADD X23, X27, X1 |
(188) 0x41f540 ADD X25, X27, X6 |
(188) 0x41f544 LDR X2, [X13, #16] |
(188) 0x41f548 ADD X26, X8, X25,LSL #3 |
(188) 0x41f54c LDR X27, [X14, #16] |
(188) 0x41f550 ADD X7, X8, X23,LSL #3 |
(188) 0x41f554 MADD X8, X9, X5, XZR |
(188) 0x41f558 MADD X23, X9, X22, X6 |
(188) 0x41f55c ADD X25, X8, X1 |
(188) 0x41f560 ADD X22, X8, X6 |
(188) 0x41f564 ADD X1, X4, X1 |
(188) 0x41f568 ADD X4, X4, X6 |
(188) 0x41f56c ADD X8, X27, X22,LSL #3 |
(188) 0x41f570 ADD X24, X27, X25,LSL #3 |
(188) 0x41f574 LDR X22, [X16] |
(188) 0x41f578 ADD X27, X2, X4,LSL #3 |
(188) 0x41f57c ADD X5, X2, X1,LSL #3 |
(188) 0x41f580 LDR X2, [X15] |
(188) 0x41f584 LDR X25, [X16, #16] |
(188) 0x41f588 MADD X1, X9, X2, X6 |
(188) 0x41f58c LDR X2, [X12, #16] |
(188) 0x41f590 MADD X6, X9, X22, X6 |
(188) 0x41f594 LDR X22, [X15, #16] |
(188) 0x41f598 ADD X4, X25, X6,LSL #3 |
(188) 0x41f59c ADD X23, X2, X23,LSL #3 |
(188) 0x41f5a0 ADD X1, X22, X1,LSL #3 |
(186) 0x41f5a4 LD1D {Z2.D}, P0/Z, [X23, X0,LSL #3] |
(186) 0x41f5a8 LD1D {Z0.D}, P0/Z, [X4, X0,LSL #3] |
(186) 0x41f5ac LD1D {Z1.D}, P0/Z, [X27, X0,LSL #3] |
(186) 0x41f5b0 LD1D {Z6.D}, P0/Z, [X5, X0,LSL #3] |
(186) 0x41f5b4 LD1D {Z3.D}, P0/Z, [X26, X0,LSL #3] |
(186) 0x41f5b8 LD1D {Z16.D}, P0/Z, [X7, X0,LSL #3] |
(186) 0x41f5bc LD1D {Z17.D}, P0/Z, [X1, X0,LSL #3] |
(186) 0x41f5c0 LD1D {Z19.D}, P0/Z, [X24, X0,LSL #3] |
(186) 0x41f5c4 LD1D {Z21.D}, P0/Z, [X8, X0,LSL #3] |
(186) 0x41f5c8 FMUL Z5.D, Z2.D, Z0.D |
(186) 0x41f5cc FADD Z4.D, Z1.D, Z2.D |
(186) 0x41f5d0 FSUB Z18.D, Z3.D, Z16.D |
(186) 0x41f5d4 FSUB Z7.D, Z4.D, Z6.D |
(186) 0x41f5d8 FMAD Z17.D, P1/M, Z5.D, Z18.D |
(186) 0x41f5dc FSUB Z20.D, Z5.D, Z19.D |
(186) 0x41f5e0 FADD Z22.D, Z20.D, Z21.D |
(186) 0x41f5e4 FDIVR Z7.D, P1/M, Z7.D, Z22.D |
(186) 0x41f5e8 FDIVR Z22.D, P1/M, Z22.D, Z17.D |
(186) 0x41f5ec ST1D {Z7.D}, P0, [X4, X0,LSL #3] |
(186) 0x41f5f0 ST1D {Z22.D}, P0, [X1, X0,LSL #3] |
(186) 0x41f5f4 ADD X0, X0, X10 |
(186) 0x41f5f8 WHILELO P0.D, X0, X3 |
(186) 0x41f5fc B.NE 41f5a4 |
(188) 0x41f600 ADD X9, X9, #1 |
(188) 0x41f604 ADD W3, W18, W9 |
(188) 0x41f608 CMP W19, W3 |
(188) 0x41f60c B.LE 41f648 |
(188) 0x41f610 SUB W3, W17, W30 |
(188) 0x41f614 ORR W26, WZR, W30 |
(188) 0x41f618 ORR W30, WZR, W21 |
(188) 0x41f61c ORR W7, WZR, W20 |
(188) 0x41f620 CMP W3, W30 |
(188) 0x41f624 CSEL X3, X3, X30, #9 |
(188) 0x41f628 ADD W30, W26, W3 |
(188) 0x41f62c CMP W26, W30 |
(188) 0x41f630 B.CC 41f510 |
(189) 0x41f634 ADD X9, X9, #1 |
(189) 0x41f638 ORR W30, WZR, W26 |
(189) 0x41f63c ADD W3, W18, W9 |
(189) 0x41f640 CMP W19, W3 |
(189) 0x41f644 B.GT 41f610 |
(187) 0x41f648 LDP X21, X22, [SP, #32] |
(187) 0x41f64c LDR X27, [SP, #80] |
(187) 0x41f650 LDP X19, X20, [SP, #16] |
(187) 0x41f654 LDP X23, X24, [SP, #48] |
(187) 0x41f658 LDP X25, X26, [SP, #64] |
(187) 0x41f65c LDP X29, X30, [SP], #96 |
(187) 0x41f660 RET |
(185) 0x41f664 LDP X19, X20, [SP, #16] |
(185) 0x41f668 LDP X21, X22, [SP, #32] |
(185) 0x41f66c LDP X23, X24, [SP, #48] |
(185) 0x41f670 LDP X25, X26, [SP, #64] |
(185) 0x41f674 LDP X29, X30, [SP], #96 |
(185) 0x41f678 RET |
(185) 0x41f67c ADD W3, W3, #1 |
(185) 0x41f680 MOVZ W2, #0 |
(185) 0x41f684 B 41f4b8 |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►98.43+ | __kmp_GOMP_microtask_wrapper(i[...] | libomp.so | |
○ | __kmp_invoke_microtask | libomp.so |
Path / |
Source file and lines | advec_cell.cpp:117-125 |
Module | exec |
nb instructions | 29 |
loop length | 116 |
nb stack references | 0 |
front end | 3.63 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 2.50 | 4.75 | 4.75 | 4.75 | 4.75 | 0.00 | 0.00 | 0.00 | 0.00 | 2.83 | 2.50 | 2.67 | 2.50 | 2.50 |
cycles | 2.50 | 2.50 | 4.75 | 4.75 | 4.75 | 4.75 | 0.00 | 0.00 | 0.00 | 0.00 | 2.83 | 2.50 | 2.67 | 2.50 | 2.50 |
Cycles executing div or sqrt instructions | 1.00-0.50 |
Front-end | 3.63 |
Overall L1 | 4.75 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STP X29, X30, [SP, #928]! | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X19, X20, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X25, X26, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDP W25, W19, [X0, #56] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STP X23, X24, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ORR X23, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W20, [X0, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD W25, W25, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD W19, W19, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W0, [X0, #52] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP W25, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 41f650 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x20c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD W20, W20, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X21, X22, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD W22, W0, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB W26, W19, W25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP W20, W22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 41f664 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x220> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB W21, W22, W20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 403530 <@plt_start@+0x4b0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MADD W26, W26, W21, WZR | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ORR W24, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 4033c0 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR W1, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
UDIV W3, W26, W24 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5-12 | 1-0.50 |
MSUB W2, W3, W24, W26 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
CMP W0, W2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.CC 41f67c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x238> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Source file and lines | advec_cell.cpp:117-125 |
Module | exec |
nb instructions | 29 |
loop length | 116 |
nb stack references | 0 |
front end | 3.63 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 2.50 | 4.75 | 4.75 | 4.75 | 4.75 | 0.00 | 0.00 | 0.00 | 0.00 | 2.83 | 2.50 | 2.67 | 2.50 | 2.50 |
cycles | 2.50 | 2.50 | 4.75 | 4.75 | 4.75 | 4.75 | 0.00 | 0.00 | 0.00 | 0.00 | 2.83 | 2.50 | 2.67 | 2.50 | 2.50 |
Cycles executing div or sqrt instructions | 1.00-0.50 |
Front-end | 3.63 |
Overall L1 | 4.75 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STP X29, X30, [SP, #928]! | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X19, X20, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X25, X26, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDP W25, W19, [X0, #56] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STP X23, X24, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ORR X23, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W20, [X0, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD W25, W25, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD W19, W19, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W0, [X0, #52] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP W25, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 41f650 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x20c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD W20, W20, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X21, X22, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD W22, W0, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB W26, W19, W25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP W20, W22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 41f664 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x220> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB W21, W22, W20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 403530 <@plt_start@+0x4b0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MADD W26, W26, W21, WZR | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ORR W24, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 4033c0 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR W1, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
UDIV W3, W26, W24 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5-12 | 1-0.50 |
MSUB W2, W3, W24, W26 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
CMP W0, W2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.CC 41f67c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x238> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D | 3.71 | 4.93 |
▼Loop 187 - advec_cell.cpp:117-125 - exec– | 0 | 0 |
▼Loop 188 - advec_cell.cpp:119-125 - exec– | 0 | 0.01 |
○Loop 186 - advec_cell.cpp:120-125 - exec | 3.71 | 4.91 |
○Loop 185 - advec_cell.cpp:117-119 - exec | 0 | 0 |
○Loop 189 - advec_cell.cpp:119-123 - exec | 0 | 0 |