Function: .omp_outlined..12#0x41d540 | Module: exec | Source: advec_mom.cpp:108-139 [...] | Coverage: 3.68% |
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Function: .omp_outlined..12#0x41d540 | Module: exec | Source: advec_mom.cpp:108-139 [...] | Coverage: 3.68% |
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/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 108 - 139 |
-------------------------------------------------------------------------------- |
108: #pragma omp parallel for simd collapse(2) |
109: for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) { |
110: for (int i = (x_min - 1 + 1); i < (x_max + 1 + 2); i++) |
111: ({ |
112: int upwind, donor, downwind, dif; |
113: double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s; |
114: if (node_flux(i, j) < 0.0) { |
115: upwind = i + 2; |
116: donor = i + 1; |
117: downwind = i; |
118: dif = donor; |
119: } else { |
120: upwind = i - 1; |
121: donor = i; |
122: downwind = i + 1; |
123: dif = upwind; |
124: } |
125: sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(donor, j)); |
126: width = celldx[i]; |
127: vdiffuw = vel1(donor, j) - vel1(upwind, j); |
128: vdiffdw = vel1(downwind, j) - vel1(donor, j); |
129: limiter = 0.0; |
130: if (vdiffuw * vdiffdw > 0.0) { |
131: auw = std::fabs(vdiffuw); |
132: adw = std::fabs(vdiffdw); |
133: wind = 1.0; |
134: if (vdiffdw <= 0.0) wind = -1.0; |
135: limiter = |
136: wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldx[dif]) / 6.0, auw), adw); |
137: } |
138: advec_vel_s = vel1(donor, j) + (1.0 - sigma) * limiter; |
139: mom_flux(i, j) = advec_vel_s * node_flux(i, j); |
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
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69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x41d540 SUB SP, SP, #192 |
0x41d544 STR D10, [SP, #64] |
0x41d548 STP D9, D8, [SP, #80] |
0x41d54c STP X29, X30, [SP, #96] |
0x41d550 STP X28, X27, [SP, #112] |
0x41d554 STP X26, X25, [SP, #128] |
0x41d558 STP X24, X23, [SP, #144] |
0x41d55c STP X22, X21, [SP, #160] |
0x41d560 STP X20, X19, [SP, #176] |
0x41d564 ADD X29, SP, #96 |
0x41d568 LDR W8, [X2] |
0x41d56c LDR W9, [X3] |
0x41d570 LDR W10, [X5] |
0x41d574 ADD W21, W8, #1 |
0x41d578 LDR W20, [X4] |
0x41d57c ADD W8, W9, #3 |
0x41d580 ADD W9, W10, #3 |
0x41d584 SUBS W8, W8, W21 |
0x41d588 CCMP W9, W20, #4, #12 |
0x41d58c B.LE 41d638 |
0x41d590 LDP X11, X10, [X29, #104] |
0x41d594 LDR X12, [X29, #96] |
0x41d598 LDR X14, [X6] |
0x41d59c SUB W24, W9, W20 |
0x41d5a0 MOVN X9, #0 |
0x41d5a4 ADD X3, SP, #44 |
0x41d5a8 SUB X4, X29, #24 |
0x41d5ac SUB X5, X29, #40 |
0x41d5b0 LDR X13, [X7] |
0x41d5b4 LDR W1, [X0] |
0x41d5b8 LDR X23, [X6, #16] |
0x41d5bc ADRP X0, |
0x41d5c0 ADD X0, X0, #4032 |
0x41d5c4 ADD X6, SP, #48 |
0x41d5c8 MOVZ W2, #34 |
0x41d5cc LDR X25, [X7, #16] |
0x41d5d0 MOVZ W7, #1 |
0x41d5d4 STUR XZR, [X29, #488] |
0x41d5d8 UMADDL X27, W24, W8, X9 |
0x41d5dc MOVZ W8, #1 |
0x41d5e0 STR X8, [SP, #48] |
0x41d5e4 LDR X26, [X12, #8] |
0x41d5e8 LDR X12, [X11] |
0x41d5ec LDR X28, [X11, #16] |
0x41d5f0 LDR X19, [X10] |
0x41d5f4 LDR X22, [X10, #16] |
0x41d5f8 STP X13, X14, [SP, #24] |
0x41d5fc STUR X27, [X29, #472] |
0x41d600 STR X8, [SP] |
0x41d604 STP W1, WZR, [SP, #40] |
0x41d608 STR X12, [SP, #16] |
0x41d60c BL 402ee0 |
0x41d610 LDUR X8, [X29, #472] |
0x41d614 LDUR X13, [X29, #488] |
0x41d618 CMP X8, X27 |
0x41d61c CSEL X8, X8, X27, #11 |
0x41d620 CMP X13, X8 |
0x41d624 B.LE 41d660 |
(308) 0x41d628 LDR W1, [SP, #40] |
(308) 0x41d62c ADRP X0, |
(308) 0x41d630 ADD X0, X0, #4056 |
(308) 0x41d634 BL 402d80 |
(308) 0x41d638 LDP D9, D8, [SP, #80] |
(308) 0x41d63c LDR D10, [SP, #64] |
(308) 0x41d640 LDP X20, X19, [SP, #176] |
(308) 0x41d644 LDP X22, X21, [SP, #160] |
(308) 0x41d648 LDP X24, X23, [SP, #144] |
(308) 0x41d64c LDP X26, X25, [SP, #128] |
(308) 0x41d650 LDP X28, X27, [SP, #112] |
(308) 0x41d654 LDP X29, X30, [SP, #96] |
(308) 0x41d658 ADD SP, SP, #192 |
(308) 0x41d65c RET |
(308) 0x41d660 ADD X8, X8, #1 |
(308) 0x41d664 CNTD X10, ALL |
(308) 0x41d668 ORR X9, XZR, X13 |
(308) 0x41d66c SUB X11, X8, X13 |
(308) 0x41d670 CMP X11, X10 |
(308) 0x41d674 B.CC 41d7fc |
(308) 0x41d678 UDIV X9, X11, X10 |
(308) 0x41d67c PTRUE P0.D, ALL |
(308) 0x41d680 FDUP Z19.D, #0 |
(308) 0x41d684 FDUP Z20.D, #24 |
(308) 0x41d688 DUP Z21.D, #0 |
(308) 0x41d68c MADD X12, X9, X10, XZR |
(308) 0x41d690 INDEX Z0.D, X13, #1 |
(308) 0x41d694 ADD X9, X13, X12 |
(308) 0x41d698 LDR X13, [SP, #32] |
(308) 0x41d69c DUP Z1.D, X10 |
(308) 0x41d6a0 SUB X11, X11, X12 |
(308) 0x41d6a4 DUP Z2.D, X24 |
(308) 0x41d6a8 DUP Z3.D, X21 |
(308) 0x41d6ac DUP Z4.D, X20 |
(308) 0x41d6b0 DUP Z16.D, X19 |
(308) 0x41d6b4 DUP Z5.D, X13 |
(308) 0x41d6b8 LDR X13, [SP, #24] |
(308) 0x41d6bc DUP Z6.D, X13 |
(308) 0x41d6c0 LDR X13, [SP, #16] |
(308) 0x41d6c4 DUP Z7.D, X13 |
(308) 0x41d6c8 ADD W13, W20, #1 |
(308) 0x41d6cc DUP Z17.D, X13 |
(308) 0x41d6d0 SUB W13, W20, #1 |
(308) 0x41d6d4 DUP Z18.D, X13 |
(308) 0x41d6d8 ADD W13, W20, #2 |
(308) 0x41d6dc DUP Z22.D, X13 |
(307) 0x41d6e0 MOVPRFX Z23, Z0 |
(307) 0x41d6e4 SDIV Z23.D, P0/M, Z23.D, Z2.D |
(307) 0x41d6e8 ADD Z24.D, Z3.D, Z23.D |
(307) 0x41d6ec MSB Z23.D, P0/M, Z2.D, Z0.D |
(307) 0x41d6f0 ADD Z0.D, Z0.D, Z1.D |
(307) 0x41d6f4 SUBS X12, X12, X10 |
(307) 0x41d6f8 SXTW Z24.D, P0/M, Z24.D |
(307) 0x41d6fc ADD Z25.D, Z4.D, Z23.D |
(307) 0x41d700 MOVPRFX Z26, Z25 |
(307) 0x41d704 SXTW Z26.D, P0/M, Z25.D |
(307) 0x41d708 MOVPRFX Z27, Z26 |
(307) 0x41d70c MLA Z27.D, P0/M, Z5.D, Z24.D |
(307) 0x41d710 LD1D {Z27.D}, P0/Z, [X23, Z27.D,LSL #3] |
(307) 0x41d714 ADD Z28.D, Z17.D, Z23.D |
(307) 0x41d718 MOVPRFX Z29, Z28 |
(307) 0x41d71c SXTW Z29.D, P0/M, Z28.D |
(307) 0x41d720 ADD Z30.D, Z18.D, Z23.D |
(307) 0x41d724 ADD Z23.D, Z22.D, Z23.D |
(307) 0x41d728 MOVPRFX Z8, Z27 |
(307) 0x41d72c FABS Z8.D, P0/M, Z27.D |
(307) 0x41d730 FCMLT P1.D, P0/Z, Z27.D, #0 |
(307) 0x41d734 SEL Z31.D, P1, Z26.D, Z29.D |
(307) 0x41d738 SEL Z29.D, P1, Z29.D, Z26.D |
(307) 0x41d73c MOVPRFX Z9, Z29 |
(307) 0x41d740 MLA Z9.D, P0/M, Z6.D, Z24.D |
(307) 0x41d744 LD1D {Z9.D}, P0/Z, [X25, Z9.D,LSL #3] |
(307) 0x41d748 SEL Z23.D, P1, Z23.D, Z30.D |
(307) 0x41d74c SEL Z28.D, P1, Z28.D, Z30.D |
(307) 0x41d750 MOVPRFX Z30, Z7 |
(307) 0x41d754 MUL Z30.D, P0/M, Z30.D, Z24.D |
(307) 0x41d758 MAD Z24.D, P0/M, Z16.D, Z26.D |
(307) 0x41d75c ADD Z29.D, Z29.D, Z30.D |
(307) 0x41d760 ADR Z23.D, [Z30, Z23.D,SXTW] |
(307) 0x41d764 ADD Z30.D, Z31.D, Z30.D |
(307) 0x41d768 FDIV Z8.D, P0/M, Z8.D, Z9.D |
(307) 0x41d76c LD1D {Z29.D}, P0/Z, [X28, Z29.D,LSL #3] |
(307) 0x41d770 LD1D {Z23.D}, P0/Z, [X28, Z23.D,LSL #3] |
(307) 0x41d774 LD1D {Z30.D}, P0/Z, [X28, Z30.D,LSL #3] |
(307) 0x41d778 FSUB Z10.D, Z29.D, Z23.D |
(307) 0x41d77c FSUB Z31.D, Z30.D, Z29.D |
(307) 0x41d780 FABD Z23.D, P0/M, Z23.D, Z29.D |
(307) 0x41d784 FABD Z30.D, P0/M, Z30.D, Z29.D |
(307) 0x41d788 FMUL Z9.D, Z10.D, Z31.D |
(307) 0x41d78c FCMLE P2.D, P0/Z, Z31.D, #0 |
(307) 0x41d790 EOR P2.B, P0/Z, P2.B, P0.B |
(307) 0x41d794 FCMGT P1.D, P0/Z, Z9.D, #0 |
(307) 0x41d798 MOVPRFX Z9, Z8 |
(307) 0x41d79c FADD Z9.D, P0/M, Z9.D, #1 |
(307) 0x41d7a0 FMUL Z9.D, Z9.D, Z23.D |
(307) 0x41d7a4 LD1D {Z25.D}, P1/Z, [X26, Z25.D,SXTW #3] |
(307) 0x41d7a8 LD1D {Z28.D}, P1/Z, [X26, Z28.D,SXTW #3] |
(307) 0x41d7ac FSUB Z31.D, Z19.D, Z8.D |
(307) 0x41d7b0 FDIVR Z28.D, P0/M, Z28.D, Z9.D |
(307) 0x41d7b4 FMUL Z31.D, Z31.D, Z30.D |
(307) 0x41d7b8 FDIV Z31.D, P0/M, Z31.D, Z25.D |
(307) 0x41d7bc FADD Z28.D, Z31.D, Z28.D |
(307) 0x41d7c0 FMUL Z25.D, Z25.D, Z28.D |
(307) 0x41d7c4 FDIV Z25.D, P0/M, Z25.D, Z20.D |
(307) 0x41d7c8 FMINNM Z23.D, P0/M, Z23.D, Z25.D |
(307) 0x41d7cc FMINNM Z23.D, P0/M, Z23.D, Z30.D |
(307) 0x41d7d0 MOVPRFX Z25, Z23 |
(307) 0x41d7d4 FNEG Z25.D, P0/M, Z23.D |
(307) 0x41d7d8 SEL Z23.D, P2, Z23.D, Z25.D |
(307) 0x41d7dc MOVPRFX Z25, Z8 |
(307) 0x41d7e0 FSUBR Z25.D, P0/M, Z25.D, #1 |
(307) 0x41d7e4 SEL Z23.D, P1, Z23.D, Z21.D |
(307) 0x41d7e8 FMAD Z23.D, P0/M, Z25.D, Z29.D |
(307) 0x41d7ec FMUL Z23.D, Z27.D, Z23.D |
(307) 0x41d7f0 ST1D {Z23.D}, P0, [X22, Z24.D,LSL #3] |
(307) 0x41d7f4 B.NE 41d6e0 |
(308) 0x41d7f8 CBZ X11, 41d628 |
(306) 0x41d7fc LDP X1, X0, [SP, #24] |
(306) 0x41d800 LDR X2, [SP, #16] |
(306) 0x41d804 SUB W10, WZR, W24 |
(306) 0x41d808 FMOV D0, #2.0000000 |
(306) 0x41d80c FMOV D1, #1.0000000 |
(306) 0x41d810 SUB W11, W20, #1 |
(306) 0x41d814 FMOV D2, #6.0000000 |
(306) 0x41d818 B 41d840 |
0x41d81c HINT #0 |
(306) 0x41d820 FSUB D4, D1, S4 |
(306) 0x41d824 MADD X12, X19, X13, X12 |
(306) 0x41d828 ADD X9, X9, #1 |
(306) 0x41d82c CMP X8, X9 |
(306) 0x41d830 FMADD D4, D4, D16, D5 |
(306) 0x41d834 FMUL D3, D3, D4 |
(306) 0x41d838 STR D3, [X22, X12,LSL #3] |
(306) 0x41d83c B.EQ 41d628 |
(306) 0x41d840 SDIV X16, X9, X24 |
(306) 0x41d844 MSUB W12, W16, W24, W9 |
(306) 0x41d848 ADD W13, W21, W16 |
(306) 0x41d84c ADD W14, W20, W12 |
(306) 0x41d850 ADD W12, W20, W9 |
(306) 0x41d854 SBFM X13, X13, #0, #31 |
(306) 0x41d858 MADD W15, W10, W16, W12 |
(306) 0x41d85c SBFM X12, X15, #0, #31 |
(306) 0x41d860 ADD W15, W15, #1 |
(306) 0x41d864 MADD X17, X0, X13, X12 |
(306) 0x41d868 SBFM X15, X15, #0, #31 |
(306) 0x41d86c LDR D3, [X23, X17,LSL #3] |
(306) 0x41d870 FCMP D3, #0 |
(306) 0x41d874 B.PL 41d8a0 |
(306) 0x41d878 ADD W17, W20, W9 |
(306) 0x41d87c ADD W14, W14, #1 |
(306) 0x41d880 MADD W16, W10, W16, W17 |
(306) 0x41d884 ADD W17, W16, #2 |
(306) 0x41d888 ORR X16, XZR, X12 |
(306) 0x41d88c B 41d8b4 |
0x41d890 HINT #0 |
0x41d894 HINT #0 |
0x41d898 HINT #0 |
0x41d89c HINT #0 |
(305) 0x41d8a0 SUB W17, W14, #1 |
(305) 0x41d8a4 ADD W14, W11, W9 |
(305) 0x41d8a8 MADD W14, W10, W16, W14 |
(305) 0x41d8ac ORR X16, XZR, X15 |
(305) 0x41d8b0 ORR X15, XZR, X12 |
(306) 0x41d8b4 MADD X18, X1, X13, X15 |
(306) 0x41d8b8 FABS D4, D3 |
(306) 0x41d8bc MOVI D16, #0 |
(306) 0x41d8c0 LDR D5, [X25, X18,LSL #3] |
(306) 0x41d8c4 MADD X18, X2, X13, XZR |
(306) 0x41d8c8 ADD X15, X15, X18 |
(306) 0x41d8cc FDIV D4, D4, D5 |
(306) 0x41d8d0 LDR D5, [X28, X15,LSL #3] |
(306) 0x41d8d4 ADD X15, X18, W17,SXTW |
(306) 0x41d8d8 LDR D6, [X28, X15,LSL #3] |
(306) 0x41d8dc ADD X15, X16, X18 |
(306) 0x41d8e0 FSUB D7, D5, S6 |
(306) 0x41d8e4 LDR D6, [X28, X15,LSL #3] |
(306) 0x41d8e8 FSUB D6, D6, S5 |
(306) 0x41d8ec FMUL D17, D7, D6 |
(306) 0x41d8f0 FCMP D17, #0 |
(306) 0x41d8f4 B.LE 41d820 |
(306) 0x41d8f8 LDR D16, [X26, X12,LSL #3] |
(306) 0x41d8fc LDR D20, [X26, X14,SXTW #3] |
(306) 0x41d900 FABS D7, D7 |
(306) 0x41d904 FABS D17, D6 |
(306) 0x41d908 FSUB D18, D0, S4 |
(306) 0x41d90c FADD D19, D4, D1 |
(306) 0x41d910 FCMP D6, #0 |
(306) 0x41d914 FMUL D18, D18, D17 |
(306) 0x41d918 FMUL D19, D19, D7 |
(306) 0x41d91c FDIV D18, D18, D16 |
(306) 0x41d920 FDIV D19, D19, D20 |
(306) 0x41d924 FADD D18, D18, D19 |
(306) 0x41d928 FMUL D16, D16, D18 |
(306) 0x41d92c FDIV D16, D16, D2 |
(306) 0x41d930 FMINNM D7, D16, D7 |
(306) 0x41d934 FMINNM D7, D7, D17 |
(306) 0x41d938 FNEG D16, D7 |
(306) 0x41d93c FCSEL D16, D7, D16, #8 |
(306) 0x41d940 B 41d820 |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○100.00 | __kmp_invoke_microtask | libomp.so |
Path / |
Source file and lines | advec_mom.cpp:108-139 |
Module | exec |
nb instructions | 63 |
loop length | 252 |
nb stack references | 0 |
front end | 7.25 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.50 | 1.50 | 5.75 | 5.75 | 5.75 | 5.75 | 1.00 | 1.00 | 0.00 | 0.00 | 11.17 | 10.83 | 11.00 | 6.50 | 6.50 |
cycles | 1.50 | 1.50 | 5.75 | 5.75 | 5.75 | 5.75 | 1.00 | 1.00 | 0.00 | 0.00 | 11.17 | 10.83 | 11.00 | 6.50 | 6.50 |
Cycles executing div or sqrt instructions | NA |
Front-end | 7.25 |
Overall L1 | 11.17 |
all | 11% |
load | NA (no load vectorizable/vectorized instructions) |
store | 50% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SUB SP, SP, #192 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR D10, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP D9, D8, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP X29, X30, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X28, X27, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X26, X25, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X24, X23, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X22, X21, [SP, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X20, X19, [SP, #176] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #96 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W8, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR W9, [X3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR W10, [X5] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD W21, W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W20, [X4] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD W8, W9, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD W9, W10, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUBS W8, W8, W21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CCMP W9, W20, #4, #12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
B.LE 41d638 <.omp_outlined..12+0xf8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDP X11, X10, [X29, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDR X12, [X29, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X14, [X6] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUB W24, W9, W20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVN X9, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X3, SP, #44 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X4, X29, #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X5, X29, #40 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X13, [X7] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR W1, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X23, [X6, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADRP X0, <4625bc> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #4032 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X6, SP, #48 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X25, [X7, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STUR XZR, [X29, #488] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
UMADDL X27, W24, W8, X9 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X8, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X26, [X12, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X12, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X28, [X11, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X19, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X22, [X10, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STP X13, X14, [SP, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STUR X27, [X29, #472] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X8, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP W1, WZR, [SP, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X12, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
BL 402ee0 <@plt_start@+0x190> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDUR X8, [X29, #472] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDUR X13, [X29, #488] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X8, X27 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CSEL X8, X8, X27, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X13, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LE 41d660 <.omp_outlined..12+0x120> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 |
Source file and lines | advec_mom.cpp:108-139 |
Module | exec |
nb instructions | 63 |
loop length | 252 |
nb stack references | 0 |
front end | 7.25 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.50 | 1.50 | 5.75 | 5.75 | 5.75 | 5.75 | 1.00 | 1.00 | 0.00 | 0.00 | 11.17 | 10.83 | 11.00 | 6.50 | 6.50 |
cycles | 1.50 | 1.50 | 5.75 | 5.75 | 5.75 | 5.75 | 1.00 | 1.00 | 0.00 | 0.00 | 11.17 | 10.83 | 11.00 | 6.50 | 6.50 |
Cycles executing div or sqrt instructions | NA |
Front-end | 7.25 |
Overall L1 | 11.17 |
all | 11% |
load | NA (no load vectorizable/vectorized instructions) |
store | 50% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SUB SP, SP, #192 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR D10, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP D9, D8, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP X29, X30, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X28, X27, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X26, X25, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X24, X23, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X22, X21, [SP, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X20, X19, [SP, #176] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #96 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W8, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR W9, [X3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR W10, [X5] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD W21, W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W20, [X4] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD W8, W9, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD W9, W10, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUBS W8, W8, W21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CCMP W9, W20, #4, #12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
B.LE 41d638 <.omp_outlined..12+0xf8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDP X11, X10, [X29, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDR X12, [X29, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X14, [X6] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUB W24, W9, W20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVN X9, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X3, SP, #44 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X4, X29, #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X5, X29, #40 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X13, [X7] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR W1, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X23, [X6, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADRP X0, <4625bc> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #4032 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X6, SP, #48 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X25, [X7, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STUR XZR, [X29, #488] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
UMADDL X27, W24, W8, X9 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X8, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X26, [X12, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X12, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X28, [X11, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X19, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X22, [X10, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STP X13, X14, [SP, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STUR X27, [X29, #472] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X8, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP W1, WZR, [SP, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X12, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
BL 402ee0 <@plt_start@+0x190> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDUR X8, [X29, #472] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDUR X13, [X29, #488] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X8, X27 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CSEL X8, X8, X27, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X13, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LE 41d660 <.omp_outlined..12+0x120> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼.omp_outlined..12#0x41d540– | 3.68 | 4.91 |
▼Loop 305 - context.h:69-69 - exec– | 0 | 0 |
▼Loop 306 - advec_mom.cpp:108-139 - exec– | 0 | 0 |
▼Loop 308 - advec_mom.cpp:108-139 - exec– | 0 | 0 |
○Loop 307 - advec_mom.cpp:109-139 - exec | 3.68 | 4.89 |