Loop Id: 212 | Module: exec | Source: generate_chunk.cpp:85-98 [...] | Coverage: 0.03% |
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Loop Id: 212 | Module: exec | Source: generate_chunk.cpp:85-98 [...] | Coverage: 0.03% |
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0x422a88 MOVPRFX Z21, Z0 |
0x422a8c SDIV Z21.D, P0/M, Z21.D, Z2.D |
0x422a90 MOVPRFX Z22, Z0 |
0x422a94 MLS Z22.D, P0/M, Z21.D, Z2.D |
0x422a98 LSL Z25.D, Z22.D, #32 |
0x422a9c ADD X13, X9, X8,LSL #3 |
0x422aa0 LD1RD {Z24.D}, P0/Z, [X10] [19] |
0x422aa4 ADD Z0.D, Z0.D, Z1.D |
0x422aa8 ADD Z25.D, Z25.D, Z7.D |
0x422aac LD1RD {Z23.D}, P0/Z, [X13] [15] |
0x422ab0 LSL Z26.D, Z21.D, #32 |
0x422ab4 ADD Z26.D, Z26.D, Z7.D |
0x422ab8 ASR Z25.D, Z25.D, #-28 |
0x422abc ASR Z26.D, Z26.D, #-28 |
0x422ac0 LD1D {Z25.D}, P0/Z, [X4, Z25.D,LSL #3] [18] |
0x422ac4 FCMGE P1.D, P0/Z, Z25.D, Z23.D |
0x422ac8 LD1D {Z23.D}, P1/Z, [X4, Z22.D,SXTW #3] [26] |
0x422acc LD1D {Z25.D}, P1/Z, [X7, Z17.D,LSL #3] [14] |
0x422ad0 SXTW Z22.D, P0/M, Z22.D |
0x422ad4 FCMGT P1.D, P1/Z, Z25.D, Z23.D |
0x422ad8 MOVPRFX Z25, Z21 |
0x422adc SXTW Z25.D, P0/M, Z21.D |
0x422ae0 LD1D {Z23.D}, P1/Z, [X5, Z26.D,LSL #3] [28] |
0x422ae4 FCMGE P1.D, P1/Z, Z23.D, Z24.D |
0x422ae8 LD1D {Z23.D}, P1/Z, [X5, Z21.D,SXTW #3] [16] |
0x422aec LD1D {Z24.D}, P1/Z, [X20, Z17.D,LSL #3] [30] |
0x422af0 MSB Z21.D, P0/M, Z2.D, Z19.D |
0x422af4 ADD Z19.D, Z19.D, Z1.D |
0x422af8 FCMGT P1.D, P1/Z, Z24.D, Z23.D |
0x422afc MOVPRFX Z24, Z22 |
0x422b00 MLA Z24.D, P0/M, Z25.D, Z3.D |
0x422b04 LD1D {Z23.D}, P1/Z, [X11, Z17.D,LSL #3] [6] |
0x422b08 ST1D {Z23.D}, P1, [X12, Z24.D,LSL #3] [12] |
0x422b0c MOVPRFX Z24, Z22 |
0x422b10 MLA Z24.D, P0/M, Z25.D, Z4.D |
0x422b14 LD1D {Z23.D}, P1/Z, [X14, Z17.D,LSL #3] [9] |
0x422b18 ST1D {Z23.D}, P1, [X15, Z24.D,LSL #3] [5] |
0x422b1c MOVPRFX Z23, Z25 |
0x422b20 MUL Z23.D, P0/M, Z23.D, Z5.D |
0x422b24 ADR Z23.D, [Z18, Z23.D,LSL #3] [29] |
0x422b28 MOVPRFX Z24, Z25 |
0x422b2c MUL Z24.D, P0/M, Z24.D, Z6.D |
0x422b30 ADR Z24.D, [Z20, Z24.D,LSL #3] [7] |
0x422b34 LD1D {Z26.D}, P1/Z, [X17, Z17.D,LSL #3] [27] |
0x422b38 ADR Z27.D, [Z23, Z21.D,SXTW #3] [21] |
0x422b3c ADR Z28.D, [Z24, Z21.D,SXTW #3] [23] |
0x422b40 ST1D {Z26.D}, P1, [V27.D] [8] |
0x422b44 MOVPRFX Z26, Z21 |
0x422b48 SXTW Z26.D, P0/M, Z21.D |
0x422b4c CMPGE P2.D, P1/Z, Z22.D, Z26.D |
0x422b50 ADR Z26.D, [Z16, Z21.D,SXTW #3] [3] |
0x422b54 SUBS X25, X25, X22 |
0x422b58 LD1D {Z27.D}, P1/Z, [X1, Z17.D,LSL #3] [4] |
0x422b5c ADD Z23.D, Z23.D, Z26.D |
0x422b60 ST1D {Z27.D}, P1, [V28.D] [24] |
0x422b64 LD1D {Z22.D}, P2/Z, [X17, Z17.D,LSL #3] [27] |
0x422b68 ST1D {Z22.D}, P2, [V23.D] [1] |
0x422b6c ADD Z23.D, Z24.D, Z26.D |
0x422b70 LD1D {Z22.D}, P2/Z, [X1, Z17.D,LSL #3] [4] |
0x422b74 ST1D {Z22.D}, P2, [V23.D] [2] |
0x422b78 MOVPRFX Z22, Z25 |
0x422b7c ADD Z22.D, Z22.D, #1 |
0x422b80 MOVPRFX Z23, Z22 |
0x422b84 MUL Z23.D, P0/M, Z23.D, Z5.D |
0x422b88 LD1D {Z24.D}, P1/Z, [X17, Z17.D,LSL #3] [27] |
0x422b8c MUL Z22.D, P0/M, Z22.D, Z6.D |
0x422b90 ADR Z23.D, [Z18, Z23.D,LSL #3] [10] |
0x422b94 ADR Z25.D, [Z23, Z21.D,SXTW #3] [20] |
0x422b98 ADD Z23.D, Z23.D, Z26.D |
0x422b9c ST1D {Z24.D}, P1, [V25.D] [17] |
0x422ba0 LD1D {Z24.D}, P1/Z, [X1, Z17.D,LSL #3] [4] |
0x422ba4 ADR Z22.D, [Z20, Z22.D,LSL #3] [31] |
0x422ba8 ADR Z21.D, [Z22, Z21.D,SXTW #3] [11] |
0x422bac ADD Z22.D, Z22.D, Z26.D |
0x422bb0 ST1D {Z24.D}, P1, [V21.D] [25] |
0x422bb4 LD1D {Z21.D}, P2/Z, [X17, Z17.D,LSL #3] [27] |
0x422bb8 ST1D {Z21.D}, P2, [V23.D] [13] |
0x422bbc LD1D {Z21.D}, P2/Z, [X1, Z17.D,LSL #3] [4] |
0x422bc0 ST1D {Z21.D}, P2, [V22.D] [22] |
0x422bc4 B.NE 422a88 |
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/generate_chunk.cpp: 85 - 98 |
-------------------------------------------------------------------------------- |
85: #pragma omp parallel for simd collapse(2) |
86: for (int j = (0); j < (yrange); j++) { |
87: for (int i = (0); i < (xrange); i++) { |
88: double x_cent = state_xmin[state]; |
89: double y_cent = state_ymin[state]; |
90: if (state_geometry[state] == g_rect) { |
91: if (field.vertexx[i + 1] >= state_xmin[state] && field.vertexx[i] < state_xmax[state]) { |
92: if (field.vertexy[j + 1] >= state_ymin[state] && field.vertexy[j] < state_ymax[state]) { |
93: field.energy0(i, j) = state_energy[state]; |
94: field.density0(i, j) = state_density[state]; |
95: for (int kt = j; kt <= j + 1; ++kt) { |
96: for (int jt = i; jt <= i + 1; ++jt) { |
97: field.xvel0(jt, kt) = state_xvel[state]; |
98: field.yvel0(jt, kt) = state_yvel[state]; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○100.00 | __kmp_invoke_microtask | libomp.so |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.16 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.75 |
Bottlenecks | P6, P7, |
Function | .omp_outlined..2#0x4228e0 |
Source | context.h:69-69,generate_chunk.cpp:85-98 |
Source loop unroll info | unrolled by 4 |
Source loop unroll confidence level | high |
Unroll/vectorization loop type | NA |
Unroll factor | 4 |
CQA cycles | 24.50 |
CQA cycles if no scalar integer | 24.50 |
CQA cycles if FP arith vectorized | 24.50 |
CQA cycles if fully vectorized | 21.13 |
Front-end cycles | 10.00 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 0.75 |
P2 cycles | 0.75 |
P3 cycles | 1.00 |
P4 cycles | 0.50 |
P5 cycles | 24.50 |
P6 cycles | 24.50 |
P7 cycles | 5.00 |
P8 cycles | 5.00 |
P9 cycles | 14.00 |
P10 cycles | 14.00 |
P11 cycles | 0.00 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
P14 cycles | 1.00 - 0.50 |
Inter-iter dependencies cycles | 2 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 80.00 |
Nb uops | 80.00 |
Nb loads | NA |
Nb stores | 10.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 34.61 |
Bytes prefetched | 0.00 |
Bytes loaded | 528.00 |
Bytes stored | 320.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 71.79 |
Vectorization ratio load | 59.26 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 54.55 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | 54.55 |
Vector-efficiency ratio all | 88.46 |
Vector-efficiency ratio load | 69.44 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | 100.00 |
Vector-efficiency ratio add_sub | 65.91 |
Vector-efficiency ratio fma | 100.00 |
Vector-efficiency ratio div_sqrt | 100.00 |
Vector-efficiency ratio other | 100.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.16 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.75 |
Bottlenecks | P6, P7, |
Function | .omp_outlined..2#0x4228e0 |
Source | context.h:69-69,generate_chunk.cpp:85-98 |
Source loop unroll info | unrolled by 4 |
Source loop unroll confidence level | high |
Unroll/vectorization loop type | NA |
Unroll factor | 4 |
CQA cycles | 24.50 |
CQA cycles if no scalar integer | 24.50 |
CQA cycles if FP arith vectorized | 24.50 |
CQA cycles if fully vectorized | 21.13 |
Front-end cycles | 10.00 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 0.75 |
P2 cycles | 0.75 |
P3 cycles | 1.00 |
P4 cycles | 0.50 |
P5 cycles | 24.50 |
P6 cycles | 24.50 |
P7 cycles | 5.00 |
P8 cycles | 5.00 |
P9 cycles | 14.00 |
P10 cycles | 14.00 |
P11 cycles | 0.00 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
P14 cycles | 1.00 - 0.50 |
Inter-iter dependencies cycles | 2 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 80.00 |
Nb uops | 80.00 |
Nb loads | NA |
Nb stores | 10.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 34.61 |
Bytes prefetched | 0.00 |
Bytes loaded | 528.00 |
Bytes stored | 320.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 71.79 |
Vectorization ratio load | 59.26 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 54.55 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | 54.55 |
Vector-efficiency ratio all | 88.46 |
Vector-efficiency ratio load | 69.44 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | 100.00 |
Vector-efficiency ratio add_sub | 65.91 |
Vector-efficiency ratio fma | 100.00 |
Vector-efficiency ratio div_sqrt | 100.00 |
Vector-efficiency ratio other | 100.00 |
Path / |
Function | .omp_outlined..2#0x4228e0 |
Source file and lines | generate_chunk.cpp:85-98 |
Module | exec |
nb instructions | 80 |
loop length | 320 |
nb stack references | 0 |
front end | 10.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 0.75 | 0.75 | 1.00 | 0.50 | 24.50 | 24.50 | 5.00 | 5.00 | 14.00 | 14.00 | 0.00 | 0.00 | 0.00 |
cycles | 0.50 | 0.50 | 0.75 | 0.75 | 1.00 | 0.50 | 24.50 | 24.50 | 5.00 | 5.00 | 14.00 | 14.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 1.00-0.50 |
Longest recurrence chain latency (RecMII) | 2.00 |
Front-end | 10.00 |
Data deps. | 2.00 |
Overall L1 | 24.50 |
all | 70% |
load | 59% |
store | 100% |
mul | 100% |
add-sub | 54% |
fma | 100% |
other | 47% |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 71% |
load | 59% |
store | 100% |
mul | 100% |
add-sub | 54% |
fma | 100% |
div/sqrt | 100% |
other | 54% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOVPRFX Z21, Z0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
SDIV Z21.D, P0/M, Z21.D, Z2.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 7-20 | 1-0.50 |
MOVPRFX Z22, Z0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
MLS Z22.D, P0/M, Z21.D, Z2.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 |
LSL Z25.D, Z22.D, #32 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ADD X13, X9, X8,LSL #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LD1RD {Z24.D}, P0/Z, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
ADD Z0.D, Z0.D, Z1.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
ADD Z25.D, Z25.D, Z7.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
LD1RD {Z23.D}, P0/Z, [X13] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
LSL Z26.D, Z21.D, #32 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ADD Z26.D, Z26.D, Z7.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
ASR Z25.D, Z25.D, #-28 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ASR Z26.D, Z26.D, #-28 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
LD1D {Z25.D}, P0/Z, [X4, Z25.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
FCMGE P1.D, P0/Z, Z25.D, Z23.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
LD1D {Z23.D}, P1/Z, [X4, Z22.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
LD1D {Z25.D}, P1/Z, [X7, Z17.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
SXTW Z22.D, P0/M, Z22.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
FCMGT P1.D, P1/Z, Z25.D, Z23.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
MOVPRFX Z25, Z21 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
SXTW Z25.D, P0/M, Z21.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
LD1D {Z23.D}, P1/Z, [X5, Z26.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
FCMGE P1.D, P1/Z, Z23.D, Z24.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
LD1D {Z23.D}, P1/Z, [X5, Z21.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
LD1D {Z24.D}, P1/Z, [X20, Z17.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
MSB Z21.D, P0/M, Z2.D, Z19.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 |
ADD Z19.D, Z19.D, Z1.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
FCMGT P1.D, P1/Z, Z24.D, Z23.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
MOVPRFX Z24, Z22 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
MLA Z24.D, P0/M, Z25.D, Z3.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 |
LD1D {Z23.D}, P1/Z, [X11, Z17.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
ST1D {Z23.D}, P1, [X12, Z24.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
MOVPRFX Z24, Z22 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
MLA Z24.D, P0/M, Z25.D, Z4.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 |
LD1D {Z23.D}, P1/Z, [X14, Z17.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
ST1D {Z23.D}, P1, [X15, Z24.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
MOVPRFX Z23, Z25 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
MUL Z23.D, P0/M, Z23.D, Z5.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 |
ADR Z23.D, [Z18, Z23.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
MOVPRFX Z24, Z25 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
MUL Z24.D, P0/M, Z24.D, Z6.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 |
ADR Z24.D, [Z20, Z24.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
LD1D {Z26.D}, P1/Z, [X17, Z17.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
ADR Z27.D, [Z23, Z21.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
ADR Z28.D, [Z24, Z21.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
ST1D {Z26.D}, P1, [V27.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 2 |
MOVPRFX Z26, Z21 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
SXTW Z26.D, P0/M, Z21.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
CMPGE P2.D, P1/Z, Z22.D, Z26.D | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 |
ADR Z26.D, [Z16, Z21.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
SUBS X25, X25, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
LD1D {Z27.D}, P1/Z, [X1, Z17.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
ADD Z23.D, Z23.D, Z26.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
ST1D {Z27.D}, P1, [V28.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 2 |
LD1D {Z22.D}, P2/Z, [X17, Z17.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
ST1D {Z22.D}, P2, [V23.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 2 |
ADD Z23.D, Z24.D, Z26.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
LD1D {Z22.D}, P2/Z, [X1, Z17.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
ST1D {Z22.D}, P2, [V23.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 2 |
MOVPRFX Z22, Z25 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
ADD Z22.D, Z22.D, #1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
MOVPRFX Z23, Z22 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
MUL Z23.D, P0/M, Z23.D, Z5.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 |
LD1D {Z24.D}, P1/Z, [X17, Z17.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
MUL Z22.D, P0/M, Z22.D, Z6.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 |
ADR Z23.D, [Z18, Z23.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
ADR Z25.D, [Z23, Z21.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
ADD Z23.D, Z23.D, Z26.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
ST1D {Z24.D}, P1, [V25.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 2 |
LD1D {Z24.D}, P1/Z, [X1, Z17.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
ADR Z22.D, [Z20, Z22.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
ADR Z21.D, [Z22, Z21.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
ADD Z22.D, Z22.D, Z26.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
ST1D {Z24.D}, P1, [V21.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 2 |
LD1D {Z21.D}, P2/Z, [X17, Z17.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
ST1D {Z21.D}, P2, [V23.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 2 |
LD1D {Z21.D}, P2/Z, [X1, Z17.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
ST1D {Z21.D}, P2, [V22.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 2 |
B.NE 422a88 <.omp_outlined..2+0x1a8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Function | .omp_outlined..2#0x4228e0 |
Source file and lines | generate_chunk.cpp:85-98 |
Module | exec |
nb instructions | 80 |
loop length | 320 |
nb stack references | 0 |
front end | 10.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 0.75 | 0.75 | 1.00 | 0.50 | 24.50 | 24.50 | 5.00 | 5.00 | 14.00 | 14.00 | 0.00 | 0.00 | 0.00 |
cycles | 0.50 | 0.50 | 0.75 | 0.75 | 1.00 | 0.50 | 24.50 | 24.50 | 5.00 | 5.00 | 14.00 | 14.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 1.00-0.50 |
Longest recurrence chain latency (RecMII) | 2.00 |
Front-end | 10.00 |
Data deps. | 2.00 |
Overall L1 | 24.50 |
all | 70% |
load | 59% |
store | 100% |
mul | 100% |
add-sub | 54% |
fma | 100% |
other | 47% |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 71% |
load | 59% |
store | 100% |
mul | 100% |
add-sub | 54% |
fma | 100% |
div/sqrt | 100% |
other | 54% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOVPRFX Z21, Z0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
SDIV Z21.D, P0/M, Z21.D, Z2.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 7-20 | 1-0.50 |
MOVPRFX Z22, Z0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
MLS Z22.D, P0/M, Z21.D, Z2.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 |
LSL Z25.D, Z22.D, #32 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ADD X13, X9, X8,LSL #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LD1RD {Z24.D}, P0/Z, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
ADD Z0.D, Z0.D, Z1.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
ADD Z25.D, Z25.D, Z7.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
LD1RD {Z23.D}, P0/Z, [X13] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
LSL Z26.D, Z21.D, #32 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ADD Z26.D, Z26.D, Z7.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
ASR Z25.D, Z25.D, #-28 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ASR Z26.D, Z26.D, #-28 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
LD1D {Z25.D}, P0/Z, [X4, Z25.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
FCMGE P1.D, P0/Z, Z25.D, Z23.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
LD1D {Z23.D}, P1/Z, [X4, Z22.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
LD1D {Z25.D}, P1/Z, [X7, Z17.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
SXTW Z22.D, P0/M, Z22.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
FCMGT P1.D, P1/Z, Z25.D, Z23.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
MOVPRFX Z25, Z21 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
SXTW Z25.D, P0/M, Z21.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
LD1D {Z23.D}, P1/Z, [X5, Z26.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
FCMGE P1.D, P1/Z, Z23.D, Z24.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
LD1D {Z23.D}, P1/Z, [X5, Z21.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
LD1D {Z24.D}, P1/Z, [X20, Z17.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
MSB Z21.D, P0/M, Z2.D, Z19.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 |
ADD Z19.D, Z19.D, Z1.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
FCMGT P1.D, P1/Z, Z24.D, Z23.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
MOVPRFX Z24, Z22 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
MLA Z24.D, P0/M, Z25.D, Z3.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 |
LD1D {Z23.D}, P1/Z, [X11, Z17.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
ST1D {Z23.D}, P1, [X12, Z24.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
MOVPRFX Z24, Z22 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
MLA Z24.D, P0/M, Z25.D, Z4.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 |
LD1D {Z23.D}, P1/Z, [X14, Z17.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
ST1D {Z23.D}, P1, [X15, Z24.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
MOVPRFX Z23, Z25 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
MUL Z23.D, P0/M, Z23.D, Z5.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 |
ADR Z23.D, [Z18, Z23.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
MOVPRFX Z24, Z25 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
MUL Z24.D, P0/M, Z24.D, Z6.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 |
ADR Z24.D, [Z20, Z24.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
LD1D {Z26.D}, P1/Z, [X17, Z17.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
ADR Z27.D, [Z23, Z21.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
ADR Z28.D, [Z24, Z21.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
ST1D {Z26.D}, P1, [V27.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 2 |
MOVPRFX Z26, Z21 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
SXTW Z26.D, P0/M, Z21.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
CMPGE P2.D, P1/Z, Z22.D, Z26.D | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 |
ADR Z26.D, [Z16, Z21.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
SUBS X25, X25, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
LD1D {Z27.D}, P1/Z, [X1, Z17.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
ADD Z23.D, Z23.D, Z26.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
ST1D {Z27.D}, P1, [V28.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 2 |
LD1D {Z22.D}, P2/Z, [X17, Z17.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
ST1D {Z22.D}, P2, [V23.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 2 |
ADD Z23.D, Z24.D, Z26.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
LD1D {Z22.D}, P2/Z, [X1, Z17.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
ST1D {Z22.D}, P2, [V23.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 2 |
MOVPRFX Z22, Z25 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
ADD Z22.D, Z22.D, #1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
MOVPRFX Z23, Z22 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
MUL Z23.D, P0/M, Z23.D, Z5.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 |
LD1D {Z24.D}, P1/Z, [X17, Z17.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
MUL Z22.D, P0/M, Z22.D, Z6.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 |
ADR Z23.D, [Z18, Z23.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
ADR Z25.D, [Z23, Z21.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
ADD Z23.D, Z23.D, Z26.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
ST1D {Z24.D}, P1, [V25.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 2 |
LD1D {Z24.D}, P1/Z, [X1, Z17.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
ADR Z22.D, [Z20, Z22.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
ADR Z21.D, [Z22, Z21.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
ADD Z22.D, Z22.D, Z26.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
ST1D {Z24.D}, P1, [V21.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 2 |
LD1D {Z21.D}, P2/Z, [X17, Z17.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
ST1D {Z21.D}, P2, [V23.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 2 |
LD1D {Z21.D}, P2/Z, [X1, Z17.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
ST1D {Z21.D}, P2, [V22.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 2 |
B.NE 422a88 <.omp_outlined..2+0x1a8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |