Function: revert_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, cl ... | Module: exec | Source: revert.cpp:34-38 [...] | Coverage: 2.05% |
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Function: revert_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, cl ... | Module: exec | Source: revert.cpp:34-38 [...] | Coverage: 2.05% |
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/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/revert.cpp: 34 - 38 |
-------------------------------------------------------------------------------- |
34: #pragma omp parallel for simd collapse(2) |
35: for (int j = (y_min + 1); j < (y_max + 2); j++) { |
36: for (int i = (x_min + 1); i < (x_max + 2); i++) { |
37: density1(i, j) = density0(i, j); |
38: energy1(i, j) = energy0(i, j); |
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x42dce0 STP X29, X30, [SP, #944]! |
0x42dce4 ADD X29, SP, #0 |
0x42dce8 STP X19, X20, [SP, #16] |
0x42dcec STP X25, X26, [SP, #64] |
0x42dcf0 LDP W25, W19, [X0, #40] |
0x42dcf4 STP X23, X24, [SP, #48] |
0x42dcf8 ORR X23, XZR, X0 |
0x42dcfc LDR W20, [X0, #32] |
0x42dd00 ADD W25, W25, #1 |
0x42dd04 ADD W19, W19, #2 |
0x42dd08 LDR W0, [X0, #36] |
0x42dd0c CMP W25, W19 |
0x42dd10 B.GE 42de54 |
0x42dd14 ADD W20, W20, #1 |
0x42dd18 STP X21, X22, [SP, #32] |
0x42dd1c ADD W22, W0, #2 |
0x42dd20 SUB W26, W19, W25 |
0x42dd24 CMP W20, W22 |
0x42dd28 B.GE 42de50 |
0x42dd2c SUB W21, W22, W20 |
0x42dd30 BL 403530 |
0x42dd34 MADD W26, W26, W21, WZR |
0x42dd38 ORR W24, WZR, W0 |
0x42dd3c BL 4033c0 |
0x42dd40 ORR W2, WZR, W0 |
0x42dd44 UDIV W1, W26, W24 |
0x42dd48 MSUB W3, W1, W24, W26 |
0x42dd4c CMP W0, W3 |
0x42dd50 B.CC 42de68 |
(421) 0x42dd54 MADD W17, W1, W2, W3 |
(421) 0x42dd58 ADD W13, W1, W17 |
(421) 0x42dd5c CMP W17, W13 |
(421) 0x42dd60 B.CS 42de50 |
(421) 0x42dd64 UDIV W4, W17, W21 |
(421) 0x42dd68 MOVZ W14, #0 |
(421) 0x42dd6c CNTD X8, ALL |
(421) 0x42dd70 LDP X12, X11, [X23] |
(421) 0x42dd74 LDP X10, X9, [X23, #16] |
(421) 0x42dd78 MSUB W7, W4, W21, W17 |
(421) 0x42dd7c ADD W5, W4, W25 |
(421) 0x42dd80 SBFM X6, X5, #0, #31 |
(421) 0x42dd84 ADD W18, W7, W20 |
(421) 0x42dd88 SUB W15, W22, W18 |
(421) 0x42dd8c CMP W1, W15 |
(421) 0x42dd90 CSEL X30, X1, X15, #9 |
(421) 0x42dd94 ADD W15, W17, W30 |
(421) 0x42dd98 CMP W17, W15 |
(421) 0x42dd9c B.CS 42de3c |
(423) 0x42dda0 LDR X16, [X9] |
(423) 0x42dda4 SBFM X23, X18, #0, #31 |
(423) 0x42dda8 MOVZ X0, #0 |
(423) 0x42ddac WHILELO P0.D, XZR, X30 |
(423) 0x42ddb0 LDR X17, [X10] |
(423) 0x42ddb4 LDR X24, [X11] |
(423) 0x42ddb8 MADD X25, X6, X16, X23 |
(423) 0x42ddbc LDR X4, [X12] |
(423) 0x42ddc0 MADD X22, X6, X17, X23 |
(423) 0x42ddc4 LDR X18, [X10, #16] |
(423) 0x42ddc8 MADD X1, X6, X24, X23 |
(423) 0x42ddcc LDR X2, [X11, #16] |
(423) 0x42ddd0 MADD X5, X6, X4, X23 |
(423) 0x42ddd4 LDR X7, [X12, #16] |
(423) 0x42ddd8 ADD X26, X18, X22,LSL #3 |
(423) 0x42dddc LDR X16, [X9, #16] |
(423) 0x42dde0 ADD X3, X2, X1,LSL #3 |
(423) 0x42dde4 ADD X23, X7, X5,LSL #3 |
(423) 0x42dde8 ADD X25, X16, X25,LSL #3 |
(422) 0x42ddec LD1D {Z0.D}, P0/Z, [X23, X0,LSL #3] |
(422) 0x42ddf0 ST1D {Z0.D}, P0, [X3, X0,LSL #3] |
(422) 0x42ddf4 LD1D {Z1.D}, P0/Z, [X26, X0,LSL #3] |
(422) 0x42ddf8 ST1D {Z1.D}, P0, [X25, X0,LSL #3] |
(422) 0x42ddfc ADD X0, X0, X8 |
(422) 0x42de00 WHILELO P0.D, X0, X30 |
(422) 0x42de04 B.NE 42ddec |
(423) 0x42de08 ADD X6, X6, #1 |
(423) 0x42de0c ADD W30, W14, W6 |
(423) 0x42de10 CMP W19, W30 |
(423) 0x42de14 B.LE 42de50 |
(423) 0x42de18 SUB W1, W13, W15 |
(423) 0x42de1c ORR W17, WZR, W15 |
(423) 0x42de20 ORR W15, WZR, W21 |
(423) 0x42de24 ORR W18, WZR, W20 |
(423) 0x42de28 CMP W1, W15 |
(423) 0x42de2c CSEL X30, X1, X15, #9 |
(423) 0x42de30 ADD W15, W17, W30 |
(423) 0x42de34 CMP W17, W15 |
(423) 0x42de38 B.CC 42dda0 |
(424) 0x42de3c ADD X6, X6, #1 |
(424) 0x42de40 ORR W15, WZR, W17 |
(424) 0x42de44 ADD W30, W14, W6 |
(424) 0x42de48 CMP W19, W30 |
(424) 0x42de4c B.GT 42de18 |
(421) 0x42de50 LDP X21, X22, [SP, #32] |
(421) 0x42de54 LDP X19, X20, [SP, #16] |
(421) 0x42de58 LDP X23, X24, [SP, #48] |
(421) 0x42de5c LDP X25, X26, [SP, #64] |
(421) 0x42de60 LDP X29, X30, [SP], #80 |
(421) 0x42de64 RET |
(421) 0x42de68 ADD W1, W1, #1 |
(421) 0x42de6c MOVZ W3, #0 |
(421) 0x42de70 B 42dd54 |
0x42de74 HINT #0 |
0x42de78 HINT #0 |
0x42de7c HINT #0 |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►98.44+ | __kmp_GOMP_microtask_wrapper(i[...] | libomp.so | |
○ | __kmp_invoke_microtask | libomp.so | |
►1.56+ | GOMP_parallel | libomp.so | |
○ | revert(global_variables&) | revert.cpp:48 | exec |
○ | PdV(global_variables&, bool) | PdV.cpp:131 | exec |
○ | hydro(global_variables&, paral[...] | basic_string.h:906 | exec |
○ | main | iostream:74 | exec |
○ | __libc_start_main | libc-2.31.so | |
○ | _start | iostream:74 | exec |
Path / |
Source file and lines | revert.cpp:34-38 |
Module | exec |
nb instructions | 32 |
loop length | 128 |
nb stack references | 0 |
front end | 3.63 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 2.50 | 4.75 | 4.75 | 4.75 | 4.75 | 0.00 | 0.00 | 0.00 | 0.00 | 2.83 | 2.50 | 2.67 | 2.50 | 2.50 |
cycles | 2.50 | 2.50 | 4.75 | 4.75 | 4.75 | 4.75 | 0.00 | 0.00 | 0.00 | 0.00 | 2.83 | 2.50 | 2.67 | 2.50 | 2.50 |
Cycles executing div or sqrt instructions | 1.00-0.50 |
Front-end | 3.63 |
Overall L1 | 4.75 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STP X29, X30, [SP, #944]! | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X19, X20, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X25, X26, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDP W25, W19, [X0, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STP X23, X24, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ORR X23, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W20, [X0, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD W25, W25, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD W19, W19, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W0, [X0, #36] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP W25, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 42de54 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x174> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD W20, W20, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X21, X22, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD W22, W0, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB W26, W19, W25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP W20, W22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 42de50 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x170> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB W21, W22, W20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 403530 <@plt_start@+0x4b0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MADD W26, W26, W21, WZR | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ORR W24, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 4033c0 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR W2, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
UDIV W1, W26, W24 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5-12 | 1-0.50 |
MSUB W3, W1, W24, W26 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
CMP W0, W3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.CC 42de68 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x188> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 |
Source file and lines | revert.cpp:34-38 |
Module | exec |
nb instructions | 32 |
loop length | 128 |
nb stack references | 0 |
front end | 3.63 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 2.50 | 4.75 | 4.75 | 4.75 | 4.75 | 0.00 | 0.00 | 0.00 | 0.00 | 2.83 | 2.50 | 2.67 | 2.50 | 2.50 |
cycles | 2.50 | 2.50 | 4.75 | 4.75 | 4.75 | 4.75 | 0.00 | 0.00 | 0.00 | 0.00 | 2.83 | 2.50 | 2.67 | 2.50 | 2.50 |
Cycles executing div or sqrt instructions | 1.00-0.50 |
Front-end | 3.63 |
Overall L1 | 4.75 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STP X29, X30, [SP, #944]! | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X19, X20, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X25, X26, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDP W25, W19, [X0, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STP X23, X24, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ORR X23, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W20, [X0, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD W25, W25, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD W19, W19, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W0, [X0, #36] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP W25, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 42de54 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x174> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD W20, W20, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X21, X22, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD W22, W0, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB W26, W19, W25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP W20, W22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 42de50 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x170> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB W21, W22, W20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 403530 <@plt_start@+0x4b0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MADD W26, W26, W21, WZR | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ORR W24, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 4033c0 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR W2, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
UDIV W1, W26, W24 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5-12 | 1-0.50 |
MSUB W3, W1, W24, W26 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
CMP W0, W3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.CC 42de68 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x188> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼revert_kernel(int, int, int, int, clover::Buffer2D | 2.05 | 2.72 |
▼Loop 421 - revert.cpp:34-38 - exec– | 0 | 0 |
▼Loop 423 - revert.cpp:36-38 - exec– | 0 | 0.01 |
○Loop 422 - revert.cpp:37-38 - exec | 2.05 | 2.71 |
○Loop 424 - revert.cpp:36-38 - exec | 0 | 0 |