Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:44-48 [...] | Coverage: 1.37% |
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Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:44-48 [...] | Coverage: 1.37% |
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/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 44 - 48 |
-------------------------------------------------------------------------------- |
44: #pragma omp parallel for simd collapse(2) |
45: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
46: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
47: pre_vol(i, j) = volume(i, j) + (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j)); |
48: post_vol(i, j) = pre_vol(i, j) - (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j)); |
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x41f080 STP X29, X30, [SP, #944]! |
0x41f084 ADD X29, SP, #0 |
0x41f088 STP X19, X20, [SP, #16] |
0x41f08c STP X25, X26, [SP, #64] |
0x41f090 LDP W25, W19, [X0, #48] |
0x41f094 LDP W20, W3, [X0, #40] |
0x41f098 SUB W25, W25, #1 |
0x41f09c ADD W19, W19, #4 |
0x41f0a0 CMP W25, W19 |
0x41f0a4 B.GE 41f268 |
0x41f0a8 SUB W20, W20, #1 |
0x41f0ac STP X21, X22, [SP, #32] |
0x41f0b0 ADD W22, W3, #4 |
0x41f0b4 SUB W26, W19, W25 |
0x41f0b8 CMP W20, W22 |
0x41f0bc B.GE 41f284 |
0x41f0c0 SUB W21, W22, W20 |
0x41f0c4 STP X23, X24, [SP, #48] |
0x41f0c8 ORR X23, XZR, X0 |
0x41f0cc MADD W26, W26, W21, WZR |
0x41f0d0 BL 403530 |
0x41f0d4 ORR W24, WZR, W0 |
0x41f0d8 BL 4033c0 |
0x41f0dc UDIV W1, W26, W24 |
0x41f0e0 ORR W2, WZR, W0 |
0x41f0e4 MSUB W0, W1, W24, W26 |
0x41f0e8 CMP W2, W0 |
0x41f0ec B.CC 41f278 |
(177) 0x41f0f0 MADD W18, W1, W2, W0 |
(177) 0x41f0f4 ADD W15, W1, W18 |
(177) 0x41f0f8 CMP W18, W15 |
(177) 0x41f0fc B.CS 41f260 |
(177) 0x41f100 UDIV W4, W18, W21 |
(177) 0x41f104 MOVZ W16, #0 |
(177) 0x41f108 CNTD X9, ALL |
(177) 0x41f10c LDP X14, X13, [X23] |
(177) 0x41f110 LDP X12, X11, [X23, #16] |
(177) 0x41f114 LDR X10, [X23, #32] |
(177) 0x41f118 MSUB W5, W4, W21, W18 |
(177) 0x41f11c ADD W6, W4, W25 |
(177) 0x41f120 SBFM X30, X6, #0, #31 |
(177) 0x41f124 ADD W8, W5, W20 |
(177) 0x41f128 SUB W17, W22, W8 |
(177) 0x41f12c CMP W1, W17 |
(177) 0x41f130 CSEL X25, X1, X17, #9 |
(177) 0x41f134 ADD W17, W18, W25 |
(177) 0x41f138 CMP W18, W17 |
(177) 0x41f13c B.CS 41f23c |
(179) 0x41f140 LDR X24, [X12] |
(179) 0x41f144 SBFM X22, X8, #0, #31 |
(179) 0x41f148 ADD X18, X30, #1 |
(179) 0x41f14c ADD X7, X22, #1 |
(179) 0x41f150 MOVZ X0, #0 |
(179) 0x41f154 WHILELO P0.D, XZR, X25 |
(179) 0x41f158 LDR X3, [X11] |
(179) 0x41f15c LDR X8, [X10] |
(179) 0x41f160 MADD X2, X30, X24, X24 |
(179) 0x41f164 LDR X6, [X12, #16] |
(179) 0x41f168 MADD X26, X30, X3, X22 |
(179) 0x41f16c LDR X3, [X10, #16] |
(179) 0x41f170 SUB X1, X2, X24 |
(179) 0x41f174 ADD X4, X2, X22 |
(179) 0x41f178 MADD X23, X30, X8, X22 |
(179) 0x41f17c ADD X5, X1, X22 |
(179) 0x41f180 LDR X2, [X13] |
(179) 0x41f184 ADD X1, X6, X4,LSL #3 |
(179) 0x41f188 ADD X8, X6, X5,LSL #3 |
(179) 0x41f18c ADD X24, X3, X23,LSL #3 |
(179) 0x41f190 LDR X3, [X14] |
(179) 0x41f194 LDR X23, [X13, #16] |
(179) 0x41f198 MADD X4, X30, X2, XZR |
(179) 0x41f19c ADD X6, X4, X22 |
(179) 0x41f1a0 ADD X7, X7, X4 |
(179) 0x41f1a4 ADD X5, X23, X7,LSL #3 |
(179) 0x41f1a8 ADD X2, X23, X6,LSL #3 |
(179) 0x41f1ac MADD X23, X30, X3, X22 |
(179) 0x41f1b0 LDR X30, [X11, #16] |
(179) 0x41f1b4 ADD X22, X30, X26,LSL #3 |
(179) 0x41f1b8 LDR X26, [X14, #16] |
(179) 0x41f1bc ADD X4, X26, X23,LSL #3 |
(178) 0x41f1c0 LD1D {Z1.D}, P0/Z, [X4, X0,LSL #3] |
(178) 0x41f1c4 LD1D {Z0.D}, P0/Z, [X5, X0,LSL #3] |
(178) 0x41f1c8 LD1D {Z3.D}, P0/Z, [X2, X0,LSL #3] |
(178) 0x41f1cc LD1D {Z5.D}, P0/Z, [X8, X0,LSL #3] |
(178) 0x41f1d0 LD1D {Z2.D}, P0/Z, [X1, X0,LSL #3] |
(178) 0x41f1d4 FADD Z4.D, Z0.D, Z1.D |
(178) 0x41f1d8 FADD Z6.D, Z5.D, Z3.D |
(178) 0x41f1dc FSUB Z7.D, Z4.D, Z6.D |
(178) 0x41f1e0 FADD Z16.D, Z7.D, Z2.D |
(178) 0x41f1e4 ST1D {Z16.D}, P0, [X22, X0,LSL #3] |
(178) 0x41f1e8 LD1D {Z17.D}, P0/Z, [X2, X0,LSL #3] |
(178) 0x41f1ec LD1D {Z18.D}, P0/Z, [X5, X0,LSL #3] |
(178) 0x41f1f0 FSUB Z19.D, Z17.D, Z18.D |
(178) 0x41f1f4 FADD Z20.D, Z19.D, Z16.D |
(178) 0x41f1f8 ST1D {Z20.D}, P0, [X24, X0,LSL #3] |
(178) 0x41f1fc ADD X0, X0, X9 |
(178) 0x41f200 WHILELO P0.D, X0, X25 |
(178) 0x41f204 B.NE 41f1c0 |
(179) 0x41f208 ADD W25, W16, W18 |
(179) 0x41f20c ORR X30, XZR, X18 |
(179) 0x41f210 CMP W19, W25 |
(179) 0x41f214 B.LE 41f260 |
(179) 0x41f218 SUB W1, W15, W17 |
(179) 0x41f21c ORR W18, WZR, W17 |
(179) 0x41f220 ORR W17, WZR, W21 |
(179) 0x41f224 ORR W8, WZR, W20 |
(179) 0x41f228 CMP W1, W17 |
(179) 0x41f22c CSEL X25, X1, X17, #9 |
(179) 0x41f230 ADD W17, W18, W25 |
(179) 0x41f234 CMP W18, W17 |
(179) 0x41f238 B.CC 41f140 |
(180) 0x41f23c ORR W17, WZR, W18 |
(180) 0x41f240 ADD X18, X30, #1 |
(180) 0x41f244 ADD W25, W16, W18 |
(180) 0x41f248 ORR X30, XZR, X18 |
(180) 0x41f24c CMP W19, W25 |
(180) 0x41f250 B.GT 41f218 |
(177) 0x41f254 HINT #0 |
(177) 0x41f258 HINT #0 |
(177) 0x41f25c HINT #0 |
(177) 0x41f260 LDP X21, X22, [SP, #32] |
(177) 0x41f264 LDP X23, X24, [SP, #48] |
(177) 0x41f268 LDP X19, X20, [SP, #16] |
(177) 0x41f26c LDP X25, X26, [SP, #64] |
(177) 0x41f270 LDP X29, X30, [SP], #80 |
(177) 0x41f274 RET |
(177) 0x41f278 ADD W1, W1, #1 |
(177) 0x41f27c MOVZ W0, #0 |
(177) 0x41f280 B 41f0f0 |
0x41f284 LDP X21, X22, [SP, #32] |
0x41f288 B 41f268 |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►98.44+ | __kmp_GOMP_microtask_wrapper(i[...] | libomp.so | |
○ | __kmp_invoke_microtask | libomp.so | |
►1.56+ | GOMP_parallel | libomp.so | |
○ | advec_cell_kernel(int, int, in[...] | advec_cell.cpp:44 | exec |
○ | advec_cell_driver(global_varia[...] | advec_cell.cpp:232 | exec |
○ | advection(global_variables&) | advection.cpp:50 | exec |
○ | hydro(global_variables&, paral[...] | basic_string.h:906 | exec |
○ | main | iostream:74 | exec |
○ | __libc_start_main | libc-2.31.so | |
○ | _start | iostream:74 | exec |
Path / |
Source file and lines | advec_cell.cpp:44-48 |
Module | exec |
nb instructions | 30 |
loop length | 120 |
nb stack references | 0 |
front end | 3.75 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.00 | 3.00 | 4.75 | 4.75 | 4.75 | 4.75 | 0.00 | 0.00 | 0.00 | 0.00 | 2.83 | 2.50 | 2.67 | 2.50 | 2.50 |
cycles | 3.00 | 3.00 | 4.75 | 4.75 | 4.75 | 4.75 | 0.00 | 0.00 | 0.00 | 0.00 | 2.83 | 2.50 | 2.67 | 2.50 | 2.50 |
Cycles executing div or sqrt instructions | 1.00-0.50 |
Front-end | 3.75 |
Overall L1 | 4.75 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STP X29, X30, [SP, #944]! | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X19, X20, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X25, X26, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDP W25, W19, [X0, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDP W20, W3, [X0, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUB W25, W25, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD W19, W19, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP W25, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 41f268 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x1e8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB W20, W20, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X21, X22, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD W22, W3, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB W26, W19, W25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP W20, W22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 41f284 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x204> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB W21, W22, W20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X23, X24, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ORR X23, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MADD W26, W26, W21, WZR | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
BL 403530 <@plt_start@+0x4b0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR W24, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 4033c0 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
UDIV W1, W26, W24 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5-12 | 1-0.50 |
ORR W2, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MSUB W0, W1, W24, W26 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
CMP W2, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.CC 41f278 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x1f8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDP X21, X22, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
B 41f268 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x1e8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Source file and lines | advec_cell.cpp:44-48 |
Module | exec |
nb instructions | 30 |
loop length | 120 |
nb stack references | 0 |
front end | 3.75 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.00 | 3.00 | 4.75 | 4.75 | 4.75 | 4.75 | 0.00 | 0.00 | 0.00 | 0.00 | 2.83 | 2.50 | 2.67 | 2.50 | 2.50 |
cycles | 3.00 | 3.00 | 4.75 | 4.75 | 4.75 | 4.75 | 0.00 | 0.00 | 0.00 | 0.00 | 2.83 | 2.50 | 2.67 | 2.50 | 2.50 |
Cycles executing div or sqrt instructions | 1.00-0.50 |
Front-end | 3.75 |
Overall L1 | 4.75 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STP X29, X30, [SP, #944]! | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X19, X20, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X25, X26, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDP W25, W19, [X0, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDP W20, W3, [X0, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUB W25, W25, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD W19, W19, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP W25, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 41f268 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x1e8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB W20, W20, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X21, X22, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD W22, W3, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB W26, W19, W25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP W20, W22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 41f284 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x204> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB W21, W22, W20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X23, X24, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ORR X23, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MADD W26, W26, W21, WZR | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
BL 403530 <@plt_start@+0x4b0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR W24, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 4033c0 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
UDIV W1, W26, W24 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5-12 | 1-0.50 |
ORR W2, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MSUB W0, W1, W24, W26 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
CMP W2, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.CC 41f278 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x1f8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDP X21, X22, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
B 41f268 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x1e8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D | 1.37 | 1.82 |
▼Loop 177 - advec_cell.cpp:44-48 - exec– | 0 | 0 |
▼Loop 179 - advec_cell.cpp:46-48 - exec– | 0 | 0.01 |
○Loop 178 - advec_cell.cpp:47-48 - exec | 1.37 | 1.81 |
○Loop 180 - advec_cell.cpp:48-48 - exec | 0 | 0 |