Function: .omp_outlined..20 | Module: exec | Source: advec_mom.cpp:180-211 [...] | Coverage: 3.99% |
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Function: .omp_outlined..20 | Module: exec | Source: advec_mom.cpp:180-211 [...] | Coverage: 3.99% |
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/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 180 - 211 |
-------------------------------------------------------------------------------- |
180: #pragma omp parallel for simd collapse(2) |
181: for (int j = (y_min - 1 + 1); j < (y_max + 1 + 2); j++) { |
182: for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) |
183: ({ |
184: int upwind, donor, downwind, dif; |
185: double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s; |
186: if (node_flux(i, j) < 0.0) { |
187: upwind = j + 2; |
188: donor = j + 1; |
189: downwind = j; |
190: dif = donor; |
191: } else { |
192: upwind = j - 1; |
193: donor = j; |
194: downwind = j + 1; |
195: dif = upwind; |
196: } |
197: sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(i, donor)); |
198: width = celldy[j]; |
199: vdiffuw = vel1(i, donor) - vel1(i, upwind); |
200: vdiffdw = vel1(i, downwind) - vel1(i, donor); |
201: limiter = 0.0; |
202: if (vdiffuw * vdiffdw > 0.0) { |
203: auw = std::fabs(vdiffuw); |
204: adw = std::fabs(vdiffdw); |
205: wind = 1.0; |
206: if (vdiffdw <= 0.0) wind = -1.0; |
207: limiter = |
208: wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldy[dif]) / 6.0, auw), adw); |
209: } |
210: advec_vel_s = vel1(i, donor) + (1.0 - sigma) * limiter; |
211: mom_flux(i, j) = advec_vel_s * node_flux(i, j); |
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x41e160 SUB SP, SP, #192 |
0x41e164 STR D10, [SP, #64] |
0x41e168 STP D9, D8, [SP, #80] |
0x41e16c STP X29, X30, [SP, #96] |
0x41e170 STP X28, X27, [SP, #112] |
0x41e174 STP X26, X25, [SP, #128] |
0x41e178 STP X24, X23, [SP, #144] |
0x41e17c STP X22, X21, [SP, #160] |
0x41e180 STP X20, X19, [SP, #176] |
0x41e184 ADD X29, SP, #96 |
0x41e188 LDR W8, [X3] |
0x41e18c LDR W20, [X2] |
0x41e190 LDR W9, [X4] |
0x41e194 ADD W8, W8, #3 |
0x41e198 LDR W10, [X5] |
0x41e19c ADD W21, W9, #1 |
0x41e1a0 ADD W9, W10, #3 |
0x41e1a4 SUBS W8, W8, W20 |
0x41e1a8 CCMP W9, W21, #4, #12 |
0x41e1ac B.LE 41e258 |
0x41e1b0 LDP X11, X10, [X29, #104] |
0x41e1b4 LDR X12, [X29, #96] |
0x41e1b8 LDR X14, [X6] |
0x41e1bc SUB W24, W9, W21 |
0x41e1c0 MOVN X9, #0 |
0x41e1c4 ADD X3, SP, #44 |
0x41e1c8 SUB X4, X29, #24 |
0x41e1cc SUB X5, X29, #40 |
0x41e1d0 LDR X13, [X7] |
0x41e1d4 LDR W1, [X0] |
0x41e1d8 LDR X23, [X6, #16] |
0x41e1dc ADRP X0, |
0x41e1e0 ADD X0, X0, #224 |
0x41e1e4 ADD X6, SP, #48 |
0x41e1e8 MOVZ W2, #34 |
0x41e1ec LDR X25, [X7, #16] |
0x41e1f0 MOVZ W7, #1 |
0x41e1f4 STUR XZR, [X29, #488] |
0x41e1f8 UMADDL X19, W24, W8, X9 |
0x41e1fc MOVZ W8, #1 |
0x41e200 STR X8, [SP, #48] |
0x41e204 LDR X27, [X11] |
0x41e208 LDR X28, [X11, #16] |
0x41e20c LDR X11, [X10] |
0x41e210 LDR X26, [X12, #8] |
0x41e214 LDR X22, [X10, #16] |
0x41e218 STP X13, X14, [SP, #24] |
0x41e21c STUR X19, [X29, #472] |
0x41e220 STR X8, [SP] |
0x41e224 STP W1, WZR, [SP, #40] |
0x41e228 STR X11, [SP, #16] |
0x41e22c BL 402ee0 |
0x41e230 LDUR X8, [X29, #472] |
0x41e234 LDUR X13, [X29, #488] |
0x41e238 CMP X8, X19 |
0x41e23c CSEL X8, X8, X19, #11 |
0x41e240 CMP X13, X8 |
0x41e244 B.LE 41e280 |
(357) 0x41e248 LDR W1, [SP, #40] |
(357) 0x41e24c ADRP X0, |
(357) 0x41e250 ADD X0, X0, #248 |
(357) 0x41e254 BL 402d80 |
(357) 0x41e258 LDP D9, D8, [SP, #80] |
(357) 0x41e25c LDR D10, [SP, #64] |
(357) 0x41e260 LDP X20, X19, [SP, #176] |
(357) 0x41e264 LDP X22, X21, [SP, #160] |
(357) 0x41e268 LDP X24, X23, [SP, #144] |
(357) 0x41e26c LDP X26, X25, [SP, #128] |
(357) 0x41e270 LDP X28, X27, [SP, #112] |
(357) 0x41e274 LDP X29, X30, [SP, #96] |
(357) 0x41e278 ADD SP, SP, #192 |
(357) 0x41e27c RET |
(357) 0x41e280 ADD X8, X8, #1 |
(357) 0x41e284 CNTD X10, ALL |
(357) 0x41e288 ORR X9, XZR, X13 |
(357) 0x41e28c SUB X11, X8, X13 |
(357) 0x41e290 CMP X11, X10 |
(357) 0x41e294 B.CC 41e424 |
(357) 0x41e298 UDIV X9, X11, X10 |
(357) 0x41e29c PTRUE P0.D, ALL |
(357) 0x41e2a0 FDUP Z19.D, #0 |
(357) 0x41e2a4 FDUP Z20.D, #24 |
(357) 0x41e2a8 DUP Z21.D, #0 |
(357) 0x41e2ac MADD X12, X9, X10, XZR |
(357) 0x41e2b0 INDEX Z0.D, X13, #1 |
(357) 0x41e2b4 ADD X9, X13, X12 |
(357) 0x41e2b8 LDR X13, [SP, #32] |
(357) 0x41e2bc DUP Z1.D, X10 |
(357) 0x41e2c0 SUB X11, X11, X12 |
(357) 0x41e2c4 DUP Z2.D, X24 |
(357) 0x41e2c8 DUP Z3.D, X20 |
(357) 0x41e2cc DUP Z4.D, X21 |
(357) 0x41e2d0 DUP Z7.D, X27 |
(357) 0x41e2d4 DUP Z5.D, X13 |
(357) 0x41e2d8 LDR X13, [SP, #24] |
(357) 0x41e2dc DUP Z6.D, X13 |
(357) 0x41e2e0 LDR X13, [SP, #16] |
(357) 0x41e2e4 DUP Z16.D, X13 |
(357) 0x41e2e8 ADD W13, W20, #1 |
(357) 0x41e2ec DUP Z17.D, X13 |
(357) 0x41e2f0 SUB W13, W20, #1 |
(357) 0x41e2f4 DUP Z18.D, X13 |
(357) 0x41e2f8 ADD W13, W20, #2 |
(357) 0x41e2fc DUP Z22.D, X13 |
(356) 0x41e300 MOVPRFX Z23, Z0 |
(356) 0x41e304 SDIV Z23.D, P0/M, Z23.D, Z2.D |
(356) 0x41e308 MOVPRFX Z25, Z0 |
(356) 0x41e30c MLS Z25.D, P0/M, Z23.D, Z2.D |
(356) 0x41e310 ADD Z25.D, Z4.D, Z25.D |
(356) 0x41e314 ADD Z24.D, Z3.D, Z23.D |
(356) 0x41e318 MOVPRFX Z26, Z24 |
(356) 0x41e31c SXTW Z26.D, P0/M, Z24.D |
(356) 0x41e320 SUBS X12, X12, X10 |
(356) 0x41e324 ADD Z28.D, Z17.D, Z23.D |
(356) 0x41e328 MOVPRFX Z29, Z28 |
(356) 0x41e32c SXTW Z29.D, P0/M, Z28.D |
(356) 0x41e330 ADD Z30.D, Z18.D, Z23.D |
(356) 0x41e334 ADD Z23.D, Z22.D, Z23.D |
(356) 0x41e338 ADD Z0.D, Z0.D, Z1.D |
(356) 0x41e33c SXTW Z25.D, P0/M, Z25.D |
(356) 0x41e340 MOVPRFX Z27, Z25 |
(356) 0x41e344 MLA Z27.D, P0/M, Z5.D, Z26.D |
(356) 0x41e348 LD1D {Z27.D}, P0/Z, [X23, Z27.D,LSL #3] |
(356) 0x41e34c MOVPRFX Z8, Z27 |
(356) 0x41e350 FABS Z8.D, P0/M, Z27.D |
(356) 0x41e354 FCMLT P1.D, P0/Z, Z27.D, #0 |
(356) 0x41e358 SEL Z31.D, P1, Z26.D, Z29.D |
(356) 0x41e35c SEL Z29.D, P1, Z29.D, Z26.D |
(356) 0x41e360 SEL Z23.D, P1, Z23.D, Z30.D |
(356) 0x41e364 MOVPRFX Z9, Z25 |
(356) 0x41e368 MLA Z9.D, P0/M, Z29.D, Z6.D |
(356) 0x41e36c LD1D {Z9.D}, P0/Z, [X25, Z9.D,LSL #3] |
(356) 0x41e370 SEL Z28.D, P1, Z28.D, Z30.D |
(356) 0x41e374 SXTW Z23.D, P0/M, Z23.D |
(356) 0x41e378 MAD Z29.D, P0/M, Z7.D, Z25.D |
(356) 0x41e37c MAD Z31.D, P0/M, Z7.D, Z25.D |
(356) 0x41e380 MAD Z23.D, P0/M, Z7.D, Z25.D |
(356) 0x41e384 FDIV Z8.D, P0/M, Z8.D, Z9.D |
(356) 0x41e388 MOVPRFX Z9, Z8 |
(356) 0x41e38c FADD Z9.D, P0/M, Z9.D, #1 |
(356) 0x41e390 LD1D {Z29.D}, P0/Z, [X28, Z29.D,LSL #3] |
(356) 0x41e394 LD1D {Z23.D}, P0/Z, [X28, Z23.D,LSL #3] |
(356) 0x41e398 LD1D {Z31.D}, P0/Z, [X28, Z31.D,LSL #3] |
(356) 0x41e39c FSUB Z30.D, Z29.D, Z23.D |
(356) 0x41e3a0 FSUB Z10.D, Z31.D, Z29.D |
(356) 0x41e3a4 FABD Z23.D, P0/M, Z23.D, Z29.D |
(356) 0x41e3a8 FMUL Z30.D, Z30.D, Z10.D |
(356) 0x41e3ac FMUL Z9.D, Z9.D, Z23.D |
(356) 0x41e3b0 FCMLE P2.D, P0/Z, Z10.D, #0 |
(356) 0x41e3b4 EOR P2.B, P0/Z, P2.B, P0.B |
(356) 0x41e3b8 FCMGT P1.D, P0/Z, Z30.D, #0 |
(356) 0x41e3bc MOVPRFX Z30, Z31 |
(356) 0x41e3c0 FABD Z30.D, P0/M, Z30.D, Z29.D |
(356) 0x41e3c4 FSUB Z31.D, Z19.D, Z8.D |
(356) 0x41e3c8 LD1D {Z24.D}, P1/Z, [X26, Z24.D,SXTW #3] |
(356) 0x41e3cc LD1D {Z28.D}, P1/Z, [X26, Z28.D,SXTW #3] |
(356) 0x41e3d0 FMUL Z31.D, Z31.D, Z30.D |
(356) 0x41e3d4 FDIV Z31.D, P0/M, Z31.D, Z24.D |
(356) 0x41e3d8 FDIVR Z28.D, P0/M, Z28.D, Z9.D |
(356) 0x41e3dc FADD Z28.D, Z31.D, Z28.D |
(356) 0x41e3e0 FMUL Z24.D, Z24.D, Z28.D |
(356) 0x41e3e4 FDIV Z24.D, P0/M, Z24.D, Z20.D |
(356) 0x41e3e8 FMINNM Z23.D, P0/M, Z23.D, Z24.D |
(356) 0x41e3ec FMINNM Z23.D, P0/M, Z23.D, Z30.D |
(356) 0x41e3f0 MOVPRFX Z24, Z23 |
(356) 0x41e3f4 FNEG Z24.D, P0/M, Z23.D |
(356) 0x41e3f8 SEL Z23.D, P2, Z23.D, Z24.D |
(356) 0x41e3fc MOVPRFX Z24, Z8 |
(356) 0x41e400 FSUBR Z24.D, P0/M, Z24.D, #1 |
(356) 0x41e404 SEL Z23.D, P1, Z23.D, Z21.D |
(356) 0x41e408 FMAD Z23.D, P0/M, Z24.D, Z29.D |
(356) 0x41e40c MOVPRFX Z24, Z25 |
(356) 0x41e410 MLA Z24.D, P0/M, Z16.D, Z26.D |
(356) 0x41e414 FMUL Z23.D, Z27.D, Z23.D |
(356) 0x41e418 ST1D {Z23.D}, P0, [X22, Z24.D,LSL #3] |
(356) 0x41e41c B.NE 41e300 |
(357) 0x41e420 CBZ X11, 41e248 |
(355) 0x41e424 LDP X0, X18, [SP, #24] |
(355) 0x41e428 LDR X1, [SP, #16] |
(355) 0x41e42c SUB W10, WZR, W24 |
(355) 0x41e430 FMOV D0, #2.0000000 |
(355) 0x41e434 FMOV D1, #1.0000000 |
(355) 0x41e438 FMOV D2, #6.0000000 |
(355) 0x41e43c B 41e460 |
(355) 0x41e440 FSUB D4, D1, S4 |
(355) 0x41e444 MADD X11, X1, X12, X11 |
(355) 0x41e448 ADD X9, X9, #1 |
(355) 0x41e44c CMP X8, X9 |
(355) 0x41e450 FMADD D4, D4, D16, D5 |
(355) 0x41e454 FMUL D3, D3, D4 |
(355) 0x41e458 STR D3, [X22, X11,LSL #3] |
(355) 0x41e45c B.EQ 41e248 |
(355) 0x41e460 SDIV X11, X9, X24 |
(355) 0x41e464 ADD W12, W21, W9 |
(355) 0x41e468 ADD W13, W20, W11 |
(355) 0x41e46c MADD W11, W10, W11, W12 |
(355) 0x41e470 SBFM X11, X11, #0, #31 |
(355) 0x41e474 SBFM X12, X13, #0, #31 |
(355) 0x41e478 ADD W13, W13, #1 |
(355) 0x41e47c MADD X14, X18, X12, X11 |
(355) 0x41e480 LDR D3, [X23, X14,LSL #3] |
(355) 0x41e484 SBFM X14, X13, #0, #31 |
(355) 0x41e488 FCMP D3, #0 |
(355) 0x41e48c B.PL 41e4a0 |
(355) 0x41e490 ADD W16, W12, #2 |
(355) 0x41e494 ORR X15, XZR, X12 |
(355) 0x41e498 B 41e4b0 |
0x41e49c HINT #0 |
(354) 0x41e4a0 SUB W13, W12, #1 |
(354) 0x41e4a4 ORR X15, XZR, X14 |
(354) 0x41e4a8 ORR X14, XZR, X12 |
(354) 0x41e4ac ORR W16, WZR, W13 |
(355) 0x41e4b0 MADD X17, X14, X0, X11 |
(355) 0x41e4b4 FABS D4, D3 |
(355) 0x41e4b8 MADD X14, X14, X27, X11 |
(355) 0x41e4bc MOVI D16, #0 |
(355) 0x41e4c0 LDR D5, [X25, X17,LSL #3] |
(355) 0x41e4c4 FDIV D4, D4, D5 |
(355) 0x41e4c8 LDR D5, [X28, X14,LSL #3] |
(355) 0x41e4cc SBFM X14, X16, #0, #31 |
(355) 0x41e4d0 MADD X14, X27, X14, X11 |
(355) 0x41e4d4 LDR D6, [X28, X14,LSL #3] |
(355) 0x41e4d8 MADD X14, X15, X27, X11 |
(355) 0x41e4dc FSUB D7, D5, S6 |
(355) 0x41e4e0 LDR D6, [X28, X14,LSL #3] |
(355) 0x41e4e4 FSUB D6, D6, S5 |
(355) 0x41e4e8 FMUL D17, D7, D6 |
(355) 0x41e4ec FCMP D17, #0 |
(355) 0x41e4f0 B.LE 41e440 |
(355) 0x41e4f4 LDR D16, [X26, X12,LSL #3] |
(355) 0x41e4f8 LDR D20, [X26, X13,SXTW #3] |
(355) 0x41e4fc FABS D7, D7 |
(355) 0x41e500 FABS D17, D6 |
(355) 0x41e504 FSUB D18, D0, S4 |
(355) 0x41e508 FADD D19, D4, D1 |
(355) 0x41e50c FCMP D6, #0 |
(355) 0x41e510 FMUL D18, D18, D17 |
(355) 0x41e514 FMUL D19, D19, D7 |
(355) 0x41e518 FDIV D18, D18, D16 |
(355) 0x41e51c FDIV D19, D19, D20 |
(355) 0x41e520 FADD D18, D18, D19 |
(355) 0x41e524 FMUL D16, D16, D18 |
(355) 0x41e528 FDIV D16, D16, D2 |
(355) 0x41e52c FMINNM D7, D16, D7 |
(355) 0x41e530 FMINNM D7, D7, D17 |
(355) 0x41e534 FNEG D16, D7 |
(355) 0x41e538 FCSEL D16, D7, D16, #8 |
(355) 0x41e53c B 41e440 |
0x42bbb8 HINT #0 |
0x42bbbc HINT #0 |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○100.00 | __kmp_invoke_microtask | libomp.so |
Path / |
Source file and lines | advec_mom.cpp:180-211 |
Module | exec |
nb instructions | 61 |
loop length | 244 |
nb stack references | 0 |
front end | 7.25 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.50 | 1.50 | 5.75 | 5.75 | 5.75 | 5.75 | 1.00 | 1.00 | 0.00 | 0.00 | 11.17 | 10.83 | 11.00 | 6.50 | 6.50 |
cycles | 1.50 | 1.50 | 5.75 | 5.75 | 5.75 | 5.75 | 1.00 | 1.00 | 0.00 | 0.00 | 11.17 | 10.83 | 11.00 | 6.50 | 6.50 |
Cycles executing div or sqrt instructions | NA |
Front-end | 7.25 |
Overall L1 | 11.17 |
all | 11% |
load | NA (no load vectorizable/vectorized instructions) |
store | 50% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SUB SP, SP, #192 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR D10, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP D9, D8, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP X29, X30, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X28, X27, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X26, X25, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X24, X23, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X22, X21, [SP, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X20, X19, [SP, #176] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #96 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W8, [X3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR W20, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR W9, [X4] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD W8, W8, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W10, [X5] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD W21, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD W9, W10, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUBS W8, W8, W20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CCMP W9, W21, #4, #12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
B.LE 41e258 <.omp_outlined..20+0xf8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDP X11, X10, [X29, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDR X12, [X29, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X14, [X6] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUB W24, W9, W21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVN X9, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X3, SP, #44 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X4, X29, #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X5, X29, #40 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X13, [X7] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR W1, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X23, [X6, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADRP X0, <4631dc> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #224 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X6, SP, #48 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X25, [X7, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STUR XZR, [X29, #488] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
UMADDL X19, W24, W8, X9 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X8, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X27, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X28, [X11, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X11, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X26, [X12, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X22, [X10, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STP X13, X14, [SP, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STUR X19, [X29, #472] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X8, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP W1, WZR, [SP, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X11, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
BL 402ee0 <@plt_start@+0x190> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDUR X8, [X29, #472] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDUR X13, [X29, #488] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X8, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CSEL X8, X8, X19, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X13, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LE 41e280 <.omp_outlined..20+0x120> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 |
Source file and lines | advec_mom.cpp:180-211 |
Module | exec |
nb instructions | 61 |
loop length | 244 |
nb stack references | 0 |
front end | 7.25 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.50 | 1.50 | 5.75 | 5.75 | 5.75 | 5.75 | 1.00 | 1.00 | 0.00 | 0.00 | 11.17 | 10.83 | 11.00 | 6.50 | 6.50 |
cycles | 1.50 | 1.50 | 5.75 | 5.75 | 5.75 | 5.75 | 1.00 | 1.00 | 0.00 | 0.00 | 11.17 | 10.83 | 11.00 | 6.50 | 6.50 |
Cycles executing div or sqrt instructions | NA |
Front-end | 7.25 |
Overall L1 | 11.17 |
all | 11% |
load | NA (no load vectorizable/vectorized instructions) |
store | 50% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SUB SP, SP, #192 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR D10, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP D9, D8, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP X29, X30, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X28, X27, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X26, X25, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X24, X23, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X22, X21, [SP, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X20, X19, [SP, #176] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #96 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W8, [X3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR W20, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR W9, [X4] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD W8, W8, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W10, [X5] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD W21, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD W9, W10, #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUBS W8, W8, W20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CCMP W9, W21, #4, #12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
B.LE 41e258 <.omp_outlined..20+0xf8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDP X11, X10, [X29, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDR X12, [X29, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X14, [X6] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUB W24, W9, W21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVN X9, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X3, SP, #44 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X4, X29, #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X5, X29, #40 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X13, [X7] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR W1, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X23, [X6, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADRP X0, <4631dc> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #224 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X6, SP, #48 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X25, [X7, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STUR XZR, [X29, #488] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
UMADDL X19, W24, W8, X9 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X8, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X27, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X28, [X11, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X11, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X26, [X12, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X22, [X10, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STP X13, X14, [SP, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STUR X19, [X29, #472] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X8, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP W1, WZR, [SP, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X11, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
BL 402ee0 <@plt_start@+0x190> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDUR X8, [X29, #472] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDUR X13, [X29, #488] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X8, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CSEL X8, X8, X19, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X13, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LE 41e280 <.omp_outlined..20+0x120> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼.omp_outlined..20– | 3.99 | 5.33 |
▼Loop 354 - context.h:69-69 - exec– | 0 | 0 |
▼Loop 355 - advec_mom.cpp:180-211 - exec– | 0 | 0 |
▼Loop 357 - advec_mom.cpp:180-211 - exec– | 0 | 0 |
○Loop 356 - advec_mom.cpp:181-211 - exec | 3.99 | 5.31 |