Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:54-58 [...] | Coverage: 1.01% |
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Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ... | Module: exec | Source: advec_cell.cpp:54-58 [...] | Coverage: 1.01% |
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/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 54 - 58 |
-------------------------------------------------------------------------------- |
54: #pragma omp parallel for simd collapse(2) |
55: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
56: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
57: pre_vol(i, j) = volume(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j); |
58: post_vol(i, j) = volume(i, j); |
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
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69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x41f28c STP X29, X30, [SP, #944]! |
0x41f290 ADD X29, SP, #0 |
0x41f294 STP X19, X20, [SP, #16] |
0x41f298 STP X25, X26, [SP, #64] |
0x41f29c LDP W25, W19, [X0, #40] |
0x41f2a0 STP X23, X24, [SP, #48] |
0x41f2a4 ORR X23, XZR, X0 |
0x41f2a8 LDR W20, [X0, #32] |
0x41f2ac SUB W25, W25, #1 |
0x41f2b0 ADD W19, W19, #4 |
0x41f2b4 LDR W0, [X0, #36] |
0x41f2b8 CMP W25, W19 |
0x41f2bc B.GE 41f424 |
0x41f2c0 SUB W20, W20, #1 |
0x41f2c4 STP X21, X22, [SP, #32] |
0x41f2c8 ADD W22, W0, #4 |
0x41f2cc SUB W26, W19, W25 |
0x41f2d0 CMP W20, W22 |
0x41f2d4 B.GE 41f420 |
0x41f2d8 SUB W21, W22, W20 |
0x41f2dc BL 403530 |
0x41f2e0 MADD W26, W26, W21, WZR |
0x41f2e4 ORR W24, WZR, W0 |
0x41f2e8 BL 4033c0 |
0x41f2ec ORR W2, WZR, W0 |
0x41f2f0 UDIV W1, W26, W24 |
0x41f2f4 MSUB W3, W1, W24, W26 |
0x41f2f8 CMP W0, W3 |
0x41f2fc B.CC 41f438 |
(181) 0x41f300 MADD W24, W1, W2, W3 |
(181) 0x41f304 ADD W14, W1, W24 |
(181) 0x41f308 CMP W24, W14 |
(181) 0x41f30c B.CS 41f420 |
(181) 0x41f310 UDIV W4, W24, W21 |
(181) 0x41f314 MOVZ W15, #0 |
(181) 0x41f318 CNTD X8, ALL |
(181) 0x41f31c LDP X13, X12, [X23] |
(181) 0x41f320 LDP X11, X10, [X23, #16] |
(181) 0x41f324 MSUB W16, W4, W21, W24 |
(181) 0x41f328 ADD W5, W4, W25 |
(181) 0x41f32c SBFM X7, X5, #0, #31 |
(181) 0x41f330 ADD W2, W16, W20 |
(181) 0x41f334 SUB W9, W22, W2 |
(181) 0x41f338 CMP W1, W9 |
(181) 0x41f33c CSEL X30, X1, X9, #9 |
(181) 0x41f340 ADD W9, W24, W30 |
(181) 0x41f344 CMP W24, W9 |
(181) 0x41f348 B.CS 41f408 |
(183) 0x41f34c LDR X17, [X10] |
(183) 0x41f350 SBFM X23, X2, #0, #31 |
(183) 0x41f354 MOVZ X0, #0 |
(183) 0x41f358 ADD X6, X23, #1 |
(183) 0x41f35c WHILELO P0.D, XZR, X30 |
(183) 0x41f360 LDR X22, [X11] |
(183) 0x41f364 LDR X2, [X12] |
(183) 0x41f368 MADD X25, X7, X17, X23 |
(183) 0x41f36c LDR X18, [X11, #16] |
(183) 0x41f370 MADD X26, X7, X22, X23 |
(183) 0x41f374 LDR X17, [X13] |
(183) 0x41f378 MADD X3, X7, X2, XZR |
(183) 0x41f37c LDR X1, [X12, #16] |
(183) 0x41f380 ADD X24, X18, X26,LSL #3 |
(183) 0x41f384 LDR X22, [X13, #16] |
(183) 0x41f388 ADD X16, X3, X23 |
(183) 0x41f38c ADD X4, X6, X3 |
(183) 0x41f390 MADD X23, X7, X17, X23 |
(183) 0x41f394 LDR X26, [X10, #16] |
(183) 0x41f398 ADD X6, X1, X4,LSL #3 |
(183) 0x41f39c ADD X5, X1, X16,LSL #3 |
(183) 0x41f3a0 ADD X18, X22, X23,LSL #3 |
(183) 0x41f3a4 ADD X25, X26, X25,LSL #3 |
(182) 0x41f3a8 LD1D {Z2.D}, P0/Z, [X18, X0,LSL #3] |
(182) 0x41f3ac LD1D {Z0.D}, P0/Z, [X6, X0,LSL #3] |
(182) 0x41f3b0 LD1D {Z1.D}, P0/Z, [X5, X0,LSL #3] |
(182) 0x41f3b4 FADD Z3.D, Z0.D, Z2.D |
(182) 0x41f3b8 FSUB Z4.D, Z3.D, Z1.D |
(182) 0x41f3bc ST1D {Z4.D}, P0, [X24, X0,LSL #3] |
(182) 0x41f3c0 LD1D {Z5.D}, P0/Z, [X18, X0,LSL #3] |
(182) 0x41f3c4 ST1D {Z5.D}, P0, [X25, X0,LSL #3] |
(182) 0x41f3c8 ADD X0, X0, X8 |
(182) 0x41f3cc WHILELO P0.D, X0, X30 |
(182) 0x41f3d0 B.NE 41f3a8 |
(183) 0x41f3d4 ADD X7, X7, #1 |
(183) 0x41f3d8 ADD W30, W15, W7 |
(183) 0x41f3dc CMP W19, W30 |
(183) 0x41f3e0 B.LE 41f420 |
(183) 0x41f3e4 SUB W1, W14, W9 |
(183) 0x41f3e8 ORR W24, WZR, W9 |
(183) 0x41f3ec ORR W9, WZR, W21 |
(183) 0x41f3f0 ORR W2, WZR, W20 |
(183) 0x41f3f4 CMP W1, W9 |
(183) 0x41f3f8 CSEL X30, X1, X9, #9 |
(183) 0x41f3fc ADD W9, W24, W30 |
(183) 0x41f400 CMP W24, W9 |
(183) 0x41f404 B.CC 41f34c |
(184) 0x41f408 ADD X7, X7, #1 |
(184) 0x41f40c ORR W9, WZR, W24 |
(184) 0x41f410 ADD W30, W15, W7 |
(184) 0x41f414 CMP W19, W30 |
(184) 0x41f418 B.GT 41f3e4 |
(181) 0x41f41c HINT #0 |
(181) 0x41f420 LDP X21, X22, [SP, #32] |
(181) 0x41f424 LDP X19, X20, [SP, #16] |
(181) 0x41f428 LDP X23, X24, [SP, #48] |
(181) 0x41f42c LDP X25, X26, [SP, #64] |
(181) 0x41f430 LDP X29, X30, [SP], #80 |
(181) 0x41f434 RET |
(181) 0x41f438 ADD W1, W1, #1 |
(181) 0x41f43c MOVZ W3, #0 |
(181) 0x41f440 B 41f300 |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►98.44+ | __kmp_GOMP_microtask_wrapper(i[...] | libomp.so | |
○ | __kmp_invoke_microtask | libomp.so | |
►1.56+ | GOMP_parallel | libomp.so | |
○ | advec_cell_kernel(int, int, in[...] | advec_cell.cpp:54 | exec |
○ | advec_cell_driver(global_varia[...] | advec_cell.cpp:232 | exec |
○ | advection(global_variables&) | advection.cpp:81 | exec |
○ | hydro(global_variables&, paral[...] | basic_string.h:906 | exec |
○ | main | iostream:74 | exec |
○ | __libc_start_main | libc-2.31.so | |
○ | _start | iostream:74 | exec |
Path / |
Source file and lines | advec_cell.cpp:54-58 |
Module | exec |
nb instructions | 29 |
loop length | 116 |
nb stack references | 0 |
front end | 3.63 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 2.50 | 4.75 | 4.75 | 4.75 | 4.75 | 0.00 | 0.00 | 0.00 | 0.00 | 2.83 | 2.50 | 2.67 | 2.50 | 2.50 |
cycles | 2.50 | 2.50 | 4.75 | 4.75 | 4.75 | 4.75 | 0.00 | 0.00 | 0.00 | 0.00 | 2.83 | 2.50 | 2.67 | 2.50 | 2.50 |
Cycles executing div or sqrt instructions | 1.00-0.50 |
Front-end | 3.63 |
Overall L1 | 4.75 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STP X29, X30, [SP, #944]! | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X19, X20, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X25, X26, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDP W25, W19, [X0, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STP X23, X24, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ORR X23, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W20, [X0, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUB W25, W25, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD W19, W19, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W0, [X0, #36] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP W25, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 41f424 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x198> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB W20, W20, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X21, X22, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD W22, W0, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB W26, W19, W25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP W20, W22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 41f420 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x194> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB W21, W22, W20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 403530 <@plt_start@+0x4b0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MADD W26, W26, W21, WZR | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ORR W24, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 4033c0 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR W2, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
UDIV W1, W26, W24 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5-12 | 1-0.50 |
MSUB W3, W1, W24, W26 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
CMP W0, W3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.CC 41f438 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x1ac> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Source file and lines | advec_cell.cpp:54-58 |
Module | exec |
nb instructions | 29 |
loop length | 116 |
nb stack references | 0 |
front end | 3.63 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 2.50 | 4.75 | 4.75 | 4.75 | 4.75 | 0.00 | 0.00 | 0.00 | 0.00 | 2.83 | 2.50 | 2.67 | 2.50 | 2.50 |
cycles | 2.50 | 2.50 | 4.75 | 4.75 | 4.75 | 4.75 | 0.00 | 0.00 | 0.00 | 0.00 | 2.83 | 2.50 | 2.67 | 2.50 | 2.50 |
Cycles executing div or sqrt instructions | 1.00-0.50 |
Front-end | 3.63 |
Overall L1 | 4.75 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STP X29, X30, [SP, #944]! | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X19, X20, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X25, X26, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDP W25, W19, [X0, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STP X23, X24, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ORR X23, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W20, [X0, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUB W25, W25, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD W19, W19, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W0, [X0, #36] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP W25, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 41f424 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x198> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB W20, W20, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X21, X22, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD W22, W0, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB W26, W19, W25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP W20, W22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 41f420 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x194> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB W21, W22, W20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 403530 <@plt_start@+0x4b0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MADD W26, W26, W21, WZR | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ORR W24, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 4033c0 <@plt_start@+0x340> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR W2, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
UDIV W1, W26, W24 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5-12 | 1-0.50 |
MSUB W3, W1, W24, W26 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
CMP W0, W3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.CC 41f438 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x1ac> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D | 1.01 | 1.34 |
▼Loop 181 - advec_cell.cpp:54-58 - exec– | 0 | 0 |
○Loop 184 - advec_cell.cpp:56-58 - exec | 0 | 0 |
▼Loop 183 - advec_cell.cpp:56-58 - exec– | 0 | 0.01 |
○Loop 182 - advec_cell.cpp:57-58 - exec | 1 | 1.33 |