Function: .omp_outlined..12 | Module: exec | Source: advec_cell.cpp:157-202 [...] | Coverage: 3.75% |
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Function: .omp_outlined..12 | Module: exec | Source: advec_cell.cpp:157-202 [...] | Coverage: 3.75% |
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/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 157 - 202 |
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157: #pragma omp parallel for simd collapse(2) |
158: for (int j = (y_min + 1); j < (y_max + 2 + 2); j++) { |
159: for (int i = (x_min + 1); i < (x_max + 2); i++) |
160: ({ |
161: int upwind, donor, downwind, dif; |
162: double sigmat, sigma3, sigma4, sigmav, sigmam, diffuw, diffdw, limiter, wind; |
163: if (vol_flux_y(i, j) > 0.0) { |
164: upwind = j - 2; |
165: donor = j - 1; |
166: downwind = j; |
167: dif = donor; |
168: } else { |
169: upwind = std::min(j + 1, y_max + 2); |
170: donor = j; |
171: downwind = j - 1; |
172: dif = upwind; |
173: } |
174: sigmat = std::fabs(vol_flux_y(i, j)) / pre_vol(i, donor); |
175: sigma3 = (1.0 + sigmat) * (vertexdy[j] / vertexdy[dif]); |
176: sigma4 = 2.0 - sigmat; |
177: sigmav = sigmat; |
178: diffuw = density1(i, donor) - density1(i, upwind); |
179: diffdw = density1(i, downwind) - density1(i, donor); |
180: wind = 1.0; |
181: if (diffdw <= 0.0) wind = -1.0; |
182: if (diffuw * diffdw > 0.0) { |
183: limiter = (1.0 - sigmav) * wind * |
184: std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)), |
185: one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw))); |
186: } else { |
187: limiter = 0.0; |
188: } |
189: mass_flux_y(i, j) = vol_flux_y(i, j) * (density1(i, donor) + limiter); |
190: sigmam = std::fabs(mass_flux_y(i, j)) / (density1(i, donor) * pre_vol(i, donor)); |
191: diffuw = energy1(i, donor) - energy1(i, upwind); |
192: diffdw = energy1(i, downwind) - energy1(i, donor); |
193: wind = 1.0; |
194: if (diffdw <= 0.0) wind = -1.0; |
195: if (diffuw * diffdw > 0.0) { |
196: limiter = (1.0 - sigmam) * wind * |
197: std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)), |
198: one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw))); |
199: } else { |
200: limiter = 0.0; |
201: } |
202: ener_flux(i, j) = mass_flux_y(i, j) * (energy1(i, donor) + limiter); |
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69 |
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69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
0x41b850 SUB SP, SP, #288 |
0x41b854 STP D15, D14, [SP, #128] |
0x41b858 STP D13, D12, [SP, #144] |
0x41b85c STP D11, D10, [SP, #160] |
0x41b860 STP D9, D8, [SP, #176] |
0x41b864 STP X29, X30, [SP, #192] |
0x41b868 STP X28, X27, [SP, #208] |
0x41b86c STP X26, X25, [SP, #224] |
0x41b870 STP X24, X23, [SP, #240] |
0x41b874 STP X22, X21, [SP, #256] |
0x41b878 STP X20, X19, [SP, #272] |
0x41b87c ADD X29, SP, #192 |
0x41b880 LDR W11, [X2] |
0x41b884 LDR W13, [X3] |
0x41b888 ADD W12, W11, #1 |
0x41b88c ADD W8, W13, #4 |
0x41b890 SUBS W8, W8, W12 |
0x41b894 B.LE 41b974 |
0x41b898 LDR W9, [X4] |
0x41b89c LDR W10, [X5] |
0x41b8a0 ADD W15, W9, #1 |
0x41b8a4 ADD W9, W10, #2 |
0x41b8a8 CMP W9, W15 |
0x41b8ac B.LE 41b974 |
0x41b8b0 STP X12, X11, [SP, #72] |
0x41b8b4 LDP X11, X10, [X29, #128] |
0x41b8b8 STR W13, [SP, #20] |
0x41b8bc LDR X12, [X29, #120] |
0x41b8c0 ADD X3, SP, #92 |
0x41b8c4 SUB X4, X29, #80 |
0x41b8c8 SUB X5, X29, #88 |
0x41b8cc LDP X14, X13, [X29, #96] |
0x41b8d0 LDR X17, [X6] |
0x41b8d4 MOVZ W2, #34 |
0x41b8d8 LDR X16, [X7] |
0x41b8dc LDR W1, [X0] |
0x41b8e0 ADRP X0, |
0x41b8e4 ADD X0, X0, #3408 |
0x41b8e8 LDR X24, [X6, #16] |
0x41b8ec ADD X6, SP, #96 |
0x41b8f0 LDR X26, [X7, #16] |
0x41b8f4 MOVZ W7, #1 |
0x41b8f8 STR X15, [SP, #64] |
0x41b8fc LDR X23, [X11] |
0x41b900 LDR X21, [X11, #16] |
0x41b904 SUB W11, W9, W15 |
0x41b908 MOVN X9, #0 |
0x41b90c LDR X28, [X13] |
0x41b910 LDR X19, [X13, #16] |
0x41b914 UMADDL X20, W11, W8, X9 |
0x41b918 LDR X13, [X12] |
0x41b91c LDR X9, [X10] |
0x41b920 LDR X27, [X14, #8] |
0x41b924 LDR X25, [X12, #16] |
0x41b928 LDR X22, [X10, #16] |
0x41b92c MOVZ W8, #1 |
0x41b930 STP X16, X17, [SP, #48] |
0x41b934 STP W1, WZR, [SP, #88] |
0x41b938 STR X8, [SP, #96] |
0x41b93c STR X8, [SP] |
0x41b940 STP X11, X13, [SP, #32] |
0x41b944 STP X20, XZR, [X29, #936] |
0x41b948 STR X9, [SP, #24] |
0x41b94c BL 4033a0 |
0x41b950 LDP X8, X14, [X29, #936] |
0x41b954 CMP X8, X20 |
0x41b958 CSEL X9, X8, X20, #11 |
0x41b95c CMP X14, X9 |
0x41b960 B.LE 41b9a4 |
(308) 0x41b964 LDR W1, [SP, #88] |
(308) 0x41b968 ADRP X0, |
(308) 0x41b96c ADD X0, X0, #3432 |
(308) 0x41b970 BL 403260 |
(308) 0x41b974 LDP D9, D8, [SP, #176] |
(308) 0x41b978 LDP D11, D10, [SP, #160] |
(308) 0x41b97c LDP D13, D12, [SP, #144] |
(308) 0x41b980 LDP D15, D14, [SP, #128] |
(308) 0x41b984 LDP X20, X19, [SP, #272] |
(308) 0x41b988 LDP X22, X21, [SP, #256] |
(308) 0x41b98c LDP X24, X23, [SP, #240] |
(308) 0x41b990 LDP X26, X25, [SP, #224] |
(308) 0x41b994 LDP X28, X27, [SP, #208] |
(308) 0x41b998 LDP X29, X30, [SP, #192] |
(308) 0x41b99c ADD SP, SP, #288 |
(308) 0x41b9a0 RET |
(308) 0x41b9a4 LDR W8, [SP, #20] |
(308) 0x41b9a8 ADD X9, X9, #1 |
(308) 0x41b9ac CNTD X11, ALL |
(308) 0x41b9b0 ORR X10, XZR, X14 |
(308) 0x41b9b4 ADD W8, W8, #2 |
(308) 0x41b9b8 SUB X12, X9, X14 |
(308) 0x41b9bc CMP X12, X11 |
(308) 0x41b9c0 B.CC 41bc0c |
(308) 0x41b9c4 UDIV X10, X12, X11 |
(308) 0x41b9c8 PTRUE P0.D, ALL |
(308) 0x41b9cc MADD X13, X10, X11, XZR |
(308) 0x41b9d0 INDEX Z0.D, X14, #1 |
(308) 0x41b9d4 ADD X10, X14, X13 |
(308) 0x41b9d8 LDR X14, [SP, #32] |
(308) 0x41b9dc DUP Z22.D, X8 |
(308) 0x41b9e0 SUB X12, X12, X13 |
(308) 0x41b9e4 SXTW Z22.D, P0/M, Z22.D |
(308) 0x41b9e8 DUP Z1.D, X11 |
(308) 0x41b9ec DUP Z16.D, X28 |
(308) 0x41b9f0 DUP Z18.D, X23 |
(308) 0x41b9f4 DUP Z2.D, X14 |
(308) 0x41b9f8 LDP X14, X15, [SP, #72] |
(308) 0x41b9fc DUP Z3.D, X14 |
(308) 0x41ba00 LDR X14, [SP, #64] |
(308) 0x41ba04 DUP Z6.D, X15 |
(308) 0x41ba08 DUP Z4.D, X14 |
(308) 0x41ba0c LDR X14, [SP, #56] |
(308) 0x41ba10 DUP Z5.D, X14 |
(308) 0x41ba14 LDR X14, [SP, #48] |
(308) 0x41ba18 DUP Z7.D, X14 |
(308) 0x41ba1c LDR X14, [SP, #40] |
(308) 0x41ba20 DUP Z17.D, X14 |
(308) 0x41ba24 LDR X14, [SP, #24] |
(308) 0x41ba28 DUP Z19.D, X14 |
(308) 0x41ba2c ADD W14, W15, #2 |
(308) 0x41ba30 DUP Z20.D, X14 |
(308) 0x41ba34 SUB W14, W15, #1 |
(308) 0x41ba38 DUP Z21.D, X14 |
(308) 0x41ba3c ORR X14, XZR, #3840 |
(308) 0x41ba40 MOVK X14, #16325 |
(308) 0x41ba44 DUP Z25.D, X14 |
(307) 0x41ba48 MOVPRFX Z28, Z0 |
(307) 0x41ba4c SDIV Z28.D, P0/M, Z28.D, Z2.D |
(307) 0x41ba50 MOVPRFX Z26, Z0 |
(307) 0x41ba54 MLS Z26.D, P0/M, Z28.D, Z2.D |
(307) 0x41ba58 ADD Z26.D, Z4.D, Z26.D |
(307) 0x41ba5c ADD Z29.D, Z3.D, Z28.D |
(307) 0x41ba60 MOVPRFX Z27, Z29 |
(307) 0x41ba64 SXTW Z27.D, P0/M, Z29.D |
(307) 0x41ba68 SUBS X13, X13, X11 |
(307) 0x41ba6c ADD Z31.D, Z20.D, Z28.D |
(307) 0x41ba70 ADD Z8.D, Z6.D, Z28.D |
(307) 0x41ba74 ADD Z28.D, Z21.D, Z28.D |
(307) 0x41ba78 FDUP Z23.D, #0 |
(307) 0x41ba7c ADD Z0.D, Z0.D, Z1.D |
(307) 0x41ba80 SXTW Z26.D, P0/M, Z26.D |
(307) 0x41ba84 MOVPRFX Z30, Z26 |
(307) 0x41ba88 MLA Z30.D, P0/M, Z5.D, Z27.D |
(307) 0x41ba8c LD1D {Z30.D}, P0/Z, [X24, Z30.D,LSL #3] |
(307) 0x41ba90 MOVPRFX Z11, Z30 |
(307) 0x41ba94 FABS Z11.D, P0/M, Z30.D |
(307) 0x41ba98 SXTW Z31.D, P0/M, Z31.D |
(307) 0x41ba9c SXTW Z8.D, P0/M, Z8.D |
(307) 0x41baa0 SXTW Z28.D, P0/M, Z28.D |
(307) 0x41baa4 SMIN Z31.D, P0/M, Z31.D, Z22.D |
(307) 0x41baa8 FCMGT P1.D, P0/Z, Z30.D, #0 |
(307) 0x41baac SEL Z28.D, P1, Z28.D, Z31.D |
(307) 0x41bab0 SEL Z31.D, P1, Z8.D, Z31.D |
(307) 0x41bab4 SEL Z9.D, P1, Z27.D, Z8.D |
(307) 0x41bab8 SEL Z8.D, P1, Z8.D, Z27.D |
(307) 0x41babc MOVPRFX Z10, Z26 |
(307) 0x41bac0 MLA Z10.D, P0/M, Z8.D, Z7.D |
(307) 0x41bac4 LD1D {Z12.D}, P0/Z, [X26, Z10.D,LSL #3] |
(307) 0x41bac8 LD1D {Z29.D}, P0/Z, [X27, Z29.D,SXTW #3] |
(307) 0x41bacc MOVPRFX Z13, Z26 |
(307) 0x41bad0 MLA Z13.D, P0/M, Z16.D, Z28.D |
(307) 0x41bad4 LD1D {Z31.D}, P0/Z, [X27, Z31.D,LSL #3] |
(307) 0x41bad8 FDIV Z11.D, P0/M, Z11.D, Z12.D |
(307) 0x41badc MAD Z28.D, P0/M, Z18.D, Z26.D |
(307) 0x41bae0 FMAD Z29.D, P0/M, Z11.D, Z29.D |
(307) 0x41bae4 FSUB Z14.D, Z23.D, Z11.D |
(307) 0x41bae8 MOVPRFX Z23, Z26 |
(307) 0x41baec MLA Z23.D, P0/M, Z9.D, Z16.D |
(307) 0x41baf0 FDIV Z29.D, P0/M, Z29.D, Z31.D |
(307) 0x41baf4 MOVPRFX Z31, Z26 |
(307) 0x41baf8 MLA Z31.D, P0/M, Z8.D, Z16.D |
(307) 0x41bafc LD1D {Z12.D}, P0/Z, [X19, Z31.D,LSL #3] |
(307) 0x41bb00 LD1D {Z13.D}, P0/Z, [X19, Z13.D,LSL #3] |
(307) 0x41bb04 LD1D {Z23.D}, P0/Z, [X19, Z23.D,LSL #3] |
(307) 0x41bb08 FSUB Z24.D, Z23.D, Z12.D |
(307) 0x41bb0c FSUB Z15.D, Z12.D, Z13.D |
(307) 0x41bb10 FABD Z23.D, P0/M, Z23.D, Z12.D |
(307) 0x41bb14 FCMGT P1.D, P0/Z, Z24.D, #0 |
(307) 0x41bb18 FMUL Z15.D, Z24.D, Z15.D |
(307) 0x41bb1c MOVPRFX Z24, Z11 |
(307) 0x41bb20 FSUBR Z24.D, P0/M, Z24.D, #1 |
(307) 0x41bb24 MOVPRFX Z11, Z24 |
(307) 0x41bb28 FNEG Z11.D, P0/M, Z24.D |
(307) 0x41bb2c SEL Z24.D, P1, Z24.D, Z11.D |
(307) 0x41bb30 MOVPRFX Z11, Z12 |
(307) 0x41bb34 FABD Z11.D, P0/M, Z11.D, Z13.D |
(307) 0x41bb38 MOVPRFX Z13, Z11 |
(307) 0x41bb3c FMINNM Z13.D, P0/M, Z13.D, Z23.D |
(307) 0x41bb40 FCMGT P2.D, P0/Z, Z15.D, #0 |
(307) 0x41bb44 FMUL Z11.D, Z11.D, Z29.D |
(307) 0x41bb48 FMAD Z23.D, P0/M, Z14.D, Z11.D |
(307) 0x41bb4c FMUL Z23.D, Z23.D, Z25.D |
(307) 0x41bb50 FMINNM Z23.D, P0/M, Z23.D, Z13.D |
(307) 0x41bb54 FMUL Z23.D, Z23.D, Z24.D |
(307) 0x41bb58 DUP Z24.D, #0 |
(307) 0x41bb5c SEL Z23.D, P2, Z23.D, Z24.D |
(307) 0x41bb60 MOVPRFX Z24, Z26 |
(307) 0x41bb64 MLA Z24.D, P0/M, Z17.D, Z27.D |
(307) 0x41bb68 FADD Z23.D, Z23.D, Z12.D |
(307) 0x41bb6c FMUL Z23.D, Z23.D, Z30.D |
(307) 0x41bb70 ST1D {Z23.D}, P0, [X25, Z24.D,LSL #3] |
(307) 0x41bb74 MOVPRFX Z24, Z26 |
(307) 0x41bb78 MLA Z24.D, P0/M, Z8.D, Z18.D |
(307) 0x41bb7c MOVPRFX Z8, Z26 |
(307) 0x41bb80 MLA Z8.D, P0/M, Z9.D, Z18.D |
(307) 0x41bb84 LD1D {Z24.D}, P0/Z, [X21, Z24.D,LSL #3] |
(307) 0x41bb88 LD1D {Z28.D}, P0/Z, [X21, Z28.D,LSL #3] |
(307) 0x41bb8c LD1D {Z8.D}, P0/Z, [X21, Z8.D,LSL #3] |
(307) 0x41bb90 LD1D {Z31.D}, P0/Z, [X19, Z31.D,LSL #3] |
(307) 0x41bb94 LD1D {Z9.D}, P0/Z, [X26, Z10.D,LSL #3] |
(307) 0x41bb98 FMUL Z31.D, Z9.D, Z31.D |
(307) 0x41bb9c MOVPRFX Z9, Z23 |
(307) 0x41bba0 FABS Z9.D, P0/M, Z23.D |
(307) 0x41bba4 FSUB Z30.D, Z24.D, Z28.D |
(307) 0x41bba8 FABD Z28.D, P0/M, Z28.D, Z24.D |
(307) 0x41bbac FMUL Z29.D, Z28.D, Z29.D |
(307) 0x41bbb0 FDIVR Z31.D, P0/M, Z31.D, Z9.D |
(307) 0x41bbb4 FSUB Z9.D, Z8.D, Z24.D |
(307) 0x41bbb8 FABD Z8.D, P0/M, Z8.D, Z24.D |
(307) 0x41bbbc FMLA Z29.D, P0/M, Z8.D, Z14.D |
(307) 0x41bbc0 FCMGT P1.D, P0/Z, Z9.D, #0 |
(307) 0x41bbc4 FMINNM Z28.D, P0/M, Z28.D, Z8.D |
(307) 0x41bbc8 FMUL Z30.D, Z9.D, Z30.D |
(307) 0x41bbcc FMUL Z29.D, Z29.D, Z25.D |
(307) 0x41bbd0 FMINNM Z28.D, P0/M, Z28.D, Z29.D |
(307) 0x41bbd4 FSUBR Z31.D, P0/M, Z31.D, #1 |
(307) 0x41bbd8 MOVPRFX Z9, Z31 |
(307) 0x41bbdc FNEG Z9.D, P0/M, Z31.D |
(307) 0x41bbe0 SEL Z31.D, P1, Z31.D, Z9.D |
(307) 0x41bbe4 FCMLE P1.D, P0/Z, Z30.D, #0 |
(307) 0x41bbe8 FMUL Z28.D, Z31.D, Z28.D |
(307) 0x41bbec CPY Z28.D, P1/M, #0 |
(307) 0x41bbf0 FADD Z24.D, Z28.D, Z24.D |
(307) 0x41bbf4 FMUL Z23.D, Z24.D, Z23.D |
(307) 0x41bbf8 MOVPRFX Z24, Z26 |
(307) 0x41bbfc MLA Z24.D, P0/M, Z19.D, Z27.D |
(307) 0x41bc00 ST1D {Z23.D}, P0, [X22, Z24.D,LSL #3] |
(307) 0x41bc04 B.NE 41ba48 |
(308) 0x41bc08 CBZ X12, 41b964 |
(306) 0x41bc0c LDP X20, X7, [SP, #32] |
(306) 0x41bc10 LDP X3, X2, [SP, #72] |
(306) 0x41bc14 LDP X5, X4, [SP, #56] |
(306) 0x41bc18 FMOV D0, #2.0000000 |
(306) 0x41bc1c FMOV D1, #1.0000000 |
(306) 0x41bc20 ORR X12, XZR, #3840 |
(306) 0x41bc24 MOVK X12, #16325 |
(306) 0x41bc28 LDR X6, [SP, #48] |
(306) 0x41bc2c LDR X30, [SP, #24] |
(306) 0x41bc30 SUB W11, WZR, W20 |
(306) 0x41bc34 B 41bc5c |
0x41bc38 HINT #0 |
0x41bc3c HINT #0 |
(306) 0x41bc40 FADD D3, D5, D6 |
(306) 0x41bc44 MADD X13, X30, X14, X13 |
(306) 0x41bc48 ADD X10, X10, #1 |
(306) 0x41bc4c CMP X9, X10 |
(306) 0x41bc50 FMUL D2, D3, D2 |
(306) 0x41bc54 STR D2, [X22, X13,LSL #3] |
(306) 0x41bc58 B.EQ 41b964 |
(306) 0x41bc5c SDIV X15, X10, X20 |
(306) 0x41bc60 ADD W13, W4, W10 |
(306) 0x41bc64 ADD W14, W3, W15 |
(306) 0x41bc68 MADD W13, W11, W15, W13 |
(306) 0x41bc6c SBFM X13, X13, #0, #31 |
(306) 0x41bc70 SBFM X14, X14, #0, #31 |
(306) 0x41bc74 MADD X16, X5, X14, X13 |
(306) 0x41bc78 LDR D2, [X24, X16,LSL #3] |
(306) 0x41bc7c FCMP D2, #0 |
(306) 0x41bc80 B.LE 41bca0 |
(306) 0x41bc84 ADD W15, W2, W15 |
(306) 0x41bc88 SUB W16, W14, #2 |
(306) 0x41bc8c SBFM X16, X16, #0, #31 |
(306) 0x41bc90 SBFM X18, X15, #0, #31 |
(306) 0x41bc94 ORR X15, XZR, X14 |
(306) 0x41bc98 ORR X0, XZR, X18 |
(306) 0x41bc9c B 41bcc0 |
(306) 0x41bca0 ADD W16, W14, #1 |
(306) 0x41bca4 ADD W15, W2, W15 |
(306) 0x41bca8 ORR X0, XZR, X14 |
(306) 0x41bcac SBFM X15, X15, #0, #31 |
(306) 0x41bcb0 CMP W8, W16 |
(306) 0x41bcb4 CSINC W16, W8, W14, #11 |
(306) 0x41bcb8 SBFM X16, X16, #0, #31 |
(306) 0x41bcbc ORR X18, XZR, X16 |
(306) 0x41bcc0 MADD X17, X0, X6, X13 |
(306) 0x41bcc4 FABS D3, D2 |
(306) 0x41bcc8 MADD X1, X28, X16, X13 |
(306) 0x41bccc LDR D4, [X26, X17,LSL #3] |
(306) 0x41bcd0 LDR D5, [X19, X1,LSL #3] |
(306) 0x41bcd4 MADD X1, X15, X28, X13 |
(306) 0x41bcd8 FDIV D7, D3, D4 |
(306) 0x41bcdc LDR D3, [X27, X14,LSL #3] |
(306) 0x41bce0 LDR D4, [X27, X18,LSL #3] |
(306) 0x41bce4 MADD X18, X0, X28, X13 |
(306) 0x41bce8 LDR D6, [X19, X18,LSL #3] |
(306) 0x41bcec FSUB D16, D6, S5 |
(306) 0x41bcf0 LDR D5, [X19, X1,LSL #3] |
(306) 0x41bcf4 FSUB D17, D5, S6 |
(306) 0x41bcf8 MOVI D5, #0 |
(306) 0x41bcfc FMADD D3, D7, D3, D3 |
(306) 0x41bd00 FMUL D18, D17, D16 |
(306) 0x41bd04 FDIV D3, D3, D4 |
(306) 0x41bd08 FSUB D4, D0, S7 |
(306) 0x41bd0c FCMP D18, #0 |
(306) 0x41bd10 MOVI D18, #0 |
(306) 0x41bd14 B.LE 41bd4c |
(306) 0x41bd18 FSUB D7, D1, S7 |
(306) 0x41bd1c FCMP D17, #0 |
(306) 0x41bd20 FABS D16, D16 |
(306) 0x41bd24 FABS D17, D17 |
(306) 0x41bd28 FNEG D18, D7 |
(306) 0x41bd2c FCSEL D7, D7, D18, #12 |
(306) 0x41bd30 FMINNM D18, D16, D17 |
(306) 0x41bd34 FMUL D16, D16, D3 |
(306) 0x41bd38 FMADD D16, D17, D4, D16 |
(306) 0x41bd3c FMOV D17, X12 |
(306) 0x41bd40 FMUL D16, D16, D17 |
(306) 0x41bd44 FMINNM D16, D18, D16 |
(306) 0x41bd48 FMUL D18, D16, D7 |
(306) 0x41bd4c FADD D6, D18, D6 |
(306) 0x41bd50 MADD X1, X7, X14, X13 |
(306) 0x41bd54 MADD X0, X0, X23, X13 |
(306) 0x41bd58 FMUL D2, D6, D2 |
(306) 0x41bd5c MADD X16, X23, X16, X13 |
(306) 0x41bd60 MADD X15, X15, X23, X13 |
(306) 0x41bd64 STR D2, [X25, X1,LSL #3] |
(306) 0x41bd68 LDR D6, [X21, X0,LSL #3] |
(306) 0x41bd6c LDR D7, [X21, X16,LSL #3] |
(306) 0x41bd70 LDR D16, [X21, X15,LSL #3] |
(306) 0x41bd74 FSUB D7, D6, S7 |
(306) 0x41bd78 FSUB D16, D16, S6 |
(306) 0x41bd7c FMUL D17, D16, D7 |
(306) 0x41bd80 FCMP D17, #0 |
(306) 0x41bd84 B.LE 41bc40 |
(306) 0x41bd88 LDR D17, [X19, X18,LSL #3] |
(306) 0x41bd8c LDR D18, [X26, X17,LSL #3] |
(306) 0x41bd90 FABS D5, D2 |
(306) 0x41bd94 FABS D7, D7 |
(306) 0x41bd98 FCMP D16, #0 |
(306) 0x41bd9c FABS D16, D16 |
(306) 0x41bda0 FMUL D3, D7, D3 |
(306) 0x41bda4 FMADD D3, D16, D4, D3 |
(306) 0x41bda8 FMOV D4, X12 |
(306) 0x41bdac FMUL D17, D18, D17 |
(306) 0x41bdb0 FDIV D5, D5, D17 |
(306) 0x41bdb4 FMUL D3, D3, D4 |
(306) 0x41bdb8 FSUB D5, D1, S5 |
(306) 0x41bdbc FNEG D17, D5 |
(306) 0x41bdc0 FCSEL D5, D5, D17, #12 |
(306) 0x41bdc4 FMINNM D17, D7, D16 |
(306) 0x41bdc8 FMINNM D3, D17, D3 |
(306) 0x41bdcc FMUL D5, D5, D3 |
(306) 0x41bdd0 B 41bc40 |
0x41bdd4 HINT #0 |
0x41bdd8 HINT #0 |
0x41bddc HINT #0 |
0x41d8c4 HINT #0 |
0x41d8c8 HINT #0 |
0x41d8cc HINT #0 |
0x42ab54 HINT #0 |
0x42ab58 HINT #0 |
0x42ab5c HINT #0 |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○100.00 | __kmp_invoke_microtask | libomp.so |
Path / |
Source file and lines | advec_cell.cpp:157-202 |
Module | exec |
nb instructions | 80 |
loop length | 320 |
nb stack references | 0 |
front end | 8.63 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.00 | 2.00 | 6.00 | 6.00 | 6.00 | 6.00 | 2.00 | 2.00 | 0.00 | 0.00 | 14.00 | 14.00 | 14.00 | 8.00 | 8.00 |
cycles | 2.00 | 2.00 | 6.00 | 6.00 | 6.00 | 6.00 | 2.00 | 2.00 | 0.00 | 0.00 | 14.00 | 14.00 | 14.00 | 8.00 | 8.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 8.63 |
Overall L1 | 14.00 |
all | 36% |
load | NA (no load vectorizable/vectorized instructions) |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SUB SP, SP, #288 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP D15, D14, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP D13, D12, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP D11, D10, [SP, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP D9, D8, [SP, #176] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP X29, X30, [SP, #192] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X28, X27, [SP, #208] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X26, X25, [SP, #224] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X24, X23, [SP, #240] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X22, X21, [SP, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X20, X19, [SP, #272] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #192 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W11, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR W13, [X3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD W12, W11, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD W8, W13, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUBS W8, W8, W12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LE 41b974 <.omp_outlined..12+0x124> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR W9, [X4] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR W10, [X5] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD W15, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD W9, W10, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP W9, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LE 41b974 <.omp_outlined..12+0x124> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
STP X12, X11, [SP, #72] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDP X11, X10, [X29, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
STR W13, [SP, #20] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X12, [X29, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X3, SP, #92 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X4, X29, #80 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X5, X29, #88 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDP X14, X13, [X29, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDR X17, [X6] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X16, [X7] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR W1, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADRP X0, <45e8e0> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #3408 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X24, [X6, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X6, SP, #96 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X26, [X7, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X15, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X23, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X21, [X11, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUB W11, W9, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVN X9, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X28, [X13] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X19, [X13, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
UMADDL X20, W11, W8, X9 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
LDR X13, [X12] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X9, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X27, [X14, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X25, [X12, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X22, [X10, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X16, X17, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP W1, WZR, [SP, #88] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X8, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X8, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X11, X13, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X20, XZR, [X29, #936] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X9, [SP, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
BL 4033a0 <@plt_start@+0x670> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDP X8, X14, [X29, #936] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
CMP X8, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CSEL X9, X8, X20, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X14, X9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LE 41b9a4 <.omp_outlined..12+0x154> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 |
Source file and lines | advec_cell.cpp:157-202 |
Module | exec |
nb instructions | 80 |
loop length | 320 |
nb stack references | 0 |
front end | 8.63 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.00 | 2.00 | 6.00 | 6.00 | 6.00 | 6.00 | 2.00 | 2.00 | 0.00 | 0.00 | 14.00 | 14.00 | 14.00 | 8.00 | 8.00 |
cycles | 2.00 | 2.00 | 6.00 | 6.00 | 6.00 | 6.00 | 2.00 | 2.00 | 0.00 | 0.00 | 14.00 | 14.00 | 14.00 | 8.00 | 8.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 8.63 |
Overall L1 | 14.00 |
all | 36% |
load | NA (no load vectorizable/vectorized instructions) |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SUB SP, SP, #288 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP D15, D14, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP D13, D12, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP D11, D10, [SP, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP D9, D8, [SP, #176] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP X29, X30, [SP, #192] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X28, X27, [SP, #208] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X26, X25, [SP, #224] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X24, X23, [SP, #240] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X22, X21, [SP, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X20, X19, [SP, #272] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #192 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W11, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR W13, [X3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD W12, W11, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD W8, W13, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUBS W8, W8, W12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LE 41b974 <.omp_outlined..12+0x124> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR W9, [X4] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR W10, [X5] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD W15, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD W9, W10, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP W9, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LE 41b974 <.omp_outlined..12+0x124> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
STP X12, X11, [SP, #72] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDP X11, X10, [X29, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
STR W13, [SP, #20] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X12, [X29, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X3, SP, #92 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X4, X29, #80 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X5, X29, #88 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDP X14, X13, [X29, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDR X17, [X6] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X16, [X7] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR W1, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADRP X0, <45e8e0> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #3408 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X24, [X6, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X6, SP, #96 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X26, [X7, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X15, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X23, [X11] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X21, [X11, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUB W11, W9, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVN X9, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X28, [X13] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X19, [X13, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
UMADDL X20, W11, W8, X9 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
LDR X13, [X12] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X9, [X10] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X27, [X14, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X25, [X12, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X22, [X10, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X16, X17, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP W1, WZR, [SP, #88] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X8, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X8, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X11, X13, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X20, XZR, [X29, #936] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X9, [SP, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
BL 4033a0 <@plt_start@+0x670> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDP X8, X14, [X29, #936] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
CMP X8, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CSEL X9, X8, X20, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X14, X9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LE 41b9a4 <.omp_outlined..12+0x154> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼.omp_outlined..12– | 3.75 | 5 |
▼Loop 306 - advec_cell.cpp:157-202 - exec– | 0 | 0 |
▼Loop 308 - advec_cell.cpp:157-202 - exec– | 0 | 0 |
○Loop 307 - advec_cell.cpp:158-202 - exec | 3.75 | 4.97 |