Loop Id: 577 | Module: exec | Source: field_summary_kernel.f90-pp.f90:62-71 | Coverage: 0.25% |
---|
Loop Id: 577 | Module: exec | Source: field_summary_kernel.f90-pp.f90:62-71 | Coverage: 0.25% |
---|
0x4243e0 UBFM X8, X15, #61, #60 |
0x4243e4 ADD X10, X5, X8 |
0x4243e8 ADD X14, X4, X8 |
0x4243ec LD1D {Z16.D}, P1/Z, [X10, MUL VL] [4] |
0x4243f0 LD1D {Z17.D}, P1/Z, [X14, MUL VL] [8] |
0x4243f4 LD1D {Z18.D}, P1/Z, [X14, X28,LSL #3] [11] |
0x4243f8 FMUL Z16.D, Z16.D, Z16.D |
0x4243fc FMLA Z16.D, P1/M, Z17.D, Z17.D |
0x424400 LD1D {Z17.D}, P1/Z, [X10, X28,LSL #3] [1] |
0x424404 ADD X10, X24, X8 |
0x424408 ADD X8, X23, X8 |
0x42440c FMLA Z16.D, P1/M, Z17.D, Z17.D |
0x424410 LD1D {Z17.D}, P1/Z, [X10, MUL VL] [10] |
0x424414 FMLA Z16.D, P1/M, Z18.D, Z18.D |
0x424418 LD1D {Z18.D}, P1/Z, [X8, MUL VL] [12] |
0x42441c LD1D {Z19.D}, P1/Z, [X21, X15,LSL #3] [9] |
0x424420 FMLA Z16.D, P1/M, Z17.D, Z17.D |
0x424424 LD1D {Z17.D}, P1/Z, [X10, X28,LSL #3] [3] |
0x424428 FMLA Z16.D, P1/M, Z18.D, Z18.D |
0x42442c LD1D {Z18.D}, P1/Z, [X8, X28,LSL #3] [6] |
0x424430 FMLA Z16.D, P1/M, Z17.D, Z17.D |
0x424434 LD1D {Z17.D}, P1/Z, [X22, X15,LSL #3] [7] |
0x424438 FMLA Z16.D, P1/M, Z18.D, Z18.D |
0x42443c LD1D {Z18.D}, P1/Z, [X7, X15,LSL #3] [2] |
0x424440 FMUL Z19.D, Z19.D, Z17.D |
0x424444 FADD Z7.D, Z17.D, Z7.D |
0x424448 FMUL Z16.D, Z16.D, Z2.D |
0x42444c FADD Z6.D, Z19.D, Z6.D |
0x424450 FMLA Z4.D, P1/M, Z18.D, Z19.D |
0x424454 LD1D {Z18.D}, P1/Z, [X6, X15,LSL #3] [5] |
0x424458 ADD X15, X15, X12 |
0x42445c FMLA Z3.D, P1/M, Z16.D, Z19.D |
0x424460 CMP X0, X15 |
0x424464 FMLA Z5.D, P1/M, Z18.D, Z17.D |
0x424468 B.NE 4243e0 |
/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/armclang_5/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/field_summary_kernel.f90-pp.f90: 62 - 71 |
-------------------------------------------------------------------------------- |
62: DO jv=j,j+1 |
63: vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2) |
64: ENDDO |
65: ENDDO |
66: cell_vol=volume(j,k) |
67: cell_mass=cell_vol*density0(j,k) |
68: vol=vol+cell_vol |
69: mass=mass+cell_mass |
70: ie=ie+cell_mass*energy0(j,k) |
71: ke=ke+cell_mass*0.5*vsqrd |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.25 |
Bottlenecks | P6, P7, P8, P9, |
Function | __nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_ |
Source | field_summary_kernel.f90-pp.f90:62-71 |
Source loop unroll info | unrolled by 4 |
Source loop unroll confidence level | low |
Unroll/vectorization loop type | NA |
Unroll factor | 4 |
CQA cycles | 7.50 |
CQA cycles if no scalar integer | 7.50 |
CQA cycles if FP arith vectorized | 7.50 |
CQA cycles if fully vectorized | 7.50 |
Front-end cycles | 4.38 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 1.75 |
P2 cycles | 1.75 |
P3 cycles | 1.75 |
P4 cycles | 1.75 |
P5 cycles | 7.50 |
P6 cycles | 7.50 |
P7 cycles | 7.50 |
P8 cycles | 7.50 |
P9 cycles | 6.00 |
P10 cycles | 6.00 |
P11 cycles | 0.00 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | 2 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 35.00 |
Nb uops | 35.00 |
Nb loads | NA |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 13.33 |
Nb FLOP add-sub | 8.00 |
Nb FLOP mul | 12.00 |
Nb FLOP fma | 40.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 51.20 |
Bytes prefetched | 0.00 |
Bytes loaded | 384.00 |
Bytes stored | 0.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | 100.00 |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | 100.00 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.25 |
Bottlenecks | P6, P7, P8, P9, |
Function | __nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_ |
Source | field_summary_kernel.f90-pp.f90:62-71 |
Source loop unroll info | unrolled by 4 |
Source loop unroll confidence level | low |
Unroll/vectorization loop type | NA |
Unroll factor | 4 |
CQA cycles | 7.50 |
CQA cycles if no scalar integer | 7.50 |
CQA cycles if FP arith vectorized | 7.50 |
CQA cycles if fully vectorized | 7.50 |
Front-end cycles | 4.38 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 1.75 |
P2 cycles | 1.75 |
P3 cycles | 1.75 |
P4 cycles | 1.75 |
P5 cycles | 7.50 |
P6 cycles | 7.50 |
P7 cycles | 7.50 |
P8 cycles | 7.50 |
P9 cycles | 6.00 |
P10 cycles | 6.00 |
P11 cycles | 0.00 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | 2 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 35.00 |
Nb uops | 35.00 |
Nb loads | NA |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 13.33 |
Nb FLOP add-sub | 8.00 |
Nb FLOP mul | 12.00 |
Nb FLOP fma | 40.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 51.20 |
Bytes prefetched | 0.00 |
Bytes loaded | 384.00 |
Bytes stored | 0.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | 100.00 |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | 100.00 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Path / |
Function | __nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_ |
Source file and lines | field_summary_kernel.f90-pp.f90:62-71 |
Module | exec |
nb instructions | 35 |
loop length | 140 |
nb stack references | 0 |
front end | 4.38 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 1.75 | 1.75 | 1.75 | 1.75 | 7.50 | 7.50 | 0.00 | 0.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 |
cycles | 0.50 | 0.50 | 1.75 | 1.75 | 1.75 | 1.75 | 7.50 | 7.50 | 7.50 | 7.50 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 2.00 |
Front-end | 4.38 |
Data deps. | 2.00 |
Overall L1 | 7.50 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
UBFM X8, X15, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X10, X5, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X14, X4, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LD1D {Z16.D}, P1/Z, [X10, MUL VL] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
LD1D {Z17.D}, P1/Z, [X14, MUL VL] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
LD1D {Z18.D}, P1/Z, [X14, X28,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
FMUL Z16.D, Z16.D, Z16.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
FMLA Z16.D, P1/M, Z17.D, Z17.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
LD1D {Z17.D}, P1/Z, [X10, X28,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
ADD X10, X24, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X8, X23, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
FMLA Z16.D, P1/M, Z17.D, Z17.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
LD1D {Z17.D}, P1/Z, [X10, MUL VL] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
FMLA Z16.D, P1/M, Z18.D, Z18.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
LD1D {Z18.D}, P1/Z, [X8, MUL VL] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
LD1D {Z19.D}, P1/Z, [X21, X15,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
FMLA Z16.D, P1/M, Z17.D, Z17.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
LD1D {Z17.D}, P1/Z, [X10, X28,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
FMLA Z16.D, P1/M, Z18.D, Z18.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
LD1D {Z18.D}, P1/Z, [X8, X28,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
FMLA Z16.D, P1/M, Z17.D, Z17.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
LD1D {Z17.D}, P1/Z, [X22, X15,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
FMLA Z16.D, P1/M, Z18.D, Z18.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
LD1D {Z18.D}, P1/Z, [X7, X15,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
FMUL Z19.D, Z19.D, Z17.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
FADD Z7.D, Z17.D, Z7.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
FMUL Z16.D, Z16.D, Z2.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
FADD Z6.D, Z19.D, Z6.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
FMLA Z4.D, P1/M, Z18.D, Z19.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
LD1D {Z18.D}, P1/Z, [X6, X15,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
ADD X15, X15, X12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
FMLA Z3.D, P1/M, Z16.D, Z19.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP X0, X15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
FMLA Z5.D, P1/M, Z18.D, Z17.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
B.NE 4243e0 <__nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_+0x240> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Function | __nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_ |
Source file and lines | field_summary_kernel.f90-pp.f90:62-71 |
Module | exec |
nb instructions | 35 |
loop length | 140 |
nb stack references | 0 |
front end | 4.38 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 1.75 | 1.75 | 1.75 | 1.75 | 7.50 | 7.50 | 0.00 | 0.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 |
cycles | 0.50 | 0.50 | 1.75 | 1.75 | 1.75 | 1.75 | 7.50 | 7.50 | 7.50 | 7.50 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 2.00 |
Front-end | 4.38 |
Data deps. | 2.00 |
Overall L1 | 7.50 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
UBFM X8, X15, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X10, X5, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X14, X4, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LD1D {Z16.D}, P1/Z, [X10, MUL VL] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
LD1D {Z17.D}, P1/Z, [X14, MUL VL] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
LD1D {Z18.D}, P1/Z, [X14, X28,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
FMUL Z16.D, Z16.D, Z16.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
FMLA Z16.D, P1/M, Z17.D, Z17.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
LD1D {Z17.D}, P1/Z, [X10, X28,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
ADD X10, X24, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X8, X23, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
FMLA Z16.D, P1/M, Z17.D, Z17.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
LD1D {Z17.D}, P1/Z, [X10, MUL VL] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
FMLA Z16.D, P1/M, Z18.D, Z18.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
LD1D {Z18.D}, P1/Z, [X8, MUL VL] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
LD1D {Z19.D}, P1/Z, [X21, X15,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
FMLA Z16.D, P1/M, Z17.D, Z17.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
LD1D {Z17.D}, P1/Z, [X10, X28,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
FMLA Z16.D, P1/M, Z18.D, Z18.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
LD1D {Z18.D}, P1/Z, [X8, X28,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
FMLA Z16.D, P1/M, Z17.D, Z17.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
LD1D {Z17.D}, P1/Z, [X22, X15,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
FMLA Z16.D, P1/M, Z18.D, Z18.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
LD1D {Z18.D}, P1/Z, [X7, X15,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
FMUL Z19.D, Z19.D, Z17.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
FADD Z7.D, Z17.D, Z7.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
FMUL Z16.D, Z16.D, Z2.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
FADD Z6.D, Z19.D, Z6.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
FMLA Z4.D, P1/M, Z18.D, Z19.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
LD1D {Z18.D}, P1/Z, [X6, X15,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
ADD X15, X15, X12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
FMLA Z3.D, P1/M, Z16.D, Z19.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP X0, X15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
FMLA Z5.D, P1/M, Z18.D, Z17.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
B.NE 4243e0 <__nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_+0x240> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |