Loop Id: 566 | Module: exec | Source: advec_mom_kernel.f90-pp.f90:96-97 | Coverage: 1.3% |
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Loop Id: 566 | Module: exec | Source: advec_mom_kernel.f90-pp.f90:96-97 | Coverage: 1.3% |
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0x41eb80 ADD X28, X6, X0,LSL #3 |
0x41eb84 LD1D {Z1.D}, P0/Z, [X5, X0,LSL #3] [2] |
0x41eb88 LD1D {Z0.D}, P0/Z, [X28, X25,LSL #3] [3] |
0x41eb8c FADD Z0.D, Z0.D, Z1.D |
0x41eb90 LD1D {Z1.D}, P0/Z, [X28, MUL VL] [1] |
0x41eb94 FSUB Z0.D, Z0.D, Z1.D |
0x41eb98 LD1D {Z1.D}, P0/Z, [X7, X0,LSL #3] [5] |
0x41eb9c ST1D {Z0.D}, P0, [X3, X0,LSL #3] [7] |
0x41eba0 FADD Z0.D, Z0.D, Z1.D |
0x41eba4 LD1D {Z1.D}, P0/Z, [X4, X0,LSL #3] [6] |
0x41eba8 FSUB Z0.D, Z0.D, Z1.D |
0x41ebac ST1D {Z0.D}, P0, [X2, X0,LSL #3] [4] |
0x41ebb0 ADD X0, X0, X12 |
0x41ebb4 CMP X26, X0 |
0x41ebb8 B.NE 41eb80 |
/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90: 96 - 97 |
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96: DO j=x_min-2,x_max+2 |
97: post_vol(j,k)= volume(j,k)+vol_flux_x(j+1,k )-vol_flux_x(j,k) |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.75 |
Bottlenecks | P10, P11, |
Function | advec_mom_kernel |
Source | advec_mom_kernel.f90-pp.f90:96-97 |
Source loop unroll info | unrolled by 4 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | 4 |
CQA cycles | 3.50 |
CQA cycles if no scalar integer | 3.50 |
CQA cycles if FP arith vectorized | 3.50 |
CQA cycles if fully vectorized | 3.50 |
Front-end cycles | 1.88 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 0.75 |
P2 cycles | 0.75 |
P3 cycles | 0.75 |
P4 cycles | 0.75 |
P5 cycles | 2.00 |
P6 cycles | 2.00 |
P7 cycles | 2.00 |
P8 cycles | 2.00 |
P9 cycles | 3.50 |
P10 cycles | 3.50 |
P11 cycles | 0.00 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 15.00 |
Nb uops | 15.00 |
Nb loads | NA |
Nb stores | 2.00 |
Nb stack references | 0.00 |
FLOP/cycle | 4.57 |
Nb FLOP add-sub | 16.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 64.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 160.00 |
Bytes stored | 64.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.75 |
Bottlenecks | P10, P11, |
Function | advec_mom_kernel |
Source | advec_mom_kernel.f90-pp.f90:96-97 |
Source loop unroll info | unrolled by 4 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | 4 |
CQA cycles | 3.50 |
CQA cycles if no scalar integer | 3.50 |
CQA cycles if FP arith vectorized | 3.50 |
CQA cycles if fully vectorized | 3.50 |
Front-end cycles | 1.88 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 0.75 |
P2 cycles | 0.75 |
P3 cycles | 0.75 |
P4 cycles | 0.75 |
P5 cycles | 2.00 |
P6 cycles | 2.00 |
P7 cycles | 2.00 |
P8 cycles | 2.00 |
P9 cycles | 3.50 |
P10 cycles | 3.50 |
P11 cycles | 0.00 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 15.00 |
Nb uops | 15.00 |
Nb loads | NA |
Nb stores | 2.00 |
Nb stack references | 0.00 |
FLOP/cycle | 4.57 |
Nb FLOP add-sub | 16.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 64.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 160.00 |
Bytes stored | 64.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Path / |
Function | advec_mom_kernel |
Source file and lines | advec_mom_kernel.f90-pp.f90:96-97 |
Module | exec |
nb instructions | 15 |
loop length | 60 |
nb stack references | 0 |
front end | 1.88 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 0.75 | 0.75 | 0.75 | 0.75 | 2.00 | 2.00 | 1.00 | 1.00 | 3.50 | 3.50 | 0.00 | 0.00 | 0.00 |
cycles | 0.50 | 0.50 | 0.75 | 0.75 | 0.75 | 0.75 | 2.00 | 2.00 | 2.00 | 2.00 | 3.50 | 3.50 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 1.88 |
Data deps. | 1.00 |
Overall L1 | 3.50 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADD X28, X6, X0,LSL #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LD1D {Z1.D}, P0/Z, [X5, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
LD1D {Z0.D}, P0/Z, [X28, X25,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
FADD Z0.D, Z0.D, Z1.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
LD1D {Z1.D}, P0/Z, [X28, MUL VL] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
FSUB Z0.D, Z0.D, Z1.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
LD1D {Z1.D}, P0/Z, [X7, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
ST1D {Z0.D}, P0, [X3, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
FADD Z0.D, Z0.D, Z1.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
LD1D {Z1.D}, P0/Z, [X4, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
FSUB Z0.D, Z0.D, Z1.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
ST1D {Z0.D}, P0, [X2, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
ADD X0, X0, X12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X26, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.NE 41eb80 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x460> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Function | advec_mom_kernel |
Source file and lines | advec_mom_kernel.f90-pp.f90:96-97 |
Module | exec |
nb instructions | 15 |
loop length | 60 |
nb stack references | 0 |
front end | 1.88 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 0.75 | 0.75 | 0.75 | 0.75 | 2.00 | 2.00 | 1.00 | 1.00 | 3.50 | 3.50 | 0.00 | 0.00 | 0.00 |
cycles | 0.50 | 0.50 | 0.75 | 0.75 | 0.75 | 0.75 | 2.00 | 2.00 | 2.00 | 2.00 | 3.50 | 3.50 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 1.88 |
Data deps. | 1.00 |
Overall L1 | 3.50 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADD X28, X6, X0,LSL #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LD1D {Z1.D}, P0/Z, [X5, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
LD1D {Z0.D}, P0/Z, [X28, X25,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
FADD Z0.D, Z0.D, Z1.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
LD1D {Z1.D}, P0/Z, [X28, MUL VL] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
FSUB Z0.D, Z0.D, Z1.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
LD1D {Z1.D}, P0/Z, [X7, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
ST1D {Z0.D}, P0, [X3, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
FADD Z0.D, Z0.D, Z1.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
LD1D {Z1.D}, P0/Z, [X4, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
FSUB Z0.D, Z0.D, Z1.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
ST1D {Z0.D}, P0, [X2, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
ADD X0, X0, X12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X26, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.NE 41eb80 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x460> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |