Function: revert_kernel._omp_fn.0 | Module: exec | Source: revert_kernel.f90:41-48 | Coverage: 2.33% |
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Function: revert_kernel._omp_fn.0 | Module: exec | Source: revert_kernel.f90:41-48 | Coverage: 2.33% |
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/home/eoseret/qaas_runs_CPU_9468/171-152-3172/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/revert_kernel.f90: 41 - 48 |
-------------------------------------------------------------------------------- |
41: !$OMP PARALLEL |
42: |
43: !$OMP DO |
44: DO k=y_min,y_max |
45: !$OMP SIMD |
46: DO j=x_min,x_max |
47: density1(j,k)=density0(j,k) |
48: energy1(j,k)=energy0(j,k) |
0x44e760 PUSH %RBP |
0x44e761 MOV %RSP,%RBP |
0x44e764 PUSH %R15 |
0x44e766 PUSH %R14 |
0x44e768 PUSH %R13 |
0x44e76a PUSH %R12 |
0x44e76c MOV %RDI,%R12 |
0x44e76f PUSH %RBX |
0x44e770 AND $-0x40,%RSP |
0x44e774 ADD $-0x80,%RSP |
0x44e778 MOV 0x70(%RDI),%RDX |
0x44e77c MOV 0x50(%RDI),%RSI |
0x44e780 MOV %RDI,0x10(%RSP) |
0x44e785 MOV 0x68(%RDI),%RCX |
0x44e789 MOV 0x40(%RDI),%R8 |
0x44e78d MOV 0x78(%RDI),%RAX |
0x44e791 MOV 0x60(%RDI),%RBX |
0x44e795 MOV %RDX,0x50(%RSP) |
0x44e79a MOV 0x58(%RDI),%R13 |
0x44e79e MOV 0x48(%RDI),%R14 |
0x44e7a2 MOV %RSI,0x40(%RSP) |
0x44e7a7 MOV 0x10(%RDI),%RDI |
0x44e7ab MOV %RCX,0x68(%RSP) |
0x44e7b0 MOV %RBX,0x48(%RSP) |
0x44e7b5 MOV %R8,0x38(%RSP) |
0x44e7ba MOV (%RDI),%EBX |
0x44e7bc MOV %RAX,0x70(%RSP) |
0x44e7c1 CALL 402080 <@plt_start@+0x60> |
0x44e7c6 MOV %EAX,%R15D |
0x44e7c9 CALL 402180 <@plt_start@+0x160> |
0x44e7ce MOV 0x18(%R12),%R9 |
0x44e7d3 MOV %EAX,%ESI |
0x44e7d5 MOV (%R9),%EAX |
0x44e7d8 INC %EAX |
0x44e7da SUB %EBX,%EAX |
0x44e7dc CLTD |
0x44e7dd IDIV %R15D |
0x44e7e0 CMP %EDX,%ESI |
0x44e7e2 JL 44ed1c |
0x44e7e8 IMUL %EAX,%ESI |
0x44e7eb ADD %EDX,%ESI |
0x44e7ed ADD %ESI,%EAX |
0x44e7ef CMP %EAX,%ESI |
0x44e7f1 JGE 44ecbd |
0x44e7f7 MOV 0x10(%RSP),%R12 |
0x44e7fc ADD %EBX,%ESI |
0x44e7fe ADD %EBX,%EAX |
0x44e800 MOV 0x38(%RSP),%RDX |
0x44e805 MOV %EAX,0x34(%RSP) |
0x44e809 MOVSXD %ESI,%RAX |
0x44e80c MOV 0x8(%R12),%R11 |
0x44e811 MOV (%R12),%R10 |
0x44e815 IMUL %RAX,%RDX |
0x44e819 MOV %ESI,0x7c(%RSP) |
0x44e81d MOV 0x68(%RSP),%RSI |
0x44e822 MOV 0x30(%R12),%R9 |
0x44e827 MOV (%R11),%R15D |
0x44e82a MOVSXD (%R10),%RCX |
0x44e82d MOV 0x20(%R12),%R11 |
0x44e832 MOV 0x28(%R12),%R10 |
0x44e837 LEA 0x1(%R15),%R8D |
0x44e83b LEA (%R13,%RCX,1),%RDI |
0x44e840 MOV 0x50(%RSP),%R13 |
0x44e845 MOV %RCX,%RBX |
0x44e848 MOV %R8D,0x2c(%RSP) |
0x44e84d LEA (%R14,%RCX,1),%R8 |
0x44e851 ADD %RCX,%RSI |
0x44e854 MOV 0x38(%R12),%R12 |
0x44e859 ADD %RDX,%R8 |
0x44e85c MOV 0x40(%RSP),%RDX |
0x44e861 MOV %ECX,0x60(%RSP) |
0x44e865 MOV %RCX,0x18(%RSP) |
0x44e86a MOV 0x70(%RSP),%RCX |
0x44e86f IMUL %RAX,%RDX |
0x44e873 MOV %R15D,0x78(%RSP) |
0x44e878 ADD %RBX,%RCX |
0x44e87b MOV %R11,0x70(%RSP) |
0x44e880 ADD %RDX,%RDI |
0x44e883 MOV 0x48(%RSP),%RDX |
0x44e888 IMUL %RAX,%RDX |
0x44e88c IMUL %R13,%RAX |
0x44e890 ADD %RDX,%RSI |
0x44e893 ADD %RAX,%RCX |
0x44e896 MOV %R15D,%EAX |
0x44e899 SUB %EBX,%EAX |
0x44e89b MOV %EAX,0x64(%RSP) |
0x44e89f INC %EAX |
0x44e8a1 MOV %EAX,%R14D |
0x44e8a4 MOV %EAX,%EDX |
0x44e8a6 SHR $0x3,%R14D |
0x44e8aa AND $-0x8,%EDX |
0x44e8ad SAL $0x6,%R14 |
0x44e8b1 CMP %R15D,%EBX |
0x44e8b4 LEA (%RDX,%RBX,1),%R13D |
0x44e8b8 MOV %EDX,0x28(%RSP) |
0x44e8bc CMOVLE 0x2c(%RSP),%EBX |
0x44e8c1 AND $0x7,%EAX |
0x44e8c4 MOV %R13D,0x24(%RSP) |
0x44e8c9 MOV %EAX,0x30(%RSP) |
0x44e8cd MOV %EBX,0x20(%RSP) |
0x44e8d1 MOV %R14,0x68(%RSP) |
0x44e8d6 XOR %R14D,%R14D |
0x44e8d9 NOPL (%RAX) |
(300) 0x44e8e0 MOV 0x78(%RSP),%EBX |
(300) 0x44e8e4 CMP %EBX,0x60(%RSP) |
(300) 0x44e8e8 JG 44ecd0 |
(300) 0x44e8ee CMPL $0x6,0x64(%RSP) |
(300) 0x44e8f3 JBE 44ed10 |
(300) 0x44e8f9 MOV 0x68(%RSP),%RDX |
(300) 0x44e8fe MOV 0x70(%RSP),%R11 |
(300) 0x44e903 LEA (%R10,%RDI,8),%R13 |
(300) 0x44e907 LEA (%R9,%RSI,8),%RBX |
(300) 0x44e90b LEA (%R12,%RCX,8),%R14 |
(300) 0x44e90f XOR %EAX,%EAX |
(300) 0x44e911 SUB $0x40,%RDX |
(300) 0x44e915 LEA (%R11,%R8,8),%R15 |
(300) 0x44e919 SHR $0x6,%RDX |
(300) 0x44e91d INC %RDX |
(300) 0x44e920 AND $0x7,%EDX |
(300) 0x44e923 JE 44ea2a |
(300) 0x44e929 CMP $0x1,%RDX |
(300) 0x44e92d JE 44e9fe |
(300) 0x44e933 CMP $0x2,%RDX |
(300) 0x44e937 JE 44e9dd |
(300) 0x44e93d CMP $0x3,%RDX |
(300) 0x44e941 JE 44e9bc |
(300) 0x44e943 CMP $0x4,%RDX |
(300) 0x44e947 JE 44e99b |
(300) 0x44e949 CMP $0x5,%RDX |
(300) 0x44e94d JE 44e97a |
(300) 0x44e94f CMP $0x6,%RDX |
(300) 0x44e953 JNE 44ece8 |
(300) 0x44e959 VMOVUPD (%R15,%RAX,1),%ZMM1 |
(300) 0x44e960 VMOVUPD %ZMM1,(%R13,%RAX,1) |
(300) 0x44e968 VMOVUPD (%RBX,%RAX,1),%ZMM2 |
(300) 0x44e96f VMOVUPD %ZMM2,(%R14,%RAX,1) |
(300) 0x44e976 ADD $0x40,%RAX |
(300) 0x44e97a VMOVUPD (%R15,%RAX,1),%ZMM0 |
(300) 0x44e981 VMOVUPD %ZMM0,(%R13,%RAX,1) |
(300) 0x44e989 VMOVUPD (%RBX,%RAX,1),%ZMM5 |
(300) 0x44e990 VMOVUPD %ZMM5,(%R14,%RAX,1) |
(300) 0x44e997 ADD $0x40,%RAX |
(300) 0x44e99b VMOVUPD (%R15,%RAX,1),%ZMM6 |
(300) 0x44e9a2 VMOVUPD %ZMM6,(%R13,%RAX,1) |
(300) 0x44e9aa VMOVUPD (%RBX,%RAX,1),%ZMM7 |
(300) 0x44e9b1 VMOVUPD %ZMM7,(%R14,%RAX,1) |
(300) 0x44e9b8 ADD $0x40,%RAX |
(300) 0x44e9bc VMOVUPD (%R15,%RAX,1),%ZMM8 |
(300) 0x44e9c3 VMOVUPD %ZMM8,(%R13,%RAX,1) |
(300) 0x44e9cb VMOVUPD (%RBX,%RAX,1),%ZMM9 |
(300) 0x44e9d2 VMOVUPD %ZMM9,(%R14,%RAX,1) |
(300) 0x44e9d9 ADD $0x40,%RAX |
(300) 0x44e9dd VMOVUPD (%R15,%RAX,1),%ZMM10 |
(300) 0x44e9e4 VMOVUPD %ZMM10,(%R13,%RAX,1) |
(300) 0x44e9ec VMOVUPD (%RBX,%RAX,1),%ZMM11 |
(300) 0x44e9f3 VMOVUPD %ZMM11,(%R14,%RAX,1) |
(300) 0x44e9fa ADD $0x40,%RAX |
(300) 0x44e9fe VMOVUPD (%R15,%RAX,1),%ZMM12 |
(300) 0x44ea05 VMOVUPD %ZMM12,(%R13,%RAX,1) |
(300) 0x44ea0d VMOVUPD (%RBX,%RAX,1),%ZMM13 |
(300) 0x44ea14 VMOVUPD %ZMM13,(%R14,%RAX,1) |
(300) 0x44ea1b ADD $0x40,%RAX |
(300) 0x44ea1f CMP %RAX,0x68(%RSP) |
(300) 0x44ea24 JE 44eb38 |
(301) 0x44ea2a VMOVUPD (%R15,%RAX,1),%ZMM14 |
(301) 0x44ea31 VMOVUPD %ZMM14,(%R13,%RAX,1) |
(301) 0x44ea39 VMOVUPD (%RBX,%RAX,1),%ZMM15 |
(301) 0x44ea40 VMOVUPD %ZMM15,(%R14,%RAX,1) |
(301) 0x44ea47 VMOVUPD 0x40(%R15,%RAX,1),%ZMM3 |
(301) 0x44ea4f VMOVUPD %ZMM3,0x40(%R13,%RAX,1) |
(301) 0x44ea57 VMOVUPD 0x40(%RBX,%RAX,1),%ZMM4 |
(301) 0x44ea5f VMOVUPD %ZMM4,0x40(%R14,%RAX,1) |
(301) 0x44ea67 VMOVUPD 0x80(%R15,%RAX,1),%ZMM1 |
(301) 0x44ea6f VMOVUPD %ZMM1,0x80(%R13,%RAX,1) |
(301) 0x44ea77 VMOVUPD 0x80(%RBX,%RAX,1),%ZMM2 |
(301) 0x44ea7f VMOVUPD %ZMM2,0x80(%R14,%RAX,1) |
(301) 0x44ea87 VMOVUPD 0xc0(%R15,%RAX,1),%ZMM0 |
(301) 0x44ea8f VMOVUPD %ZMM0,0xc0(%R13,%RAX,1) |
(301) 0x44ea97 VMOVUPD 0xc0(%RBX,%RAX,1),%ZMM5 |
(301) 0x44ea9f VMOVUPD %ZMM5,0xc0(%R14,%RAX,1) |
(301) 0x44eaa7 VMOVUPD 0x100(%R15,%RAX,1),%ZMM6 |
(301) 0x44eaaf VMOVUPD %ZMM6,0x100(%R13,%RAX,1) |
(301) 0x44eab7 VMOVUPD 0x100(%RBX,%RAX,1),%ZMM7 |
(301) 0x44eabf VMOVUPD %ZMM7,0x100(%R14,%RAX,1) |
(301) 0x44eac7 VMOVUPD 0x140(%R15,%RAX,1),%ZMM8 |
(301) 0x44eacf VMOVUPD %ZMM8,0x140(%R13,%RAX,1) |
(301) 0x44ead7 VMOVUPD 0x140(%RBX,%RAX,1),%ZMM9 |
(301) 0x44eadf VMOVUPD %ZMM9,0x140(%R14,%RAX,1) |
(301) 0x44eae7 VMOVUPD 0x180(%R15,%RAX,1),%ZMM10 |
(301) 0x44eaef VMOVUPD %ZMM10,0x180(%R13,%RAX,1) |
(301) 0x44eaf7 VMOVUPD 0x180(%RBX,%RAX,1),%ZMM11 |
(301) 0x44eaff VMOVUPD %ZMM11,0x180(%R14,%RAX,1) |
(301) 0x44eb07 VMOVUPD 0x1c0(%R15,%RAX,1),%ZMM12 |
(301) 0x44eb0f VMOVUPD %ZMM12,0x1c0(%R13,%RAX,1) |
(301) 0x44eb17 VMOVUPD 0x1c0(%RBX,%RAX,1),%ZMM13 |
(301) 0x44eb1f VMOVUPD %ZMM13,0x1c0(%R14,%RAX,1) |
(301) 0x44eb27 ADD $0x200,%RAX |
(301) 0x44eb2d CMP %RAX,0x68(%RSP) |
(301) 0x44eb32 JNE 44ea2a |
(300) 0x44eb38 MOV 0x30(%RSP),%R11D |
(300) 0x44eb3d TEST %R11D,%R11D |
(300) 0x44eb40 JE 44ec5b |
(300) 0x44eb46 MOV 0x28(%RSP),%R14D |
(300) 0x44eb4b MOV 0x24(%RSP),%EAX |
(300) 0x44eb4f MOV 0x64(%RSP),%R15D |
(300) 0x44eb54 SUB %R14D,%R15D |
(300) 0x44eb57 LEA 0x1(%R15),%R13D |
(300) 0x44eb5b CMP $0x2,%R15D |
(300) 0x44eb5f JBE 44eb9d |
(300) 0x44eb61 MOV 0x70(%RSP),%RDX |
(300) 0x44eb66 LEA (%R8,%R14,1),%RBX |
(300) 0x44eb6a LEA (%RDI,%R14,1),%R11 |
(300) 0x44eb6e LEA (%RSI,%R14,1),%R15 |
(300) 0x44eb72 ADD %RCX,%R14 |
(300) 0x44eb75 VMOVUPD (%RDX,%RBX,8),%YMM14 |
(300) 0x44eb7a VMOVUPD %YMM14,(%R10,%R11,8) |
(300) 0x44eb80 VMOVUPD (%R9,%R15,8),%YMM15 |
(300) 0x44eb86 VMOVUPD %YMM15,(%R12,%R14,8) |
(300) 0x44eb8c TEST $0x3,%R13B |
(300) 0x44eb90 JE 44ec5b |
(300) 0x44eb96 AND $-0x4,%R13D |
(300) 0x44eb9a ADD %R13D,%EAX |
(300) 0x44eb9d MOV 0x18(%RSP),%RDX |
(300) 0x44eba2 MOV %RCX,%R11 |
(300) 0x44eba5 MOV %R8,%R14 |
(300) 0x44eba8 MOV %RDI,%R13 |
(300) 0x44ebab MOV %RSI,%RBX |
(300) 0x44ebae SUB %RDX,%R11 |
(300) 0x44ebb1 SUB %RDX,%R14 |
(300) 0x44ebb4 SUB %RDX,%R13 |
(300) 0x44ebb7 SUB %RDX,%RBX |
(300) 0x44ebba MOV %R11,0x58(%RSP) |
(300) 0x44ebbf MOVSXD %EAX,%RDX |
(300) 0x44ebc2 MOV 0x70(%RSP),%R11 |
(300) 0x44ebc7 LEA (%R14,%RDX,1),%R15 |
(300) 0x44ebcb VMOVSD (%R11,%R15,8),%XMM3 |
(300) 0x44ebd1 LEA (%RDX,%R13,1),%R15 |
(300) 0x44ebd5 VMOVSD %XMM3,(%R10,%R15,8) |
(300) 0x44ebdb LEA (%RDX,%RBX,1),%R15 |
(300) 0x44ebdf VMOVSD (%R9,%R15,8),%XMM4 |
(300) 0x44ebe5 MOV 0x58(%RSP),%R15 |
(300) 0x44ebea ADD %R15,%RDX |
(300) 0x44ebed VMOVSD %XMM4,(%R12,%RDX,8) |
(300) 0x44ebf3 LEA 0x1(%RAX),%EDX |
(300) 0x44ebf6 CMP %EDX,0x78(%RSP) |
(300) 0x44ebfa JL 44ec5b |
(300) 0x44ebfc MOVSXD %EDX,%RDX |
(300) 0x44ebff ADD $0x2,%EAX |
(300) 0x44ec02 LEA (%R14,%RDX,1),%R15 |
(300) 0x44ec06 VMOVSD (%R11,%R15,8),%XMM1 |
(300) 0x44ec0c LEA (%R13,%RDX,1),%R15 |
(300) 0x44ec11 VMOVSD %XMM1,(%R10,%R15,8) |
(300) 0x44ec17 LEA (%RBX,%RDX,1),%R15 |
(300) 0x44ec1b VMOVSD (%R9,%R15,8),%XMM2 |
(300) 0x44ec21 MOV 0x58(%RSP),%R15 |
(300) 0x44ec26 ADD %R15,%RDX |
(300) 0x44ec29 VMOVSD %XMM2,(%R12,%RDX,8) |
(300) 0x44ec2f CMP %EAX,0x78(%RSP) |
(300) 0x44ec33 JL 44ec5b |
(300) 0x44ec35 CLTQ |
(300) 0x44ec37 ADD %RAX,%R14 |
(300) 0x44ec3a ADD %RAX,%R13 |
(300) 0x44ec3d ADD %RAX,%RBX |
(300) 0x44ec40 ADD %RAX,%R15 |
(300) 0x44ec43 VMOVSD (%R11,%R14,8),%XMM0 |
(300) 0x44ec49 VMOVSD %XMM0,(%R10,%R13,8) |
(300) 0x44ec4f VMOVSD (%R9,%RBX,8),%XMM5 |
(300) 0x44ec55 VMOVSD %XMM5,(%R12,%R15,8) |
(300) 0x44ec5b MOV 0x20(%RSP),%EAX |
(300) 0x44ec5f MOV $0x1,%R14D |
(300) 0x44ec65 MOV %EAX,0x58(%RSP) |
(300) 0x44ec69 NOPL (%RAX) |
(300) 0x44ec70 INCL 0x7c(%RSP) |
(300) 0x44ec74 MOV 0x38(%RSP),%RBX |
(300) 0x44ec79 MOV 0x40(%RSP),%R11 |
(300) 0x44ec7e MOV 0x48(%RSP),%RDX |
(300) 0x44ec83 MOV 0x50(%RSP),%R15 |
(300) 0x44ec88 ADD %RBX,%R8 |
(300) 0x44ec8b ADD %R11,%RDI |
(300) 0x44ec8e ADD %RDX,%RSI |
(300) 0x44ec91 MOV 0x7c(%RSP),%R13D |
(300) 0x44ec96 ADD %R15,%RCX |
(300) 0x44ec99 CMP %R13D,0x34(%RSP) |
(300) 0x44ec9e JG 44e8e0 |
0x44eca4 TEST %R14B,%R14B |
0x44eca7 JE 44ed25 |
0x44eca9 MOV 0x10(%RSP),%R10 |
0x44ecae MOV 0x58(%RSP),%R9D |
0x44ecb3 MOV %R9D,0x80(%R10) |
0x44ecba VZEROUPPER |
0x44ecbd LEA -0x28(%RBP),%RSP |
0x44ecc1 POP %RBX |
0x44ecc2 POP %R12 |
0x44ecc4 POP %R13 |
0x44ecc6 POP %R14 |
0x44ecc8 POP %R15 |
0x44ecca POP %RBP |
0x44eccb RET |
0x44eccc NOPL (%RAX) |
(300) 0x44ecd0 MOV 0x20(%RSP),%R15D |
(300) 0x44ecd5 CMP %R15D,0x2c(%RSP) |
(300) 0x44ecda JNE 44ec70 |
(300) 0x44ecdc JMP 44ec5b |
0x44ece1 NOPL (%RAX) |
(300) 0x44ece8 VMOVUPD (%R15),%ZMM3 |
(300) 0x44ecee MOV $0x40,%EAX |
(300) 0x44ecf3 VMOVUPD %ZMM3,(%R13) |
(300) 0x44ecfa VMOVUPD (%RBX),%ZMM4 |
(300) 0x44ed00 VMOVUPD %ZMM4,(%R14) |
(300) 0x44ed06 JMP 44e959 |
0x44ed0b NOPL (%RAX,%RAX,1) |
(300) 0x44ed10 MOV 0x60(%RSP),%EAX |
(300) 0x44ed14 XOR %R14D,%R14D |
(300) 0x44ed17 JMP 44eb4f |
0x44ed1c INC %EAX |
0x44ed1e XOR %EDX,%EDX |
0x44ed20 JMP 44e7e8 |
0x44ed25 VZEROUPPER |
0x44ed28 LEA -0x28(%RBP),%RSP |
0x44ed2c POP %RBX |
0x44ed2d POP %R12 |
0x44ed2f POP %R13 |
0x44ed31 POP %R14 |
0x44ed33 POP %R15 |
0x44ed35 POP %RBP |
0x44ed36 RET |
0x44ed37 NOPW (%RAX,%RAX,1) |
Path / |
Source file and lines | revert_kernel.f90:41-48 |
Module | exec |
nb instructions | 133 |
nb uops | 140 |
loop length | 476 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 20 |
micro-operation queue | 23.33 cycles |
front end | 23.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 8.50 | 8.40 | 14.67 | 14.67 | 14.50 | 8.47 | 8.30 | 14.50 | 14.50 | 14.50 | 8.33 | 14.67 |
cycles | 8.50 | 13.13 | 14.67 | 14.67 | 14.50 | 8.47 | 8.30 | 14.50 | 14.50 | 14.50 | 8.33 | 14.67 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 26.69-27.29 |
Stall cycles | 3.83-4.42 |
LM full (events) | 4.30-4.90 |
Front-end | 23.33 |
Dispatch | 14.67 |
DIV/SQRT | 6.00 |
Overall L1 | 23.33 |
all | 5% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 28% |
all | 9% |
load | 12% |
store | 9% |
mul | 6% |
add-sub | 10% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x70(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x50(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x68(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x58(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x48(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 402080 <@plt_start@+0x60> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 402180 <@plt_start@+0x160> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x18(%R12),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R9),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %EBX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R15D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 44ed1c <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x5bc> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %ESI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 44ecbd <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x55d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x10(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %EBX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EBX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x38(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x34(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %ESI,%RAX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV 0x8(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RAX,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %ESI,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x68(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%R12),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R11),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD (%R10),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%R12),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%R15),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R13,%RCX,1),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x50(%RSP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8D,0x2c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R14,%RCX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %RCX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x38(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x40(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %ECX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RAX,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R15D,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RBX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RDX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x48(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RAX,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
IMUL %R13,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EBX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,0x64(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EAX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x3,%R14D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
AND $-0x8,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SAL $0x6,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
CMP %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RDX,%RBX,1),%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMOVLE 0x2c(%RSP),%EBX | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.50 |
AND $0x7,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R13D,0x24(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EBX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R14D,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
TEST %R14B,%R14B | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 44ed25 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x5c5> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x10(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RSP),%R9D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9D,0x80(%R10) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 44e7e8 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x88> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | revert_kernel.f90:41-48 |
Module | exec |
nb instructions | 133 |
nb uops | 140 |
loop length | 476 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 20 |
micro-operation queue | 23.33 cycles |
front end | 23.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 8.50 | 8.40 | 14.67 | 14.67 | 14.50 | 8.47 | 8.30 | 14.50 | 14.50 | 14.50 | 8.33 | 14.67 |
cycles | 8.50 | 13.13 | 14.67 | 14.67 | 14.50 | 8.47 | 8.30 | 14.50 | 14.50 | 14.50 | 8.33 | 14.67 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 26.69-27.29 |
Stall cycles | 3.83-4.42 |
LM full (events) | 4.30-4.90 |
Front-end | 23.33 |
Dispatch | 14.67 |
DIV/SQRT | 6.00 |
Overall L1 | 23.33 |
all | 5% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 28% |
all | 9% |
load | 12% |
store | 9% |
mul | 6% |
add-sub | 10% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD $-0x80,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x70(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x50(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x68(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x58(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x48(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 402080 <@plt_start@+0x60> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 402180 <@plt_start@+0x160> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x18(%R12),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R9),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %EBX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R15D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 44ed1c <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x5bc> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %ESI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 44ecbd <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x55d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x10(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %EBX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EBX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x38(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x34(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %ESI,%RAX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV 0x8(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RAX,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %ESI,0x7c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x68(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%R12),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R11),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD (%R10),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%R12),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%R15),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA (%R13,%RCX,1),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x50(%RSP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8D,0x2c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R14,%RCX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %RCX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x38(%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x40(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %ECX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RAX,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R15D,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RBX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RDX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x48(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RAX,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
IMUL %R13,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %EBX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,0x64(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EAX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x3,%R14D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
AND $-0x8,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SAL $0x6,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
CMP %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RDX,%RBX,1),%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMOVLE 0x2c(%RSP),%EBX | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.50 |
AND $0x7,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R13D,0x24(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EBX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R14D,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
TEST %R14B,%R14B | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 44ed25 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x5c5> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x10(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RSP),%R9D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9D,0x80(%R10) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 44e7e8 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x88> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼revert_kernel._omp_fn.0– | 2.33 | 1.71 |
▼Loop 300 - revert_kernel.f90:41-48 - exec– | 0 | 0 |
○Loop 301 - revert_kernel.f90:47-48 - exec | 2.33 | 1.71 |