Function: generate_chunk_kernel._omp_fn.0 | Module: exec | Source: generate_chunk_kernel.f90:85-161 | Coverage: 0.04% |
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Function: generate_chunk_kernel._omp_fn.0 | Module: exec | Source: generate_chunk_kernel.f90:85-161 | Coverage: 0.04% |
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/home/eoseret/qaas_runs_CPU_9468/171-152-3172/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90: 85 - 161 |
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85: !$OMP PARALLEL SHARED(x_cent,y_cent) |
86: !$OMP DO |
87: DO k=y_min-2,y_max+2 |
88: !$OMP SIMD |
89: DO j=x_min-2,x_max+2 |
90: energy0(j,k)=state_energy(1) |
91: ENDDO |
92: ENDDO |
93: !$OMP END DO |
94: !$OMP DO |
95: DO k=y_min-2,y_max+2 |
96: !$OMP SIMD |
97: DO j=x_min-2,x_max+2 |
98: density0(j,k)=state_density(1) |
99: ENDDO |
100: ENDDO |
101: !$OMP END DO |
102: !$OMP DO |
103: DO k=y_min-2,y_max+2 |
104: !$OMP SIMD |
105: DO j=x_min-2,x_max+2 |
106: xvel0(j,k)=state_xvel(1) |
107: ENDDO |
108: ENDDO |
109: !$OMP END DO |
110: !$OMP DO |
111: DO k=y_min-2,y_max+2 |
112: !$OMP SIMD |
113: DO j=x_min-2,x_max+2 |
114: yvel0(j,k)=state_yvel(1) |
115: ENDDO |
116: ENDDO |
117: !$OMP END DO |
118: |
119: DO state=2,number_of_states |
120: |
121: ! Could the velocity setting be thread unsafe? |
122: x_cent=state_xmin(state) |
123: y_cent=state_ymin(state) |
124: |
125: !$OMP DO PRIVATE(radius,jt,kt) |
126: DO k=y_min-2,y_max+2 |
127: !$OMP SIMD |
128: DO j=x_min-2,x_max+2 |
129: IF(state_geometry(state).EQ.g_rect ) THEN |
130: IF(vertexx(j+1).GE.state_xmin(state).AND.vertexx(j).LT.state_xmax(state)) THEN |
131: IF(vertexy(k+1).GE.state_ymin(state).AND.vertexy(k).LT.state_ymax(state)) THEN |
132: energy0(j,k)=state_energy(state) |
133: density0(j,k)=state_density(state) |
134: DO kt=k,k+1 |
135: DO jt=j,j+1 |
136: xvel0(jt,kt)=state_xvel(state) |
137: yvel0(jt,kt)=state_yvel(state) |
138: ENDDO |
139: ENDDO |
140: ENDIF |
141: ENDIF |
142: ELSEIF(state_geometry(state).EQ.g_circ ) THEN |
143: radius=SQRT((cellx(j)-x_cent)*(cellx(j)-x_cent)+(celly(k)-y_cent)*(celly(k)-y_cent)) |
144: IF(radius.LE.state_radius(state))THEN |
145: energy0(j,k)=state_energy(state) |
146: density0(j,k)=state_density(state) |
147: DO kt=k,k+1 |
148: DO jt=j,j+1 |
149: xvel0(jt,kt)=state_xvel(state) |
150: yvel0(jt,kt)=state_yvel(state) |
151: ENDDO |
152: ENDDO |
153: ENDIF |
154: ELSEIF(state_geometry(state).EQ.g_point) THEN |
155: IF(vertexx(j).EQ.x_cent .AND. vertexy(k).EQ.y_cent) THEN |
156: energy0(j,k)=state_energy(state) |
157: density0(j,k)=state_density(state) |
158: DO kt=k,k+1 |
159: DO jt=j,j+1 |
160: xvel0(jt,kt)=state_xvel(state) |
161: yvel0(jt,kt)=state_yvel(state) |
0x43f960 PUSH %RBP |
0x43f961 MOV %RSP,%RBP |
0x43f964 PUSH %R15 |
0x43f966 PUSH %R14 |
0x43f968 PUSH %R13 |
0x43f96a PUSH %R12 |
0x43f96c MOV %RDI,%R12 |
0x43f96f PUSH %RBX |
0x43f970 AND $-0x40,%RSP |
0x43f974 SUB $0x180,%RSP |
0x43f97b MOV 0x128(%RDI),%RAX |
0x43f982 MOV 0x120(%RDI),%RDX |
0x43f989 MOV 0x118(%RDI),%RCX |
0x43f990 MOV 0x108(%RDI),%RSI |
0x43f997 MOV 0x100(%RDI),%R8 |
0x43f99e MOV 0xf8(%RDI),%R9 |
0x43f9a5 MOV %RAX,0x48(%RSP) |
0x43f9aa MOV 0xf0(%RDI),%R10 |
0x43f9b1 MOV 0xe8(%RDI),%R11 |
0x43f9b8 MOV %RDX,0x140(%RSP) |
0x43f9c0 MOV 0xe0(%RDI),%R13 |
0x43f9c7 MOV 0xd0(%RDI),%RDX |
0x43f9ce MOV %RCX,0x40(%RSP) |
0x43f9d3 MOV 0xd8(%RDI),%RAX |
0x43f9da MOV 0x110(%RDI),%RBX |
0x43f9e1 MOV %RSI,0x38(%RSP) |
0x43f9e6 MOV 0x10(%RDI),%RDI |
0x43f9ea MOV %RDX,0x20(%RSP) |
0x43f9ef MOV %R8,0x118(%RSP) |
0x43f9f7 MOV %R9,0x30(%RSP) |
0x43f9fc MOV %R10,0xf8(%RSP) |
0x43fa04 MOV %R11,0x120(%RSP) |
0x43fa0c MOV %R13,0x100(%RSP) |
0x43fa14 MOV %RAX,0x110(%RSP) |
0x43fa1c MOV %RBX,0x138(%RSP) |
0x43fa24 MOV (%RDI),%EBX |
0x43fa26 CALL 402080 <@plt_start@+0x60> |
0x43fa2b MOV %EAX,%R13D |
0x43fa2e MOV %EAX,0xc8(%RSP) |
0x43fa35 SUB $0x2,%EBX |
0x43fa38 CALL 402180 <@plt_start@+0x160> |
0x43fa3d MOV 0x18(%R12),%RSI |
0x43fa42 MOV %EAX,0xdc(%RSP) |
0x43fa49 MOV %EAX,%ECX |
0x43fa4b MOV (%RSI),%EAX |
0x43fa4d ADD $0x3,%EAX |
0x43fa50 SUB %EBX,%EAX |
0x43fa52 CLTD |
0x43fa53 IDIV %R13D |
0x43fa56 CMP %EDX,%ECX |
0x43fa58 JL 441075 |
0x43fa5e MOV 0xdc(%RSP),%EDI |
0x43fa65 IMUL %EAX,%EDI |
0x43fa68 ADD %EDX,%EDI |
0x43fa6a ADD %EDI,%EAX |
0x43fa6c CMP %EAX,%EDI |
0x43fa6e JGE 43fdb6 |
0x43fa74 ADD %EBX,%EAX |
0x43fa76 ADD %EBX,%EDI |
0x43fa78 MOV 0xf8(%RSP),%RBX |
0x43fa80 MOV (%R12),%R8 |
0x43fa84 MOV 0x8(%R12),%R11 |
0x43fa89 MOV 0x30(%RSP),%RDX |
0x43fa8e MOV %EAX,0x170(%RSP) |
0x43fa95 LEA (,%RBX,8),%RSI |
0x43fa9d MOVSXD (%R8),%R9 |
0x43faa0 MOV 0x70(%R12),%RAX |
0x43faa5 MOV %R14D,0xd0(%RSP) |
0x43faad MOV %RSI,0x160(%RSP) |
0x43fab5 MOVSXD %EDI,%RSI |
0x43fab8 MOV (%R11),%ECX |
0x43fabb IMUL %RBX,%RSI |
0x43fabf MOV %R9,%R13 |
0x43fac2 LEA -0x2(%R9),%R10D |
0x43fac6 MOV %R9,0xe0(%RSP) |
0x43face LEA 0x3(%RCX),%R8D |
0x43fad2 ADD %RDX,%R9 |
0x43fad5 SUB %R13D,%ECX |
0x43fad8 MOV %R10D,0x178(%RSP) |
0x43fae0 MOV %ECX,%R13D |
0x43fae3 MOV %ECX,0x150(%RSP) |
0x43faea MOV 0x48(%R12),%R11 |
0x43faef ADD %RSI,%R9 |
0x43faf2 ADD %RDX,%RSI |
0x43faf5 LEA 0x5(%RCX),%EDX |
0x43faf8 MOV %EDX,%ECX |
0x43fafa MOV %EDX,%EBX |
0x43fafc LEA -0x10(%R11,%R9,8),%R9 |
0x43fb01 SHR $0x3,%ECX |
0x43fb04 AND $-0x8,%EBX |
0x43fb07 SAL $0x6,%RCX |
0x43fb0b MOV %EBX,0x134(%RSP) |
0x43fb12 CMP %R8D,%R10D |
0x43fb15 MOV %RCX,0xe8(%RSP) |
0x43fb1d LEA (%RBX,%R10,1),%ECX |
0x43fb21 MOV %R13D,%EBX |
0x43fb24 LEA 0x5(%R10,%R13,1),%R13D |
0x43fb29 CMOVGE %R10D,%R13D |
0x43fb2d LEA 0x4(%RBX),%R10D |
0x43fb31 AND $0x7,%EDX |
0x43fb34 MOV %ECX,0x128(%RSP) |
0x43fb3b MOV %R10D,0x158(%RSP) |
0x43fb43 XOR %ECX,%ECX |
0x43fb45 MOV %R13D,0x168(%RSP) |
0x43fb4d MOV 0xe8(%RSP),%RBX |
0x43fb55 MOV %ECX,%R14D |
0x43fb58 MOV %R12,0xe8(%RSP) |
0x43fb60 MOV 0xe0(%RSP),%R12 |
0x43fb68 MOV %EDX,0x148(%RSP) |
0x43fb6f MOV $0x1,%EDX |
0x43fb74 KMOVB %EDX,%K1 |
0x43fb78 NOPL (%RAX,%RAX,1) |
(211) 0x43fb80 CMP %R8D,0x178(%RSP) |
(211) 0x43fb88 JGE 43fd53 |
(211) 0x43fb8e CMPL $0x6,0x158(%RSP) |
(211) 0x43fb96 JBE 44105e |
(211) 0x43fb9c LEA -0x40(%RBX),%R10 |
(211) 0x43fba0 LEA (%RBX,%R9,1),%R13 |
(211) 0x43fba4 MOV %R9,%RDX |
(211) 0x43fba7 SHR $0x6,%R10 |
(211) 0x43fbab INC %R10 |
(211) 0x43fbae AND $0x7,%R10D |
(211) 0x43fbb2 JE 43fc4b |
(211) 0x43fbb8 CMP $0x1,%R10 |
(211) 0x43fbbc JE 43fc35 |
(211) 0x43fbbe CMP $0x2,%R10 |
(211) 0x43fbc2 JE 43fc24 |
(211) 0x43fbc4 CMP $0x3,%R10 |
(211) 0x43fbc8 JE 43fc13 |
(211) 0x43fbca CMP $0x4,%R10 |
(211) 0x43fbce JE 43fc02 |
(211) 0x43fbd0 CMP $0x5,%R10 |
(211) 0x43fbd4 JE 43fbf1 |
(211) 0x43fbd6 CMP $0x6,%R10 |
(211) 0x43fbda JNE 44101f |
(211) 0x43fbe0 VBROADCASTSD (%RAX),%ZMM1 |
(211) 0x43fbe6 ADD $0x40,%RDX |
(211) 0x43fbea VMOVUPD %ZMM1,-0x40(%RDX) |
(211) 0x43fbf1 VBROADCASTSD (%RAX),%ZMM2 |
(211) 0x43fbf7 ADD $0x40,%RDX |
(211) 0x43fbfb VMOVUPD %ZMM2,-0x40(%RDX) |
(211) 0x43fc02 VBROADCASTSD (%RAX),%ZMM3 |
(211) 0x43fc08 ADD $0x40,%RDX |
(211) 0x43fc0c VMOVUPD %ZMM3,-0x40(%RDX) |
(211) 0x43fc13 VBROADCASTSD (%RAX),%ZMM4 |
(211) 0x43fc19 ADD $0x40,%RDX |
(211) 0x43fc1d VMOVUPD %ZMM4,-0x40(%RDX) |
(211) 0x43fc24 VBROADCASTSD (%RAX),%ZMM5 |
(211) 0x43fc2a ADD $0x40,%RDX |
(211) 0x43fc2e VMOVUPD %ZMM5,-0x40(%RDX) |
(211) 0x43fc35 VBROADCASTSD (%RAX),%ZMM6 |
(211) 0x43fc3b ADD $0x40,%RDX |
(211) 0x43fc3f VMOVUPD %ZMM6,-0x40(%RDX) |
(211) 0x43fc46 CMP %R13,%RDX |
(211) 0x43fc49 JE 43fcbf |
(212) 0x43fc4b VBROADCASTSD (%RAX),%ZMM7 |
(212) 0x43fc51 ADD $0x200,%RDX |
(212) 0x43fc58 VMOVUPD %ZMM7,-0x200(%RDX) |
(212) 0x43fc5f VBROADCASTSD (%RAX),%ZMM8 |
(212) 0x43fc65 VMOVUPD %ZMM8,-0x1c0(%RDX) |
(212) 0x43fc6c VBROADCASTSD (%RAX),%ZMM9 |
(212) 0x43fc72 VMOVUPD %ZMM9,-0x180(%RDX) |
(212) 0x43fc79 VBROADCASTSD (%RAX),%ZMM10 |
(212) 0x43fc7f VMOVUPD %ZMM10,-0x140(%RDX) |
(212) 0x43fc86 VBROADCASTSD (%RAX),%ZMM11 |
(212) 0x43fc8c VMOVUPD %ZMM11,-0x100(%RDX) |
(212) 0x43fc93 VBROADCASTSD (%RAX),%ZMM12 |
(212) 0x43fc99 VMOVUPD %ZMM12,-0xc0(%RDX) |
(212) 0x43fca0 VBROADCASTSD (%RAX),%ZMM13 |
(212) 0x43fca6 VMOVUPD %ZMM13,-0x80(%RDX) |
(212) 0x43fcad VBROADCASTSD (%RAX),%ZMM14 |
(212) 0x43fcb3 VMOVUPD %ZMM14,-0x40(%RDX) |
(212) 0x43fcba CMP %R13,%RDX |
(212) 0x43fcbd JNE 43fc4b |
(211) 0x43fcbf MOV 0x148(%RSP),%ECX |
(211) 0x43fcc6 TEST %ECX,%ECX |
(211) 0x43fcc8 JE 43fd53 |
(211) 0x43fcce MOV 0x134(%RSP),%ECX |
(211) 0x43fcd5 MOV 0x128(%RSP),%EDX |
(211) 0x43fcdc MOV 0x150(%RSP),%R13D |
(211) 0x43fce4 SUB %ECX,%R13D |
(211) 0x43fce7 LEA 0x5(%R13),%R10D |
(211) 0x43fceb ADD $0x4,%R13D |
(211) 0x43fcef CMP $0x2,%R13D |
(211) 0x43fcf3 JBE 43fd16 |
(211) 0x43fcf5 VBROADCASTSD (%RAX),%YMM15 |
(211) 0x43fcfa LEA (%R12,%RSI,1),%R13 |
(211) 0x43fcfe ADD %R13,%RCX |
(211) 0x43fd01 VMOVUPD %YMM15,-0x10(%R11,%RCX,8) |
(211) 0x43fd08 MOV %R10D,%ECX |
(211) 0x43fd0b AND $-0x4,%ECX |
(211) 0x43fd0e ADD %ECX,%EDX |
(211) 0x43fd10 AND $0x3,%R10D |
(211) 0x43fd14 JE 43fd53 |
(211) 0x43fd16 VMOVSD (%RAX),%XMM0 |
(211) 0x43fd1a MOVSXD %EDX,%R10 |
(211) 0x43fd1d LEA 0x1(%RDX),%R13D |
(211) 0x43fd21 ADD %RSI,%R10 |
(211) 0x43fd24 VMOVSD %XMM0,(%R11,%R10,8) |
(211) 0x43fd2a CMP %R13D,%R8D |
(211) 0x43fd2d JLE 43fd53 |
(211) 0x43fd2f MOVSXD %R13D,%RCX |
(211) 0x43fd32 ADD $0x2,%EDX |
(211) 0x43fd35 ADD %RSI,%RCX |
(211) 0x43fd38 VMOVSD %XMM0,(%R11,%RCX,8) |
(211) 0x43fd3e CMP %EDX,%R8D |
(211) 0x43fd41 JLE 43fd53 |
(211) 0x43fd43 VMOVSD (%RAX),%XMM1 |
(211) 0x43fd47 MOVSXD %EDX,%RDX |
(211) 0x43fd4a ADD %RSI,%RDX |
(211) 0x43fd4d VMOVSD %XMM1,(%R11,%RDX,8) |
(211) 0x43fd53 MOV 0x168(%RSP),%R10D |
(211) 0x43fd5b MOV 0x160(%RSP),%RCX |
(211) 0x43fd63 KMOVB %K1,%R13D |
(211) 0x43fd67 MOV 0xf8(%RSP),%RDX |
(211) 0x43fd6f CMP %R10D,%R8D |
(211) 0x43fd72 CMOVE %R8D,%R15D |
(211) 0x43fd76 CMOVE %R13D,%R14D |
(211) 0x43fd7a INC %EDI |
(211) 0x43fd7c ADD %RCX,%R9 |
(211) 0x43fd7f ADD %RDX,%RSI |
(211) 0x43fd82 CMP %EDI,0x170(%RSP) |
(211) 0x43fd89 JG 43fb80 |
0x43fd8f MOV %R14D,%EDI |
0x43fd92 MOV 0xe8(%RSP),%R12 |
0x43fd9a MOV 0xd0(%RSP),%R14D |
0x43fda2 TEST %DIL,%DIL |
0x43fda5 JE 4410a0 |
0x43fdab MOV %R15D,0x140(%R12) |
0x43fdb3 VZEROUPPER |
0x43fdb6 CALL 402220 <@plt_start@+0x200> |
0x43fdbb MOV 0x10(%R12),%R15 |
0x43fdc0 MOV 0x18(%R12),%RAX |
0x43fdc5 MOV (%R15),%R8D |
0x43fdc8 MOV (%RAX),%EAX |
0x43fdca SUB $0x2,%R8D |
0x43fdce ADD $0x3,%EAX |
0x43fdd1 SUB %R8D,%EAX |
0x43fdd4 CLTD |
0x43fdd5 IDIVL 0xc8(%RSP) |
0x43fddc CMP %EDX,0xdc(%RSP) |
0x43fde3 JL 44107e |
0x43fde9 MOV 0xdc(%RSP),%EDI |
0x43fdf0 IMUL %EAX,%EDI |
0x43fdf3 ADD %EDX,%EDI |
0x43fdf5 ADD %EDI,%EAX |
0x43fdf7 CMP %EAX,%EDI |
0x43fdf9 JGE 440117 |
0x43fdff MOV (%R12),%R11 |
0x43fe03 MOV 0x8(%R12),%RSI |
0x43fe08 ADD %R8D,%EDI |
0x43fe0b ADD %R8D,%EAX |
0x43fe0e MOV 0x100(%RSP),%RBX |
0x43fe16 MOV 0x120(%RSP),%RDX |
0x43fe1e MOV %EAX,0x170(%RSP) |
0x43fe25 MOVSXD (%R11),%R9 |
0x43fe28 MOV (%RSI),%ECX |
0x43fe2a MOVSXD %EDI,%RSI |
0x43fe2d MOV %R12,0xe8(%RSP) |
0x43fe35 IMUL %RBX,%RSI |
0x43fe39 LEA (,%RBX,8),%R10 |
0x43fe41 MOV 0x40(%R12),%R11 |
0x43fe46 MOV 0x68(%R12),%RAX |
0x43fe4b MOV %R9,%R13 |
0x43fe4e LEA -0x2(%R9),%R15D |
0x43fe52 LEA 0x3(%RCX),%R8D |
0x43fe56 MOV %R9,%RBX |
0x43fe59 SUB %R13D,%ECX |
0x43fe5c LEA (%R9,%RDX,1),%R9 |
0x43fe60 MOV %R10,0x160(%RSP) |
0x43fe68 ADD %RSI,%R9 |
0x43fe6b ADD %RDX,%RSI |
0x43fe6e LEA 0x5(%RCX),%EDX |
0x43fe71 MOV %ECX,%R10D |
0x43fe74 MOV %ECX,0x150(%RSP) |
0x43fe7b MOV %EDX,%ECX |
0x43fe7d MOV %EDX,%R13D |
0x43fe80 LEA -0x10(%R11,%R9,8),%R9 |
0x43fe85 AND $-0x8,%ECX |
0x43fe88 SHR $0x3,%R13D |
0x43fe8c MOV %R15D,0x178(%RSP) |
0x43fe94 MOV %ECX,0x134(%RSP) |
0x43fe9b ADD %R15D,%ECX |
0x43fe9e SAL $0x6,%R13 |
0x43fea2 CMP %R8D,%R15D |
0x43fea5 MOV %ECX,0x128(%RSP) |
0x43feac LEA 0x5(%R15,%R10,1),%ECX |
0x43feb1 LEA 0x4(%R10),%R10D |
0x43feb5 CMOVGE %R15D,%ECX |
0x43feb9 MOV %R10D,0x158(%RSP) |
0x43fec1 AND $0x7,%EDX |
0x43fec4 XOR %R15D,%R15D |
0x43fec7 MOV %EDX,0x148(%RSP) |
0x43fece MOV %R15D,%R12D |
0x43fed1 MOV $0x1,%EDX |
0x43fed6 MOV %ECX,0x168(%RSP) |
0x43fedd KMOVB %EDX,%K0 |
0x43fee1 NOPL (%RAX) |
(209) 0x43fee8 CMP %R8D,0x178(%RSP) |
(209) 0x43fef0 JGE 4400bc |
(209) 0x43fef6 CMPL $0x6,0x158(%RSP) |
(209) 0x43fefe JBE 441034 |
(209) 0x43ff04 LEA -0x40(%R13),%R10 |
(209) 0x43ff08 LEA (%R13,%R9,1),%R15 |
(209) 0x43ff0d MOV %R9,%RDX |
(209) 0x43ff10 SHR $0x6,%R10 |
(209) 0x43ff14 INC %R10 |
(209) 0x43ff17 AND $0x7,%R10D |
(209) 0x43ff1b JE 43ffb4 |
(209) 0x43ff21 CMP $0x1,%R10 |
(209) 0x43ff25 JE 43ff9e |
(209) 0x43ff27 CMP $0x2,%R10 |
(209) 0x43ff2b JE 43ff8d |
(209) 0x43ff2d CMP $0x3,%R10 |
(209) 0x43ff31 JE 43ff7c |
(209) 0x43ff33 CMP $0x4,%R10 |
(209) 0x43ff37 JE 43ff6b |
(209) 0x43ff39 CMP $0x5,%R10 |
(209) 0x43ff3d JE 43ff5a |
(209) 0x43ff3f CMP $0x6,%R10 |
(209) 0x43ff43 JNE 44100a |
(209) 0x43ff49 VBROADCASTSD (%RAX),%ZMM3 |
(209) 0x43ff4f ADD $0x40,%RDX |
(209) 0x43ff53 VMOVUPD %ZMM3,-0x40(%RDX) |
(209) 0x43ff5a VBROADCASTSD (%RAX),%ZMM4 |
(209) 0x43ff60 ADD $0x40,%RDX |
(209) 0x43ff64 VMOVUPD %ZMM4,-0x40(%RDX) |
(209) 0x43ff6b VBROADCASTSD (%RAX),%ZMM5 |
(209) 0x43ff71 ADD $0x40,%RDX |
(209) 0x43ff75 VMOVUPD %ZMM5,-0x40(%RDX) |
(209) 0x43ff7c VBROADCASTSD (%RAX),%ZMM6 |
(209) 0x43ff82 ADD $0x40,%RDX |
(209) 0x43ff86 VMOVUPD %ZMM6,-0x40(%RDX) |
(209) 0x43ff8d VBROADCASTSD (%RAX),%ZMM7 |
(209) 0x43ff93 ADD $0x40,%RDX |
(209) 0x43ff97 VMOVUPD %ZMM7,-0x40(%RDX) |
(209) 0x43ff9e VBROADCASTSD (%RAX),%ZMM8 |
(209) 0x43ffa4 ADD $0x40,%RDX |
(209) 0x43ffa8 VMOVUPD %ZMM8,-0x40(%RDX) |
(209) 0x43ffaf CMP %R15,%RDX |
(209) 0x43ffb2 JE 440028 |
(210) 0x43ffb4 VBROADCASTSD (%RAX),%ZMM9 |
(210) 0x43ffba ADD $0x200,%RDX |
(210) 0x43ffc1 VMOVUPD %ZMM9,-0x200(%RDX) |
(210) 0x43ffc8 VBROADCASTSD (%RAX),%ZMM10 |
(210) 0x43ffce VMOVUPD %ZMM10,-0x1c0(%RDX) |
(210) 0x43ffd5 VBROADCASTSD (%RAX),%ZMM11 |
(210) 0x43ffdb VMOVUPD %ZMM11,-0x180(%RDX) |
(210) 0x43ffe2 VBROADCASTSD (%RAX),%ZMM12 |
(210) 0x43ffe8 VMOVUPD %ZMM12,-0x140(%RDX) |
(210) 0x43ffef VBROADCASTSD (%RAX),%ZMM13 |
(210) 0x43fff5 VMOVUPD %ZMM13,-0x100(%RDX) |
(210) 0x43fffc VBROADCASTSD (%RAX),%ZMM14 |
(210) 0x440002 VMOVUPD %ZMM14,-0xc0(%RDX) |
(210) 0x440009 VBROADCASTSD (%RAX),%ZMM15 |
(210) 0x44000f VMOVUPD %ZMM15,-0x80(%RDX) |
(210) 0x440016 VBROADCASTSD (%RAX),%ZMM0 |
(210) 0x44001c VMOVUPD %ZMM0,-0x40(%RDX) |
(210) 0x440023 CMP %R15,%RDX |
(210) 0x440026 JNE 43ffb4 |
(209) 0x440028 MOV 0x148(%RSP),%ECX |
(209) 0x44002f TEST %ECX,%ECX |
(209) 0x440031 JE 4400bc |
(209) 0x440037 MOV 0x134(%RSP),%ECX |
(209) 0x44003e MOV 0x128(%RSP),%EDX |
(209) 0x440045 MOV 0x150(%RSP),%R15D |
(209) 0x44004d SUB %ECX,%R15D |
(209) 0x440050 LEA 0x5(%R15),%R10D |
(209) 0x440054 ADD $0x4,%R15D |
(209) 0x440058 CMP $0x2,%R15D |
(209) 0x44005c JBE 44007f |
(209) 0x44005e VBROADCASTSD (%RAX),%YMM1 |
(209) 0x440063 LEA (%RBX,%RSI,1),%R15 |
(209) 0x440067 ADD %R15,%RCX |
(209) 0x44006a VMOVUPD %YMM1,-0x10(%R11,%RCX,8) |
(209) 0x440071 MOV %R10D,%ECX |
(209) 0x440074 AND $-0x4,%ECX |
(209) 0x440077 ADD %ECX,%EDX |
(209) 0x440079 AND $0x3,%R10D |
(209) 0x44007d JE 4400bc |
(209) 0x44007f VMOVSD (%RAX),%XMM2 |
(209) 0x440083 MOVSXD %EDX,%R10 |
(209) 0x440086 LEA 0x1(%RDX),%R15D |
(209) 0x44008a ADD %RSI,%R10 |
(209) 0x44008d VMOVSD %XMM2,(%R11,%R10,8) |
(209) 0x440093 CMP %R15D,%R8D |
(209) 0x440096 JLE 4400bc |
(209) 0x440098 MOVSXD %R15D,%RCX |
(209) 0x44009b ADD $0x2,%EDX |
(209) 0x44009e ADD %RSI,%RCX |
(209) 0x4400a1 VMOVSD %XMM2,(%R11,%RCX,8) |
(209) 0x4400a7 CMP %EDX,%R8D |
(209) 0x4400aa JLE 4400bc |
(209) 0x4400ac VMOVSD (%RAX),%XMM3 |
(209) 0x4400b0 MOVSXD %EDX,%RDX |
(209) 0x4400b3 ADD %RSI,%RDX |
(209) 0x4400b6 VMOVSD %XMM3,(%R11,%RDX,8) |
(209) 0x4400bc MOV 0x168(%RSP),%R10D |
(209) 0x4400c4 MOV 0x160(%RSP),%RCX |
(209) 0x4400cc KMOVB %K0,%R15D |
(209) 0x4400d0 MOV 0x100(%RSP),%RDX |
(209) 0x4400d8 CMP %R10D,%R8D |
(209) 0x4400db CMOVE %R8D,%R14D |
(209) 0x4400df CMOVE %R15D,%R12D |
(209) 0x4400e3 INC %EDI |
(209) 0x4400e5 ADD %RCX,%R9 |
(209) 0x4400e8 ADD %RDX,%RSI |
(209) 0x4400eb CMP %EDI,0x170(%RSP) |
(209) 0x4400f2 JG 43fee8 |
0x4400f8 MOV %R12D,%EDI |
0x4400fb MOV 0xe8(%RSP),%R12 |
0x440103 TEST %DIL,%DIL |
0x440106 JE 4410a8 |
0x44010c MOV %R14D,0x140(%R12) |
0x440114 VZEROUPPER |
0x440117 CALL 402220 <@plt_start@+0x200> |
0x44011c MOV 0x10(%R12),%R14 |
0x440121 MOV 0x18(%R12),%RAX |
0x440126 MOV (%R14),%R8D |
0x440129 MOV (%RAX),%EAX |
0x44012b SUB $0x2,%R8D |
0x44012f ADD $0x3,%EAX |
0x440132 SUB %R8D,%EAX |
0x440135 CLTD |
0x440136 IDIVL 0xc8(%RSP) |
0x44013d CMP %EDX,0xdc(%RSP) |
0x440144 JL 44106c |
0x44014a MOV 0xdc(%RSP),%EDI |
0x440151 IMUL %EAX,%EDI |
0x440154 ADD %EDX,%EDI |
0x440156 ADD %EDI,%EAX |
0x440158 CMP %EAX,%EDI |
0x44015a JGE 44047e |
0x440160 MOV 0x8(%R12),%RSI |
0x440165 MOV (%R12),%R11 |
0x440169 ADD %R8D,%EDI |
0x44016c ADD %R8D,%EAX |
0x44016f MOV 0x138(%RSP),%R9 |
0x440177 MOV 0x40(%RSP),%R14 |
0x44017c MOV %EAX,0x170(%RSP) |
0x440183 MOV (%RSI),%ECX |
0x440185 MOVSXD %EDI,%RSI |
0x440188 MOVSXD (%R11),%R13 |
0x44018b MOV %R12,0xe8(%RSP) |
0x440193 IMUL %R9,%RSI |
0x440197 MOV 0x50(%R12),%R11 |
0x44019c LEA (,%R9,8),%R15 |
0x4401a4 MOV 0x78(%R12),%RAX |
0x4401a9 LEA (%R13,%R14,1),%RDX |
0x4401ae LEA 0x3(%RCX),%R8D |
0x4401b2 SUB %R13D,%ECX |
0x4401b5 MOV %R15,0x160(%RSP) |
0x4401bd LEA -0x2(%R13),%EBX |
0x4401c1 MOV %ECX,%R10D |
0x4401c4 MOV %ECX,0x150(%RSP) |
0x4401cb ADD %RSI,%RDX |
0x4401ce ADD %R14,%RSI |
0x4401d1 MOV %EBX,0x178(%RSP) |
0x4401d8 LEA -0x10(%R11,%RDX,8),%R9 |
0x4401dd LEA 0x5(%RCX),%EDX |
0x4401e0 MOV %EDX,%R14D |
0x4401e3 MOV %EDX,%R15D |
0x4401e6 LEA 0x5(%RBX,%RCX,1),%ECX |
0x4401ea AND $-0x8,%R15D |
0x4401ee SHR $0x3,%R14D |
0x4401f2 MOV %R15D,0x134(%RSP) |
0x4401fa SAL $0x6,%R14 |
0x4401fe ADD %EBX,%R15D |
0x440201 CMP %R8D,%EBX |
0x440204 CMOVGE %EBX,%ECX |
0x440207 AND $0x7,%EDX |
0x44020a LEA 0x4(%R10),%EBX |
0x44020e MOV %R15D,0x128(%RSP) |
0x440216 MOV %EDX,0x148(%RSP) |
0x44021d XOR %R15D,%R15D |
0x440220 MOV $0x1,%R10D |
0x440226 MOV %ECX,0x168(%RSP) |
0x44022d MOV %R15D,%R12D |
0x440230 KMOVB %R10D,%K2 |
0x440235 MOV %EBX,0x158(%RSP) |
0x44023c MOV 0xf0(%RSP),%EBX |
0x440243 NOPL (%RAX,%RAX,1) |
(207) 0x440248 CMP %R8D,0x178(%RSP) |
(207) 0x440250 JGE 44041c |
(207) 0x440256 CMPL $0x6,0x158(%RSP) |
(207) 0x44025e JBE 441050 |
(207) 0x440264 LEA -0x40(%R14),%R10 |
(207) 0x440268 LEA (%R14,%R9,1),%R15 |
(207) 0x44026c MOV %R9,%RDX |
(207) 0x44026f SHR $0x6,%R10 |
(207) 0x440273 INC %R10 |
(207) 0x440276 AND $0x7,%R10D |
(207) 0x44027a JE 440313 |
(207) 0x440280 CMP $0x1,%R10 |
(207) 0x440284 JE 4402fd |
(207) 0x440286 CMP $0x2,%R10 |
(207) 0x44028a JE 4402ec |
(207) 0x44028c CMP $0x3,%R10 |
(207) 0x440290 JE 4402db |
(207) 0x440292 CMP $0x4,%R10 |
(207) 0x440296 JE 4402ca |
(207) 0x440298 CMP $0x5,%R10 |
(207) 0x44029c JE 4402b9 |
(207) 0x44029e CMP $0x6,%R10 |
(207) 0x4402a2 JNE 440ff5 |
(207) 0x4402a8 VBROADCASTSD (%RAX),%ZMM5 |
(207) 0x4402ae ADD $0x40,%RDX |
(207) 0x4402b2 VMOVUPD %ZMM5,-0x40(%RDX) |
(207) 0x4402b9 VBROADCASTSD (%RAX),%ZMM6 |
(207) 0x4402bf ADD $0x40,%RDX |
(207) 0x4402c3 VMOVUPD %ZMM6,-0x40(%RDX) |
(207) 0x4402ca VBROADCASTSD (%RAX),%ZMM7 |
(207) 0x4402d0 ADD $0x40,%RDX |
(207) 0x4402d4 VMOVUPD %ZMM7,-0x40(%RDX) |
(207) 0x4402db VBROADCASTSD (%RAX),%ZMM8 |
(207) 0x4402e1 ADD $0x40,%RDX |
(207) 0x4402e5 VMOVUPD %ZMM8,-0x40(%RDX) |
(207) 0x4402ec VBROADCASTSD (%RAX),%ZMM9 |
(207) 0x4402f2 ADD $0x40,%RDX |
(207) 0x4402f6 VMOVUPD %ZMM9,-0x40(%RDX) |
(207) 0x4402fd VBROADCASTSD (%RAX),%ZMM10 |
(207) 0x440303 ADD $0x40,%RDX |
(207) 0x440307 VMOVUPD %ZMM10,-0x40(%RDX) |
(207) 0x44030e CMP %R15,%RDX |
(207) 0x440311 JE 440387 |
(208) 0x440313 VBROADCASTSD (%RAX),%ZMM11 |
(208) 0x440319 ADD $0x200,%RDX |
(208) 0x440320 VMOVUPD %ZMM11,-0x200(%RDX) |
(208) 0x440327 VBROADCASTSD (%RAX),%ZMM12 |
(208) 0x44032d VMOVUPD %ZMM12,-0x1c0(%RDX) |
(208) 0x440334 VBROADCASTSD (%RAX),%ZMM13 |
(208) 0x44033a VMOVUPD %ZMM13,-0x180(%RDX) |
(208) 0x440341 VBROADCASTSD (%RAX),%ZMM14 |
(208) 0x440347 VMOVUPD %ZMM14,-0x140(%RDX) |
(208) 0x44034e VBROADCASTSD (%RAX),%ZMM15 |
(208) 0x440354 VMOVUPD %ZMM15,-0x100(%RDX) |
(208) 0x44035b VBROADCASTSD (%RAX),%ZMM0 |
(208) 0x440361 VMOVUPD %ZMM0,-0xc0(%RDX) |
(208) 0x440368 VBROADCASTSD (%RAX),%ZMM1 |
(208) 0x44036e VMOVUPD %ZMM1,-0x80(%RDX) |
(208) 0x440375 VBROADCASTSD (%RAX),%ZMM2 |
(208) 0x44037b VMOVUPD %ZMM2,-0x40(%RDX) |
(208) 0x440382 CMP %R15,%RDX |
(208) 0x440385 JNE 440313 |
(207) 0x440387 MOV 0x148(%RSP),%ECX |
(207) 0x44038e TEST %ECX,%ECX |
(207) 0x440390 JE 44041c |
(207) 0x440396 MOV 0x134(%RSP),%ECX |
(207) 0x44039d MOV 0x128(%RSP),%EDX |
(207) 0x4403a4 MOV 0x150(%RSP),%R15D |
(207) 0x4403ac SUB %ECX,%R15D |
(207) 0x4403af LEA 0x5(%R15),%R10D |
(207) 0x4403b3 ADD $0x4,%R15D |
(207) 0x4403b7 CMP $0x2,%R15D |
(207) 0x4403bb JBE 4403df |
(207) 0x4403bd VBROADCASTSD (%RAX),%YMM3 |
(207) 0x4403c2 LEA (%R13,%RSI,1),%R15 |
(207) 0x4403c7 ADD %R15,%RCX |
(207) 0x4403ca VMOVUPD %YMM3,-0x10(%R11,%RCX,8) |
(207) 0x4403d1 MOV %R10D,%ECX |
(207) 0x4403d4 AND $-0x4,%ECX |
(207) 0x4403d7 ADD %ECX,%EDX |
(207) 0x4403d9 AND $0x3,%R10D |
(207) 0x4403dd JE 44041c |
(207) 0x4403df VMOVSD (%RAX),%XMM4 |
(207) 0x4403e3 MOVSXD %EDX,%R10 |
(207) 0x4403e6 LEA 0x1(%RDX),%R15D |
(207) 0x4403ea ADD %RSI,%R10 |
(207) 0x4403ed VMOVSD %XMM4,(%R11,%R10,8) |
(207) 0x4403f3 CMP %R15D,%R8D |
(207) 0x4403f6 JLE 44041c |
(207) 0x4403f8 MOVSXD %R15D,%RCX |
(207) 0x4403fb ADD $0x2,%EDX |
(207) 0x4403fe ADD %RSI,%RCX |
(207) 0x440401 VMOVSD %XMM4,(%R11,%RCX,8) |
(207) 0x440407 CMP %EDX,%R8D |
(207) 0x44040a JLE 44041c |
(207) 0x44040c VMOVSD (%RAX),%XMM5 |
(207) 0x440410 MOVSXD %EDX,%RDX |
(207) 0x440413 ADD %RSI,%RDX |
(207) 0x440416 VMOVSD %XMM5,(%R11,%RDX,8) |
(207) 0x44041c MOV 0x168(%RSP),%R10D |
(207) 0x440424 MOV 0x160(%RSP),%RCX |
(207) 0x44042c KMOVB %K2,%R15D |
(207) 0x440430 MOV 0x138(%RSP),%RDX |
(207) 0x440438 CMP %R10D,%R8D |
(207) 0x44043b CMOVE %R8D,%EBX |
(207) 0x44043f CMOVE %R15D,%R12D |
(207) 0x440443 INC %EDI |
(207) 0x440445 ADD %RCX,%R9 |
(207) 0x440448 ADD %RDX,%RSI |
(207) 0x44044b CMP %EDI,0x170(%RSP) |
(207) 0x440452 JG 440248 |
0x440458 MOV %R12D,%EDI |
0x44045b MOV %EBX,0xf0(%RSP) |
0x440462 MOV 0xe8(%RSP),%R12 |
0x44046a TEST %DIL,%DIL |
0x44046d JE 441098 |
0x440473 MOV %EBX,0x140(%R12) |
0x44047b VZEROUPPER |
0x44047e CALL 402220 <@plt_start@+0x200> |
0x440483 MOV 0x10(%R12),%R13 |
0x440488 MOV 0x18(%R12),%RAX |
0x44048d MOV (%R13),%R8D |
0x440491 MOV (%RAX),%EAX |
0x440493 SUB $0x2,%R8D |
0x440497 ADD $0x3,%EAX |
0x44049a SUB %R8D,%EAX |
0x44049d CLTD |
0x44049e IDIVL 0xc8(%RSP) |
0x4404a5 CMP %EDX,0xdc(%RSP) |
0x4404ac JL 441087 |
0x4404b2 MOV 0xdc(%RSP),%EDI |
0x4404b9 IMUL %EAX,%EDI |
0x4404bc ADD %EDX,%EDI |
0x4404be ADD %EDI,%EAX |
0x4404c0 CMP %EAX,%EDI |
0x4404c2 JGE 4407ea |
0x4404c8 MOV 0x8(%R12),%RSI |
0x4404cd MOV (%R12),%R11 |
0x4404d1 ADD %R8D,%EDI |
0x4404d4 ADD %R8D,%EAX |
0x4404d7 MOV 0x140(%RSP),%R9 |
0x4404df MOV 0x48(%RSP),%RBX |
0x4404e4 MOV %EAX,0x170(%RSP) |
0x4404eb MOV (%RSI),%R15D |
0x4404ee MOVSXD %EDI,%RSI |
0x4404f1 MOVSXD (%R11),%R10 |
0x4404f4 MOV %R12,0xf0(%RSP) |
0x4404fc IMUL %R9,%RSI |
0x440500 MOV 0x58(%R12),%R11 |
0x440505 LEA (,%R9,8),%RCX |
0x44050d MOV 0x80(%R12),%RAX |
0x440515 LEA (%R10,%RBX,1),%RDX |
0x440519 LEA 0x3(%R15),%R8D |
0x44051d SUB %R10D,%R15D |
0x440520 MOV %RCX,0x160(%RSP) |
0x440528 MOV %R15D,0x150(%RSP) |
0x440530 LEA -0x2(%R10),%R13D |
0x440534 MOV %R10,%R12 |
0x440537 ADD %RSI,%RDX |
0x44053a ADD %RBX,%RSI |
0x44053d MOV %R15D,%EBX |
0x440540 MOV %R13D,0x178(%RSP) |
0x440548 LEA -0x10(%R11,%RDX,8),%R9 |
0x44054d LEA 0x5(%R15),%EDX |
0x440551 MOV %EDX,%R14D |
0x440554 MOV %EDX,%R15D |
0x440557 LEA 0x5(%R13,%RBX,1),%ECX |
0x44055c AND $-0x8,%R15D |
0x440560 SHR $0x3,%R14D |
0x440564 MOV %R15D,0x128(%RSP) |
0x44056c SAL $0x6,%R14 |
0x440570 ADD %R13D,%R15D |
0x440573 CMP %R8D,%R13D |
0x440576 CMOVGE %R13D,%ECX |
0x44057a ADD $0x4,%EBX |
0x44057d AND $0x7,%EDX |
0x440580 MOV %R15D,0x134(%RSP) |
0x440588 MOV %EBX,0x158(%RSP) |
0x44058f MOV $0x1,%EBX |
0x440594 XOR %R15D,%R15D |
0x440597 MOV %ECX,0x168(%RSP) |
0x44059e KMOVB %EBX,%K3 |
0x4405a2 MOV 0x108(%RSP),%EBX |
0x4405a9 MOV %R15D,%R13D |
0x4405ac MOV %EDX,0x148(%RSP) |
0x4405b3 NOPL (%RAX,%RAX,1) |
(205) 0x4405b8 CMP %R8D,0x178(%RSP) |
(205) 0x4405c0 JGE 44078b |
(205) 0x4405c6 CMPL $0x6,0x158(%RSP) |
(205) 0x4405ce JBE 441042 |
(205) 0x4405d4 LEA -0x40(%R14),%R15 |
(205) 0x4405d8 LEA (%R14,%R9,1),%R10 |
(205) 0x4405dc MOV %R9,%RDX |
(205) 0x4405df SHR $0x6,%R15 |
(205) 0x4405e3 INC %R15 |
(205) 0x4405e6 AND $0x7,%R15D |
(205) 0x4405ea JE 440683 |
(205) 0x4405f0 CMP $0x1,%R15 |
(205) 0x4405f4 JE 44066d |
(205) 0x4405f6 CMP $0x2,%R15 |
(205) 0x4405fa JE 44065c |
(205) 0x4405fc CMP $0x3,%R15 |
(205) 0x440600 JE 44064b |
(205) 0x440602 CMP $0x4,%R15 |
(205) 0x440606 JE 44063a |
(205) 0x440608 CMP $0x5,%R15 |
(205) 0x44060c JE 440629 |
(205) 0x44060e CMP $0x6,%R15 |
(205) 0x440612 JNE 440fe0 |
(205) 0x440618 VBROADCASTSD (%RAX),%ZMM7 |
(205) 0x44061e ADD $0x40,%RDX |
(205) 0x440622 VMOVUPD %ZMM7,-0x40(%RDX) |
(205) 0x440629 VBROADCASTSD (%RAX),%ZMM8 |
(205) 0x44062f ADD $0x40,%RDX |
(205) 0x440633 VMOVUPD %ZMM8,-0x40(%RDX) |
(205) 0x44063a VBROADCASTSD (%RAX),%ZMM9 |
(205) 0x440640 ADD $0x40,%RDX |
(205) 0x440644 VMOVUPD %ZMM9,-0x40(%RDX) |
(205) 0x44064b VBROADCASTSD (%RAX),%ZMM10 |
(205) 0x440651 ADD $0x40,%RDX |
(205) 0x440655 VMOVUPD %ZMM10,-0x40(%RDX) |
(205) 0x44065c VBROADCASTSD (%RAX),%ZMM11 |
(205) 0x440662 ADD $0x40,%RDX |
(205) 0x440666 VMOVUPD %ZMM11,-0x40(%RDX) |
(205) 0x44066d VBROADCASTSD (%RAX),%ZMM12 |
(205) 0x440673 ADD $0x40,%RDX |
(205) 0x440677 VMOVUPD %ZMM12,-0x40(%RDX) |
(205) 0x44067e CMP %R10,%RDX |
(205) 0x440681 JE 4406f7 |
(206) 0x440683 VBROADCASTSD (%RAX),%ZMM13 |
(206) 0x440689 ADD $0x200,%RDX |
(206) 0x440690 VMOVUPD %ZMM13,-0x200(%RDX) |
(206) 0x440697 VBROADCASTSD (%RAX),%ZMM14 |
(206) 0x44069d VMOVUPD %ZMM14,-0x1c0(%RDX) |
(206) 0x4406a4 VBROADCASTSD (%RAX),%ZMM15 |
(206) 0x4406aa VMOVUPD %ZMM15,-0x180(%RDX) |
(206) 0x4406b1 VBROADCASTSD (%RAX),%ZMM0 |
(206) 0x4406b7 VMOVUPD %ZMM0,-0x140(%RDX) |
(206) 0x4406be VBROADCASTSD (%RAX),%ZMM1 |
(206) 0x4406c4 VMOVUPD %ZMM1,-0x100(%RDX) |
(206) 0x4406cb VBROADCASTSD (%RAX),%ZMM2 |
(206) 0x4406d1 VMOVUPD %ZMM2,-0xc0(%RDX) |
(206) 0x4406d8 VBROADCASTSD (%RAX),%ZMM3 |
(206) 0x4406de VMOVUPD %ZMM3,-0x80(%RDX) |
(206) 0x4406e5 VBROADCASTSD (%RAX),%ZMM4 |
(206) 0x4406eb VMOVUPD %ZMM4,-0x40(%RDX) |
(206) 0x4406f2 CMP %R10,%RDX |
(206) 0x4406f5 JNE 440683 |
(205) 0x4406f7 MOV 0x148(%RSP),%ECX |
(205) 0x4406fe TEST %ECX,%ECX |
(205) 0x440700 JE 44078b |
(205) 0x440706 MOV 0x128(%RSP),%ECX |
(205) 0x44070d MOV 0x134(%RSP),%EDX |
(205) 0x440714 MOV 0x150(%RSP),%R15D |
(205) 0x44071c SUB %ECX,%R15D |
(205) 0x44071f LEA 0x5(%R15),%R10D |
(205) 0x440723 ADD $0x4,%R15D |
(205) 0x440727 CMP $0x2,%R15D |
(205) 0x44072b JBE 44074e |
(205) 0x44072d VBROADCASTSD (%RAX),%YMM5 |
(205) 0x440732 LEA (%R12,%RSI,1),%R15 |
(205) 0x440736 ADD %R15,%RCX |
(205) 0x440739 VMOVUPD %YMM5,-0x10(%R11,%RCX,8) |
(205) 0x440740 MOV %R10D,%ECX |
(205) 0x440743 AND $-0x4,%ECX |
(205) 0x440746 ADD %ECX,%EDX |
(205) 0x440748 AND $0x3,%R10D |
(205) 0x44074c JE 44078b |
(205) 0x44074e VMOVSD (%RAX),%XMM6 |
(205) 0x440752 MOVSXD %EDX,%R10 |
(205) 0x440755 LEA 0x1(%RDX),%R15D |
(205) 0x440759 ADD %RSI,%R10 |
(205) 0x44075c VMOVSD %XMM6,(%R11,%R10,8) |
(205) 0x440762 CMP %R8D,%R15D |
(205) 0x440765 JGE 44078b |
(205) 0x440767 MOVSXD %R15D,%RCX |
(205) 0x44076a ADD $0x2,%EDX |
(205) 0x44076d ADD %RSI,%RCX |
(205) 0x440770 VMOVSD %XMM6,(%R11,%RCX,8) |
(205) 0x440776 CMP %R8D,%EDX |
(205) 0x440779 JGE 44078b |
(205) 0x44077b VMOVSD (%RAX),%XMM7 |
(205) 0x44077f MOVSXD %EDX,%RDX |
(205) 0x440782 ADD %RSI,%RDX |
(205) 0x440785 VMOVSD %XMM7,(%R11,%RDX,8) |
(205) 0x44078b MOV 0x168(%RSP),%R10D |
(205) 0x440793 MOV 0x160(%RSP),%RCX |
(205) 0x44079b KMOVB %K3,%R15D |
(205) 0x44079f MOV 0x140(%RSP),%RDX |
(205) 0x4407a7 CMP %R10D,%R8D |
(205) 0x4407aa CMOVE %R8D,%EBX |
(205) 0x4407ae CMOVE %R15D,%R13D |
(205) 0x4407b2 INC %EDI |
(205) 0x4407b4 ADD %RCX,%R9 |
(205) 0x4407b7 ADD %RDX,%RSI |
(205) 0x4407ba CMP %EDI,0x170(%RSP) |
(205) 0x4407c1 JG 4405b8 |
0x4407c7 MOV %EBX,0x108(%RSP) |
0x4407ce MOV 0xf0(%RSP),%R12 |
0x4407d6 TEST %R13B,%R13B |
0x4407d9 JE 441090 |
0x4407df MOV %EBX,0x140(%R12) |
0x4407e7 VZEROUPPER |
0x4407ea CALL 402220 <@plt_start@+0x200> |
0x4407ef MOV 0x60(%R12),%RDI |
0x4407f4 MOV (%RDI),%R8D |
0x4407f7 CMP $0x1,%R8D |
0x4407fb JLE 440fd1 |
0x440801 MOV 0x120(%RSP),%RSI |
0x440809 MOV 0x100(%RSP),%RAX |
0x440811 MOV %R8,0x58(%RSP) |
0x440816 MOV $0x1,%EBX |
0x44081b MOV 0x118(%RSP),%R11 |
0x440823 MOV 0x110(%RSP),%R14 |
0x44082b MOV 0x38(%RSP),%R10 |
0x440830 NEG %RAX |
0x440833 LEA -0x1(%RSI),%RCX |
0x440837 SUB %RSI,%R11 |
0x44083a SAL $0x3,%RAX |
0x44083e MOV %RCX,0x8(%RSP) |
0x440843 SUB %R10,%R14 |
0x440846 LEA (,%R11,8),%R9 |
0x44084e MOV %RAX,0xd0(%RSP) |
0x440856 LEA (,%R14,8),%R15 |
0x44085e MOV %R9,0x18(%RSP) |
0x440863 MOV %R15,0x10(%RSP) |
0x440868 JMP 440886 |
0x44086a NOPW (%RAX,%RAX,1) |
(202) 0x440870 CALL 402220 <@plt_start@+0x200> |
(202) 0x440875 MOV 0x58(%RSP),%R13 |
(202) 0x44087a INC %RBX |
(202) 0x44087d CMP %R13,%RBX |
(202) 0x440880 JE 440fd1 |
(202) 0x440886 MOV 0x10(%R12),%RDI |
(202) 0x44088b MOV 0x18(%R12),%RAX |
(202) 0x440890 MOV 0x88(%R12),%RDX |
(202) 0x440898 MOV 0x98(%R12),%R13 |
(202) 0x4408a0 MOV (%RDI),%R8D |
(202) 0x4408a3 MOV (%RAX),%EAX |
(202) 0x4408a5 VMOVSD (%RDX,%RBX,8),%XMM2 |
(202) 0x4408aa VMOVSD (%R13,%RBX,8),%XMM3 |
(202) 0x4408b1 MOV %RDX,0x158(%RSP) |
(202) 0x4408b9 SUB $0x2,%R8D |
(202) 0x4408bd ADD $0x3,%EAX |
(202) 0x4408c0 MOV %R13,0xb0(%RSP) |
(202) 0x4408c8 SUB %R8D,%EAX |
(202) 0x4408cb VUNPCKLPD %XMM2,%XMM3,%XMM8 |
(202) 0x4408cf CLTD |
(202) 0x4408d0 VMOVUPD %XMM8,0x130(%R12) |
(202) 0x4408da IDIVL 0xc8(%RSP) |
(202) 0x4408e1 CMP %EDX,0xdc(%RSP) |
(202) 0x4408e8 JL 440fc8 |
(202) 0x4408ee MOV 0xdc(%RSP),%R11D |
(202) 0x4408f6 IMUL %EAX,%R11D |
(202) 0x4408fa ADD %R11D,%EDX |
(202) 0x4408fd ADD %EDX,%EAX |
(202) 0x4408ff CMP %EAX,%EDX |
(202) 0x440901 JGE 440870 |
(202) 0x440907 MOV 0x8(%R12),%R14 |
(202) 0x44090c MOV 0xb8(%R12),%RCX |
(202) 0x440914 LEA (%R8,%RDX,1),%ESI |
(202) 0x440918 ADD %R8D,%EAX |
(202) 0x44091b KXORB %K4,%K4,%K4 |
(202) 0x44091f MOV (%R12),%R9 |
(202) 0x440923 MOV 0x78(%R12),%RDX |
(202) 0x440928 MOV %EAX,0xd8(%RSP) |
(202) 0x44092f MOV (%R14),%R8D |
(202) 0x440932 MOV 0xc8(%R12),%RAX |
(202) 0x44093a MOV %RCX,0xa0(%RSP) |
(202) 0x440942 MOV 0x90(%R12),%RCX |
(202) 0x44094a MOV (%R9),%R9D |
(202) 0x44094d MOV %ESI,0x160(%RSP) |
(202) 0x440954 MOV 0x50(%R12),%R11 |
(202) 0x440959 LEA 0x3(%R8),%R10D |
(202) 0x44095d MOV 0xc0(%R12),%R13 |
(202) 0x440965 MOV %RDX,0x50(%RSP) |
(202) 0x44096a MOV %RCX,0xf0(%RSP) |
(202) 0x440972 MOV 0x100(%RSP),%RCX |
(202) 0x44097a MOVSXD %ESI,%RDX |
(202) 0x44097d LEA -0x2(%R9),%EDI |
(202) 0x440981 MOV 0x8(%RSP),%RSI |
(202) 0x440986 MOV 0xb0(%R12),%R15 |
(202) 0x44098e MOV %R10D,0x134(%RSP) |
(202) 0x440996 MOV 0x58(%R12),%R10 |
(202) 0x44099b IMUL %RDX,%RCX |
(202) 0x44099f MOV 0x80(%R12),%R14 |
(202) 0x4409a7 MOV %RAX,0x168(%RSP) |
(202) 0x4409af MOV %R11,0xc0(%RSP) |
(202) 0x4409b7 MOVSXD %R9D,%RAX |
(202) 0x4409ba LEA 0x4(%R8),%R11D |
(202) 0x4409be SUB %R9D,%R11D |
(202) 0x4409c1 MOV %R10,0xb8(%RSP) |
(202) 0x4409c9 LEA (%RSI,%RAX,1),%R10 |
(202) 0x4409cd ADD %R11,%R10 |
(202) 0x4409d0 MOV %R13,0x178(%RSP) |
(202) 0x4409d8 MOV 0x18(%RSP),%R13 |
(202) 0x4409dd ADD %RCX,%R10 |
(202) 0x4409e0 MOV 0xd0(%RSP),%RCX |
(202) 0x4409e8 MOV %R15,0xa8(%RSP) |
(202) 0x4409f0 MOV 0xa8(%R12),%R15 |
(202) 0x4409f8 MOV %R14,0x68(%RSP) |
(202) 0x4409fd IMUL %RDX,%RCX |
(202) 0x440a01 MOV %R15,0x110(%RSP) |
(202) 0x440a09 ADD %R13,%RCX |
(202) 0x440a0c MOV 0x20(%R12),%R13 |
(202) 0x440a11 MOV 0x38(%RSP),%R14 |
(202) 0x440a16 MOV %EDI,0xe0(%RSP) |
(202) 0x440a1d MOV 0x40(%RSP),%RSI |
(202) 0x440a22 ADD %RCX,%R13 |
(202) 0x440a25 MOV 0x138(%RSP),%RCX |
(202) 0x440a2d LEA (%RDX,%R14,1),%R15 |
(202) 0x440a31 IMUL %RDX,%RCX |
(202) 0x440a35 LEA (%RCX,%RSI,1),%R14 |
(202) 0x440a39 MOV 0x140(%RSP),%RCX |
(202) 0x440a41 MOV 0x48(%RSP),%RSI |
(202) 0x440a46 IMUL %RDX,%RCX |
(202) 0x440a4a ADD %RSI,%RCX |
(202) 0x440a4d MOVSXD %EDI,%RSI |
(202) 0x440a50 MOV 0xf8(%RSP),%RDI |
(202) 0x440a58 MOV %RCX,0x128(%RSP) |
(202) 0x440a60 MOV 0x30(%RSP),%RCX |
(202) 0x440a65 IMUL %RDI,%RDX |
(202) 0x440a69 MOV 0x30(%R12),%RDI |
(202) 0x440a6e ADD %RSI,%RCX |
(202) 0x440a71 ADD %RDX,%RCX |
(202) 0x440a74 MOV 0x20(%RSP),%RDX |
(202) 0x440a79 MOV %RCX,0x120(%RSP) |
(202) 0x440a81 LEA (,%RAX,8),%RCX |
(202) 0x440a89 ADD %RAX,%RDX |
(202) 0x440a8c ADD %R11,%RDX |
(202) 0x440a8f LEA (%RDI,%RDX,8),%RDX |
(202) 0x440a93 MOV 0x10(%RSP),%RDI |
(202) 0x440a98 MOV %RDX,0x98(%RSP) |
(202) 0x440aa0 MOV $0x1,%EDX |
(202) 0x440aa5 ADD 0x38(%R12),%RDI |
(202) 0x440aaa MOV %RDI,0x108(%RSP) |
(202) 0x440ab2 MOV 0xe0(%RSP),%EDI |
(202) 0x440ab9 LEA 0x5(%RDI,%R8,1),%R8D |
(202) 0x440abe SUB %R9D,%R8D |
(202) 0x440ac1 CMP %EDI,0x134(%RSP) |
(202) 0x440ac8 MOV 0xc0(%RSP),%R9 |
(202) 0x440ad0 CMOVLE %EDI,%R8D |
(202) 0x440ad4 SUB %RAX,%RDX |
(202) 0x440ad7 MOV %RDX,%RDI |
(202) 0x440ada ADD %RSI,%RDI |
(202) 0x440add MOV %R8D,0xcc(%RSP) |
(202) 0x440ae5 MOV 0xb8(%RSP),%RSI |
(202) 0x440aed SUB %R11,%RDI |
(202) 0x440af0 LEA -0x10(%R9,%RCX,1),%R11 |
(202) 0x440af5 MOV 0x40(%RSP),%R8 |
(202) 0x440afa LEA (,%RBX,8),%R9 |
(202) 0x440b02 MOV %RDI,0x90(%RSP) |
(202) 0x440b0a MOV 0x48(%RSP),%RDI |
(202) 0x440b0f LEA -0x10(%RSI,%RCX,1),%RCX |
(202) 0x440b14 MOV %R11,0x88(%RSP) |
(202) 0x440b1c MOV 0x50(%RSP),%R11 |
(202) 0x440b21 LEA (%RAX,%R8,1),%RDX |
(202) 0x440b25 LEA (%RAX,%RDI,1),%RAX |
(202) 0x440b29 MOV %RCX,0x80(%RSP) |
(202) 0x440b31 ADD %R9,%R11 |
(202) 0x440b34 MOV %RDX,0x78(%RSP) |
(202) 0x440b39 MOV %RAX,0x70(%RSP) |
(202) 0x440b3e MOV %R9,0x60(%RSP) |
(202) 0x440b43 MOV %R11,0xe8(%RSP) |
(202) 0x440b4b NOPL (%RAX,%RAX,1) |
(203) 0x440b50 MOV 0xe0(%RSP),%ESI |
(203) 0x440b57 INCL 0x160(%RSP) |
(203) 0x440b5e CMP %ESI,0x134(%RSP) |
(203) 0x440b65 JLE 440fb0 |
(203) 0x440b6b MOV 0xa8(%RSP),%RCX |
(203) 0x440b73 MOV 0xa0(%RSP),%RDX |
(203) 0x440b7b MOV %R14,0x118(%RSP) |
(203) 0x440b83 MOV 0x90(%RSP),%RDI |
(203) 0x440b8b MOV 0x88(%RSP),%RAX |
(203) 0x440b93 MOV (%RCX,%RBX,4),%R8D |
(203) 0x440b97 MOV (%RDX),%R11D |
(203) 0x440b9a MOV 0x138(%RSP),%RCX |
(203) 0x440ba2 MOVSXD 0x160(%RSP),%RDX |
(203) 0x440baa ADD %R10,%RDI |
(203) 0x440bad MOV 0x80(%RSP),%R9 |
(203) 0x440bb5 MOV 0x128(%RSP),%RSI |
(203) 0x440bbd MOV %RDI,0x170(%RSP) |
(203) 0x440bc5 LEA (%RAX,%R14,8),%RDI |
(203) 0x440bc9 IMUL %RDX,%RCX |
(203) 0x440bcd MOV 0x78(%RSP),%RAX |
(203) 0x440bd2 LEA (%R9,%RSI,8),%RSI |
(203) 0x440bd6 MOV 0xc0(%RSP),%R9 |
(203) 0x440bde ADD %RAX,%RCX |
(203) 0x440be1 MOV 0x140(%RSP),%RAX |
(203) 0x440be9 LEA -0x10(%R9,%RCX,8),%RCX |
(203) 0x440bee MOV 0x70(%RSP),%R9 |
(203) 0x440bf3 IMUL %RAX,%RDX |
(203) 0x440bf7 MOV 0xb8(%RSP),%RAX |
(203) 0x440bff ADD %R9,%RDX |
(203) 0x440c02 MOV %R10,%R9 |
(203) 0x440c05 LEA -0x10(%RAX,%RDX,8),%RDX |
(203) 0x440c0a MOV 0x98(%RSP),%RAX |
(203) 0x440c12 NEG %R9 |
(203) 0x440c15 LEA -0x8(%RAX,%R9,8),%R9 |
(203) 0x440c1a LEA 0x1(%R15),%RAX |
(203) 0x440c1e MOV %R9,0x148(%RSP) |
(203) 0x440c26 MOV 0x120(%RSP),%R9 |
(203) 0x440c2e MOV %RAX,0x150(%RSP) |
(203) 0x440c36 MOV 0x170(%RSP),%RAX |
(203) 0x440c3e MOV %R15,0x170(%RSP) |
(203) 0x440c46 JMP 440c91 |
0x440c48 NOPL (%RAX,%RAX,1) |
(204) 0x440c50 MOV 0x178(%RSP),%R14 |
(204) 0x440c58 CMP (%R14),%R8D |
(204) 0x440c5b JE 440db0 |
(204) 0x440c61 MOV 0x168(%RSP),%R15 |
(204) 0x440c69 CMP (%R15),%R8D |
(204) 0x440c6c JE 440e68 |
(204) 0x440c72 INC %RAX |
(204) 0x440c75 INC %R9 |
(204) 0x440c78 ADD $0x8,%RDI |
(204) 0x440c7c ADD $0x8,%RSI |
(204) 0x440c80 ADD $0x8,%RCX |
(204) 0x440c84 ADD $0x8,%RDX |
(204) 0x440c88 CMP %R10,%RAX |
(204) 0x440c8b JE 440ef0 |
(204) 0x440c91 CMP %R11D,%R8D |
(204) 0x440c94 JNE 440c50 |
(204) 0x440c96 VMOVSD 0x8(%R13,%RAX,8),%XMM11 |
(204) 0x440c9d MOV 0x158(%RSP),%R14 |
(204) 0x440ca5 VCOMISD (%R14,%RBX,8),%XMM11 |
(204) 0x440cab JB 440c72 |
(204) 0x440cad MOV 0xf0(%RSP),%R15 |
(204) 0x440cb5 VMOVSD (%R15,%RBX,8),%XMM12 |
(204) 0x440cbb VCOMISD (%R13,%RAX,8),%XMM12 |
(204) 0x440cc2 JBE 440c72 |
(204) 0x440cc4 MOV 0x150(%RSP),%R15 |
(204) 0x440ccc MOV 0x28(%R12),%R14 |
(204) 0x440cd1 VMOVSD (%R14,%R15,8),%XMM13 |
(204) 0x440cd7 MOV 0xb0(%RSP),%R15 |
(204) 0x440cdf VCOMISD (%R15,%RBX,8),%XMM13 |
(204) 0x440ce5 JB 440c72 |
(204) 0x440ce7 MOV 0xa0(%R12),%R15 |
(204) 0x440cef VMOVSD (%R15,%RBX,8),%XMM14 |
(204) 0x440cf5 MOV 0x170(%RSP),%R15 |
(204) 0x440cfd VCOMISD (%R14,%R15,8),%XMM14 |
(204) 0x440d03 JBE 440c72 |
(204) 0x440d09 MOV 0x70(%R12),%R14 |
(204) 0x440d0e MOV 0x48(%R12),%R15 |
(204) 0x440d13 VMOVSD (%R14,%RBX,8),%XMM15 |
(204) 0x440d19 MOV 0x68(%R12),%R14 |
(204) 0x440d1e VMOVSD %XMM15,(%R15,%R9,8) |
(204) 0x440d24 MOV 0x40(%R12),%R15 |
(204) 0x440d29 VMOVSD (%R14,%RBX,8),%XMM0 |
(204) 0x440d2f LEA (,%RBX,8),%R14 |
(204) 0x440d37 VMOVSD %XMM0,(%R15,%RAX,8) |
(204) 0x440d3d MOV 0x50(%RSP),%R15 |
(204) 0x440d42 ADD %R14,%R15 |
(204) 0x440d45 VMOVSD (%R15),%XMM1 |
(204) 0x440d4a MOV %R15,0x28(%RSP) |
(204) 0x440d4f MOV 0x68(%RSP),%R15 |
(204) 0x440d54 VMOVSD %XMM1,(%RDI) |
(204) 0x440d58 ADD %R15,%R14 |
(204) 0x440d5b MOV 0x28(%RSP),%R15 |
(204) 0x440d60 VMOVSD (%R14),%XMM4 |
(204) 0x440d65 VMOVSD %XMM4,(%RSI) |
(204) 0x440d69 NOPL (%RAX) |
(204) 0x440d70 VMOVSD (%R15),%XMM5 |
(204) 0x440d75 VMOVSD %XMM5,0x8(%RDI) |
(204) 0x440d7a VMOVSD (%R14),%XMM6 |
(204) 0x440d7f VMOVSD %XMM6,0x8(%RSI) |
(204) 0x440d84 VMOVSD (%R15),%XMM7 |
(204) 0x440d89 VMOVSD %XMM7,(%RCX) |
(204) 0x440d8d VMOVSD (%R14),%XMM8 |
(204) 0x440d92 VMOVSD %XMM8,(%RDX) |
(204) 0x440d96 VMOVSD (%R15),%XMM9 |
(204) 0x440d9b VMOVSD %XMM9,0x8(%RCX) |
(204) 0x440da0 VMOVSD (%R14),%XMM10 |
(204) 0x440da5 VMOVSD %XMM10,0x8(%RDX) |
(204) 0x440daa JMP 440c72 |
0x440daf NOP |
(204) 0x440db0 MOV 0x148(%RSP),%R14 |
(204) 0x440db8 MOV 0x170(%RSP),%R15 |
(204) 0x440dc0 VMOVSD (%R14,%RAX,8),%XMM13 |
(204) 0x440dc6 MOV 0x108(%RSP),%R14 |
(204) 0x440dce VMOVSD (%R14,%R15,8),%XMM15 |
(204) 0x440dd4 VSUBSD %XMM2,%XMM13,%XMM14 |
(204) 0x440dd8 MOV 0x110(%RSP),%R14 |
(204) 0x440de0 VSUBSD %XMM3,%XMM15,%XMM0 |
(204) 0x440de4 VUNPCKLPD %XMM0,%XMM14,%XMM1 |
(204) 0x440de8 VMULPD %XMM1,%XMM1,%XMM4 |
(204) 0x440dec VUNPCKHPD %XMM4,%XMM4,%XMM5 |
(204) 0x440df0 VADDPD %XMM4,%XMM5,%XMM6 |
(204) 0x440df4 VSQRTSD %XMM6,%XMM6,%XMM6 |
(204) 0x440df8 VCOMISD (%R14,%RBX,8),%XMM6 |
(204) 0x440dfe JA 440c72 |
(204) 0x440e04 MOV 0x70(%R12),%R15 |
(204) 0x440e09 MOV 0x48(%R12),%R14 |
(204) 0x440e0e VMOVSD (%R15,%RBX,8),%XMM7 |
(204) 0x440e14 MOV 0x68(%R12),%R15 |
(204) 0x440e19 VMOVSD %XMM7,(%R14,%R9,8) |
(204) 0x440e1f MOV 0x40(%R12),%R14 |
(204) 0x440e24 VMOVSD (%R15,%RBX,8),%XMM8 |
(204) 0x440e2a MOV 0xe8(%RSP),%R15 |
(204) 0x440e32 VMOVSD %XMM8,(%R14,%RAX,8) |
(204) 0x440e38 MOV 0x60(%RSP),%R14 |
(204) 0x440e3d VMOVSD (%R15),%XMM9 |
(204) 0x440e42 MOV 0x68(%RSP),%R15 |
(204) 0x440e47 VMOVSD %XMM9,(%RDI) |
(204) 0x440e4b ADD %R15,%R14 |
(204) 0x440e4e MOV 0xe8(%RSP),%R15 |
(204) 0x440e56 VMOVSD (%R14),%XMM10 |
(204) 0x440e5b VMOVSD %XMM10,(%RSI) |
(204) 0x440e5f JMP 440d70 |
0x440e64 NOPL (%RAX) |
(204) 0x440e68 VCOMISD (%R13,%RAX,8),%XMM2 |
(204) 0x440e6f JNE 440c72 |
(204) 0x440e75 MOV 0x28(%R12),%R14 |
(204) 0x440e7a MOV 0x170(%RSP),%R15 |
(204) 0x440e82 VCOMISD (%R14,%R15,8),%XMM3 |
(204) 0x440e88 JNE 440c72 |
(204) 0x440e8e MOV 0x70(%R12),%R14 |
(204) 0x440e93 MOV 0x48(%R12),%R15 |
(204) 0x440e98 VMOVSD (%R14,%RBX,8),%XMM9 |
(204) 0x440e9e MOV 0x68(%R12),%R14 |
(204) 0x440ea3 VMOVSD %XMM9,(%R15,%R9,8) |
(204) 0x440ea9 MOV 0x40(%R12),%R15 |
(204) 0x440eae VMOVSD (%R14,%RBX,8),%XMM10 |
(204) 0x440eb4 MOV 0xe8(%RSP),%R14 |
(204) 0x440ebc VMOVSD %XMM10,(%R15,%RAX,8) |
(204) 0x440ec2 MOV 0x60(%RSP),%R15 |
(204) 0x440ec7 VMOVSD (%R14),%XMM11 |
(204) 0x440ecc MOV 0x68(%RSP),%R14 |
(204) 0x440ed1 VMOVSD %XMM11,(%RDI) |
(204) 0x440ed5 ADD %R15,%R14 |
(204) 0x440ed8 MOV 0xe8(%RSP),%R15 |
(204) 0x440ee0 VMOVSD (%R14),%XMM12 |
(204) 0x440ee5 VMOVSD %XMM12,(%RSI) |
(204) 0x440ee9 JMP 440d70 |
0x440eee XCHG %AX,%AX |
(203) 0x440ef0 MOV 0x118(%RSP),%R14 |
(203) 0x440ef8 MOV 0x134(%RSP),%R15D |
(203) 0x440f00 MOV 0xcc(%RSP),%EAX |
(203) 0x440f07 MOV $0x1,%ECX |
(203) 0x440f0c KMOVB %K4,%ESI |
(203) 0x440f10 MOV 0x130(%RSP),%EDX |
(203) 0x440f17 MOV 0x100(%RSP),%RDI |
(203) 0x440f1f CMP %EAX,%R15D |
(203) 0x440f22 MOV 0xd0(%RSP),%R8 |
(203) 0x440f2a MOV 0x138(%RSP),%R9 |
(203) 0x440f32 CMOVE %R15D,%EDX |
(203) 0x440f36 CMOVE %ECX,%ESI |
(203) 0x440f39 MOV 0x140(%RSP),%R11 |
(203) 0x440f41 MOV 0xf8(%RSP),%RAX |
(203) 0x440f49 MOV 0x150(%RSP),%R15 |
(203) 0x440f51 ADD %RDI,%R10 |
(203) 0x440f54 ADD %R8,%R13 |
(203) 0x440f57 MOV %EDX,0x130(%RSP) |
(203) 0x440f5e MOV 0x160(%RSP),%EDX |
(203) 0x440f65 ADD %R9,%R14 |
(203) 0x440f68 KMOVB %ESI,%K4 |
(203) 0x440f6c ADD %R11,0x128(%RSP) |
(203) 0x440f74 ADD %RAX,0x120(%RSP) |
(203) 0x440f7c CMP %EDX,0xd8(%RSP) |
(203) 0x440f83 JG 440b50 |
(202) 0x440f89 KORTESTB %K4,%K4 |
(202) 0x440f8d JE 440870 |
(202) 0x440f93 MOV 0x130(%RSP),%R10D |
(202) 0x440f9b MOV %R10D,0x140(%R12) |
(202) 0x440fa3 JMP 440870 |
0x440fa8 NOPL (%RAX,%RAX,1) |
(203) 0x440fb0 LEA 0x1(%R15),%R15 |
(203) 0x440fb4 MOV %R15,0x150(%RSP) |
(203) 0x440fbc JMP 440ef8 |
0x440fc1 NOPL (%RAX) |
(202) 0x440fc8 INC %EAX |
(202) 0x440fca XOR %EDX,%EDX |
(202) 0x440fcc JMP 4408ee |
0x440fd1 LEA -0x28(%RBP),%RSP |
0x440fd5 POP %RBX |
0x440fd6 POP %R12 |
0x440fd8 POP %R13 |
0x440fda POP %R14 |
0x440fdc POP %R15 |
0x440fde POP %RBP |
0x440fdf RET |
(205) 0x440fe0 VBROADCASTSD (%RAX),%ZMM6 |
(205) 0x440fe6 LEA 0x40(%R9),%RDX |
(205) 0x440fea VMOVUPD %ZMM6,(%R9) |
(205) 0x440ff0 JMP 440618 |
(207) 0x440ff5 VBROADCASTSD (%RAX),%ZMM4 |
(207) 0x440ffb LEA 0x40(%R9),%RDX |
(207) 0x440fff VMOVUPD %ZMM4,(%R9) |
(207) 0x441005 JMP 4402a8 |
(209) 0x44100a VBROADCASTSD (%RAX),%ZMM2 |
(209) 0x441010 LEA 0x40(%R9),%RDX |
(209) 0x441014 VMOVUPD %ZMM2,(%R9) |
(209) 0x44101a JMP 43ff49 |
(211) 0x44101f VBROADCASTSD (%RAX),%ZMM0 |
(211) 0x441025 LEA 0x40(%R9),%RDX |
(211) 0x441029 VMOVUPD %ZMM0,(%R9) |
(211) 0x44102f JMP 43fbe0 |
(209) 0x441034 MOV 0x178(%RSP),%EDX |
(209) 0x44103b XOR %ECX,%ECX |
(209) 0x44103d JMP 440045 |
(205) 0x441042 MOV 0x178(%RSP),%EDX |
(205) 0x441049 XOR %ECX,%ECX |
(205) 0x44104b JMP 440714 |
(207) 0x441050 MOV 0x178(%RSP),%EDX |
(207) 0x441057 XOR %ECX,%ECX |
(207) 0x441059 JMP 4403a4 |
(211) 0x44105e MOV 0x178(%RSP),%EDX |
(211) 0x441065 XOR %ECX,%ECX |
(211) 0x441067 JMP 43fcdc |
0x44106c INC %EAX |
0x44106e XOR %EDX,%EDX |
0x441070 JMP 44014a |
0x441075 INC %EAX |
0x441077 XOR %EDX,%EDX |
0x441079 JMP 43fa5e |
0x44107e INC %EAX |
0x441080 XOR %EDX,%EDX |
0x441082 JMP 43fde9 |
0x441087 INC %EAX |
0x441089 XOR %EDX,%EDX |
0x44108b JMP 4404b2 |
0x441090 VZEROUPPER |
0x441093 JMP 4407ea |
0x441098 VZEROUPPER |
0x44109b JMP 44047e |
0x4410a0 VZEROUPPER |
0x4410a3 JMP 43fdb6 |
0x4410a8 VZEROUPPER |
0x4410ab JMP 440117 |
Path / |
Source file and lines | generate_chunk_kernel.f90:85-161 |
Module | exec |
nb instructions | 400 |
nb uops | 429 |
loop length | 1859 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 33 |
micro-operation queue | 71.50 cycles |
front end | 71.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 33.50 | 33.40 | 31.00 | 31.00 | 40.00 | 33.40 | 33.30 | 40.00 | 40.00 | 40.00 | 33.40 | 31.00 |
cycles | 33.50 | 49.33 | 31.00 | 31.00 | 40.00 | 33.40 | 33.30 | 40.00 | 40.00 | 40.00 | 33.40 | 31.00 |
Cycles executing div or sqrt instructions | 24.00 |
FE+BE cycles | 68.21-68.28 |
Stall cycles | 0.00 |
Front-end | 71.50 |
Dispatch | 49.33 |
DIV/SQRT | 24.00 |
Overall L1 | 71.50 |
all | 8% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 32% |
all | 9% |
load | 6% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x180,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x128(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x120(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x118(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x108(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf8(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe8(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe0(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd8(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x110(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x118(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x120(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x110(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 402080 <@plt_start@+0x60> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EAX,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x2,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 402180 <@plt_start@+0x160> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x18(%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0xdc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%RSI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %EBX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 441075 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1715> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xdc(%RSP),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EAX,%EDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43fdb6 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x456> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %EBX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EBX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xf8(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%RBX,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOVSXD (%R8),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x70(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %EDI,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV (%R11),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RBX,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R9,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x2(%R9),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x3(%RCX),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %RDX,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R13D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10D,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %ECX,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RSI,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x5(%RCX),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x10(%R11,%R9,8),%R9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SHR $0x3,%ECX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
AND $-0x8,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SAL $0x6,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %EBX,0x134(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R8D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RBX,%R10,1),%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R13D,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x5(%R10,%R13,1),%R13D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMOVGE %R10D,%R13D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LEA 0x4(%RBX),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ECX,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10D,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R13D,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %ECX,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R12,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe0(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EDX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x1,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
KMOVB %EDX,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xe8(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RSP),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %DIL,%DIL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 4410a0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1740> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R15D,0x140(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 402220 <@plt_start@+0x200> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x10(%R12),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R15),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x2,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD $0x3,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIVL 0xc8(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
CMP %EDX,0xdc(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JL 44107e <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x171e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xdc(%RSP),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EAX,%EDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 440117 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x7b7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R8D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x100(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x120(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD (%R11),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDI,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R12,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %RBX,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (,%RBX,8),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x40(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x2(%R9),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x3(%RCX),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R13D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%R9,%RDX,1),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R10,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RSI,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x5(%RCX),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ECX,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %ECX,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EDX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x10(%R11,%R9,8),%R9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
AND $-0x8,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x3,%R13D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R15D,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,0x134(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R15D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SAL $0x6,%R13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
CMP %R8D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x5(%R15,%R10,1),%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA 0x4(%R10),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMOVGE %R15D,%ECX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %R10D,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EDX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x1,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
KMOVB %EDX,%K0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R12D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xe8(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %DIL,%DIL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 4410a8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1748> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,0x140(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 402220 <@plt_start@+0x200> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x10(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R14),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x2,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD $0x3,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIVL 0xc8(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
CMP %EDX,0xdc(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JL 44106c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x170c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xdc(%RSP),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EAX,%EDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 44047e <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb1e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x8(%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R8D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x138(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RSI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDI,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOVSXD (%R11),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R12,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %R9,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x50(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%R9,8),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x78(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R13,%R14,1),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x3(%RCX),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R13D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x2(%R13),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ECX,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %ECX,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RSI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R14,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EBX,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x10(%R11,%RDX,8),%R9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA 0x5(%RCX),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EDX,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x5(%RBX,%RCX,1),%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
AND $-0x8,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x3,%R14D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R15D,0x134(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x6,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %EBX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R8D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVGE %EBX,%ECX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x4(%R10),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R15D,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x1,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
KMOVB %R10D,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EBX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RSP),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R12D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EBX,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %DIL,%DIL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 441098 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1738> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EBX,0x140(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 402220 <@plt_start@+0x200> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x10(%R12),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x2,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD $0x3,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIVL 0xc8(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
CMP %EDX,0xdc(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JL 441087 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1727> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xdc(%RSP),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EAX,%EDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4407ea <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xe8a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x8(%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R8D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x140(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x48(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RSI),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDI,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOVSXD (%R11),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R12,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %R9,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x58(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%R9,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x80(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R10,%RBX,1),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x3(%R15),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R10D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x2(%R10),%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD %RSI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RBX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15D,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R13D,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x10(%R11,%RDX,8),%R9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA 0x5(%R15),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EDX,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x5(%R13,%RBX,1),%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
AND $-0x8,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x3,%R14D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R15D,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x6,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %R13D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R8D,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVGE %R13D,%ECX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD $0x4,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R15D,0x134(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EBX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x1,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %ECX,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
KMOVB %EBX,%K3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x108(%RSP),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EDX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EBX,0x108(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R13B,%R13B | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 441090 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1730> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EBX,0x140(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 402220 <@plt_start@+0x200> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x60(%R12),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP $0x1,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 440fd1 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1671> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x120(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x1,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x118(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x110(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
NEG %RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RSI),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %RSI,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SAL $0x3,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RCX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (,%R11,8),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%R14,8),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R9,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 440886 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xf26> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 44014a <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x7ea> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43fa5e <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xfe> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43fde9 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x489> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4404b2 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb52> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 4407ea <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xe8a> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 44047e <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb1e> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 43fdb6 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x456> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 440117 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x7b7> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Source file and lines | generate_chunk_kernel.f90:85-161 |
Module | exec |
nb instructions | 400 |
nb uops | 429 |
loop length | 1859 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 33 |
micro-operation queue | 71.50 cycles |
front end | 71.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 33.50 | 33.40 | 31.00 | 31.00 | 40.00 | 33.40 | 33.30 | 40.00 | 40.00 | 40.00 | 33.40 | 31.00 |
cycles | 33.50 | 49.33 | 31.00 | 31.00 | 40.00 | 33.40 | 33.30 | 40.00 | 40.00 | 40.00 | 33.40 | 31.00 |
Cycles executing div or sqrt instructions | 24.00 |
FE+BE cycles | 68.21-68.28 |
Stall cycles | 0.00 |
Front-end | 71.50 |
Dispatch | 49.33 |
DIV/SQRT | 24.00 |
Overall L1 | 71.50 |
all | 8% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 32% |
all | 9% |
load | 6% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x180,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x128(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x120(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x118(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x108(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf8(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe8(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe0(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd8(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x110(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x118(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x120(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x110(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 402080 <@plt_start@+0x60> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EAX,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x2,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 402180 <@plt_start@+0x160> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x18(%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0xdc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%RSI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %EBX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 441075 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1715> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xdc(%RSP),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EAX,%EDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 43fdb6 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x456> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %EBX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EBX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xf8(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%RBX,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOVSXD (%R8),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x70(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14D,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %EDI,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV (%R11),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RBX,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %R9,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x2(%R9),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x3(%RCX),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %RDX,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R13D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10D,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %ECX,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RSI,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x5(%RCX),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EDX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x10(%R11,%R9,8),%R9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SHR $0x3,%ECX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
AND $-0x8,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SAL $0x6,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %EBX,0x134(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %R8D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RBX,%R10,1),%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R13D,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x5(%R10,%R13,1),%R13D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMOVGE %R10D,%R13D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LEA 0x4(%RBX),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ECX,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10D,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R13D,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %ECX,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R12,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe0(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EDX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x1,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
KMOVB %EDX,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R14D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xe8(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RSP),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %DIL,%DIL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 4410a0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1740> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R15D,0x140(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 402220 <@plt_start@+0x200> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x10(%R12),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R15),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x2,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD $0x3,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIVL 0xc8(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
CMP %EDX,0xdc(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JL 44107e <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x171e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xdc(%RSP),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EAX,%EDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 440117 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x7b7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R8D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x100(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x120(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD (%R11),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDI,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV %R12,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %RBX,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (,%RBX,8),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x40(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x2(%R9),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x3(%RCX),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R13D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%R9,%RDX,1),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R10,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RSI,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x5(%RCX),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ECX,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %ECX,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EDX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x10(%R11,%R9,8),%R9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
AND $-0x8,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x3,%R13D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R15D,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,0x134(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R15D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SAL $0x6,%R13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
CMP %R8D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x5(%R15,%R10,1),%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA 0x4(%R10),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMOVGE %R15D,%ECX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %R10D,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EDX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x1,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
KMOVB %EDX,%K0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R12D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xe8(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %DIL,%DIL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 4410a8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1748> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14D,0x140(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 402220 <@plt_start@+0x200> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x10(%R12),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R14),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x2,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD $0x3,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIVL 0xc8(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
CMP %EDX,0xdc(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JL 44106c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x170c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xdc(%RSP),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EAX,%EDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 44047e <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb1e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x8(%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R8D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x138(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RSI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDI,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOVSXD (%R11),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R12,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %R9,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x50(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%R9,8),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x78(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R13,%R14,1),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x3(%RCX),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R13D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x2(%R13),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ECX,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %ECX,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RSI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R14,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EBX,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x10(%R11,%RDX,8),%R9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA 0x5(%RCX),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EDX,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x5(%RBX,%RCX,1),%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
AND $-0x8,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x3,%R14D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R15D,0x134(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x6,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %EBX,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R8D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVGE %EBX,%ECX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x4(%R10),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R15D,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x1,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
KMOVB %R10D,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EBX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RSP),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R12D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EBX,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %DIL,%DIL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 441098 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1738> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EBX,0x140(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 402220 <@plt_start@+0x200> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x10(%R12),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R13),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x2,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD $0x3,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIVL 0xc8(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
CMP %EDX,0xdc(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JL 441087 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1727> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xdc(%RSP),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EAX,%EDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4407ea <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xe8a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x8(%R12),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R8D,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x140(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x48(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RSI),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDI,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOVSXD (%R11),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R12,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %R9,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x58(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%R9,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x80(%R12),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R10,%RBX,1),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x3(%R15),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R10D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15D,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x2(%R10),%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD %RSI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RBX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15D,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R13D,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x10(%R11,%RDX,8),%R9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA 0x5(%R15),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EDX,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x5(%R13,%RBX,1),%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
AND $-0x8,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x3,%R14D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R15D,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x6,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %R13D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R8D,%R13D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVGE %R13D,%ECX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD $0x4,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R15D,0x134(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EBX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x1,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %ECX,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
KMOVB %EBX,%K3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV 0x108(%RSP),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EDX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %EBX,0x108(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R13B,%R13B | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 441090 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1730> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EBX,0x140(%R12) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 402220 <@plt_start@+0x200> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x60(%R12),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP $0x1,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 440fd1 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1671> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x120(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x1,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x118(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x110(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
NEG %RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RSI),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %RSI,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SAL $0x3,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RCX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %R10,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (,%R11,8),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%R14,8),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R9,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 440886 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xf26> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 44014a <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x7ea> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43fa5e <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xfe> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43fde9 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x489> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4404b2 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb52> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 4407ea <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xe8a> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 44047e <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb1e> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 43fdb6 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x456> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 440117 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x7b7> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼generate_chunk_kernel._omp_fn.0– | 0.04 | 0.03 |
▼Loop 205 - generate_chunk_kernel.f90:112-114 - exec– | 0 | 0 |
○Loop 206 - generate_chunk_kernel.f90:114-114 - exec | 0.01 | 0.01 |
▼Loop 202 - generate_chunk_kernel.f90:119-161 - exec– | 0 | 0 |
▼Loop 203 - generate_chunk_kernel.f90:127-161 - exec– | 0 | 0 |
○Loop 204 - generate_chunk_kernel.f90:129-161 - exec | 0.01 | 0.01 |
▼Loop 209 - generate_chunk_kernel.f90:96-98 - exec– | 0 | 0 |
○Loop 210 - generate_chunk_kernel.f90:98-98 - exec | 0.01 | 0.01 |
▼Loop 207 - generate_chunk_kernel.f90:104-106 - exec– | 0 | 0 |
○Loop 208 - generate_chunk_kernel.f90:106-106 - exec | 0.01 | 0.01 |
▼Loop 211 - generate_chunk_kernel.f90:88-90 - exec– | 0 | 0 |
○Loop 212 - generate_chunk_kernel.f90:90-90 - exec | 0.01 | 0.01 |