Loop Id: 351 | Module: exec | Source: generate_chunk_kernel.f90:87-163 [...] | Coverage: 0.01% |
---|
Loop Id: 351 | Module: exec | Source: generate_chunk_kernel.f90:87-163 [...] | Coverage: 0.01% |
---|
0x443140 MOV -0x60(%RBP),%R8D |
0x443144 INC %R8D |
0x443147 MOV -0x138(%RBP),%RDI |
0x44314e INC %RDI |
0x443151 MOV -0x58(%RBP),%RSI |
0x443155 INC %RSI |
0x443158 MOV -0x130(%RBP),%RAX |
0x44315f CMP %RAX,%RDI |
0x443162 MOV -0xd0(%RBP),%ECX |
0x443168 JE 443080 |
0x44316e MOVSXD %R8D,%RDX |
0x443171 LEA (,%RDX,8),%R10 |
0x443179 CMP %RDX,%RSI |
0x44317c MOV %RDX,%R9 |
0x44317f CMOVG %RSI,%R9 |
0x443183 SUB %RDX,%R9 |
0x443186 INC %R9 |
0x443189 SHR $0x3,%R9 |
0x44318d NEG %R9 |
0x443190 MOV -0x128(%RBP),%RAX |
0x443197 ADD %RDI,%RAX |
0x44319a MOV %RAX,-0x38(%RBP) |
0x44319e CMP $0x2,%ECX |
0x4431a1 MOV %R8D,-0x60(%RBP) |
0x4431a5 MOV %RSI,-0x58(%RBP) |
0x4431a9 MOV %RDI,-0x138(%RBP) |
0x4431b0 JGE 443340 |
0x4431b6 CMP $0x1,%ECX |
0x4431b9 JNE 443140 |
0x4431bb MOV -0x38(%RBP),%RAX |
0x4431bf LEA 0x1(%RAX),%R8 |
0x4431c3 MOV %R8,%RCX |
0x4431c6 SUB %RBX,%RCX |
0x4431c9 MOV 0xb8(%RBP),%RAX |
0x4431d0 VMOVSD (%RAX,%RCX,8),%XMM0 |
0x4431d5 MOV 0x50(%RBP),%RAX |
0x4431d9 MOV -0x50(%RBP),%RCX |
0x4431dd VUCOMISD -0x8(%RAX,%RCX,8),%XMM0 |
0x4431e3 JB 443140 |
0x4431e9 MOV -0x38(%RBP),%RSI |
0x4431ed SUB %RBX,%RSI |
0x4431f0 MOV 0x48(%RBP),%RAX |
0x4431f4 MOV -0x50(%RBP),%RCX |
0x4431f8 VMOVSD -0x8(%RAX,%RCX,8),%XMM0 |
0x4431fe MOV 0xb8(%RBP),%RAX |
0x443205 VUCOMISD (%RAX,%RSI,8),%XMM0 |
0x44320a JBE 443140 |
0x443210 MOV %RSI,%R14 |
0x443213 MOVSXD -0x64(%RBP),%RCX |
0x443217 MOV %RCX,%RAX |
0x44321a MOV %RCX,-0x38(%RBP) |
0x44321e SUB -0x30(%RBP),%RCX |
0x443222 MOV 0xb0(%RBP),%RAX |
0x443229 VMOVSD 0x8(%RAX,%RCX,8),%XMM0 |
0x44322f MOV 0x40(%RBP),%RAX |
0x443233 MOV -0x50(%RBP),%RSI |
0x443237 VUCOMISD -0x8(%RAX,%RSI,8),%XMM0 |
0x44323d JB 443140 |
0x443243 MOV 0x38(%RBP),%RAX |
0x443247 MOV -0x50(%RBP),%RSI |
0x44324b VMOVSD -0x8(%RAX,%RSI,8),%XMM0 |
0x443251 MOV 0xb0(%RBP),%RAX |
0x443258 VUCOMISD (%RAX,%RCX,8),%XMM0 |
0x44325d JBE 443140 |
0x443263 MOV 0xe0(%RBP),%RSI |
0x44326a MOV (%RSI),%RDI |
0x44326d IMUL %RCX,%RDI |
0x443271 ADD 0x90(%RBP),%RDI |
0x443278 MOV 0x68(%RBP),%RSI |
0x44327c MOV -0x50(%RBP),%R11 |
0x443280 VMOVSD -0x8(%RSI,%R11,8),%XMM0 |
0x443287 VMOVSD %XMM0,(%RDI,%R14,8) |
0x44328d MOV 0xf0(%RBP),%RSI |
0x443294 IMUL (%RSI),%RCX |
0x443298 ADD 0x98(%RBP),%RCX |
0x44329f MOV 0x70(%RBP),%RSI |
0x4432a3 VMOVSD -0x8(%RSI,%R11,8),%XMM0 |
0x4432aa MOV 0x88(%RBP),%RSI |
0x4432b1 VMOVSD %XMM0,(%RCX,%R14,8) |
0x4432b7 MOV 0x60(%RBP),%RAX |
0x4432bb VMOVSD -0x8(%RAX,%R11,8),%XMM0 |
0x4432c2 MOV 0x100(%RBP),%RAX |
0x4432c9 MOV (%RAX),%R13 |
0x4432cc MOV 0x58(%RBP),%RAX |
0x4432d0 VMOVSD -0x8(%RAX,%R11,8),%XMM1 |
0x4432d7 MOV 0x110(%RBP),%RAX |
0x4432de MOV (%RAX),%R11 |
0x4432e1 MOV -0xb0(%RBP),%RCX |
0x4432e8 MOV %RCX,%R14 |
0x4432eb IMUL %R11,%R14 |
0x4432ef MOV -0xa8(%RBP),%RAX |
0x4432f6 ADD %R10,%RAX |
0x4432f9 ADD %RAX,%R14 |
0x4432fc MOV %RCX,%RAX |
0x4432ff IMUL %R13,%RAX |
0x443303 ADD -0xa0(%RBP),%R10 |
0x44330a ADD %RAX,%R10 |
0x44330d VBROADCASTSD %XMM0,%ZMM2 |
0x443313 VBROADCASTSD %XMM1,%ZMM3 |
0x443319 XOR %R15D,%R15D |
0x44331c MOV %R11,-0x40(%RBP) |
0x443320 JMP 4437f3 |
0x443340 JE 443980 |
0x443346 CMP $0x3,%ECX |
0x443349 JNE 443140 |
0x44334f MOV -0x38(%RBP),%RCX |
0x443353 SUB %RBX,%RCX |
0x443356 MOV 0xb8(%RBP),%RAX |
0x44335d VMOVSD (%RAX,%RCX,8),%XMM0 |
0x443362 MOV -0xc0(%RBP),%RSI |
0x443369 VUCOMISD (%RSI),%XMM0 |
0x44336d JNE 443140 |
0x443373 JP 443140 |
0x443379 MOVSXD -0x64(%RBP),%RDI |
0x44337d MOV %RDI,%RAX |
0x443380 MOV %RDI,-0x40(%RBP) |
0x443384 SUB -0x30(%RBP),%RDI |
0x443388 MOV 0xb0(%RBP),%RAX |
0x44338f VMOVSD (%RAX,%RDI,8),%XMM0 |
0x443394 MOV -0xb8(%RBP),%RSI |
0x44339b VUCOMISD (%RSI),%XMM0 |
0x44339f JNE 443140 |
0x4433a5 JP 443140 |
0x4433ab MOV 0xe0(%RBP),%RSI |
0x4433b2 MOV (%RSI),%RSI |
0x4433b5 IMUL %RDI,%RSI |
0x4433b9 ADD 0x90(%RBP),%RSI |
0x4433c0 MOV 0x68(%RBP),%R8 |
0x4433c4 MOV -0x50(%RBP),%R11 |
0x4433c8 VMOVSD -0x8(%R8,%R11,8),%XMM0 |
0x4433cf VMOVSD %XMM0,(%RSI,%RCX,8) |
0x4433d4 MOV 0xf0(%RBP),%RSI |
0x4433db IMUL (%RSI),%RDI |
0x4433df ADD 0x98(%RBP),%RDI |
0x4433e6 MOV 0x70(%RBP),%RSI |
0x4433ea VMOVSD -0x8(%RSI,%R11,8),%XMM0 |
0x4433f1 MOV 0x88(%RBP),%RSI |
0x4433f8 VMOVSD %XMM0,(%RDI,%RCX,8) |
0x4433fd MOV 0x60(%RBP),%RCX |
0x443401 VMOVSD -0x8(%RCX,%R11,8),%XMM0 |
0x443408 MOV 0x100(%RBP),%RCX |
0x44340f MOV (%RCX),%R12 |
0x443412 MOV 0x58(%RBP),%RAX |
0x443416 VMOVSD -0x8(%RAX,%R11,8),%XMM1 |
0x44341d MOV 0x110(%RBP),%RCX |
0x443424 MOV (%RCX),%R11 |
0x443427 MOV -0xb0(%RBP),%RDI |
0x44342e MOV %RDI,%R14 |
0x443431 IMUL %R11,%R14 |
0x443435 MOV -0xa8(%RBP),%RAX |
0x44343c ADD %RAX,%R14 |
0x44343f ADD %R10,%R14 |
0x443442 MOV %RDI,%RCX |
0x443445 IMUL %R12,%RCX |
0x443449 ADD -0xa0(%RBP),%R10 |
0x443450 ADD %RCX,%R10 |
0x443453 VBROADCASTSD %XMM0,%ZMM2 |
0x443459 VBROADCASTSD %XMM1,%ZMM3 |
0x44345f XOR %R15D,%R15D |
0x443462 JMP 443570 |
(354) 0x443480 MOV -0x40(%RBP),%RAX |
(354) 0x443484 LEA (%R15,%RAX,1),%R8 |
(354) 0x443488 SUB -0x30(%RBP),%R8 |
(354) 0x44348c MOV %R12,%R13 |
(354) 0x44348f IMUL %R8,%R13 |
(354) 0x443493 ADD %RDX,%RDI |
(354) 0x443496 IMUL %R11,%R8 |
(354) 0x44349a MOV 0x80(%RBP),%RAX |
(354) 0x4434a1 LEA (%RSI,%R13,1),%RCX |
(354) 0x4434a5 MOV %RDI,%RSI |
(354) 0x4434a8 SUB %RBX,%RSI |
(354) 0x4434ab VMOVSD %XMM0,0x28(%RCX,%RSI,8) |
(354) 0x4434b1 LEA (%RAX,%R8,1),%RCX |
(354) 0x4434b5 VMOVSD %XMM1,0x28(%RCX,%RSI,8) |
(354) 0x4434bb MOV 0x88(%RBP),%RSI |
(354) 0x4434c2 LEA (%RSI,%R13,1),%RCX |
(354) 0x4434c6 MOV %RDI,%RSI |
(354) 0x4434c9 SUB %RBX,%RSI |
(354) 0x4434cc VMOVSD %XMM0,0x20(%RCX,%RSI,8) |
(354) 0x4434d2 LEA (%RAX,%R8,1),%RCX |
(354) 0x4434d6 VMOVSD %XMM1,0x20(%RCX,%RSI,8) |
(354) 0x4434dc MOV 0x88(%RBP),%RSI |
(354) 0x4434e3 LEA (%RSI,%R13,1),%RCX |
(354) 0x4434e7 MOV %RDI,%RSI |
(354) 0x4434ea SUB %RBX,%RSI |
(354) 0x4434ed VMOVSD %XMM0,0x18(%RCX,%RSI,8) |
(354) 0x4434f3 LEA (%RAX,%R8,1),%RCX |
(354) 0x4434f7 VMOVSD %XMM1,0x18(%RCX,%RSI,8) |
(354) 0x4434fd MOV 0x88(%RBP),%RSI |
(354) 0x443504 LEA (%RSI,%R13,1),%RCX |
(354) 0x443508 MOV %RDI,%RSI |
(354) 0x44350b SUB %RBX,%RSI |
(354) 0x44350e VMOVSD %XMM0,0x10(%RCX,%RSI,8) |
(354) 0x443514 LEA (%RAX,%R8,1),%RCX |
(354) 0x443518 VMOVSD %XMM1,0x10(%RCX,%RSI,8) |
(354) 0x44351e MOV 0x88(%RBP),%RSI |
(354) 0x443525 LEA (%RSI,%R13,1),%RCX |
(354) 0x443529 MOV %RDI,%RSI |
(354) 0x44352c SUB %RBX,%RSI |
(354) 0x44352f VMOVSD %XMM0,0x8(%RCX,%RSI,8) |
(354) 0x443535 LEA (%RAX,%R8,1),%RCX |
(354) 0x443539 VMOVSD %XMM1,0x8(%RCX,%RSI,8) |
(354) 0x44353f MOV 0x88(%RBP),%RSI |
(354) 0x443546 ADD %RSI,%R13 |
(354) 0x443549 SUB %RBX,%RDI |
(354) 0x44354c VMOVSD %XMM0,(%R13,%RDI,8) |
(354) 0x443553 ADD %RAX,%R8 |
(354) 0x443556 VMOVSD %XMM1,(%R8,%RDI,8) |
(354) 0x44355c ADD %R11,%R14 |
(354) 0x44355f ADD %R12,%R10 |
(354) 0x443562 CMP $0x1,%R15 |
(354) 0x443566 LEA 0x1(%R15),%R15 |
(354) 0x44356a JE 443140 |
(354) 0x443570 MOV -0x38(%RBP),%RAX |
(354) 0x443574 LEA 0x1(%RAX),%RCX |
(354) 0x443578 CMP %RDX,%RCX |
(354) 0x44357b CMOVLE %RDX,%RCX |
(354) 0x44357f SUB %RDX,%RCX |
(354) 0x443582 LEA 0x1(%RCX),%RDI |
(354) 0x443586 CMP $0x8,%RDI |
(354) 0x44358a JB 4435b7 |
(354) 0x44358c MOV %R9,%R8 |
(354) 0x44358f XOR %R13D,%R13D |
(354) 0x443592 NOPW %CS:(%RAX,%RAX,1) |
(355) 0x4435a0 VMOVUPD %ZMM2,(%R10,%R13,1) |
(355) 0x4435a7 VMOVUPD %ZMM3,(%R14,%R13,1) |
(355) 0x4435ae ADD $0x40,%R13 |
(355) 0x4435b2 INC %R8 |
(355) 0x4435b5 JNE 4435a0 |
(354) 0x4435b7 AND $-0x8,%RDI |
(354) 0x4435bb SUB %RDI,%RCX |
(354) 0x4435be CMP $0x3,%RCX |
(354) 0x4435c2 JGE 443600 |
(354) 0x4435c4 TEST %RCX,%RCX |
(354) 0x4435c7 JLE 4436c0 |
(354) 0x4435cd MOV -0x40(%RBP),%RAX |
(354) 0x4435d1 LEA (%R15,%RAX,1),%R8 |
(354) 0x4435d5 SUB -0x30(%RBP),%R8 |
(354) 0x4435d9 MOV %R12,%R13 |
(354) 0x4435dc IMUL %R8,%R13 |
(354) 0x4435e0 ADD %RDX,%RDI |
(354) 0x4435e3 IMUL %R11,%R8 |
(354) 0x4435e7 CMP $0x1,%RCX |
(354) 0x4435eb MOV 0x80(%RBP),%RAX |
(354) 0x4435f2 JNE 443504 |
(354) 0x4435f8 JMP 443525 |
(354) 0x443600 CMP $0x5,%RCX |
(354) 0x443604 JGE 443640 |
(354) 0x443606 MOV -0x40(%RBP),%RAX |
(354) 0x44360a LEA (%R15,%RAX,1),%R8 |
(354) 0x44360e SUB -0x30(%RBP),%R8 |
(354) 0x443612 MOV %R12,%R13 |
(354) 0x443615 IMUL %R8,%R13 |
(354) 0x443619 ADD %RDX,%RDI |
(354) 0x44361c IMUL %R11,%R8 |
(354) 0x443620 CMP $0x4,%RCX |
(354) 0x443624 MOV 0x80(%RBP),%RAX |
(354) 0x44362b JE 4434c2 |
(354) 0x443631 JMP 4434e3 |
(354) 0x443640 JE 443480 |
(354) 0x443646 CMP $0x6,%RCX |
(354) 0x44364a JNE 44355c |
(354) 0x443650 MOV -0x40(%RBP),%RAX |
(354) 0x443654 LEA (%R15,%RAX,1),%R8 |
(354) 0x443658 SUB -0x30(%RBP),%R8 |
(354) 0x44365c MOV %R12,%R13 |
(354) 0x44365f IMUL %R8,%R13 |
(354) 0x443663 LEA (%RSI,%R13,1),%RCX |
(354) 0x443667 ADD %RDX,%RDI |
(354) 0x44366a MOV %RDI,%RSI |
(354) 0x44366d SUB %RBX,%RSI |
(354) 0x443670 VMOVSD %XMM0,0x30(%RCX,%RSI,8) |
(354) 0x443676 IMUL %R11,%R8 |
(354) 0x44367a MOV 0x80(%RBP),%RAX |
(354) 0x443681 LEA (%RAX,%R8,1),%RCX |
(354) 0x443685 VMOVSD %XMM1,0x30(%RCX,%RSI,8) |
(354) 0x44368b MOV 0x88(%RBP),%RSI |
(354) 0x443692 JMP 4434a1 |
(354) 0x4436c0 JNE 44355c |
(354) 0x4436c6 MOV -0x40(%RBP),%RAX |
(354) 0x4436ca LEA (%R15,%RAX,1),%R8 |
(354) 0x4436ce SUB -0x30(%RBP),%R8 |
(354) 0x4436d2 MOV %R12,%R13 |
(354) 0x4436d5 IMUL %R8,%R13 |
(354) 0x4436d9 ADD %RDX,%RDI |
(354) 0x4436dc IMUL %R11,%R8 |
(354) 0x4436e0 MOV 0x80(%RBP),%RAX |
(354) 0x4436e7 JMP 443546 |
(356) 0x443700 MOV -0x38(%RBP),%RAX |
(356) 0x443704 LEA (%R15,%RAX,1),%RDI |
(356) 0x443708 SUB -0x30(%RBP),%RDI |
(356) 0x44370c MOV %R13,%RAX |
(356) 0x44370f IMUL %RDI,%RAX |
(356) 0x443713 ADD %RDX,%R12 |
(356) 0x443716 IMUL %R11,%RDI |
(356) 0x44371a MOV 0x80(%RBP),%R11 |
(356) 0x443721 LEA (%RSI,%RAX,1),%RCX |
(356) 0x443725 MOV %R12,%RSI |
(356) 0x443728 SUB %RBX,%RSI |
(356) 0x44372b VMOVSD %XMM0,0x28(%RCX,%RSI,8) |
(356) 0x443731 LEA (%R11,%RDI,1),%RCX |
(356) 0x443735 VMOVSD %XMM1,0x28(%RCX,%RSI,8) |
(356) 0x44373b MOV 0x88(%RBP),%RSI |
(356) 0x443742 LEA (%RSI,%RAX,1),%RCX |
(356) 0x443746 MOV %R12,%RSI |
(356) 0x443749 SUB %RBX,%RSI |
(356) 0x44374c VMOVSD %XMM0,0x20(%RCX,%RSI,8) |
(356) 0x443752 LEA (%R11,%RDI,1),%RCX |
(356) 0x443756 VMOVSD %XMM1,0x20(%RCX,%RSI,8) |
(356) 0x44375c MOV 0x88(%RBP),%RSI |
(356) 0x443763 LEA (%RSI,%RAX,1),%RCX |
(356) 0x443767 MOV %R12,%RSI |
(356) 0x44376a SUB %RBX,%RSI |
(356) 0x44376d VMOVSD %XMM0,0x18(%RCX,%RSI,8) |
(356) 0x443773 LEA (%R11,%RDI,1),%RCX |
(356) 0x443777 VMOVSD %XMM1,0x18(%RCX,%RSI,8) |
(356) 0x44377d MOV 0x88(%RBP),%RSI |
(356) 0x443784 LEA (%RSI,%RAX,1),%RCX |
(356) 0x443788 MOV %R12,%RSI |
(356) 0x44378b SUB %RBX,%RSI |
(356) 0x44378e VMOVSD %XMM0,0x10(%RCX,%RSI,8) |
(356) 0x443794 LEA (%R11,%RDI,1),%RCX |
(356) 0x443798 VMOVSD %XMM1,0x10(%RCX,%RSI,8) |
(356) 0x44379e MOV 0x88(%RBP),%RSI |
(356) 0x4437a5 LEA (%RSI,%RAX,1),%RCX |
(356) 0x4437a9 MOV %R12,%RSI |
(356) 0x4437ac SUB %RBX,%RSI |
(356) 0x4437af VMOVSD %XMM0,0x8(%RCX,%RSI,8) |
(356) 0x4437b5 LEA (%R11,%RDI,1),%RCX |
(356) 0x4437b9 VMOVSD %XMM1,0x8(%RCX,%RSI,8) |
(356) 0x4437bf MOV 0x88(%RBP),%RSI |
(356) 0x4437c6 ADD %RSI,%RAX |
(356) 0x4437c9 SUB %RBX,%R12 |
(356) 0x4437cc VMOVSD %XMM0,(%RAX,%R12,8) |
(356) 0x4437d2 ADD %R11,%RDI |
(356) 0x4437d5 VMOVSD %XMM1,(%RDI,%R12,8) |
(356) 0x4437db MOV -0x40(%RBP),%R11 |
(356) 0x4437df ADD %R11,%R14 |
(356) 0x4437e2 ADD %R13,%R10 |
(356) 0x4437e5 CMP $0x1,%R15 |
(356) 0x4437e9 LEA 0x1(%R15),%R15 |
(356) 0x4437ed JE 443140 |
(356) 0x4437f3 CMP %RDX,%R8 |
(356) 0x4437f6 MOV %RDX,%RCX |
(356) 0x4437f9 CMOVG %R8,%RCX |
(356) 0x4437fd SUB %RDX,%RCX |
(356) 0x443800 LEA 0x1(%RCX),%R12 |
(356) 0x443804 CMP $0x8,%R12 |
(356) 0x443808 JB 443827 |
(356) 0x44380a MOV %R9,%RAX |
(356) 0x44380d XOR %EDI,%EDI |
(356) 0x44380f NOP |
(357) 0x443810 VMOVUPD %ZMM2,(%R10,%RDI,1) |
(357) 0x443817 VMOVUPD %ZMM3,(%R14,%RDI,1) |
(357) 0x44381e ADD $0x40,%RDI |
(357) 0x443822 INC %RAX |
(357) 0x443825 JNE 443810 |
(356) 0x443827 AND $-0x8,%R12 |
(356) 0x44382b SUB %R12,%RCX |
(356) 0x44382e CMP $0x3,%RCX |
(356) 0x443832 JGE 443880 |
(356) 0x443834 TEST %RCX,%RCX |
(356) 0x443837 JLE 443940 |
(356) 0x44383d MOV -0x38(%RBP),%RAX |
(356) 0x443841 LEA (%R15,%RAX,1),%RDI |
(356) 0x443845 SUB -0x30(%RBP),%RDI |
(356) 0x443849 MOV %R13,%RAX |
(356) 0x44384c IMUL %RDI,%RAX |
(356) 0x443850 ADD %RDX,%R12 |
(356) 0x443853 IMUL %R11,%RDI |
(356) 0x443857 CMP $0x1,%RCX |
(356) 0x44385b MOV 0x80(%RBP),%R11 |
(356) 0x443862 JNE 443784 |
(356) 0x443868 JMP 4437a5 |
(356) 0x443880 CMP $0x5,%RCX |
(356) 0x443884 JGE 4438c0 |
(356) 0x443886 MOV -0x38(%RBP),%RAX |
(356) 0x44388a LEA (%R15,%RAX,1),%RDI |
(356) 0x44388e SUB -0x30(%RBP),%RDI |
(356) 0x443892 MOV %R13,%RAX |
(356) 0x443895 IMUL %RDI,%RAX |
(356) 0x443899 ADD %RDX,%R12 |
(356) 0x44389c IMUL %R11,%RDI |
(356) 0x4438a0 CMP $0x4,%RCX |
(356) 0x4438a4 MOV 0x80(%RBP),%R11 |
(356) 0x4438ab JE 443742 |
(356) 0x4438b1 JMP 443763 |
(356) 0x4438c0 JE 443700 |
(356) 0x4438c6 CMP $0x6,%RCX |
(356) 0x4438ca JNE 4437df |
(356) 0x4438d0 MOV -0x38(%RBP),%RAX |
(356) 0x4438d4 LEA (%R15,%RAX,1),%RDI |
(356) 0x4438d8 SUB -0x30(%RBP),%RDI |
(356) 0x4438dc MOV %R13,%RAX |
(356) 0x4438df IMUL %RDI,%RAX |
(356) 0x4438e3 LEA (%RSI,%RAX,1),%RCX |
(356) 0x4438e7 ADD %RDX,%R12 |
(356) 0x4438ea MOV %R12,%RSI |
(356) 0x4438ed SUB %RBX,%RSI |
(356) 0x4438f0 VMOVSD %XMM0,0x30(%RCX,%RSI,8) |
(356) 0x4438f6 IMUL %R11,%RDI |
(356) 0x4438fa MOV 0x80(%RBP),%R11 |
(356) 0x443901 LEA (%R11,%RDI,1),%RCX |
(356) 0x443905 VMOVSD %XMM1,0x30(%RCX,%RSI,8) |
(356) 0x44390b MOV 0x88(%RBP),%RSI |
(356) 0x443912 JMP 443721 |
(356) 0x443940 JNE 4437df |
(356) 0x443946 MOV -0x38(%RBP),%RAX |
(356) 0x44394a LEA (%R15,%RAX,1),%RDI |
(356) 0x44394e SUB -0x30(%RBP),%RDI |
(356) 0x443952 MOV %R13,%RAX |
(356) 0x443955 IMUL %RDI,%RAX |
(356) 0x443959 ADD %RDX,%R12 |
(356) 0x44395c IMUL %R11,%RDI |
(356) 0x443960 MOV 0x80(%RBP),%R11 |
(356) 0x443967 JMP 4437c6 |
0x443980 MOV -0x38(%RBP),%RCX |
0x443984 SUB %RBX,%RCX |
0x443987 MOV 0xa8(%RBP),%RAX |
0x44398e VMOVSD (%RAX,%RCX,8),%XMM0 |
0x443993 MOV -0xc0(%RBP),%RSI |
0x44399a VSUBSD (%RSI),%XMM0,%XMM0 |
0x44399e VMULSD %XMM0,%XMM0,%XMM0 |
0x4439a2 MOVSXD -0x64(%RBP),%RDI |
0x4439a6 MOV %RDI,%RAX |
0x4439a9 MOV %RDI,-0x40(%RBP) |
0x4439ad SUB -0x30(%RBP),%RDI |
0x4439b1 MOV 0xa0(%RBP),%RAX |
0x4439b8 VMOVSD (%RAX,%RDI,8),%XMM1 |
0x4439bd MOV -0xb8(%RBP),%RSI |
0x4439c4 VSUBSD (%RSI),%XMM1,%XMM1 |
0x4439c8 VFMADD213SD %XMM0,%XMM1,%XMM1 |
0x4439cd VSQRTSD %XMM1,%XMM1,%XMM0 |
0x4439d1 MOV 0x30(%RBP),%RAX |
0x4439d5 MOV -0x50(%RBP),%RSI |
0x4439d9 VMOVSD -0x8(%RAX,%RSI,8),%XMM1 |
0x4439df VUCOMISD %XMM0,%XMM1 |
0x4439e3 JB 443140 |
0x4439e9 MOV 0xe0(%RBP),%RSI |
0x4439f0 MOV (%RSI),%RSI |
0x4439f3 IMUL %RDI,%RSI |
0x4439f7 ADD 0x90(%RBP),%RSI |
0x4439fe MOV 0x68(%RBP),%R8 |
0x443a02 MOV -0x50(%RBP),%R11 |
0x443a06 VMOVSD -0x8(%R8,%R11,8),%XMM0 |
0x443a0d VMOVSD %XMM0,(%RSI,%RCX,8) |
0x443a12 MOV 0xf0(%RBP),%RSI |
0x443a19 IMUL (%RSI),%RDI |
0x443a1d ADD 0x98(%RBP),%RDI |
0x443a24 MOV 0x70(%RBP),%RSI |
0x443a28 VMOVSD -0x8(%RSI,%R11,8),%XMM0 |
0x443a2f MOV 0x88(%RBP),%RSI |
0x443a36 VMOVSD %XMM0,(%RDI,%RCX,8) |
0x443a3b MOV 0x60(%RBP),%RCX |
0x443a3f VMOVSD -0x8(%RCX,%R11,8),%XMM0 |
0x443a46 MOV 0x100(%RBP),%RCX |
0x443a4d MOV (%RCX),%R12 |
0x443a50 MOV 0x58(%RBP),%RAX |
0x443a54 VMOVSD -0x8(%RAX,%R11,8),%XMM1 |
0x443a5b MOV 0x110(%RBP),%RCX |
0x443a62 MOV (%RCX),%R11 |
0x443a65 MOV -0xb0(%RBP),%RDI |
0x443a6c MOV %RDI,%R14 |
0x443a6f IMUL %R11,%R14 |
0x443a73 MOV -0xa8(%RBP),%RAX |
0x443a7a ADD %RAX,%R14 |
0x443a7d ADD %R10,%R14 |
0x443a80 MOV %RDI,%RCX |
0x443a83 IMUL %R12,%RCX |
0x443a87 ADD -0xa0(%RBP),%R10 |
0x443a8e ADD %RCX,%R10 |
0x443a91 VBROADCASTSD %XMM0,%ZMM2 |
0x443a97 VBROADCASTSD %XMM1,%ZMM3 |
0x443a9d XOR %R15D,%R15D |
0x443aa0 JMP 443bb0 |
(352) 0x443ac0 MOV -0x40(%RBP),%RAX |
(352) 0x443ac4 LEA (%R15,%RAX,1),%R8 |
(352) 0x443ac8 SUB -0x30(%RBP),%R8 |
(352) 0x443acc MOV %R12,%R13 |
(352) 0x443acf IMUL %R8,%R13 |
(352) 0x443ad3 ADD %RDX,%RDI |
(352) 0x443ad6 IMUL %R11,%R8 |
(352) 0x443ada MOV 0x80(%RBP),%RAX |
(352) 0x443ae1 LEA (%RSI,%R13,1),%RCX |
(352) 0x443ae5 MOV %RDI,%RSI |
(352) 0x443ae8 SUB %RBX,%RSI |
(352) 0x443aeb VMOVSD %XMM0,0x28(%RCX,%RSI,8) |
(352) 0x443af1 LEA (%RAX,%R8,1),%RCX |
(352) 0x443af5 VMOVSD %XMM1,0x28(%RCX,%RSI,8) |
(352) 0x443afb MOV 0x88(%RBP),%RSI |
(352) 0x443b02 LEA (%RSI,%R13,1),%RCX |
(352) 0x443b06 MOV %RDI,%RSI |
(352) 0x443b09 SUB %RBX,%RSI |
(352) 0x443b0c VMOVSD %XMM0,0x20(%RCX,%RSI,8) |
(352) 0x443b12 LEA (%RAX,%R8,1),%RCX |
(352) 0x443b16 VMOVSD %XMM1,0x20(%RCX,%RSI,8) |
(352) 0x443b1c MOV 0x88(%RBP),%RSI |
(352) 0x443b23 LEA (%RSI,%R13,1),%RCX |
(352) 0x443b27 MOV %RDI,%RSI |
(352) 0x443b2a SUB %RBX,%RSI |
(352) 0x443b2d VMOVSD %XMM0,0x18(%RCX,%RSI,8) |
(352) 0x443b33 LEA (%RAX,%R8,1),%RCX |
(352) 0x443b37 VMOVSD %XMM1,0x18(%RCX,%RSI,8) |
(352) 0x443b3d MOV 0x88(%RBP),%RSI |
(352) 0x443b44 LEA (%RSI,%R13,1),%RCX |
(352) 0x443b48 MOV %RDI,%RSI |
(352) 0x443b4b SUB %RBX,%RSI |
(352) 0x443b4e VMOVSD %XMM0,0x10(%RCX,%RSI,8) |
(352) 0x443b54 LEA (%RAX,%R8,1),%RCX |
(352) 0x443b58 VMOVSD %XMM1,0x10(%RCX,%RSI,8) |
(352) 0x443b5e MOV 0x88(%RBP),%RSI |
(352) 0x443b65 LEA (%RSI,%R13,1),%RCX |
(352) 0x443b69 MOV %RDI,%RSI |
(352) 0x443b6c SUB %RBX,%RSI |
(352) 0x443b6f VMOVSD %XMM0,0x8(%RCX,%RSI,8) |
(352) 0x443b75 LEA (%RAX,%R8,1),%RCX |
(352) 0x443b79 VMOVSD %XMM1,0x8(%RCX,%RSI,8) |
(352) 0x443b7f MOV 0x88(%RBP),%RSI |
(352) 0x443b86 ADD %RSI,%R13 |
(352) 0x443b89 SUB %RBX,%RDI |
(352) 0x443b8c VMOVSD %XMM0,(%R13,%RDI,8) |
(352) 0x443b93 ADD %RAX,%R8 |
(352) 0x443b96 VMOVSD %XMM1,(%R8,%RDI,8) |
(352) 0x443b9c ADD %R11,%R14 |
(352) 0x443b9f ADD %R12,%R10 |
(352) 0x443ba2 CMP $0x1,%R15 |
(352) 0x443ba6 LEA 0x1(%R15),%R15 |
(352) 0x443baa JE 443140 |
(352) 0x443bb0 MOV -0x38(%RBP),%RAX |
(352) 0x443bb4 LEA 0x1(%RAX),%RCX |
(352) 0x443bb8 CMP %RDX,%RCX |
(352) 0x443bbb CMOVLE %RDX,%RCX |
(352) 0x443bbf SUB %RDX,%RCX |
(352) 0x443bc2 LEA 0x1(%RCX),%RDI |
(352) 0x443bc6 CMP $0x8,%RDI |
(352) 0x443bca JB 443bf7 |
(352) 0x443bcc MOV %R9,%R8 |
(352) 0x443bcf XOR %R13D,%R13D |
(352) 0x443bd2 NOPW %CS:(%RAX,%RAX,1) |
(353) 0x443be0 VMOVUPD %ZMM2,(%R10,%R13,1) |
(353) 0x443be7 VMOVUPD %ZMM3,(%R14,%R13,1) |
(353) 0x443bee ADD $0x40,%R13 |
(353) 0x443bf2 INC %R8 |
(353) 0x443bf5 JNE 443be0 |
(352) 0x443bf7 AND $-0x8,%RDI |
(352) 0x443bfb SUB %RDI,%RCX |
(352) 0x443bfe CMP $0x3,%RCX |
(352) 0x443c02 JGE 443c40 |
(352) 0x443c04 TEST %RCX,%RCX |
(352) 0x443c07 JLE 443d00 |
(352) 0x443c0d MOV -0x40(%RBP),%RAX |
(352) 0x443c11 LEA (%R15,%RAX,1),%R8 |
(352) 0x443c15 SUB -0x30(%RBP),%R8 |
(352) 0x443c19 MOV %R12,%R13 |
(352) 0x443c1c IMUL %R8,%R13 |
(352) 0x443c20 ADD %RDX,%RDI |
(352) 0x443c23 IMUL %R11,%R8 |
(352) 0x443c27 CMP $0x1,%RCX |
(352) 0x443c2b MOV 0x80(%RBP),%RAX |
(352) 0x443c32 JNE 443b44 |
(352) 0x443c38 JMP 443b65 |
(352) 0x443c40 CMP $0x5,%RCX |
(352) 0x443c44 JGE 443c80 |
(352) 0x443c46 MOV -0x40(%RBP),%RAX |
(352) 0x443c4a LEA (%R15,%RAX,1),%R8 |
(352) 0x443c4e SUB -0x30(%RBP),%R8 |
(352) 0x443c52 MOV %R12,%R13 |
(352) 0x443c55 IMUL %R8,%R13 |
(352) 0x443c59 ADD %RDX,%RDI |
(352) 0x443c5c IMUL %R11,%R8 |
(352) 0x443c60 CMP $0x4,%RCX |
(352) 0x443c64 MOV 0x80(%RBP),%RAX |
(352) 0x443c6b JE 443b02 |
(352) 0x443c71 JMP 443b23 |
(352) 0x443c80 JE 443ac0 |
(352) 0x443c86 CMP $0x6,%RCX |
(352) 0x443c8a JNE 443b9c |
(352) 0x443c90 MOV -0x40(%RBP),%RAX |
(352) 0x443c94 LEA (%R15,%RAX,1),%R8 |
(352) 0x443c98 SUB -0x30(%RBP),%R8 |
(352) 0x443c9c MOV %R12,%R13 |
(352) 0x443c9f IMUL %R8,%R13 |
(352) 0x443ca3 LEA (%RSI,%R13,1),%RCX |
(352) 0x443ca7 ADD %RDX,%RDI |
(352) 0x443caa MOV %RDI,%RSI |
(352) 0x443cad SUB %RBX,%RSI |
(352) 0x443cb0 VMOVSD %XMM0,0x30(%RCX,%RSI,8) |
(352) 0x443cb6 IMUL %R11,%R8 |
(352) 0x443cba MOV 0x80(%RBP),%RAX |
(352) 0x443cc1 LEA (%RAX,%R8,1),%RCX |
(352) 0x443cc5 VMOVSD %XMM1,0x30(%RCX,%RSI,8) |
(352) 0x443ccb MOV 0x88(%RBP),%RSI |
(352) 0x443cd2 JMP 443ae1 |
(352) 0x443d00 JNE 443b9c |
(352) 0x443d06 MOV -0x40(%RBP),%RAX |
(352) 0x443d0a LEA (%R15,%RAX,1),%R8 |
(352) 0x443d0e SUB -0x30(%RBP),%R8 |
(352) 0x443d12 MOV %R12,%R13 |
(352) 0x443d15 IMUL %R8,%R13 |
(352) 0x443d19 ADD %RDX,%RDI |
(352) 0x443d1c IMUL %R11,%R8 |
(352) 0x443d20 MOV 0x80(%RBP),%RAX |
(352) 0x443d27 JMP 443b86 |
/home/eoseret/qaas_runs_CPU_9468/171-152-3172/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90: 87 - 163 |
-------------------------------------------------------------------------------- |
87: DO k=y_min-2,y_max+2 |
[...] |
128: DO j=x_min-2,x_max+2 |
129: IF(state_geometry(state).EQ.g_rect ) THEN |
130: IF(vertexx(j+1).GE.state_xmin(state).AND.vertexx(j).LT.state_xmax(state)) THEN |
131: IF(vertexy(k+1).GE.state_ymin(state).AND.vertexy(k).LT.state_ymax(state)) THEN |
132: energy0(j,k)=state_energy(state) |
133: density0(j,k)=state_density(state) |
134: DO kt=k,k+1 |
135: DO jt=j,j+1 |
136: xvel0(jt,kt)=state_xvel(state) |
137: yvel0(jt,kt)=state_yvel(state) |
138: ENDDO |
139: ENDDO |
140: ENDIF |
141: ENDIF |
142: ELSEIF(state_geometry(state).EQ.g_circ ) THEN |
143: radius=SQRT((cellx(j)-x_cent)*(cellx(j)-x_cent)+(celly(k)-y_cent)*(celly(k)-y_cent)) |
144: IF(radius.LE.state_radius(state))THEN |
145: energy0(j,k)=state_energy(state) |
146: density0(j,k)=state_density(state) |
147: DO kt=k,k+1 |
148: DO jt=j,j+1 |
149: xvel0(jt,kt)=state_xvel(state) |
150: yvel0(jt,kt)=state_yvel(state) |
151: ENDDO |
152: ENDDO |
153: ENDIF |
154: ELSEIF(state_geometry(state).EQ.g_point) THEN |
155: IF(vertexx(j).EQ.x_cent .AND. vertexy(k).EQ.y_cent) THEN |
156: energy0(j,k)=state_energy(state) |
157: density0(j,k)=state_density(state) |
158: DO kt=k,k+1 |
159: DO jt=j,j+1 |
160: xvel0(jt,kt)=state_xvel(state) |
161: yvel0(jt,kt)=state_yvel(state) |
162: ENDDO |
163: ENDDO |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.53 |
CQA speedup if FP arith vectorized | 2.85 |
CQA speedup if fully vectorized | 12.72 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.10 |
Bottlenecks | P2, P3, P11, |
Function | generate_chunk_kernel_.DIR.OMP.PARALLEL.2 |
Source | generate_chunk_kernel.f90:128-133,generate_chunk_kernel.f90:136-137,generate_chunk_kernel.f90:143-146,generate_chunk_kernel.f90:149-150,generate_chunk_kernel.f90:155-157,generate_chunk_kernel.f90:160-161 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 41.33 |
CQA cycles if no scalar integer | 16.33 |
CQA cycles if FP arith vectorized | 14.50 |
CQA cycles if fully vectorized | 3.25 |
Front-end cycles | 37.50 |
DIV/SQRT cycles | 16.20 |
P0 cycles | 19.13 |
P1 cycles | 41.33 |
P2 cycles | 41.33 |
P3 cycles | 7.00 |
P4 cycles | 16.20 |
P5 cycles | 16.10 |
P6 cycles | 7.00 |
P7 cycles | 7.00 |
P8 cycles | 7.00 |
P9 cycles | 16.20 |
P10 cycles | 41.33 |
P11 cycles | 4.50 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 47.60 - 47.23 |
Stall cycles (UFS) | 9.81 - 9.39 |
Nb insns | 219.00 |
Nb uops | 225.00 |
Nb loads | 124.00 |
Nb stores | 14.00 |
Nb stack references | 36.00 |
FLOP/cycle | 0.15 |
Nb FLOP add-sub | 2.00 |
Nb FLOP mul | 1.00 |
Nb FLOP fma | 1.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 1.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 26.13 |
Bytes prefetched | 0.00 |
Bytes loaded | 972.00 |
Bytes stored | 108.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | 0.00 |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 11.88 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.05 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | 12.50 |
Vector-efficiency ratio div_sqrt | 12.50 |
Vector-efficiency ratio other | 11.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.53 |
CQA speedup if FP arith vectorized | 2.85 |
CQA speedup if fully vectorized | 12.72 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.10 |
Bottlenecks | P2, P3, P11, |
Function | generate_chunk_kernel_.DIR.OMP.PARALLEL.2 |
Source | generate_chunk_kernel.f90:128-133,generate_chunk_kernel.f90:136-137,generate_chunk_kernel.f90:143-146,generate_chunk_kernel.f90:149-150,generate_chunk_kernel.f90:155-157,generate_chunk_kernel.f90:160-161 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 41.33 |
CQA cycles if no scalar integer | 16.33 |
CQA cycles if FP arith vectorized | 14.50 |
CQA cycles if fully vectorized | 3.25 |
Front-end cycles | 37.50 |
DIV/SQRT cycles | 16.20 |
P0 cycles | 19.13 |
P1 cycles | 41.33 |
P2 cycles | 41.33 |
P3 cycles | 7.00 |
P4 cycles | 16.20 |
P5 cycles | 16.10 |
P6 cycles | 7.00 |
P7 cycles | 7.00 |
P8 cycles | 7.00 |
P9 cycles | 16.20 |
P10 cycles | 41.33 |
P11 cycles | 4.50 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 47.60 - 47.23 |
Stall cycles (UFS) | 9.81 - 9.39 |
Nb insns | 219.00 |
Nb uops | 225.00 |
Nb loads | 124.00 |
Nb stores | 14.00 |
Nb stack references | 36.00 |
FLOP/cycle | 0.15 |
Nb FLOP add-sub | 2.00 |
Nb FLOP mul | 1.00 |
Nb FLOP fma | 1.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 1.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 26.13 |
Bytes prefetched | 0.00 |
Bytes loaded | 972.00 |
Bytes stored | 108.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | 0.00 |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 11.88 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.05 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | 12.50 |
Vector-efficiency ratio div_sqrt | 12.50 |
Vector-efficiency ratio other | 11.00 |
Path / |
Function | generate_chunk_kernel_.DIR.OMP.PARALLEL.2 |
Source file and lines | generate_chunk_kernel.f90:87-163 |
Module | exec |
nb instructions | 219 |
nb uops | 225 |
loop length | 1073 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 2 |
nb stack references | 36 |
ADD-SUB / MUL ratio | 2.00 |
micro-operation queue | 37.50 cycles |
front end | 37.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 16.20 | 16.30 | 41.33 | 41.33 | 7.00 | 16.20 | 16.10 | 7.00 | 7.00 | 7.00 | 16.20 | 41.33 |
cycles | 16.20 | 19.13 | 41.33 | 41.33 | 7.00 | 16.20 | 16.10 | 7.00 | 7.00 | 7.00 | 16.20 | 41.33 |
Cycles executing div or sqrt instructions | 4.50 |
FE+BE cycles | 47.60-47.23 |
Stall cycles | 9.81-9.39 |
LM full (events) | 21.37-19.95 |
Front-end | 37.50 |
Dispatch | 41.33 |
DIV/SQRT | 4.50 |
Overall L1 | 41.33 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
all | 10% |
load | 12% |
store | 11% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | 12% |
other | 12% |
all | 11% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | 12% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x60(%RBP),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x138(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x58(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x130(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RAX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0xd0(%RBP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 443080 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x540> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD %R8D,%RDX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
LEA (,%RDX,8),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMOVG %RSI,%R9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB %RDX,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
INC %R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x3,%R9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
NEG %R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x128(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP $0x2,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8D,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,-0x138(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JGE 443340 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x800> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x1,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 443140 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x600> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x38(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%RAX),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RBX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RAX,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD -0x8(%RAX,%RCX,8),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JB 443140 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x600> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x38(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RBX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x48(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD (%RAX,%RSI,8),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE 443140 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x600> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RSI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOVSXD -0x64(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB -0x30(%RBP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x8(%RAX,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD -0x8(%RAX,%RSI,8),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JB 443140 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x600> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x38(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%RSI,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD (%RAX,%RCX,8),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE 443140 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x600> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xe0(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RCX,%RDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0x90(%RBP),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x68(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RSI,%R11,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RDI,%R14,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL (%RSI),%RCX | 1 | 0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
ADD 0x98(%RBP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x70(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RSI,%R11,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RCX,%R14,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x60(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%R11,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%R11,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x110(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb0(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R11,%R14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV -0xa8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R10,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RAX,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R13,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD -0xa0(%RBP),%R10 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
ADD %RAX,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VBROADCASTSD %XMM0,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM1,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R11,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 4437f3 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0xcb3> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
JE 443980 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0xe40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x3,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 443140 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x600> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x38(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RBX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RAX,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xc0(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD (%RSI),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JNE 443140 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x600> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JP 443140 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x600> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD -0x64(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDI,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB -0x30(%RBP),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RAX,%RDI,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb8(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD (%RSI),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JNE 443140 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x600> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JP 443140 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x600> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xe0(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RDI,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0x90(%RBP),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x68(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%R8,%R11,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RSI,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL (%RSI),%RDI | 1 | 0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
ADD 0x98(%RBP),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x70(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RSI,%R11,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RDI,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x60(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RCX,%R11,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%R11,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x110(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb0(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R11,%R14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV -0xa8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RAX,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R10,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R12,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD -0xa0(%RBP),%R10 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
ADD %RCX,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VBROADCASTSD %XMM0,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM1,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 443570 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0xa30> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV -0x38(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RBX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xa8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RAX,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xc0(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VSUBSD (%RSI),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMULSD %XMM0,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOVSXD -0x64(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDI,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB -0x30(%RBP),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RAX,%RDI,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb8(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VSUBSD (%RSI),%XMM1,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VFMADD213SD %XMM0,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VSQRTSD %XMM1,%XMM1,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-19 | 4.50 |
MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%RSI,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD %XMM0,%XMM1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JB 443140 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x600> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xe0(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RDI,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0x90(%RBP),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x68(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%R8,%R11,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RSI,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL (%RSI),%RDI | 1 | 0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
ADD 0x98(%RBP),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x70(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RSI,%R11,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RDI,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x60(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RCX,%R11,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%R11,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x110(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb0(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R11,%R14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV -0xa8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RAX,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R10,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R12,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD -0xa0(%RBP),%R10 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
ADD %RCX,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VBROADCASTSD %XMM0,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM1,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 443bb0 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x1070> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Function | generate_chunk_kernel_.DIR.OMP.PARALLEL.2 |
Source file and lines | generate_chunk_kernel.f90:87-163 |
Module | exec |
nb instructions | 219 |
nb uops | 225 |
loop length | 1073 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 2 |
nb stack references | 36 |
ADD-SUB / MUL ratio | 2.00 |
micro-operation queue | 37.50 cycles |
front end | 37.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 16.20 | 16.30 | 41.33 | 41.33 | 7.00 | 16.20 | 16.10 | 7.00 | 7.00 | 7.00 | 16.20 | 41.33 |
cycles | 16.20 | 19.13 | 41.33 | 41.33 | 7.00 | 16.20 | 16.10 | 7.00 | 7.00 | 7.00 | 16.20 | 41.33 |
Cycles executing div or sqrt instructions | 4.50 |
FE+BE cycles | 47.60-47.23 |
Stall cycles | 9.81-9.39 |
LM full (events) | 21.37-19.95 |
Front-end | 37.50 |
Dispatch | 41.33 |
DIV/SQRT | 4.50 |
Overall L1 | 41.33 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
all | 10% |
load | 12% |
store | 11% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | 12% |
other | 12% |
all | 11% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | 12% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x60(%RBP),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x138(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x58(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x130(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RAX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0xd0(%RBP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 443080 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x540> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD %R8D,%RDX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
LEA (,%RDX,8),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMOVG %RSI,%R9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB %RDX,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
INC %R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x3,%R9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
NEG %R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x128(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RDI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP $0x2,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8D,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,-0x138(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JGE 443340 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x800> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x1,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 443140 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x600> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x38(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%RAX),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RBX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RAX,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD -0x8(%RAX,%RCX,8),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JB 443140 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x600> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x38(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RBX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x48(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD (%RAX,%RSI,8),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE 443140 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x600> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RSI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOVSXD -0x64(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB -0x30(%RBP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x8(%RAX,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD -0x8(%RAX,%RSI,8),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JB 443140 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x600> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x38(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%RSI,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD (%RAX,%RCX,8),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE 443140 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x600> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xe0(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RCX,%RDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0x90(%RBP),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x68(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RSI,%R11,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RDI,%R14,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL (%RSI),%RCX | 1 | 0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
ADD 0x98(%RBP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x70(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RSI,%R11,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RCX,%R14,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x60(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%R11,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%R11,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x110(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb0(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R11,%R14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV -0xa8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R10,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RAX,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R13,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD -0xa0(%RBP),%R10 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
ADD %RAX,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VBROADCASTSD %XMM0,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM1,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R11,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 4437f3 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0xcb3> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
JE 443980 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0xe40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x3,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 443140 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x600> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x38(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RBX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xb8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RAX,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xc0(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD (%RSI),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JNE 443140 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x600> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JP 443140 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x600> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD -0x64(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDI,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB -0x30(%RBP),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RAX,%RDI,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb8(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD (%RSI),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JNE 443140 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x600> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JP 443140 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x600> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xe0(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RDI,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0x90(%RBP),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x68(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%R8,%R11,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RSI,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL (%RSI),%RDI | 1 | 0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
ADD 0x98(%RBP),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x70(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RSI,%R11,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RDI,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x60(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RCX,%R11,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%R11,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x110(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb0(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R11,%R14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV -0xa8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RAX,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R10,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R12,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD -0xa0(%RBP),%R10 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
ADD %RCX,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VBROADCASTSD %XMM0,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM1,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 443570 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0xa30> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV -0x38(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RBX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xa8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RAX,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xc0(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VSUBSD (%RSI),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMULSD %XMM0,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOVSXD -0x64(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDI,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB -0x30(%RBP),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RAX,%RDI,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb8(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VSUBSD (%RSI),%XMM1,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VFMADD213SD %XMM0,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VSQRTSD %XMM1,%XMM1,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-19 | 4.50 |
MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%RSI,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD %XMM0,%XMM1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JB 443140 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x600> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xe0(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RDI,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0x90(%RBP),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x68(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%R8,%R11,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RSI,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL (%RSI),%RDI | 1 | 0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
ADD 0x98(%RBP),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x70(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RSI,%R11,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RDI,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x60(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RCX,%R11,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%R11,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x110(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb0(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R11,%R14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV -0xa8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RAX,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R10,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R12,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD -0xa0(%RBP),%R10 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
ADD %RCX,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VBROADCASTSD %XMM0,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBROADCASTSD %XMM1,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 443bb0 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x1070> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |