Function: calc_dt_kernel_.DIR.OMP.PARALLEL.2 | Module: exec | Source: calc_dt_kernel.f90:89-133 [...] | Coverage: 4.46% |
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Function: calc_dt_kernel_.DIR.OMP.PARALLEL.2 | Module: exec | Source: calc_dt_kernel.f90:89-133 [...] | Coverage: 4.46% |
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/scratch_na/users/xoserete/qaas_runs/171-415-7190/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90: 89 - 133 |
-------------------------------------------------------------------------------- |
89: !$OMP PARALLEL |
90: |
91: !$OMP DO PRIVATE(dsx,dsy,cc,dv1,dv2,div,dtct,dtut,dtvt,dtdivt) REDUCTION(MIN : dt_min_val) |
92: DO k=y_min,y_max |
93: !$OMP SIMD |
94: DO j=x_min,x_max |
95: |
96: dsx=celldx(j) |
97: dsy=celldy(k) |
98: |
99: cc=soundspeed(j,k)*soundspeed(j,k) |
100: cc=cc+2.0_8*viscosity_a(j,k)/density0(j,k) |
101: cc=MAX(SQRT(cc),g_small) |
102: |
103: dtct=dtc_safe*MIN(dsx,dsy)/cc |
104: |
105: div=0.0 |
106: |
107: dv1=(xvel0(j ,k)+xvel0(j ,k+1))*xarea(j ,k) |
108: dv2=(xvel0(j+1,k)+xvel0(j+1,k+1))*xarea(j+1,k) |
109: |
110: div=div+dv2-dv1 |
111: |
112: dtut=dtu_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k)) |
113: |
114: dv1=(yvel0(j,k )+yvel0(j+1,k ))*yarea(j,k ) |
115: dv2=(yvel0(j,k+1)+yvel0(j+1,k+1))*yarea(j,k+1) |
116: |
117: div=div+dv2-dv1 |
118: |
119: dtvt=dtv_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k)) |
120: |
121: div=div/(2.0_8*volume(j,k)) |
122: |
123: IF(div.LT.-g_small)THEN |
[...] |
129: dt_min_val=MIN(dt_min_val,dtct,dtut,dtvt,dtdivt) |
130: |
131: ENDDO |
132: ENDDO |
133: !$OMP END DO |
0x43fd00 PUSH %RBP |
0x43fd01 MOV %RSP,%RBP |
0x43fd04 PUSH %R15 |
0x43fd06 PUSH %R14 |
0x43fd08 PUSH %R13 |
0x43fd0a PUSH %R12 |
0x43fd0c PUSH %RBX |
0x43fd0d AND $-0x40,%RSP |
0x43fd11 SUB $0x480,%RSP |
0x43fd18 MOV 0xa0(%RBP),%EBX |
0x43fd1e MOV 0x98(%RBP),%EAX |
0x43fd24 SUB %EBX,%EAX |
0x43fd26 MOVL $0,0x5c(%RSP) |
0x43fd2e JS 4409ca |
0x43fd34 MOV %RCX,%R14 |
0x43fd37 MOV %R9,%R15 |
0x43fd3a MOV %RDI,0x60(%RSP) |
0x43fd3f MOV (%RDI),%ESI |
0x43fd41 MOVL $0,0x44(%RSP) |
0x43fd49 MOV %EAX,0x40(%RSP) |
0x43fd4d MOVL $0x1,0x58(%RSP) |
0x43fd55 SUB $0x8,%RSP |
0x43fd59 LEA 0x60(%RSP),%RAX |
0x43fd5e LEA 0x64(%RSP),%RCX |
0x43fd63 LEA 0x4c(%RSP),%R8 |
0x43fd68 LEA 0x48(%RSP),%R9 |
0x43fd6d MOV $0x74b0b0,%EDI |
0x43fd72 MOV %ESI,0x44(%RSP) |
0x43fd76 MOV $0x22,%EDX |
0x43fd7b PUSH $0x1 |
0x43fd7d PUSH $0x1 |
0x43fd7f PUSH %RAX |
0x43fd80 CALL 4044c0 <__kmpc_for_static_init_4@plt> |
0x43fd85 ADD $0x20,%RSP |
0x43fd89 MOV 0x44(%RSP),%EDX |
0x43fd8d MOV 0x40(%RSP),%EAX |
0x43fd91 SUB %EDX,%EAX |
0x43fd93 MOV %EAX,0x54(%RSP) |
0x43fd97 JAE 43fdc0 |
0x43fd99 VMOVSD 0xc9067(%RIP),%XMM0 |
0x43fda1 JMP 440947 |
0x43fda6 NOPW %CS:(%RAX,%RAX,1) |
0x43fdb5 NOPW %CS:(%RAX,%RAX,1) |
0x43fdc0 MOV 0x60(%RBP),%R12 |
0x43fdc4 MOV 0x58(%RBP),%R8 |
0x43fdc8 MOV 0x40(%RBP),%R9 |
0x43fdcc MOV 0x38(%RBP),%R10 |
0x43fdd0 MOV 0x18(%RBP),%RCX |
0x43fdd4 MOV %R15,0x88(%RSP) |
0x43fddc MOVSXD %R15D,%RAX |
0x43fddf SAL $0x3,%RAX |
0x43fde3 MOV $0x18,%R11D |
0x43fde9 SUB %RAX,%R11 |
0x43fdec ADD %R11,%RCX |
0x43fdef MOV %RCX,0xd8(%RSP) |
0x43fdf7 MOV %R14,0x68(%RSP) |
0x43fdfc MOVSXD %R14D,%RCX |
0x43fdff MOV $0x3,%R14D |
0x43fe05 SUB %RCX,%R14 |
0x43fe08 MOV %R14,0xd0(%RSP) |
0x43fe10 MOV $0x2,%R14D |
0x43fe16 SUB %RCX,%R14 |
0x43fe19 MOV %R14,0xc8(%RSP) |
0x43fe21 MOV $0x10,%ECX |
0x43fe26 SUB %RAX,%RCX |
0x43fe29 LEA (%R12,%R11,1),%RAX |
0x43fe2d MOV %RAX,0xb8(%RSP) |
0x43fe35 ADD 0x20(%RBP),%R11 |
0x43fe39 MOV %R11,0xe0(%RSP) |
0x43fe41 MOV 0x30(%RBP),%RAX |
0x43fe45 MOV 0x28(%RBP),%R11 |
0x43fe49 ADD %RCX,%R8 |
0x43fe4c MOV %R8,0xb0(%RSP) |
0x43fe54 LEA (%R9,%RCX,1),%R8 |
0x43fe58 MOV %R8,0xa8(%RSP) |
0x43fe60 LEA (%R10,%RCX,1),%R8 |
0x43fe64 MOV %R8,0xa0(%RSP) |
0x43fe6c ADD %RCX,%RAX |
0x43fe6f MOV %RAX,0x98(%RSP) |
0x43fe77 LEA (%R11,%RCX,1),%RAX |
0x43fe7b MOV %RAX,0x90(%RSP) |
0x43fe83 ADD 0x50(%RBP),%RCX |
0x43fe87 MOV %RCX,0xc0(%RSP) |
0x43fe8f VMOVDDUP 0xc8f6f(%RIP),%XMM28 |
0x43fe99 VBROADCASTSD 0xc8f15(%RIP),%ZMM2 |
0x43fea3 VBROADCASTSD 0xc8ed3(%RIP),%ZMM3 |
0x43fead VBROADCASTSD 0xc8f59(%RIP),%ZMM4 |
0x43feb7 VBROADCASTSD 0xc8f57(%RIP),%ZMM5 |
0x43fec1 MOV 0xa8(%RBP),%R9 |
0x43fec8 MOV %RDX,%RDI |
0x43fecb LEA (%RDX,%RBX,1),%R10D |
0x43fecf XOR %R8D,%R8D |
0x43fed2 MOV %RDX,0xe8(%RSP) |
0x43feda JMP 43ff25 |
0x43fedc NOPW %CS:(%RAX,%RAX,1) |
0x43feeb NOPW %CS:(%RAX,%RAX,1) |
0x43fefa NOPW (%RAX,%RAX,1) |
(323) 0x43ff00 VMOVDDUP %XMM28,%XMM28 |
(323) 0x43ff06 NOPW %CS:(%RAX,%RAX,1) |
(323) 0x43ff10 LEA 0x1(%R8),%EAX |
(323) 0x43ff14 INC %R10D |
(323) 0x43ff17 CMP 0x54(%RSP),%R8D |
(323) 0x43ff1c MOV %EAX,%R8D |
(323) 0x43ff1f JE 440940 |
(323) 0x43ff25 MOV 0xb0(%RBP),%RAX |
(323) 0x43ff2c MOVSXD (%RAX),%RSI |
(323) 0x43ff2f MOV (%R9),%R14D |
(323) 0x43ff32 CMP %ESI,%R14D |
(323) 0x43ff35 JS 43ff10 |
(323) 0x43ff37 MOV 0xa0(%RBP),%EAX |
(323) 0x43ff3d ADD %EDI,%EAX |
(323) 0x43ff3f ADD %R8D,%EAX |
(323) 0x43ff42 MOVSXD %EAX,%R12 |
(323) 0x43ff45 MOV 0x68(%RSP),%RAX |
(323) 0x43ff4a ADD $-0x2,%EAX |
(323) 0x43ff4d CLTQ |
(323) 0x43ff4f MOV %R12,%RCX |
(323) 0x43ff52 SUB %RAX,%RCX |
(323) 0x43ff55 MOV 0x48(%RBP),%RAX |
(323) 0x43ff59 VMOVSD (%RAX,%RCX,8),%XMM25 |
(323) 0x43ff60 MOV 0xb8(%RBP),%RAX |
(323) 0x43ff67 MOV (%RAX),%RAX |
(323) 0x43ff6a MOV %RAX,0x78(%RSP) |
(323) 0x43ff6f MOV 0xc0(%RBP),%RAX |
(323) 0x43ff76 MOV (%RAX),%RAX |
(323) 0x43ff79 MOV %RAX,0x48(%RSP) |
(323) 0x43ff7e MOV 0xc8(%RBP),%RAX |
(323) 0x43ff85 MOV (%RAX),%R11 |
(323) 0x43ff88 VMOVSD 0x312dde(%RIP),%XMM26 |
(323) 0x43ff92 MOV 0xd0(%RBP),%RAX |
(323) 0x43ff99 MOV (%RAX),%R15 |
(323) 0x43ff9c MOV 0xd8(%RBP),%RAX |
(323) 0x43ffa3 MOV (%RAX),%RCX |
(323) 0x43ffa6 VMOVSD 0x312db8(%RIP),%XMM23 |
(323) 0x43ffb0 MOV 0xe0(%RBP),%RAX |
(323) 0x43ffb7 MOV (%RAX),%R13 |
(323) 0x43ffba MOV 0xe8(%RBP),%RAX |
(323) 0x43ffc1 MOV (%RAX),%RBX |
(323) 0x43ffc4 MOV 0xf0(%RBP),%RAX |
(323) 0x43ffcb MOV (%RAX),%RDX |
(323) 0x43ffce VMOVSD 0x312d88(%RIP),%XMM24 |
(323) 0x43ffd8 VMOVSD 0x312d78(%RIP),%XMM0 |
(323) 0x43ffe0 VXORPD 0xc8e0e(%RIP){1to2},%XMM0,%XMM27 |
(323) 0x43ffea SUB %ESI,%R14D |
(323) 0x43ffed INC %R14D |
(323) 0x43fff0 CMP $0x2,%R14D |
(323) 0x43fff4 MOV $0x1,%EAX |
(323) 0x43fff9 CMOVL %EAX,%R14D |
(323) 0x43fffd MOV %R14,%RAX |
(323) 0x440000 MOV %R14,0x138(%RSP) |
(323) 0x440008 VPBROADCASTQ %R14,%ZMM29 |
(323) 0x44000e AND $0x7ffffff8,%R14 |
(323) 0x440015 MOV %R11,0x130(%RSP) |
(323) 0x44001d MOV %RSI,0x128(%RSP) |
(323) 0x440025 JE 440440 |
(323) 0x44002b MOV %R12,0x118(%RSP) |
(323) 0x440033 MOV %R8,0x120(%RSP) |
(323) 0x44003b MOV %R10D,0x50(%RSP) |
(323) 0x440040 MOV %R11,%R12 |
(323) 0x440043 MOV %RDX,%R11 |
(323) 0x440046 MOV %RBX,%RDI |
(323) 0x440049 MOV %R13,0x70(%RSP) |
(323) 0x44004e MOV %RCX,%RBX |
(323) 0x440051 MOVSXD %R10D,%RCX |
(323) 0x440054 MOV 0xd0(%RSP),%RAX |
(323) 0x44005c ADD %RCX,%RAX |
(323) 0x44005f ADD 0xc8(%RSP),%RCX |
(323) 0x440067 VBROADCASTSD %XMM28,%ZMM28 |
(323) 0x44006d VBROADCASTSD %XMM25,%ZMM30 |
(323) 0x440073 VBROADCASTSD %XMM26,%ZMM31 |
(323) 0x440079 VBROADCASTSD %XMM23,%ZMM1 |
(323) 0x44007f VBROADCASTSD %XMM24,%ZMM0 |
(323) 0x440085 VBROADCASTSD %XMM27,%ZMM6 |
(323) 0x44008b MOV %RDI,%RDX |
(323) 0x44008e IMUL %RAX,%RDX |
(323) 0x440092 LEA (%RDX,%RSI,8),%R9 |
(323) 0x440096 MOV %R14,0xf0(%RSP) |
(323) 0x44009e MOV %RSI,%R14 |
(323) 0x4400a1 MOV 0xd8(%RSP),%RSI |
(323) 0x4400a9 ADD %RSI,%R9 |
(323) 0x4400ac MOV %RDI,0x108(%RSP) |
(323) 0x4400b4 MOV %RDI,%RDX |
(323) 0x4400b7 IMUL %RCX,%RDX |
(323) 0x4400bb LEA (%RDX,%R14,8),%R8 |
(323) 0x4400bf ADD %RSI,%R8 |
(323) 0x4400c2 MOV %RBX,0x100(%RSP) |
(323) 0x4400ca MOV %RBX,%RDX |
(323) 0x4400cd IMUL %RCX,%RDX |
(323) 0x4400d1 MOV %R15,%R10 |
(323) 0x4400d4 LEA (%RDX,%R14,8),%R15 |
(323) 0x4400d8 ADD 0xb8(%RSP),%R15 |
(323) 0x4400e0 MOV %R10,%RDX |
(323) 0x4400e3 IMUL %RCX,%RDX |
(323) 0x4400e7 LEA (%RDX,%R14,8),%RDI |
(323) 0x4400eb MOV 0xe0(%RSP),%RSI |
(323) 0x4400f3 ADD %RSI,%RDI |
(323) 0x4400f6 MOV %R10,0xf8(%RSP) |
(323) 0x4400fe MOV %R10,%RDX |
(323) 0x440101 IMUL %RAX,%RDX |
(323) 0x440105 LEA (%RDX,%R14,8),%R13 |
(323) 0x440109 ADD %RSI,%R13 |
(323) 0x44010c IMUL %R11,%RAX |
(323) 0x440110 LEA (%RAX,%R14,8),%RSI |
(323) 0x440114 MOV 0xb0(%RSP),%RDX |
(323) 0x44011c ADD %RDX,%RSI |
(323) 0x44011f MOV %R11,0x110(%RSP) |
(323) 0x440127 MOV %R11,%RAX |
(323) 0x44012a IMUL %RCX,%RAX |
(323) 0x44012e LEA (%RAX,%R14,8),%RBX |
(323) 0x440132 ADD %RDX,%RBX |
(323) 0x440135 MOV 0x70(%RSP),%RAX |
(323) 0x44013a IMUL %RCX,%RAX |
(323) 0x44013e LEA (%RAX,%R14,8),%RAX |
(323) 0x440142 ADD 0xa8(%RSP),%RAX |
(323) 0x44014a MOV %R12,%RDX |
(323) 0x44014d IMUL %RCX,%RDX |
(323) 0x440151 LEA (%RDX,%R14,8),%R11 |
(323) 0x440155 ADD 0xa0(%RSP),%R11 |
(323) 0x44015d MOV 0x48(%RSP),%RDX |
(323) 0x440162 IMUL %RCX,%RDX |
(323) 0x440166 LEA (%RDX,%R14,8),%RDX |
(323) 0x44016a ADD 0x98(%RSP),%RDX |
(323) 0x440172 IMUL 0x78(%RSP),%RCX |
(323) 0x440178 LEA (%RCX,%R14,8),%R10 |
(323) 0x44017c ADD 0x90(%RSP),%R10 |
(323) 0x440184 MOV 0xc0(%RSP),%RCX |
(323) 0x44018c LEA (%RCX,%R14,8),%R12 |
(323) 0x440190 MOV 0xf0(%RSP),%R14 |
(323) 0x440198 XOR %ECX,%ECX |
(323) 0x44019a NOPW (%RAX,%RAX,1) |
(324) 0x4401a0 VMOVUPD (%RDX,%RCX,8),%ZMM7 |
(324) 0x4401a7 VADDPD %ZMM7,%ZMM7,%ZMM7 |
(324) 0x4401ad VDIVPD (%R11,%RCX,8),%ZMM7,%ZMM7 |
(324) 0x4401b4 VMOVUPD (%R12,%RCX,8),%ZMM8 |
(324) 0x4401bb VMOVUPD -0x8(%R13,%RCX,8),%ZMM9 |
(324) 0x4401c6 VADDPD -0x8(%RDI,%RCX,8),%ZMM9,%ZMM9 |
(324) 0x4401d1 VMULPD -0x8(%R15,%RCX,8),%ZMM9,%ZMM9 |
(324) 0x4401dc VMINPD %ZMM30,%ZMM8,%ZMM8 |
(324) 0x4401e2 VMOVUPD (%R13,%RCX,8),%ZMM11 |
(324) 0x4401ea VADDPD (%RDI,%RCX,8),%ZMM11,%ZMM11 |
(324) 0x4401f1 VMULPD (%R15,%RCX,8),%ZMM11,%ZMM11 |
(324) 0x4401f8 VMULPD %ZMM8,%ZMM31,%ZMM8 |
(324) 0x4401fe VMOVUPD (%R10,%RCX,8),%ZMM12 |
(324) 0x440205 VMOVUPD (%RAX,%RCX,8),%ZMM13 |
(324) 0x44020c VADDPD %ZMM13,%ZMM13,%ZMM14 |
(324) 0x440212 VMULPD %ZMM2,%ZMM13,%ZMM13 |
(324) 0x440218 VMOVUPD (%R8,%RCX,8),%ZMM15 |
(324) 0x44021f VANDPD %ZMM3,%ZMM11,%ZMM16 |
(324) 0x440225 VADDPD -0x8(%R8,%RCX,8),%ZMM15,%ZMM15 |
(324) 0x440230 VMULPD (%RBX,%RCX,8),%ZMM15,%ZMM15 |
(324) 0x440237 VMOVUPD (%R9,%RCX,8),%ZMM17 |
(324) 0x44023e VMAXPD %ZMM13,%ZMM16,%ZMM16 |
(324) 0x440244 VADDPD -0x8(%R9,%RCX,8),%ZMM17,%ZMM17 |
(324) 0x44024f VMULPD (%RSI,%RCX,8),%ZMM17,%ZMM17 |
(324) 0x440256 VADDPD %ZMM15,%ZMM9,%ZMM18 |
(324) 0x44025c VFMADD231PD %ZMM12,%ZMM12,%ZMM7 |
(324) 0x440262 VSUBPD %ZMM18,%ZMM11,%ZMM11 |
(324) 0x440268 VANDPD %ZMM3,%ZMM17,%ZMM12 |
(324) 0x44026e VMAXPD %ZMM13,%ZMM12,%ZMM12 |
(324) 0x440274 VMULPD %ZMM1,%ZMM14,%ZMM13 |
(324) 0x44027a VANDPD %ZMM3,%ZMM9,%ZMM9 |
(324) 0x440280 VMAXPD %ZMM16,%ZMM9,%ZMM9 |
(324) 0x440286 VANDPD %ZMM3,%ZMM15,%ZMM15 |
(324) 0x44028c VMAXPD %ZMM12,%ZMM15,%ZMM12 |
(324) 0x440292 VMULPD %ZMM0,%ZMM14,%ZMM15 |
(324) 0x440298 VDIVPD %ZMM9,%ZMM13,%ZMM9 |
(324) 0x44029e VDIVPD %ZMM12,%ZMM15,%ZMM12 |
(324) 0x4402a4 VSQRTPD %ZMM7,%ZMM7 |
(324) 0x4402aa VADDPD %ZMM17,%ZMM11,%ZMM11 |
(324) 0x4402b0 VDIVPD %ZMM14,%ZMM11,%ZMM11 |
(324) 0x4402b6 VCMPPD $0x1,%ZMM4,%ZMM11,%K1 |
(324) 0x4402bd VMOVAPD %ZMM5,%ZMM13 |
(324) 0x4402c3 VMAXPD %ZMM2,%ZMM7,%ZMM7 |
(324) 0x4402c9 VDIVPD %ZMM11,%ZMM6,%ZMM13{%K1} |
(324) 0x4402cf VDIVPD %ZMM7,%ZMM8,%ZMM7 |
(324) 0x4402d5 VMINPD %ZMM13,%ZMM12,%ZMM8 |
(324) 0x4402db VMINPD %ZMM8,%ZMM9,%ZMM8 |
(324) 0x4402e1 VMINPD %ZMM8,%ZMM7,%ZMM7 |
(324) 0x4402e7 VMINPD %ZMM7,%ZMM28,%ZMM28 |
(324) 0x4402ed ADD $0x8,%RCX |
(324) 0x4402f1 CMP %R14,%RCX |
(324) 0x4402f4 JB 4401a0 |
(323) 0x4402fa VMOVAPD %XMM28,%XMM0 |
(323) 0x440300 VSHUFPD $0x1,%XMM28,%XMM28,%XMM1 |
(323) 0x440307 VMINSD %XMM28,%XMM1,%XMM6 |
(323) 0x44030d VCMPSD $0x3,%XMM28,%XMM28,%K1 |
(323) 0x440314 VMOVSD %XMM1,%XMM6,%XMM6{%K1} |
(323) 0x44031a VCMPSD $0x3,%XMM6,%XMM6,%K1 |
(323) 0x440321 VMOVAPD %YMM28,%YMM0 |
(323) 0x440327 VEXTRACTF32X4 $0x1,%YMM28,%XMM0 |
(323) 0x44032e VMINSD %XMM6,%XMM0,%XMM1 |
(323) 0x440332 VMOVSD %XMM0,%XMM1,%XMM1{%K1} |
(323) 0x440338 VCMPSD $0x3,%XMM1,%XMM1,%K1 |
(323) 0x44033f VSHUFPD $0x1,%XMM0,%XMM0,%XMM0 |
(323) 0x440344 VMINSD %XMM1,%XMM0,%XMM1 |
(323) 0x440348 VMOVSD %XMM0,%XMM1,%XMM1{%K1} |
(323) 0x44034e VCMPSD $0x3,%XMM1,%XMM1,%K1 |
(323) 0x440355 VEXTRACTF32X4 $0x2,%ZMM28,%XMM0 |
(323) 0x44035c VMINSD %XMM1,%XMM0,%XMM1 |
(323) 0x440360 VMOVSD %XMM0,%XMM1,%XMM1{%K1} |
(323) 0x440366 VCMPSD $0x3,%XMM1,%XMM1,%K1 |
(323) 0x44036d VSHUFPD $0x1,%XMM0,%XMM0,%XMM0 |
(323) 0x440372 VMINSD %XMM1,%XMM0,%XMM1 |
(323) 0x440376 VMOVSD %XMM0,%XMM1,%XMM1{%K1} |
(323) 0x44037c VCMPSD $0x3,%XMM1,%XMM1,%K1 |
(323) 0x440383 VEXTRACTF32X4 $0x3,%ZMM28,%XMM0 |
(323) 0x44038a VMINSD %XMM1,%XMM0,%XMM1 |
(323) 0x44038e VMOVSD %XMM0,%XMM1,%XMM1{%K1} |
(323) 0x440394 VCMPSD $0x3,%XMM1,%XMM1,%K1 |
(323) 0x44039b VSHUFPD $0x1,%XMM0,%XMM0,%XMM0 |
(323) 0x4403a0 VMINSD %XMM1,%XMM0,%XMM28 |
(323) 0x4403a6 VMOVSD %XMM0,%XMM28,%XMM28{%K1} |
(323) 0x4403ac CMP 0x138(%RSP),%R14 |
(323) 0x4403b4 MOV 0xe8(%RSP),%RDI |
(323) 0x4403bc MOV 0xa8(%RBP),%R9 |
(323) 0x4403c3 MOV 0x50(%RSP),%R10D |
(323) 0x4403c8 MOV 0x120(%RSP),%R8 |
(323) 0x4403d0 MOV 0x48(%RSP),%RAX |
(323) 0x4403d5 MOV 0x118(%RSP),%R12 |
(323) 0x4403dd MOV 0x110(%RSP),%RDX |
(323) 0x4403e5 MOV 0x108(%RSP),%RBX |
(323) 0x4403ed MOV 0x70(%RSP),%R13 |
(323) 0x4403f2 MOV 0x100(%RSP),%RCX |
(323) 0x4403fa MOV 0xf8(%RSP),%R15 |
(323) 0x440402 JE 43ff00 |
(323) 0x440408 JMP 440448 |
0x44040a NOPW %CS:(%RAX,%RAX,1) |
0x440419 NOPW %CS:(%RAX,%RAX,1) |
0x440428 NOPW %CS:(%RAX,%RAX,1) |
0x440437 NOPW (%RAX,%RAX,1) |
(323) 0x440440 XOR %R14D,%R14D |
(323) 0x440443 MOV 0x48(%RSP),%RAX |
(323) 0x440448 VBROADCASTSD %XMM28,%ZMM28 |
(323) 0x44044e VPBROADCASTQ %R14,%ZMM0 |
(323) 0x440454 VPSUBQ %ZMM0,%ZMM29,%ZMM0 |
(323) 0x44045a VPCMPNLEUQ 0xc79db(%RIP),%ZMM0,%K1 |
(323) 0x440465 KORTESTB %K1,%K1 |
(323) 0x440469 JE 440840 |
(323) 0x44046f ADD 0x128(%RSP),%R14 |
(323) 0x440477 MOV %RAX,%RSI |
(323) 0x44047a MOVSXD 0x88(%RSP),%RAX |
(323) 0x440482 SUB %RAX,%R14 |
(323) 0x440485 MOV 0x68(%RSP),%RAX |
(323) 0x44048a CLTQ |
(323) 0x44048c SUB %RAX,%R12 |
(323) 0x44048f MOV %R15,%R9 |
(323) 0x440492 MOV %RCX,%R11 |
(323) 0x440495 LEA 0x2(%R12),%RCX |
(323) 0x44049a ADD $0x3,%R12 |
(323) 0x44049e MOV %R15,%RAX |
(323) 0x4404a1 IMUL %R12,%RAX |
(323) 0x4404a5 MOV %RDI,%R15 |
(323) 0x4404a8 MOV 0x20(%RBP),%RDI |
(323) 0x4404ac ADD %RDI,%RAX |
(323) 0x4404af VMOVUPD 0x10(%RAX,%R14,8),%ZMM6{%K1}{z} |
(323) 0x4404ba VMOVUPD 0x18(%RAX,%R14,8),%ZMM0{%K1}{z} |
(323) 0x4404c5 IMUL %RCX,%R9 |
(323) 0x4404c9 ADD %RDI,%R9 |
(323) 0x4404cc VMOVUPD 0x10(%R9,%R14,8),%ZMM7{%K1}{z} |
(323) 0x4404d7 VMOVUPD 0x18(%R9,%R14,8),%ZMM1{%K1}{z} |
(323) 0x4404e2 IMUL %RCX,%R11 |
(323) 0x4404e6 ADD 0x60(%RBP),%R11 |
(323) 0x4404ea VMOVUPD 0x10(%R11,%R14,8),%ZMM8{%K1}{z} |
(323) 0x4404f5 VMOVUPD 0x18(%R11,%R14,8),%ZMM9{%K1}{z} |
(323) 0x440500 IMUL %RCX,%R13 |
(323) 0x440504 ADD 0x40(%RBP),%R13 |
(323) 0x440508 VMOVUPD 0x10(%R13,%R14,8),%ZMM11{%K1}{z} |
(323) 0x440513 MOV %RBX,%RAX |
(323) 0x440516 IMUL %RCX,%RAX |
(323) 0x44051a MOV 0x18(%RBP),%RDI |
(323) 0x44051e ADD %RDI,%RAX |
(323) 0x440521 VMOVUPD 0x18(%RAX,%R14,8),%ZMM12{%K1}{z} |
(323) 0x44052c VMOVUPD 0x10(%RAX,%R14,8),%ZMM13{%K1}{z} |
(323) 0x440537 MOV 0x78(%RSP),%R13 |
(323) 0x44053c IMUL %RCX,%R13 |
(323) 0x440540 IMUL %RCX,%RSI |
(323) 0x440544 MOV 0x130(%RSP),%R11 |
(323) 0x44054c IMUL %RCX,%R11 |
(323) 0x440550 VMOVAPD 0x140(%RSP),%ZMM29 |
(323) 0x440558 VMOVAPD %ZMM6,%ZMM29{%K1} |
(323) 0x44055e IMUL %RDX,%RCX |
(323) 0x440562 MOV 0x58(%RBP),%RAX |
(323) 0x440566 ADD %RAX,%RCX |
(323) 0x440569 VMOVUPD 0x10(%RCX,%R14,8),%ZMM6{%K1}{z} |
(323) 0x440574 VMOVAPD 0x180(%RSP),%ZMM18 |
(323) 0x44057c VMOVAPD %ZMM7,%ZMM18{%K1} |
(323) 0x440582 VMOVAPD 0x400(%RSP),%ZMM14 |
(323) 0x44058a VMOVAPD %ZMM8,%ZMM14{%K1} |
(323) 0x440590 IMUL %R12,%RBX |
(323) 0x440594 ADD %RDI,%RBX |
(323) 0x440597 MOV %R15,%RDI |
(323) 0x44059a MOV 0xa8(%RBP),%R9 |
(323) 0x4405a1 VMOVUPD 0x18(%RBX,%R14,8),%ZMM7{%K1}{z} |
(323) 0x4405ac VMOVUPD 0x10(%RBX,%R14,8),%ZMM8{%K1}{z} |
(323) 0x4405b7 VMOVAPD 0x3c0(%RSP),%ZMM15 |
(323) 0x4405bf VMOVAPD %ZMM0,%ZMM15{%K1} |
(323) 0x4405c5 IMUL %RDX,%R12 |
(323) 0x4405c9 VMOVAPD 0x380(%RSP),%ZMM16 |
(323) 0x4405d1 VMOVAPD %ZMM1,%ZMM16{%K1} |
(323) 0x4405d7 ADD %RAX,%R12 |
(323) 0x4405da VMOVUPD 0x10(%R12,%R14,8),%ZMM0{%K1}{z} |
(323) 0x4405e5 VMOVAPD 0x340(%RSP),%ZMM17 |
(323) 0x4405ed VMOVAPD %ZMM9,%ZMM17{%K1} |
(323) 0x4405f3 VMOVAPD %ZMM11,%ZMM10{%K1} |
(323) 0x4405f9 VMOVAPD %ZMM18,0x180(%RSP) |
(323) 0x440601 VMOVAPD %ZMM29,0x140(%RSP) |
(323) 0x440609 VADDPD %ZMM18,%ZMM29,%ZMM1 |
(323) 0x44060f VMOVAPD %ZMM14,0x400(%RSP) |
(323) 0x440617 VMULPD %ZMM1,%ZMM14,%ZMM1 |
(323) 0x44061d VMOVAPD 0x300(%RSP),%ZMM14 |
(323) 0x440625 VMOVAPD %ZMM12,%ZMM14{%K1} |
(323) 0x44062b VMOVAPD %ZMM15,0x3c0(%RSP) |
(323) 0x440633 VMOVAPD %ZMM16,0x380(%RSP) |
(323) 0x44063b VADDPD %ZMM16,%ZMM15,%ZMM9 |
(323) 0x440641 VMOVAPD %ZMM17,0x340(%RSP) |
(323) 0x440649 VMULPD %ZMM17,%ZMM9,%ZMM9 |
(323) 0x44064f VMOVAPD 0x2c0(%RSP),%ZMM12 |
(323) 0x440657 VMOVAPD %ZMM13,%ZMM12{%K1} |
(323) 0x44065d VADDPD %ZMM10,%ZMM10,%ZMM11 |
(323) 0x440663 VMOVAPD 0x280(%RSP),%ZMM13 |
(323) 0x44066b VMOVAPD %ZMM6,%ZMM13{%K1} |
(323) 0x440671 VMOVAPD %ZMM14,0x300(%RSP) |
(323) 0x440679 VMOVAPD %ZMM12,0x2c0(%RSP) |
(323) 0x440681 VADDPD %ZMM12,%ZMM14,%ZMM6 |
(323) 0x440687 VMOVAPD %ZMM13,0x280(%RSP) |
(323) 0x44068f VMULPD %ZMM6,%ZMM13,%ZMM6 |
(323) 0x440695 VMOVAPD 0x240(%RSP),%ZMM12 |
(323) 0x44069d VMOVAPD %ZMM7,%ZMM12{%K1} |
(323) 0x4406a3 VMOVAPD 0x200(%RSP),%ZMM7 |
(323) 0x4406ab VMOVAPD %ZMM8,%ZMM7{%K1} |
(323) 0x4406b1 VMOVAPD %ZMM12,0x240(%RSP) |
(323) 0x4406b9 VMOVAPD %ZMM7,0x200(%RSP) |
(323) 0x4406c1 VADDPD %ZMM7,%ZMM12,%ZMM7 |
(323) 0x4406c7 VMOVAPD 0x1c0(%RSP),%ZMM8 |
(323) 0x4406cf VMOVAPD %ZMM0,%ZMM8{%K1} |
(323) 0x4406d5 VMOVAPD %ZMM8,0x1c0(%RSP) |
(323) 0x4406dd VMULPD %ZMM8,%ZMM7,%ZMM0 |
(323) 0x4406e3 VADDPD %ZMM6,%ZMM1,%ZMM7 |
(323) 0x4406e9 VSUBPD %ZMM7,%ZMM9,%ZMM7 |
(323) 0x4406ef VADDPD %ZMM0,%ZMM7,%ZMM7 |
(323) 0x4406f5 VDIVPD %ZMM11,%ZMM7,%ZMM7 |
(323) 0x4406fb VBROADCASTSD %XMM27,%ZMM8 |
(323) 0x440701 VCMPPD $0x1,%ZMM4,%ZMM7,%K2 |
(323) 0x440708 VMOVAPD %ZMM5,%ZMM12 |
(323) 0x44070e VDIVPD %ZMM7,%ZMM8,%ZMM12{%K2} |
(323) 0x440714 MOV 0x50(%RBP),%RAX |
(323) 0x440718 VMOVUPD 0x10(%RAX,%R14,8),%ZMM7{%K1}{z} |
(323) 0x440723 VMOVAPD %ZMM7,%ZMM22{%K1} |
(323) 0x440729 ADD 0x28(%RBP),%R13 |
(323) 0x44072d VMOVUPD 0x10(%R13,%R14,8),%ZMM7{%K1}{z} |
(323) 0x440738 VMOVAPD %ZMM7,%ZMM21{%K1} |
(323) 0x44073e ADD 0x30(%RBP),%RSI |
(323) 0x440742 VMOVUPD 0x10(%RSI,%R14,8),%ZMM7{%K1}{z} |
(323) 0x44074d VMOVAPD %ZMM7,%ZMM20{%K1} |
(323) 0x440753 ADD 0x38(%RBP),%R11 |
(323) 0x440757 VMOVUPD 0x10(%R11,%R14,8),%ZMM7{%K1}{z} |
(323) 0x440762 VMOVAPD %ZMM7,%ZMM19{%K1} |
(323) 0x440768 VADDPD %ZMM20,%ZMM20,%ZMM7 |
(323) 0x44076e VDIVPD %ZMM19,%ZMM7,%ZMM7 |
(323) 0x440774 VFMADD231PD %ZMM21,%ZMM21,%ZMM7 |
(323) 0x44077a VSQRTPD %ZMM7,%ZMM7 |
(323) 0x440780 VBROADCASTSD %XMM25,%ZMM8 |
(323) 0x440786 VMINPD %ZMM8,%ZMM22,%ZMM8 |
(323) 0x44078c VBROADCASTSD %XMM26,%ZMM13 |
(323) 0x440792 VMULPD %ZMM8,%ZMM13,%ZMM8 |
(323) 0x440798 VMAXPD %ZMM2,%ZMM7,%ZMM7 |
(323) 0x44079e VDIVPD %ZMM7,%ZMM8,%ZMM7 |
(323) 0x4407a4 VANDPD %ZMM3,%ZMM1,%ZMM1 |
(323) 0x4407aa VANDPD %ZMM3,%ZMM9,%ZMM8 |
(323) 0x4407b0 VMULPD %ZMM2,%ZMM10,%ZMM9 |
(323) 0x4407b6 VMAXPD %ZMM9,%ZMM8,%ZMM8 |
(323) 0x4407bc VMAXPD %ZMM8,%ZMM1,%ZMM1 |
(323) 0x4407c2 VBROADCASTSD %XMM23,%ZMM8 |
(323) 0x4407c8 VMULPD %ZMM8,%ZMM11,%ZMM8 |
(323) 0x4407ce VDIVPD %ZMM1,%ZMM8,%ZMM1 |
(323) 0x4407d4 VBROADCASTSD %XMM24,%ZMM8 |
(323) 0x4407da VMULPD %ZMM8,%ZMM11,%ZMM8 |
(323) 0x4407e0 VANDPD %ZMM3,%ZMM0,%ZMM0 |
(323) 0x4407e6 VMAXPD %ZMM9,%ZMM0,%ZMM0 |
(323) 0x4407ec VANDPD %ZMM3,%ZMM6,%ZMM6 |
(323) 0x4407f2 VMAXPD %ZMM0,%ZMM6,%ZMM0 |
(323) 0x4407f8 VDIVPD %ZMM0,%ZMM8,%ZMM0 |
(323) 0x4407fe VMINPD %ZMM12,%ZMM0,%ZMM0 |
(323) 0x440804 VMINPD %ZMM0,%ZMM1,%ZMM0 |
(323) 0x44080a VMINPD %ZMM0,%ZMM7,%ZMM0 |
(323) 0x440810 VMINPD %ZMM0,%ZMM28,%ZMM0 |
(323) 0x440816 JMP 440844 |
0x440818 NOPW %CS:(%RAX,%RAX,1) |
0x440827 NOPW %CS:(%RAX,%RAX,1) |
0x440836 NOPW %CS:(%RAX,%RAX,1) |
(323) 0x440840 VPXOR %XMM0,%XMM0,%XMM0 |
(323) 0x440844 VMOVAPD %ZMM0,%ZMM28{%K1} |
(323) 0x44084a VEXTRACTF32X4 $0x3,%ZMM28,%XMM0 |
(323) 0x440851 VSHUFPD $0x1,%XMM0,%XMM0,%XMM1 |
(323) 0x440856 VEXTRACTF32X4 $0x2,%ZMM28,%XMM6 |
(323) 0x44085d VSHUFPD $0x1,%XMM6,%XMM6,%XMM7 |
(323) 0x440862 VMOVAPD %YMM28,%YMM8 |
(323) 0x440868 VEXTRACTF32X4 $0x1,%YMM28,%XMM8 |
(323) 0x44086f VSHUFPD $0x1,%XMM8,%XMM8,%XMM9 |
(323) 0x440875 VMOVAPD %XMM28,%XMM11 |
(323) 0x44087b VSHUFPD $0x1,%XMM28,%XMM28,%XMM12 |
(323) 0x440882 VMINSD %XMM28,%XMM12,%XMM13 |
(323) 0x440888 VCMPSD $0x3,%XMM28,%XMM28,%K1 |
(323) 0x44088f VMOVSD %XMM12,%XMM13,%XMM13{%K1} |
(323) 0x440895 VCMPSD $0x3,%XMM13,%XMM13,%K1 |
(323) 0x44089c VMINSD %XMM13,%XMM8,%XMM11 |
(323) 0x4408a1 VMOVSD %XMM8,%XMM11,%XMM11{%K1} |
(323) 0x4408a7 VCMPSD $0x3,%XMM11,%XMM11,%K1 |
(323) 0x4408ae VMINSD %XMM11,%XMM9,%XMM8 |
(323) 0x4408b3 VMOVSD %XMM9,%XMM8,%XMM8{%K1} |
(323) 0x4408b9 VCMPSD $0x3,%XMM8,%XMM8,%K1 |
(323) 0x4408c0 VMINSD %XMM8,%XMM6,%XMM8 |
(323) 0x4408c5 VMOVSD %XMM6,%XMM8,%XMM8{%K1} |
(323) 0x4408cb VCMPSD $0x3,%XMM8,%XMM8,%K1 |
(323) 0x4408d2 VMINSD %XMM8,%XMM7,%XMM6 |
(323) 0x4408d7 VMOVSD %XMM7,%XMM6,%XMM6{%K1} |
(323) 0x4408dd VCMPSD $0x3,%XMM6,%XMM6,%K1 |
(323) 0x4408e4 VMINSD %XMM6,%XMM0,%XMM6 |
(323) 0x4408e8 VMOVSD %XMM0,%XMM6,%XMM6{%K1} |
(323) 0x4408ee VCMPSD $0x3,%XMM6,%XMM6,%K1 |
(323) 0x4408f5 VMINSD %XMM6,%XMM1,%XMM0 |
(323) 0x4408f9 VMOVSD %XMM1,%XMM0,%XMM0{%K1} |
(323) 0x4408ff VMOVDDUP %XMM0,%XMM28 |
(323) 0x440905 JMP 43ff10 |
0x44090a NOPW %CS:(%RAX,%RAX,1) |
0x440919 NOPW %CS:(%RAX,%RAX,1) |
0x440928 NOPW %CS:(%RAX,%RAX,1) |
0x440937 NOPW (%RAX,%RAX,1) |
0x440940 VSHUFPD $0x1,%XMM28,%XMM28,%XMM0 |
0x440947 MOV 0x3c(%RSP),%ESI |
0x44094b VMOVSD %XMM0,0x80(%RSP) |
0x440954 MOV $0x74b0d0,%EDI |
0x440959 VZEROUPPER |
0x44095c CALL 4040b0 <__kmpc_for_static_fini@plt> |
0x440961 MOV 0x60(%RSP),%RBX |
0x440966 MOV (%RBX),%ESI |
0x440968 SUB $0x8,%RSP |
0x44096c LEA 0x88(%RSP),%R8 |
0x440974 MOV $0x74b0f0,%EDI |
0x440979 MOV $0x4409f0,%R9D |
0x44097f MOV $0x1,%EDX |
0x440984 MOV $0x8,%ECX |
0x440989 PUSH $0x75233c |
0x44098e CALL 4046b0 <__kmpc_reduce@plt> |
0x440993 MOV %RBX,%RDI |
0x440996 ADD $0x10,%RSP |
0x44099a CMP $0x1,%EAX |
0x44099d JNE 4409ca |
0x44099f MOV 0x10(%RBP),%RAX |
0x4409a3 VMOVSD 0x80(%RSP),%XMM0 |
0x4409ac VMINSD (%RAX),%XMM0,%XMM0 |
0x4409b0 VMOVSD %XMM0,(%RAX) |
0x4409b4 MOV (%RDI),%ESI |
0x4409b6 MOV $0x74b110,%EDI |
0x4409bb MOV $0x75233c,%EDX |
0x4409c0 CALL 404820 <__kmpc_end_reduce@plt> |
0x4409c5 MOV 0x60(%RSP),%RDI |
0x4409ca MOV (%RDI),%ESI |
0x4409cc MOV $0x74b130,%EDI |
0x4409d1 CALL 404580 <__kmpc_barrier@plt> |
0x4409d6 LEA -0x28(%RBP),%RSP |
0x4409da POP %RBX |
0x4409db POP %R12 |
0x4409dd POP %R13 |
0x4409df POP %R14 |
0x4409e1 POP %R15 |
0x4409e3 POP %RBP |
0x4409e4 RET |
0x4409e5 NOPW %CS:(%RAX,%RAX,1) |
0x4409ef NOP |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_invoke_task_func | libiomp5.so |
Path / |
Source file and lines | calc_dt_kernel.f90:89-133 |
Module | exec |
nb instructions | 150 |
nb uops | 156 |
loop length | 836 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 4 |
nb stack references | 39 |
micro-operation queue | 26.00 cycles |
front end | 26.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.70 | 7.70 | 12.33 | 12.33 | 19.00 | 7.57 | 7.50 | 19.00 | 19.00 | 19.00 | 7.53 | 12.33 |
cycles | 7.70 | 7.70 | 12.33 | 12.33 | 19.00 | 7.57 | 7.50 | 19.00 | 19.00 | 19.00 | 7.53 | 12.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 25.20 |
Stall cycles | 0.00 |
Front-end | 26.00 |
Dispatch | 19.00 |
Overall L1 | 26.00 |
all | 2% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 16% |
all | 9% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 16% |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 16% |
all | 10% |
load | 7% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 14% |
all | 11% |
load | 10% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 13% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x480,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xa0(%RBP),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x98(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %EBX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVL $0,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JS 4409ca <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0xcca> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RCX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R9,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDI,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x60(%RSP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x64(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x4c(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x48(%RSP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x74b0b0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 4044c0 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x44(%RSP),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JAE 43fdc0 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0xc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD 0xc9067(%RIP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 440947 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0xc47> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x60(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R15D,%RAX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
SAL $0x3,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV $0x18,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %RAX,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R11,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R14D,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV $0x3,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %RCX,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x2,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %RCX,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x10,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%R12,%R11,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD 0x20(%RBP),%R11 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %R11,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R9,%RCX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R10,%RCX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R11,%RCX,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD 0x50(%RBP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RCX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVDDUP 0xc8f6f(%RIP),%XMM28 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VBROADCASTSD 0xc8f15(%RIP),%ZMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSD 0xc8ed3(%RIP),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSD 0xc8f59(%RIP),%ZMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSD 0xc8f57(%RIP),%ZMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
MOV 0xa8(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%RDX,%RBX,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
XOR %R8D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDX,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 43ff25 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x225> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VSHUFPD $0x1,%XMM28,%XMM28,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0x3c(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x74b0d0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 4040b0 <__kmpc_for_static_fini@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x60(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x88(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x74b0f0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x4409f0,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x8,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x75233c | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 4046b0 <__kmpc_reduce@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x10,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP $0x1,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 4409ca <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0xcca> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x10(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x80(%RSP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMINSD (%RAX),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM0,(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x74b110,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x75233c,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 404820 <__kmpc_end_reduce@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x60(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x74b130,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 404580 <__kmpc_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | calc_dt_kernel.f90:89-133 |
Module | exec |
nb instructions | 150 |
nb uops | 156 |
loop length | 836 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 4 |
nb stack references | 39 |
micro-operation queue | 26.00 cycles |
front end | 26.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.70 | 7.70 | 12.33 | 12.33 | 19.00 | 7.57 | 7.50 | 19.00 | 19.00 | 19.00 | 7.53 | 12.33 |
cycles | 7.70 | 7.70 | 12.33 | 12.33 | 19.00 | 7.57 | 7.50 | 19.00 | 19.00 | 19.00 | 7.53 | 12.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 25.20 |
Stall cycles | 0.00 |
Front-end | 26.00 |
Dispatch | 19.00 |
Overall L1 | 26.00 |
all | 2% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 16% |
all | 9% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 16% |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 16% |
all | 10% |
load | 7% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 14% |
all | 11% |
load | 10% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 13% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x480,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xa0(%RBP),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x98(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %EBX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVL $0,0x5c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JS 4409ca <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0xcca> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RCX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R9,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDI,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x60(%RSP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x64(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x4c(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x48(%RSP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x74b0b0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,0x44(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 4044c0 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x44(%RSP),%EDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RSP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JAE 43fdc0 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0xc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD 0xc9067(%RIP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 440947 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0xc47> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x60(%RBP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R15D,%RAX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
SAL $0x3,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV $0x18,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %RAX,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R11,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD %R14D,%RCX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV $0x3,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %RCX,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x2,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %RCX,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x10,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%R12,%R11,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD 0x20(%RBP),%R11 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %R11,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RBP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R9,%RCX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R10,%RCX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R11,%RCX,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD 0x50(%RBP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RCX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVDDUP 0xc8f6f(%RIP),%XMM28 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VBROADCASTSD 0xc8f15(%RIP),%ZMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSD 0xc8ed3(%RIP),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSD 0xc8f59(%RIP),%ZMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBROADCASTSD 0xc8f57(%RIP),%ZMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
MOV 0xa8(%RBP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%RDX,%RBX,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
XOR %R8D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDX,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 43ff25 <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0x225> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VSHUFPD $0x1,%XMM28,%XMM28,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0x3c(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x74b0d0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 4040b0 <__kmpc_for_static_fini@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x60(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x88(%RSP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x74b0f0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x4409f0,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x8,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x75233c | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 4046b0 <__kmpc_reduce@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x10,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP $0x1,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 4409ca <calc_dt_kernel_module_mp_calc_dt_kernel_.DIR.OMP.PARALLEL.2+0xcca> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x10(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x80(%RSP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMINSD (%RAX),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM0,(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x74b110,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x75233c,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 404820 <__kmpc_end_reduce@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x60(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x74b130,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 404580 <__kmpc_barrier@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼calc_dt_kernel_.DIR.OMP.PARALLEL.2– | 4.46 | 1.45 |
▼Loop 323 - calc_dt_kernel.f90:92-129 - exec– | 0 | 0 |
○Loop 324 - calc_dt_kernel.f90:94-129 - exec | 4.46 | 1.44 |