Loop Id: 69 | Module: exec | Source: advec_cell_kernel.f90:256-261 | Coverage: 2.78% |
---|
Loop Id: 69 | Module: exec | Source: advec_cell_kernel.f90:256-261 | Coverage: 2.78% |
---|
0x4196ba VMOVUPD (%R15,%RAX,1),%YMM12 [4] |
0x4196c0 VMOVUPD (%R10,%RAX,1),%YMM13 [5] |
0x4196c6 MOV 0xd8(%RSP),%RDX [9] |
0x4196ce VMULPD (%RSI,%RAX,1),%YMM12,%YMM14 [2] |
0x4196d3 VSUBPD (%R9,%RAX,1),%YMM13,%YMM1 [7] |
0x4196d9 VADDPD (%R8,%RAX,1),%YMM12,%YMM6 [8] |
0x4196df VSUBPD (%RDI,%RAX,1),%YMM6,%YMM5 [1] |
0x4196e4 VSUBPD (%RBX,%RAX,1),%YMM14,%YMM0 [10] |
0x4196e9 VFMADD132PD (%RCX,%RAX,1),%YMM1,%YMM14 [6] |
0x4196ef VADDPD (%R12,%RAX,1),%YMM0,%YMM2 [3] |
0x4196f5 VDIVPD %YMM2,%YMM14,%YMM8 |
0x4196f9 VDIVPD %YMM5,%YMM2,%YMM4 |
0x4196fd VMOVUPD %YMM4,(%RSI,%RAX,1) [2] |
0x419702 VMOVUPD %YMM8,(%RCX,%RAX,1) [6] |
0x419707 VMOVUPD 0x20(%R15,%RAX,1),%YMM9 [4] |
0x41970e VMOVUPD 0x20(%R10,%RAX,1),%YMM3 [5] |
0x419715 VMULPD 0x20(%RSI,%RAX,1),%YMM9,%YMM11 [2] |
0x41971b VSUBPD 0x20(%R9,%RAX,1),%YMM3,%YMM15 [7] |
0x419722 VADDPD 0x20(%R8,%RAX,1),%YMM9,%YMM12 [8] |
0x419729 VSUBPD 0x20(%RDI,%RAX,1),%YMM12,%YMM14 [1] |
0x41972f VSUBPD 0x20(%RBX,%RAX,1),%YMM11,%YMM7 [10] |
0x419735 VFMADD132PD 0x20(%RCX,%RAX,1),%YMM15,%YMM11 [6] |
0x41973c VADDPD 0x20(%R12,%RAX,1),%YMM7,%YMM10 [3] |
0x419743 VDIVPD %YMM14,%YMM10,%YMM0 |
0x419748 VDIVPD %YMM10,%YMM11,%YMM2 |
0x41974d VMOVUPD %YMM0,0x20(%RSI,%RAX,1) [2] |
0x419753 VMOVUPD %YMM2,0x20(%RCX,%RAX,1) [6] |
0x419759 ADD $0x40,%RAX |
0x41975d CMP %RDX,%RAX |
0x419760 JNE 4196ba |
/scratch_na/users/xoserete/qaas_runs/171-415-7190/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 256 - 261 |
-------------------------------------------------------------------------------- |
256: pre_mass_s=density1(j,k)*pre_vol(j,k) |
257: post_mass_s=pre_mass_s+mass_flux_y(j,k)-mass_flux_y(j,k+1) |
258: post_ener_s=(energy1(j,k)*pre_mass_s+ener_flux(j,k)-ener_flux(j,k+1))/post_mass_s |
259: advec_vol_s=pre_vol(j,k)+vol_flux_y(j,k)-vol_flux_y(j,k+1) |
260: density1(j,k)=post_mass_s/advec_vol_s |
261: energy1(j,k)=post_ener_s |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○98.14 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
○1.86 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 4.47 |
Bottlenecks | P0, |
Function | __advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0 |
Source | advec_cell_kernel.f90:256-261 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 32.00 |
CQA cycles if no scalar integer | 32.00 |
CQA cycles if FP arith vectorized | 32.00 |
CQA cycles if fully vectorized | 32.00 |
Front-end cycles | 7.17 |
DIV/SQRT cycles | 5.50 |
P0 cycles | 7.00 |
P1 cycles | 6.33 |
P2 cycles | 6.33 |
P3 cycles | 2.00 |
P4 cycles | 6.00 |
P5 cycles | 1.00 |
P6 cycles | 2.00 |
P7 cycles | 2.00 |
P8 cycles | 2.00 |
P9 cycles | 0.00 |
P10 cycles | 6.33 |
P11 cycles | 32.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 32.29 - 32.31 |
Stall cycles (UFS) | 24.40 - 24.42 |
Nb insns | 30.00 |
Nb uops | 29.00 |
Nb loads | 19.00 |
Nb stores | 4.00 |
Nb stack references | 1.00 |
FLOP/cycle | 2.50 |
Nb FLOP add-sub | 40.00 |
Nb FLOP mul | 8.00 |
Nb FLOP fma | 8.00 |
Nb FLOP div | 16.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 22.25 |
Bytes prefetched | 0.00 |
Bytes loaded | 584.00 |
Bytes stored | 128.00 |
Stride 0 | 1.00 |
Stride 1 | 9.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 50.00 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | 50.00 |
Vector-efficiency ratio mul | 50.00 |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | 50.00 |
Vector-efficiency ratio div_sqrt | 50.00 |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 4.47 |
Bottlenecks | P0, |
Function | __advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0 |
Source | advec_cell_kernel.f90:256-261 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 32.00 |
CQA cycles if no scalar integer | 32.00 |
CQA cycles if FP arith vectorized | 32.00 |
CQA cycles if fully vectorized | 32.00 |
Front-end cycles | 7.17 |
DIV/SQRT cycles | 5.50 |
P0 cycles | 7.00 |
P1 cycles | 6.33 |
P2 cycles | 6.33 |
P3 cycles | 2.00 |
P4 cycles | 6.00 |
P5 cycles | 1.00 |
P6 cycles | 2.00 |
P7 cycles | 2.00 |
P8 cycles | 2.00 |
P9 cycles | 0.00 |
P10 cycles | 6.33 |
P11 cycles | 32.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 32.29 - 32.31 |
Stall cycles (UFS) | 24.40 - 24.42 |
Nb insns | 30.00 |
Nb uops | 29.00 |
Nb loads | 19.00 |
Nb stores | 4.00 |
Nb stack references | 1.00 |
FLOP/cycle | 2.50 |
Nb FLOP add-sub | 40.00 |
Nb FLOP mul | 8.00 |
Nb FLOP fma | 8.00 |
Nb FLOP div | 16.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 22.25 |
Bytes prefetched | 0.00 |
Bytes loaded | 584.00 |
Bytes stored | 128.00 |
Stride 0 | 1.00 |
Stride 1 | 9.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 50.00 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | 50.00 |
Vector-efficiency ratio mul | 50.00 |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | 50.00 |
Vector-efficiency ratio div_sqrt | 50.00 |
Vector-efficiency ratio other | NA |
Path / |
Function | __advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0 |
Source file and lines | advec_cell_kernel.f90:256-261 |
Module | exec |
nb instructions | 30 |
nb uops | 29 |
loop length | 172 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 16 |
used zmm registers | 0 |
nb stack references | 1 |
ADD-SUB / MUL ratio | 5.00 |
micro-operation queue | 7.17 cycles |
front end | 7.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.50 | 6.50 | 6.33 | 6.33 | 2.00 | 6.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 6.33 |
cycles | 5.50 | 7.00 | 6.33 | 6.33 | 2.00 | 6.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 6.33 |
Cycles executing div or sqrt instructions | 32.00 |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 32.29-32.31 |
Stall cycles | 24.40-24.42 |
LB full (events) | 25.55-25.57 |
Front-end | 7.17 |
Dispatch | 7.00 |
DIV/SQRT | 32.00 |
Data deps. | 1.00 |
Overall L1 | 32.00 |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | NA (no other vectorizable/vectorized instructions) |
all | 50% |
load | 50% |
store | 50% |
mul | 50% |
add-sub | 50% |
fma | 50% |
div/sqrt | 50% |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R15,%RAX,1),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD (%R10,%RAX,1),%YMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
MOV 0xd8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMULPD (%RSI,%RAX,1),%YMM12,%YMM14 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VSUBPD (%R9,%RAX,1),%YMM13,%YMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VADDPD (%R8,%RAX,1),%YMM12,%YMM6 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VSUBPD (%RDI,%RAX,1),%YMM6,%YMM5 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VSUBPD (%RBX,%RAX,1),%YMM14,%YMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VFMADD132PD (%RCX,%RAX,1),%YMM1,%YMM14 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VADDPD (%R12,%RAX,1),%YMM0,%YMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VDIVPD %YMM2,%YMM14,%YMM8 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 8 |
VDIVPD %YMM5,%YMM2,%YMM4 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 8 |
VMOVUPD %YMM4,(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVUPD %YMM8,(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVUPD 0x20(%R15,%RAX,1),%YMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x20(%R10,%RAX,1),%YMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMULPD 0x20(%RSI,%RAX,1),%YMM9,%YMM11 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VSUBPD 0x20(%R9,%RAX,1),%YMM3,%YMM15 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VADDPD 0x20(%R8,%RAX,1),%YMM9,%YMM12 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VSUBPD 0x20(%RDI,%RAX,1),%YMM12,%YMM14 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VSUBPD 0x20(%RBX,%RAX,1),%YMM11,%YMM7 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VFMADD132PD 0x20(%RCX,%RAX,1),%YMM15,%YMM11 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VADDPD 0x20(%R12,%RAX,1),%YMM7,%YMM10 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VDIVPD %YMM14,%YMM10,%YMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 8 |
VDIVPD %YMM10,%YMM11,%YMM2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 8 |
VMOVUPD %YMM0,0x20(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVUPD %YMM2,0x20(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
ADD $0x40,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RDX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 4196ba <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x231a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | __advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0 |
Source file and lines | advec_cell_kernel.f90:256-261 |
Module | exec |
nb instructions | 30 |
nb uops | 29 |
loop length | 172 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 16 |
used zmm registers | 0 |
nb stack references | 1 |
ADD-SUB / MUL ratio | 5.00 |
micro-operation queue | 7.17 cycles |
front end | 7.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.50 | 6.50 | 6.33 | 6.33 | 2.00 | 6.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 6.33 |
cycles | 5.50 | 7.00 | 6.33 | 6.33 | 2.00 | 6.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 6.33 |
Cycles executing div or sqrt instructions | 32.00 |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 32.29-32.31 |
Stall cycles | 24.40-24.42 |
LB full (events) | 25.55-25.57 |
Front-end | 7.17 |
Dispatch | 7.00 |
DIV/SQRT | 32.00 |
Data deps. | 1.00 |
Overall L1 | 32.00 |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | NA (no other vectorizable/vectorized instructions) |
all | 50% |
load | 50% |
store | 50% |
mul | 50% |
add-sub | 50% |
fma | 50% |
div/sqrt | 50% |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R15,%RAX,1),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD (%R10,%RAX,1),%YMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
MOV 0xd8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMULPD (%RSI,%RAX,1),%YMM12,%YMM14 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VSUBPD (%R9,%RAX,1),%YMM13,%YMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VADDPD (%R8,%RAX,1),%YMM12,%YMM6 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VSUBPD (%RDI,%RAX,1),%YMM6,%YMM5 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VSUBPD (%RBX,%RAX,1),%YMM14,%YMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VFMADD132PD (%RCX,%RAX,1),%YMM1,%YMM14 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VADDPD (%R12,%RAX,1),%YMM0,%YMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VDIVPD %YMM2,%YMM14,%YMM8 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 8 |
VDIVPD %YMM5,%YMM2,%YMM4 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 8 |
VMOVUPD %YMM4,(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVUPD %YMM8,(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVUPD 0x20(%R15,%RAX,1),%YMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x20(%R10,%RAX,1),%YMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMULPD 0x20(%RSI,%RAX,1),%YMM9,%YMM11 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VSUBPD 0x20(%R9,%RAX,1),%YMM3,%YMM15 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VADDPD 0x20(%R8,%RAX,1),%YMM9,%YMM12 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VSUBPD 0x20(%RDI,%RAX,1),%YMM12,%YMM14 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VSUBPD 0x20(%RBX,%RAX,1),%YMM11,%YMM7 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VFMADD132PD 0x20(%RCX,%RAX,1),%YMM15,%YMM11 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VADDPD 0x20(%R12,%RAX,1),%YMM7,%YMM10 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VDIVPD %YMM14,%YMM10,%YMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 8 |
VDIVPD %YMM10,%YMM11,%YMM2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 8 |
VMOVUPD %YMM0,0x20(%RSI,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVUPD %YMM2,0x20(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
ADD $0x40,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RDX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 4196ba <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x231a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |