Loop Id: 107 | Module: exec | Source: advec_mom_kernel.f90:196-196 | Coverage: 0.88% |
---|
Loop Id: 107 | Module: exec | Source: advec_mom_kernel.f90:196-196 | Coverage: 0.88% |
---|
0x41ed2c VMOVUPD (%R13,%RAX,1),%YMM11 [1] |
0x41ed33 VMOVUPD (%R12,%RAX,1),%YMM13 [2] |
0x41ed39 VADDPD (%R9,%RAX,1),%YMM11,%YMM12 [5] |
0x41ed3f VADDPD (%R8,%RAX,1),%YMM13,%YMM14 [3] |
0x41ed45 VADDPD %YMM14,%YMM12,%YMM15 |
0x41ed4a VMULPD %YMM5,%YMM15,%YMM1 |
0x41ed4e VMOVUPD %YMM1,(%RBX,%RAX,1) [4] |
0x41ed53 VMOVUPD 0x20(%R13,%RAX,1),%YMM0 [1] |
0x41ed5a VMOVUPD 0x20(%R12,%RAX,1),%YMM7 [2] |
0x41ed61 VADDPD 0x20(%R9,%RAX,1),%YMM0,%YMM2 [5] |
0x41ed68 VADDPD 0x20(%R8,%RAX,1),%YMM7,%YMM6 [3] |
0x41ed6f VADDPD %YMM6,%YMM2,%YMM8 |
0x41ed73 VMULPD %YMM5,%YMM8,%YMM9 |
0x41ed77 VMOVUPD %YMM9,0x20(%RBX,%RAX,1) [4] |
0x41ed7d VMOVUPD 0x40(%R13,%RAX,1),%YMM10 [1] |
0x41ed84 VMOVUPD 0x40(%R12,%RAX,1),%YMM12 [2] |
0x41ed8b VADDPD 0x40(%R9,%RAX,1),%YMM10,%YMM11 [5] |
0x41ed92 VADDPD 0x40(%R8,%RAX,1),%YMM12,%YMM13 [3] |
0x41ed99 VADDPD %YMM13,%YMM11,%YMM14 |
0x41ed9e VMULPD %YMM5,%YMM14,%YMM15 |
0x41eda2 VMOVUPD %YMM15,0x40(%RBX,%RAX,1) [4] |
0x41eda8 VMOVUPD 0x60(%R13,%RAX,1),%YMM1 [1] |
0x41edaf VMOVUPD 0x60(%R12,%RAX,1),%YMM2 [2] |
0x41edb6 VADDPD 0x60(%R9,%RAX,1),%YMM1,%YMM0 [5] |
0x41edbd VADDPD 0x60(%R8,%RAX,1),%YMM2,%YMM7 [3] |
0x41edc4 VADDPD %YMM7,%YMM0,%YMM6 |
0x41edc8 VMULPD %YMM5,%YMM6,%YMM8 |
0x41edcc VMOVUPD %YMM8,0x60(%RBX,%RAX,1) [4] |
0x41edd2 SUB $-0x80,%RAX |
0x41edd6 CMP %R10,%RAX |
0x41edd9 JNE 41ed2c |
/scratch_na/users/xoserete/qaas_runs/171-415-7190/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 196 - 196 |
-------------------------------------------------------------------------------- |
196: +mass_flux_y(j-1,k+1)+mass_flux_y(j ,k+1)) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○98.19 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
○1.81 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.50 |
CQA speedup if fully vectorized | 2.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.26 |
Bottlenecks | P1, |
Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
Source | advec_mom_kernel.f90:196-196 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 8.00 |
CQA cycles if no scalar integer | 8.00 |
CQA cycles if FP arith vectorized | 5.33 |
CQA cycles if fully vectorized | 4.00 |
Front-end cycles | 6.33 |
DIV/SQRT cycles | 4.00 |
P0 cycles | 8.00 |
P1 cycles | 5.33 |
P2 cycles | 5.33 |
P3 cycles | 2.00 |
P4 cycles | 6.00 |
P5 cycles | 1.00 |
P6 cycles | 2.00 |
P7 cycles | 2.00 |
P8 cycles | 2.00 |
P9 cycles | 0.00 |
P10 cycles | 5.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 6.56 |
Stall cycles (UFS) | 0.00 |
Nb insns | 31.00 |
Nb uops | 30.00 |
Nb loads | 16.00 |
Nb stores | 4.00 |
Nb stack references | 0.00 |
FLOP/cycle | 8.00 |
Nb FLOP add-sub | 48.00 |
Nb FLOP mul | 16.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 80.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 512.00 |
Bytes stored | 128.00 |
Stride 0 | 0.00 |
Stride 1 | 5.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 50.00 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | 50.00 |
Vector-efficiency ratio mul | 50.00 |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.50 |
CQA speedup if fully vectorized | 2.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.26 |
Bottlenecks | P1, |
Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
Source | advec_mom_kernel.f90:196-196 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 8.00 |
CQA cycles if no scalar integer | 8.00 |
CQA cycles if FP arith vectorized | 5.33 |
CQA cycles if fully vectorized | 4.00 |
Front-end cycles | 6.33 |
DIV/SQRT cycles | 4.00 |
P0 cycles | 8.00 |
P1 cycles | 5.33 |
P2 cycles | 5.33 |
P3 cycles | 2.00 |
P4 cycles | 6.00 |
P5 cycles | 1.00 |
P6 cycles | 2.00 |
P7 cycles | 2.00 |
P8 cycles | 2.00 |
P9 cycles | 0.00 |
P10 cycles | 5.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 6.56 |
Stall cycles (UFS) | 0.00 |
Nb insns | 31.00 |
Nb uops | 30.00 |
Nb loads | 16.00 |
Nb stores | 4.00 |
Nb stack references | 0.00 |
FLOP/cycle | 8.00 |
Nb FLOP add-sub | 48.00 |
Nb FLOP mul | 16.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 80.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 512.00 |
Bytes stored | 128.00 |
Stride 0 | 0.00 |
Stride 1 | 5.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 50.00 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | 50.00 |
Vector-efficiency ratio mul | 50.00 |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Path / |
Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
Source file and lines | advec_mom_kernel.f90:196-196 |
Module | exec |
nb instructions | 31 |
nb uops | 30 |
loop length | 179 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 14 |
used zmm registers | 0 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 3.00 |
micro-operation queue | 6.33 cycles |
front end | 6.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.00 | 6.00 | 5.33 | 5.33 | 2.00 | 6.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 5.33 |
cycles | 4.00 | 8.00 | 5.33 | 5.33 | 2.00 | 6.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 5.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 6.56 |
Stall cycles | 0.00 |
Front-end | 6.33 |
Dispatch | 8.00 |
Data deps. | 1.00 |
Overall L1 | 8.00 |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 50% |
load | 50% |
store | 50% |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R13,%RAX,1),%YMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD (%R12,%RAX,1),%YMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VADDPD (%R9,%RAX,1),%YMM11,%YMM12 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VADDPD (%R8,%RAX,1),%YMM13,%YMM14 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VADDPD %YMM14,%YMM12,%YMM15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD %YMM5,%YMM15,%YMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM1,(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVUPD 0x20(%R13,%RAX,1),%YMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x20(%R12,%RAX,1),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VADDPD 0x20(%R9,%RAX,1),%YMM0,%YMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VADDPD 0x20(%R8,%RAX,1),%YMM7,%YMM6 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VADDPD %YMM6,%YMM2,%YMM8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD %YMM5,%YMM8,%YMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM9,0x20(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVUPD 0x40(%R13,%RAX,1),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x40(%R12,%RAX,1),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VADDPD 0x40(%R9,%RAX,1),%YMM10,%YMM11 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VADDPD 0x40(%R8,%RAX,1),%YMM12,%YMM13 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VADDPD %YMM13,%YMM11,%YMM14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD %YMM5,%YMM14,%YMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM15,0x40(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVUPD 0x60(%R13,%RAX,1),%YMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x60(%R12,%RAX,1),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VADDPD 0x60(%R9,%RAX,1),%YMM1,%YMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VADDPD 0x60(%R8,%RAX,1),%YMM2,%YMM7 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VADDPD %YMM7,%YMM0,%YMM6 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD %YMM5,%YMM6,%YMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM8,0x60(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
SUB $-0x80,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R10,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 41ed2c <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x277c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | __advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0 |
Source file and lines | advec_mom_kernel.f90:196-196 |
Module | exec |
nb instructions | 31 |
nb uops | 30 |
loop length | 179 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 14 |
used zmm registers | 0 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 3.00 |
micro-operation queue | 6.33 cycles |
front end | 6.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.00 | 6.00 | 5.33 | 5.33 | 2.00 | 6.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 5.33 |
cycles | 4.00 | 8.00 | 5.33 | 5.33 | 2.00 | 6.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 5.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 6.56 |
Stall cycles | 0.00 |
Front-end | 6.33 |
Dispatch | 8.00 |
Data deps. | 1.00 |
Overall L1 | 8.00 |
all | 100% |
load | 100% |
store | 100% |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 50% |
load | 50% |
store | 50% |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R13,%RAX,1),%YMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD (%R12,%RAX,1),%YMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VADDPD (%R9,%RAX,1),%YMM11,%YMM12 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VADDPD (%R8,%RAX,1),%YMM13,%YMM14 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VADDPD %YMM14,%YMM12,%YMM15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD %YMM5,%YMM15,%YMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM1,(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVUPD 0x20(%R13,%RAX,1),%YMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x20(%R12,%RAX,1),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VADDPD 0x20(%R9,%RAX,1),%YMM0,%YMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VADDPD 0x20(%R8,%RAX,1),%YMM7,%YMM6 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VADDPD %YMM6,%YMM2,%YMM8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD %YMM5,%YMM8,%YMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM9,0x20(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVUPD 0x40(%R13,%RAX,1),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x40(%R12,%RAX,1),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VADDPD 0x40(%R9,%RAX,1),%YMM10,%YMM11 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VADDPD 0x40(%R8,%RAX,1),%YMM12,%YMM13 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VADDPD %YMM13,%YMM11,%YMM14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD %YMM5,%YMM14,%YMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM15,0x40(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVUPD 0x60(%R13,%RAX,1),%YMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x60(%R12,%RAX,1),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VADDPD 0x60(%R9,%RAX,1),%YMM1,%YMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VADDPD 0x60(%R8,%RAX,1),%YMM2,%YMM7 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VADDPD %YMM7,%YMM0,%YMM6 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPD %YMM5,%YMM6,%YMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVUPD %YMM8,0x60(%RBX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
SUB $-0x80,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R10,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 41ed2c <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x277c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |