Function: generate_chunk_kernel._omp_fn.0 | Module: exec | Source: generate_chunk_kernel.f90:85-161 | Coverage: 0.03% |
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Function: generate_chunk_kernel._omp_fn.0 | Module: exec | Source: generate_chunk_kernel.f90:85-161 | Coverage: 0.03% |
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/scratch_na/users/xoserete/qaas_runs/171-322-0339/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90: 85 - 161 |
-------------------------------------------------------------------------------- |
85: !$OMP PARALLEL SHARED(x_cent,y_cent) |
86: !$OMP DO |
87: DO k=y_min-2,y_max+2 |
88: !$OMP SIMD |
89: DO j=x_min-2,x_max+2 |
90: energy0(j,k)=state_energy(1) |
91: ENDDO |
92: ENDDO |
93: !$OMP END DO |
94: !$OMP DO |
95: DO k=y_min-2,y_max+2 |
96: !$OMP SIMD |
97: DO j=x_min-2,x_max+2 |
98: density0(j,k)=state_density(1) |
99: ENDDO |
100: ENDDO |
101: !$OMP END DO |
102: !$OMP DO |
103: DO k=y_min-2,y_max+2 |
104: !$OMP SIMD |
105: DO j=x_min-2,x_max+2 |
106: xvel0(j,k)=state_xvel(1) |
107: ENDDO |
108: ENDDO |
109: !$OMP END DO |
110: !$OMP DO |
111: DO k=y_min-2,y_max+2 |
112: !$OMP SIMD |
113: DO j=x_min-2,x_max+2 |
114: yvel0(j,k)=state_yvel(1) |
115: ENDDO |
116: ENDDO |
117: !$OMP END DO |
118: |
119: DO state=2,number_of_states |
120: |
121: ! Could the velocity setting be thread unsafe? |
122: x_cent=state_xmin(state) |
123: y_cent=state_ymin(state) |
124: |
125: !$OMP DO PRIVATE(radius,jt,kt) |
126: DO k=y_min-2,y_max+2 |
127: !$OMP SIMD |
128: DO j=x_min-2,x_max+2 |
129: IF(state_geometry(state).EQ.g_rect ) THEN |
130: IF(vertexx(j+1).GE.state_xmin(state).AND.vertexx(j).LT.state_xmax(state)) THEN |
131: IF(vertexy(k+1).GE.state_ymin(state).AND.vertexy(k).LT.state_ymax(state)) THEN |
132: energy0(j,k)=state_energy(state) |
133: density0(j,k)=state_density(state) |
134: DO kt=k,k+1 |
135: DO jt=j,j+1 |
136: xvel0(jt,kt)=state_xvel(state) |
137: yvel0(jt,kt)=state_yvel(state) |
138: ENDDO |
139: ENDDO |
140: ENDIF |
141: ENDIF |
142: ELSEIF(state_geometry(state).EQ.g_circ ) THEN |
143: radius=SQRT((cellx(j)-x_cent)*(cellx(j)-x_cent)+(celly(k)-y_cent)*(celly(k)-y_cent)) |
144: IF(radius.LE.state_radius(state))THEN |
145: energy0(j,k)=state_energy(state) |
146: density0(j,k)=state_density(state) |
147: DO kt=k,k+1 |
148: DO jt=j,j+1 |
149: xvel0(jt,kt)=state_xvel(state) |
150: yvel0(jt,kt)=state_yvel(state) |
151: ENDDO |
152: ENDDO |
153: ENDIF |
154: ELSEIF(state_geometry(state).EQ.g_point) THEN |
155: IF(vertexx(j).EQ.x_cent .AND. vertexy(k).EQ.y_cent) THEN |
156: energy0(j,k)=state_energy(state) |
157: density0(j,k)=state_density(state) |
158: DO kt=k,k+1 |
159: DO jt=j,j+1 |
160: xvel0(jt,kt)=state_xvel(state) |
161: yvel0(jt,kt)=state_yvel(state) |
0x44a420 PUSH %RBP |
0x44a421 MOV %RSP,%RBP |
0x44a424 PUSH %R15 |
0x44a426 PUSH %R14 |
0x44a428 MOV %RDI,%R14 |
0x44a42b PUSH %R13 |
0x44a42d PUSH %R12 |
0x44a42f PUSH %RBX |
0x44a430 AND $-0x40,%RSP |
0x44a434 SUB $0x180,%RSP |
0x44a43b MOV 0x120(%RDI),%RDX |
0x44a442 MOV 0x118(%RDI),%RCX |
0x44a449 MOV 0x108(%RDI),%RSI |
0x44a450 MOV 0x100(%RDI),%R8 |
0x44a457 MOV 0xf8(%RDI),%R9 |
0x44a45e MOV 0xf0(%RDI),%R10 |
0x44a465 MOV %RDX,0x160(%RSP) |
0x44a46d MOV 0xe8(%RDI),%R11 |
0x44a474 MOV 0x128(%RDI),%RAX |
0x44a47b MOV %RCX,0x60(%RSP) |
0x44a480 MOV 0x110(%RDI),%RBX |
0x44a487 MOV 0xe0(%RDI),%R12 |
0x44a48e MOV %RSI,0x40(%RSP) |
0x44a493 MOV 0xd8(%RDI),%R13 |
0x44a49a MOV 0xd0(%RDI),%R15 |
0x44a4a1 MOV %R8,0x30(%RSP) |
0x44a4a6 MOV 0x10(%RDI),%RDI |
0x44a4aa MOV %R9,0x48(%RSP) |
0x44a4af MOV %R10,0x138(%RSP) |
0x44a4b7 MOV %R11,0x50(%RSP) |
0x44a4bc MOV %RAX,0x38(%RSP) |
0x44a4c1 MOV %RBX,0x170(%RSP) |
0x44a4c9 MOV %R12,0x130(%RSP) |
0x44a4d1 MOV %R13,0x118(%RSP) |
0x44a4d9 MOV %R15,0x28(%RSP) |
0x44a4de MOV (%RDI),%R12D |
0x44a4e1 CALL 402080 <@plt_start@+0x60> |
0x44a4e6 MOV %EAX,%EBX |
0x44a4e8 MOV %EAX,0xb8(%RSP) |
0x44a4ef SUB $0x2,%R12D |
0x44a4f3 CALL 402180 <@plt_start@+0x160> |
0x44a4f8 MOV %EAX,0x124(%RSP) |
0x44a4ff MOV %EAX,%ECX |
0x44a501 MOV 0x18(%R14),%RAX |
0x44a505 MOV (%RAX),%EAX |
0x44a507 ADD $0x3,%EAX |
0x44a50a SUB %R12D,%EAX |
0x44a50d CLTD |
0x44a50e IDIV %EBX |
0x44a510 CMP %EDX,%ECX |
0x44a512 JL 44be0d |
0x44a518 MOV 0x124(%RSP),%ESI |
0x44a51f IMUL %EAX,%ESI |
0x44a522 ADD %ESI,%EDX |
0x44a524 ADD %EDX,%EAX |
0x44a526 CMP %EAX,%EDX |
0x44a528 JGE 44a80e |
0x44a52e MOV 0x138(%RSP),%RDI |
0x44a536 LEA (%R12,%RDX,1),%EBX |
0x44a53a MOV (%R14),%R8 |
0x44a53d ADD %R12D,%EAX |
0x44a540 KXORB %K4,%K4,%K4 |
0x44a544 MOV 0x8(%R14),%R9 |
0x44a548 MOVSXD %EBX,%RSI |
0x44a54b MOV 0x48(%RSP),%RDX |
0x44a550 MOV %EAX,0x16c(%RSP) |
0x44a557 IMUL %RDI,%RSI |
0x44a55b MOVSXD (%R8),%R13 |
0x44a55e LEA (,%RDI,8),%RCX |
0x44a566 MOV 0x48(%R14),%R10 |
0x44a56a MOV (%R9),%R12D |
0x44a56d MOV 0x70(%R14),%RAX |
0x44a571 MOV %RCX,0x158(%RSP) |
0x44a579 LEA (%R13,%RDX,1),%R9 |
0x44a57e LEA -0x2(%R13),%R15D |
0x44a582 LEA 0x3(%R12),%R8D |
0x44a587 SUB %R13D,%R12D |
0x44a58a ADD %RSI,%R9 |
0x44a58d ADD %RDX,%RSI |
0x44a590 MOV %R12D,%R11D |
0x44a593 LEA 0x5(%R12),%EDX |
0x44a598 MOV %R12D,0x148(%RSP) |
0x44a5a0 LEA 0x4(%R12),%R12D |
0x44a5a5 MOV %EDX,%ECX |
0x44a5a7 MOV %R12D,0x150(%RSP) |
0x44a5af MOV %EDX,%R12D |
0x44a5b2 LEA -0x10(%R10,%R9,8),%RDI |
0x44a5b7 AND $-0x8,%ECX |
0x44a5ba SHR $0x3,%R12D |
0x44a5be LEA 0x5(%R15,%R11,1),%R9D |
0x44a5c3 MOV %ECX,0x168(%RSP) |
0x44a5ca SAL $0x6,%R12 |
0x44a5ce ADD %R15D,%ECX |
0x44a5d1 CMP %R8D,%R15D |
0x44a5d4 CMOVGE %R15D,%R9D |
0x44a5d8 AND $0x7,%EDX |
0x44a5db MOV %ECX,0x128(%RSP) |
0x44a5e2 MOV %EDX,0x140(%RSP) |
0x44a5e9 MOV %R9D,0x178(%RSP) |
0x44a5f1 NOPL (%RAX) |
(240) 0x44a5f8 CMP %R8D,%R15D |
(240) 0x44a5fb JGE 44a7cb |
(240) 0x44a601 CMPL $0x6,0x150(%RSP) |
(240) 0x44a609 JBE 44bd46 |
(240) 0x44a60f LEA -0x40(%R12),%R9 |
(240) 0x44a614 LEA (%R12,%RDI,1),%R11 |
(240) 0x44a618 MOV %RDI,%RDX |
(240) 0x44a61b SHR $0x6,%R9 |
(240) 0x44a61f INC %R9 |
(240) 0x44a622 AND $0x7,%R9D |
(240) 0x44a626 JE 44a6bf |
(240) 0x44a62c CMP $0x1,%R9 |
(240) 0x44a630 JE 44a6a9 |
(240) 0x44a632 CMP $0x2,%R9 |
(240) 0x44a636 JE 44a698 |
(240) 0x44a638 CMP $0x3,%R9 |
(240) 0x44a63c JE 44a687 |
(240) 0x44a63e CMP $0x4,%R9 |
(240) 0x44a642 JE 44a676 |
(240) 0x44a644 CMP $0x5,%R9 |
(240) 0x44a648 JE 44a665 |
(240) 0x44a64a CMP $0x6,%R9 |
(240) 0x44a64e JNE 44bcd0 |
(240) 0x44a654 VBROADCASTSD (%RAX),%ZMM1 |
(240) 0x44a65a ADD $0x40,%RDX |
(240) 0x44a65e VMOVUPD %ZMM1,-0x40(%RDX) |
(240) 0x44a665 VBROADCASTSD (%RAX),%ZMM2 |
(240) 0x44a66b ADD $0x40,%RDX |
(240) 0x44a66f VMOVUPD %ZMM2,-0x40(%RDX) |
(240) 0x44a676 VBROADCASTSD (%RAX),%ZMM3 |
(240) 0x44a67c ADD $0x40,%RDX |
(240) 0x44a680 VMOVUPD %ZMM3,-0x40(%RDX) |
(240) 0x44a687 VBROADCASTSD (%RAX),%ZMM4 |
(240) 0x44a68d ADD $0x40,%RDX |
(240) 0x44a691 VMOVUPD %ZMM4,-0x40(%RDX) |
(240) 0x44a698 VBROADCASTSD (%RAX),%ZMM5 |
(240) 0x44a69e ADD $0x40,%RDX |
(240) 0x44a6a2 VMOVUPD %ZMM5,-0x40(%RDX) |
(240) 0x44a6a9 VBROADCASTSD (%RAX),%ZMM6 |
(240) 0x44a6af ADD $0x40,%RDX |
(240) 0x44a6b3 VMOVUPD %ZMM6,-0x40(%RDX) |
(240) 0x44a6ba CMP %R11,%RDX |
(240) 0x44a6bd JE 44a733 |
(241) 0x44a6bf VBROADCASTSD (%RAX),%ZMM7 |
(241) 0x44a6c5 ADD $0x200,%RDX |
(241) 0x44a6cc VMOVUPD %ZMM7,-0x200(%RDX) |
(241) 0x44a6d3 VBROADCASTSD (%RAX),%ZMM8 |
(241) 0x44a6d9 VMOVUPD %ZMM8,-0x1c0(%RDX) |
(241) 0x44a6e0 VBROADCASTSD (%RAX),%ZMM9 |
(241) 0x44a6e6 VMOVUPD %ZMM9,-0x180(%RDX) |
(241) 0x44a6ed VBROADCASTSD (%RAX),%ZMM10 |
(241) 0x44a6f3 VMOVUPD %ZMM10,-0x140(%RDX) |
(241) 0x44a6fa VBROADCASTSD (%RAX),%ZMM11 |
(241) 0x44a700 VMOVUPD %ZMM11,-0x100(%RDX) |
(241) 0x44a707 VBROADCASTSD (%RAX),%ZMM12 |
(241) 0x44a70d VMOVUPD %ZMM12,-0xc0(%RDX) |
(241) 0x44a714 VBROADCASTSD (%RAX),%ZMM13 |
(241) 0x44a71a VMOVUPD %ZMM13,-0x80(%RDX) |
(241) 0x44a721 VBROADCASTSD (%RAX),%ZMM14 |
(241) 0x44a727 VMOVUPD %ZMM14,-0x40(%RDX) |
(241) 0x44a72e CMP %R11,%RDX |
(241) 0x44a731 JNE 44a6bf |
(240) 0x44a733 MOV 0x140(%RSP),%ECX |
(240) 0x44a73a TEST %ECX,%ECX |
(240) 0x44a73c JE 44a7cb |
(240) 0x44a742 MOV 0x168(%RSP),%ECX |
(240) 0x44a749 MOV 0x128(%RSP),%EDX |
(240) 0x44a750 MOV 0x148(%RSP),%R11D |
(240) 0x44a758 SUB %ECX,%R11D |
(240) 0x44a75b LEA 0x5(%R11),%R9D |
(240) 0x44a75f ADD $0x4,%R11D |
(240) 0x44a763 CMP $0x2,%R11D |
(240) 0x44a767 JBE 44a78f |
(240) 0x44a769 MOV %ECX,%R11D |
(240) 0x44a76c LEA (%RSI,%R13,1),%RCX |
(240) 0x44a770 VBROADCASTSD (%RAX),%YMM15 |
(240) 0x44a775 ADD %R11,%RCX |
(240) 0x44a778 MOV %R9D,%R11D |
(240) 0x44a77b AND $-0x4,%R11D |
(240) 0x44a77f VMOVUPD %YMM15,-0x10(%R10,%RCX,8) |
(240) 0x44a786 ADD %R11D,%EDX |
(240) 0x44a789 AND $0x3,%R9D |
(240) 0x44a78d JE 44a7cb |
(240) 0x44a78f VMOVSD (%RAX),%XMM0 |
(240) 0x44a793 MOVSXD %EDX,%R9 |
(240) 0x44a796 LEA 0x1(%RDX),%ECX |
(240) 0x44a799 ADD %RSI,%R9 |
(240) 0x44a79c VMOVSD %XMM0,(%R10,%R9,8) |
(240) 0x44a7a2 CMP %ECX,%R8D |
(240) 0x44a7a5 JLE 44a7cb |
(240) 0x44a7a7 MOVSXD %ECX,%R11 |
(240) 0x44a7aa ADD $0x2,%EDX |
(240) 0x44a7ad ADD %RSI,%R11 |
(240) 0x44a7b0 VMOVSD %XMM0,(%R10,%R11,8) |
(240) 0x44a7b6 CMP %EDX,%R8D |
(240) 0x44a7b9 JLE 44a7cb |
(240) 0x44a7bb VMOVSD (%RAX),%XMM1 |
(240) 0x44a7bf MOVSXD %EDX,%RDX |
(240) 0x44a7c2 ADD %RSI,%RDX |
(240) 0x44a7c5 VMOVSD %XMM1,(%R10,%RDX,8) |
(240) 0x44a7cb MOV 0x178(%RSP),%R9D |
(240) 0x44a7d3 INC %EBX |
(240) 0x44a7d5 MOV 0x158(%RSP),%RCX |
(240) 0x44a7dd CMP %R9D,%R8D |
(240) 0x44a7e0 JE 44b800 |
(240) 0x44a7e6 MOV 0x138(%RSP),%R11 |
(240) 0x44a7ee ADD %RCX,%RDI |
(240) 0x44a7f1 ADD %R11,%RSI |
(240) 0x44a7f4 CMP %EBX,0x16c(%RSP) |
(240) 0x44a7fb JG 44a5f8 |
0x44a801 KORTESTB %K4,%K4 |
0x44a805 JNE 44bdcd |
0x44a80b VZEROUPPER |
0x44a80e CALL 402220 <@plt_start@+0x200> |
0x44a813 MOV 0x10(%R14),%R15 |
0x44a817 MOV 0x18(%R14),%RAX |
0x44a81b MOV (%R15),%R8D |
0x44a81e MOV (%RAX),%EAX |
0x44a820 SUB $0x2,%R8D |
0x44a824 ADD $0x3,%EAX |
0x44a827 SUB %R8D,%EAX |
0x44a82a CLTD |
0x44a82b IDIVL 0xb8(%RSP) |
0x44a832 CMP %EDX,0x124(%RSP) |
0x44a839 JL 44bdfb |
0x44a83f MOV 0x124(%RSP),%R10D |
0x44a847 IMUL %EAX,%R10D |
0x44a84b ADD %R10D,%EDX |
0x44a84e ADD %EDX,%EAX |
0x44a850 CMP %EAX,%EDX |
0x44a852 JGE 44ab2e |
0x44a858 MOV (%R14),%RSI |
0x44a85b MOV 0x8(%R14),%RDI |
0x44a85f ADD %R8D,%EAX |
0x44a862 LEA (%R8,%RDX,1),%R11D |
0x44a866 KXORB %K3,%K3,%K3 |
0x44a86a MOV 0x130(%RSP),%R8 |
0x44a872 MOV 0x50(%RSP),%R10 |
0x44a877 MOV %EAX,0x16c(%RSP) |
0x44a87e MOVSXD (%RSI),%R13 |
0x44a881 MOV (%RDI),%ECX |
0x44a883 MOVSXD %R11D,%RSI |
0x44a886 IMUL %R8,%RSI |
0x44a88a LEA (,%R8,8),%RDX |
0x44a892 MOV 0x40(%R14),%R9 |
0x44a896 MOV 0x68(%R14),%RAX |
0x44a89a LEA 0x3(%RCX),%EBX |
0x44a89d SUB %R13D,%ECX |
0x44a8a0 MOV %RDX,0x158(%RSP) |
0x44a8a8 LEA -0x2(%R13),%R15D |
0x44a8ac LEA 0x5(%RCX),%EDX |
0x44a8af LEA 0x4(%RCX),%R12D |
0x44a8b3 MOV %ECX,%R8D |
0x44a8b6 MOV %ECX,0x148(%RSP) |
0x44a8bd MOV %R12D,0x150(%RSP) |
0x44a8c5 MOV %EDX,%ECX |
0x44a8c7 MOV %EDX,%R12D |
0x44a8ca LEA (%R10,%R13,1),%RDI |
0x44a8ce AND $-0x8,%ECX |
0x44a8d1 SHR $0x3,%R12D |
0x44a8d5 ADD %RSI,%RDI |
0x44a8d8 ADD %R10,%RSI |
0x44a8db MOV %ECX,0x168(%RSP) |
0x44a8e2 SAL $0x6,%R12 |
0x44a8e6 ADD %R15D,%ECX |
0x44a8e9 LEA 0x5(%R15,%R8,1),%R10D |
0x44a8ee CMP %R15D,%EBX |
0x44a8f1 MOV %ECX,0x128(%RSP) |
0x44a8f8 LEA -0x10(%R9,%RDI,8),%RDI |
0x44a8fd CMOVLE %R15D,%R10D |
0x44a901 AND $0x7,%EDX |
0x44a904 MOV %EDX,0x140(%RSP) |
0x44a90b MOV %R10D,0x178(%RSP) |
0x44a913 NOPL (%RAX,%RAX,1) |
(238) 0x44a918 CMP %R15D,%EBX |
(238) 0x44a91b JLE 44aae9 |
(238) 0x44a921 CMPL $0x6,0x150(%RSP) |
(238) 0x44a929 JBE 44bd32 |
(238) 0x44a92f LEA -0x40(%R12),%R10 |
(238) 0x44a934 LEA (%R12,%RDI,1),%R8 |
(238) 0x44a938 MOV %RDI,%RDX |
(238) 0x44a93b SHR $0x6,%R10 |
(238) 0x44a93f INC %R10 |
(238) 0x44a942 AND $0x7,%R10D |
(238) 0x44a946 JE 44a9df |
(238) 0x44a94c CMP $0x1,%R10 |
(238) 0x44a950 JE 44a9c9 |
(238) 0x44a952 CMP $0x2,%R10 |
(238) 0x44a956 JE 44a9b8 |
(238) 0x44a958 CMP $0x3,%R10 |
(238) 0x44a95c JE 44a9a7 |
(238) 0x44a95e CMP $0x4,%R10 |
(238) 0x44a962 JE 44a996 |
(238) 0x44a964 CMP $0x5,%R10 |
(238) 0x44a968 JE 44a985 |
(238) 0x44a96a CMP $0x6,%R10 |
(238) 0x44a96e JNE 44bcbb |
(238) 0x44a974 VBROADCASTSD (%RAX),%ZMM3 |
(238) 0x44a97a ADD $0x40,%RDX |
(238) 0x44a97e VMOVUPD %ZMM3,-0x40(%RDX) |
(238) 0x44a985 VBROADCASTSD (%RAX),%ZMM4 |
(238) 0x44a98b ADD $0x40,%RDX |
(238) 0x44a98f VMOVUPD %ZMM4,-0x40(%RDX) |
(238) 0x44a996 VBROADCASTSD (%RAX),%ZMM5 |
(238) 0x44a99c ADD $0x40,%RDX |
(238) 0x44a9a0 VMOVUPD %ZMM5,-0x40(%RDX) |
(238) 0x44a9a7 VBROADCASTSD (%RAX),%ZMM6 |
(238) 0x44a9ad ADD $0x40,%RDX |
(238) 0x44a9b1 VMOVUPD %ZMM6,-0x40(%RDX) |
(238) 0x44a9b8 VBROADCASTSD (%RAX),%ZMM7 |
(238) 0x44a9be ADD $0x40,%RDX |
(238) 0x44a9c2 VMOVUPD %ZMM7,-0x40(%RDX) |
(238) 0x44a9c9 VBROADCASTSD (%RAX),%ZMM8 |
(238) 0x44a9cf ADD $0x40,%RDX |
(238) 0x44a9d3 VMOVUPD %ZMM8,-0x40(%RDX) |
(238) 0x44a9da CMP %R8,%RDX |
(238) 0x44a9dd JE 44aa53 |
(239) 0x44a9df VBROADCASTSD (%RAX),%ZMM9 |
(239) 0x44a9e5 ADD $0x200,%RDX |
(239) 0x44a9ec VMOVUPD %ZMM9,-0x200(%RDX) |
(239) 0x44a9f3 VBROADCASTSD (%RAX),%ZMM10 |
(239) 0x44a9f9 VMOVUPD %ZMM10,-0x1c0(%RDX) |
(239) 0x44aa00 VBROADCASTSD (%RAX),%ZMM11 |
(239) 0x44aa06 VMOVUPD %ZMM11,-0x180(%RDX) |
(239) 0x44aa0d VBROADCASTSD (%RAX),%ZMM12 |
(239) 0x44aa13 VMOVUPD %ZMM12,-0x140(%RDX) |
(239) 0x44aa1a VBROADCASTSD (%RAX),%ZMM13 |
(239) 0x44aa20 VMOVUPD %ZMM13,-0x100(%RDX) |
(239) 0x44aa27 VBROADCASTSD (%RAX),%ZMM14 |
(239) 0x44aa2d VMOVUPD %ZMM14,-0xc0(%RDX) |
(239) 0x44aa34 VBROADCASTSD (%RAX),%ZMM15 |
(239) 0x44aa3a VMOVUPD %ZMM15,-0x80(%RDX) |
(239) 0x44aa41 VBROADCASTSD (%RAX),%ZMM0 |
(239) 0x44aa47 VMOVUPD %ZMM0,-0x40(%RDX) |
(239) 0x44aa4e CMP %R8,%RDX |
(239) 0x44aa51 JNE 44a9df |
(238) 0x44aa53 MOV 0x140(%RSP),%ECX |
(238) 0x44aa5a TEST %ECX,%ECX |
(238) 0x44aa5c JE 44aae9 |
(238) 0x44aa62 MOV 0x168(%RSP),%ECX |
(238) 0x44aa69 MOV 0x128(%RSP),%EDX |
(238) 0x44aa70 MOV 0x148(%RSP),%R10D |
(238) 0x44aa78 SUB %ECX,%R10D |
(238) 0x44aa7b LEA 0x5(%R10),%R8D |
(238) 0x44aa7f ADD $0x4,%R10D |
(238) 0x44aa83 CMP $0x2,%R10D |
(238) 0x44aa87 JBE 44aaaf |
(238) 0x44aa89 MOV %ECX,%R10D |
(238) 0x44aa8c LEA (%RSI,%R13,1),%RCX |
(238) 0x44aa90 VBROADCASTSD (%RAX),%YMM1 |
(238) 0x44aa95 ADD %R10,%RCX |
(238) 0x44aa98 MOV %R8D,%R10D |
(238) 0x44aa9b AND $-0x4,%R10D |
(238) 0x44aa9f VMOVUPD %YMM1,-0x10(%R9,%RCX,8) |
(238) 0x44aaa6 ADD %R10D,%EDX |
(238) 0x44aaa9 AND $0x3,%R8D |
(238) 0x44aaad JE 44aae9 |
(238) 0x44aaaf VMOVSD (%RAX),%XMM2 |
(238) 0x44aab3 MOVSXD %EDX,%R8 |
(238) 0x44aab6 LEA 0x1(%RDX),%ECX |
(238) 0x44aab9 ADD %RSI,%R8 |
(238) 0x44aabc VMOVSD %XMM2,(%R9,%R8,8) |
(238) 0x44aac2 CMP %ECX,%EBX |
(238) 0x44aac4 JLE 44aae9 |
(238) 0x44aac6 MOVSXD %ECX,%R10 |
(238) 0x44aac9 ADD $0x2,%EDX |
(238) 0x44aacc ADD %RSI,%R10 |
(238) 0x44aacf VMOVSD %XMM2,(%R9,%R10,8) |
(238) 0x44aad5 CMP %EDX,%EBX |
(238) 0x44aad7 JLE 44aae9 |
(238) 0x44aad9 VMOVSD (%RAX),%XMM3 |
(238) 0x44aadd MOVSXD %EDX,%RDX |
(238) 0x44aae0 ADD %RSI,%RDX |
(238) 0x44aae3 VMOVSD %XMM3,(%R9,%RDX,8) |
(238) 0x44aae9 MOV 0x178(%RSP),%R8D |
(238) 0x44aaf1 INC %R11D |
(238) 0x44aaf4 MOV 0x158(%RSP),%RCX |
(238) 0x44aafc CMP %R8D,%EBX |
(238) 0x44aaff JE 44b833 |
(238) 0x44ab05 MOV 0x130(%RSP),%R10 |
(238) 0x44ab0d ADD %RCX,%RDI |
(238) 0x44ab10 ADD %R10,%RSI |
(238) 0x44ab13 CMP %R11D,0x16c(%RSP) |
(238) 0x44ab1b JG 44a918 |
0x44ab21 KORTESTB %K3,%K3 |
0x44ab25 JNE 44bda6 |
0x44ab2b VZEROUPPER |
0x44ab2e CALL 402220 <@plt_start@+0x200> |
0x44ab33 MOV 0x10(%R14),%R15 |
0x44ab37 MOV 0x18(%R14),%RAX |
0x44ab3b MOV (%R15),%EBX |
0x44ab3e MOV (%RAX),%EAX |
0x44ab40 SUB $0x2,%EBX |
0x44ab43 ADD $0x3,%EAX |
0x44ab46 SUB %EBX,%EAX |
0x44ab48 CLTD |
0x44ab49 IDIVL 0xb8(%RSP) |
0x44ab50 CMP %EDX,0x124(%RSP) |
0x44ab57 JL 44be04 |
0x44ab5d MOV 0x124(%RSP),%R9D |
0x44ab65 IMUL %EAX,%R9D |
0x44ab69 ADD %R9D,%EDX |
0x44ab6c ADD %EDX,%EAX |
0x44ab6e CMP %EAX,%EDX |
0x44ab70 JGE 44ae4e |
0x44ab76 MOV (%R14),%RSI |
0x44ab79 MOV 0x8(%R14),%RDI |
0x44ab7d LEA (%RBX,%RDX,1),%R11D |
0x44ab81 ADD %EBX,%EAX |
0x44ab83 KXORB %K2,%K2,%K2 |
0x44ab87 MOV 0x170(%RSP),%RCX |
0x44ab8f MOV 0x60(%RSP),%RDX |
0x44ab94 MOV %EAX,0x16c(%RSP) |
0x44ab9b MOVSXD (%RSI),%R13 |
0x44ab9e MOV (%RDI),%R8D |
0x44aba1 MOVSXD %R11D,%RSI |
0x44aba4 IMUL %RCX,%RSI |
0x44aba8 LEA (,%RCX,8),%R10 |
0x44abb0 MOV 0x50(%R14),%R9 |
0x44abb4 MOV 0x78(%R14),%RAX |
0x44abb8 LEA 0x3(%R8),%EBX |
0x44abbc SUB %R13D,%R8D |
0x44abbf MOV %R10,0x158(%RSP) |
0x44abc7 LEA -0x2(%R13),%R15D |
0x44abcb LEA 0x5(%R8),%R10D |
0x44abcf LEA 0x4(%R8),%R12D |
0x44abd3 MOV %R8D,0x148(%RSP) |
0x44abdb MOV %R10D,%ECX |
0x44abde MOV %R12D,0x150(%RSP) |
0x44abe6 MOV %R10D,%R12D |
0x44abe9 LEA (%R13,%RDX,1),%RDI |
0x44abee AND $-0x8,%ECX |
0x44abf1 SHR $0x3,%R12D |
0x44abf5 ADD %RSI,%RDI |
0x44abf8 ADD %RDX,%RSI |
0x44abfb MOV %ECX,0x168(%RSP) |
0x44ac02 SAL $0x6,%R12 |
0x44ac06 ADD %R15D,%ECX |
0x44ac09 LEA 0x5(%R15,%R8,1),%EDX |
0x44ac0e CMP %R15D,%EBX |
0x44ac11 MOV %ECX,0x128(%RSP) |
0x44ac18 LEA -0x10(%R9,%RDI,8),%RDI |
0x44ac1d CMOVLE %R15D,%EDX |
0x44ac21 AND $0x7,%R10D |
0x44ac25 MOV %R10D,0x140(%RSP) |
0x44ac2d MOV %EDX,0x178(%RSP) |
0x44ac34 NOPL (%RAX) |
(236) 0x44ac38 CMP %R15D,%EBX |
(236) 0x44ac3b JLE 44ae09 |
(236) 0x44ac41 CMPL $0x6,0x150(%RSP) |
(236) 0x44ac49 JBE 44bd3c |
(236) 0x44ac4f LEA -0x40(%R12),%R10 |
(236) 0x44ac54 LEA (%R12,%RDI,1),%R8 |
(236) 0x44ac58 MOV %RDI,%RDX |
(236) 0x44ac5b SHR $0x6,%R10 |
(236) 0x44ac5f INC %R10 |
(236) 0x44ac62 AND $0x7,%R10D |
(236) 0x44ac66 JE 44acff |
(236) 0x44ac6c CMP $0x1,%R10 |
(236) 0x44ac70 JE 44ace9 |
(236) 0x44ac72 CMP $0x2,%R10 |
(236) 0x44ac76 JE 44acd8 |
(236) 0x44ac78 CMP $0x3,%R10 |
(236) 0x44ac7c JE 44acc7 |
(236) 0x44ac7e CMP $0x4,%R10 |
(236) 0x44ac82 JE 44acb6 |
(236) 0x44ac84 CMP $0x5,%R10 |
(236) 0x44ac88 JE 44aca5 |
(236) 0x44ac8a CMP $0x6,%R10 |
(236) 0x44ac8e JNE 44bca6 |
(236) 0x44ac94 VBROADCASTSD (%RAX),%ZMM5 |
(236) 0x44ac9a ADD $0x40,%RDX |
(236) 0x44ac9e VMOVUPD %ZMM5,-0x40(%RDX) |
(236) 0x44aca5 VBROADCASTSD (%RAX),%ZMM6 |
(236) 0x44acab ADD $0x40,%RDX |
(236) 0x44acaf VMOVUPD %ZMM6,-0x40(%RDX) |
(236) 0x44acb6 VBROADCASTSD (%RAX),%ZMM7 |
(236) 0x44acbc ADD $0x40,%RDX |
(236) 0x44acc0 VMOVUPD %ZMM7,-0x40(%RDX) |
(236) 0x44acc7 VBROADCASTSD (%RAX),%ZMM8 |
(236) 0x44accd ADD $0x40,%RDX |
(236) 0x44acd1 VMOVUPD %ZMM8,-0x40(%RDX) |
(236) 0x44acd8 VBROADCASTSD (%RAX),%ZMM9 |
(236) 0x44acde ADD $0x40,%RDX |
(236) 0x44ace2 VMOVUPD %ZMM9,-0x40(%RDX) |
(236) 0x44ace9 VBROADCASTSD (%RAX),%ZMM10 |
(236) 0x44acef ADD $0x40,%RDX |
(236) 0x44acf3 VMOVUPD %ZMM10,-0x40(%RDX) |
(236) 0x44acfa CMP %R8,%RDX |
(236) 0x44acfd JE 44ad73 |
(237) 0x44acff VBROADCASTSD (%RAX),%ZMM11 |
(237) 0x44ad05 ADD $0x200,%RDX |
(237) 0x44ad0c VMOVUPD %ZMM11,-0x200(%RDX) |
(237) 0x44ad13 VBROADCASTSD (%RAX),%ZMM12 |
(237) 0x44ad19 VMOVUPD %ZMM12,-0x1c0(%RDX) |
(237) 0x44ad20 VBROADCASTSD (%RAX),%ZMM13 |
(237) 0x44ad26 VMOVUPD %ZMM13,-0x180(%RDX) |
(237) 0x44ad2d VBROADCASTSD (%RAX),%ZMM14 |
(237) 0x44ad33 VMOVUPD %ZMM14,-0x140(%RDX) |
(237) 0x44ad3a VBROADCASTSD (%RAX),%ZMM15 |
(237) 0x44ad40 VMOVUPD %ZMM15,-0x100(%RDX) |
(237) 0x44ad47 VBROADCASTSD (%RAX),%ZMM0 |
(237) 0x44ad4d VMOVUPD %ZMM0,-0xc0(%RDX) |
(237) 0x44ad54 VBROADCASTSD (%RAX),%ZMM1 |
(237) 0x44ad5a VMOVUPD %ZMM1,-0x80(%RDX) |
(237) 0x44ad61 VBROADCASTSD (%RAX),%ZMM2 |
(237) 0x44ad67 VMOVUPD %ZMM2,-0x40(%RDX) |
(237) 0x44ad6e CMP %R8,%RDX |
(237) 0x44ad71 JNE 44acff |
(236) 0x44ad73 MOV 0x140(%RSP),%ECX |
(236) 0x44ad7a TEST %ECX,%ECX |
(236) 0x44ad7c JE 44ae09 |
(236) 0x44ad82 MOV 0x168(%RSP),%ECX |
(236) 0x44ad89 MOV 0x128(%RSP),%EDX |
(236) 0x44ad90 MOV 0x148(%RSP),%R10D |
(236) 0x44ad98 SUB %ECX,%R10D |
(236) 0x44ad9b LEA 0x5(%R10),%R8D |
(236) 0x44ad9f ADD $0x4,%R10D |
(236) 0x44ada3 CMP $0x2,%R10D |
(236) 0x44ada7 JBE 44adcf |
(236) 0x44ada9 MOV %ECX,%R10D |
(236) 0x44adac LEA (%RSI,%R13,1),%RCX |
(236) 0x44adb0 VBROADCASTSD (%RAX),%YMM3 |
(236) 0x44adb5 ADD %R10,%RCX |
(236) 0x44adb8 MOV %R8D,%R10D |
(236) 0x44adbb AND $-0x4,%R10D |
(236) 0x44adbf VMOVUPD %YMM3,-0x10(%R9,%RCX,8) |
(236) 0x44adc6 ADD %R10D,%EDX |
(236) 0x44adc9 AND $0x3,%R8D |
(236) 0x44adcd JE 44ae09 |
(236) 0x44adcf VMOVSD (%RAX),%XMM4 |
(236) 0x44add3 MOVSXD %EDX,%R8 |
(236) 0x44add6 LEA 0x1(%RDX),%ECX |
(236) 0x44add9 ADD %RSI,%R8 |
(236) 0x44addc VMOVSD %XMM4,(%R9,%R8,8) |
(236) 0x44ade2 CMP %ECX,%EBX |
(236) 0x44ade4 JLE 44ae09 |
(236) 0x44ade6 MOVSXD %ECX,%R10 |
(236) 0x44ade9 ADD $0x2,%EDX |
(236) 0x44adec ADD %RSI,%R10 |
(236) 0x44adef VMOVSD %XMM4,(%R9,%R10,8) |
(236) 0x44adf5 CMP %EDX,%EBX |
(236) 0x44adf7 JLE 44ae09 |
(236) 0x44adf9 VMOVSD (%RAX),%XMM5 |
(236) 0x44adfd MOVSXD %EDX,%RDX |
(236) 0x44ae00 ADD %RSI,%RDX |
(236) 0x44ae03 VMOVSD %XMM5,(%R9,%RDX,8) |
(236) 0x44ae09 MOV 0x178(%RSP),%R8D |
(236) 0x44ae11 INC %R11D |
(236) 0x44ae14 MOV 0x158(%RSP),%RCX |
(236) 0x44ae1c CMP %R8D,%EBX |
(236) 0x44ae1f JE 44b866 |
(236) 0x44ae25 MOV 0x170(%RSP),%R10 |
(236) 0x44ae2d ADD %RCX,%RDI |
(236) 0x44ae30 ADD %R10,%RSI |
(236) 0x44ae33 CMP %R11D,0x16c(%RSP) |
(236) 0x44ae3b JG 44ac38 |
0x44ae41 KORTESTB %K2,%K2 |
0x44ae45 JNE 44bd5a |
0x44ae4b VZEROUPPER |
0x44ae4e CALL 402220 <@plt_start@+0x200> |
0x44ae53 MOV 0x10(%R14),%R15 |
0x44ae57 MOV 0x18(%R14),%RBX |
0x44ae5b MOV (%R15),%R9D |
0x44ae5e MOV (%RBX),%EAX |
0x44ae60 SUB $0x2,%R9D |
0x44ae64 ADD $0x3,%EAX |
0x44ae67 SUB %R9D,%EAX |
0x44ae6a CLTD |
0x44ae6b IDIVL 0xb8(%RSP) |
0x44ae72 CMP %EDX,0x124(%RSP) |
0x44ae79 JL 44bdf2 |
0x44ae7f MOV 0x124(%RSP),%ESI |
0x44ae86 IMUL %EAX,%ESI |
0x44ae89 ADD %ESI,%EDX |
0x44ae8b ADD %EDX,%EAX |
0x44ae8d CMP %EAX,%EDX |
0x44ae8f JGE 44b176 |
0x44ae95 MOV (%R14),%RDI |
0x44ae98 MOV 0x8(%R14),%R8 |
0x44ae9c LEA (%R9,%RDX,1),%EBX |
0x44aea0 ADD %R9D,%EAX |
0x44aea3 KXORB %K1,%K1,%K1 |
0x44aea7 MOV 0x160(%RSP),%R11 |
0x44aeaf MOVSXD %EBX,%RSI |
0x44aeb2 MOV 0x38(%RSP),%RDX |
0x44aeb7 MOV %EAX,0x16c(%RSP) |
0x44aebe MOVSXD (%RDI),%R13 |
0x44aec1 MOV (%R8),%ECX |
0x44aec4 IMUL %R11,%RSI |
0x44aec8 LEA (,%R11,8),%R9 |
0x44aed0 MOV 0x58(%R14),%R10 |
0x44aed4 MOV 0x80(%R14),%RAX |
0x44aedb LEA 0x3(%RCX),%R8D |
0x44aedf SUB %R13D,%ECX |
0x44aee2 MOV %R9,0x158(%RSP) |
0x44aeea LEA -0x2(%R13),%R15D |
0x44aeee LEA 0x5(%RCX),%R9D |
0x44aef2 LEA 0x4(%RCX),%R12D |
0x44aef6 MOV %ECX,%R11D |
0x44aef9 MOV %ECX,0x148(%RSP) |
0x44af00 MOV %R12D,0x150(%RSP) |
0x44af08 MOV %R9D,%ECX |
0x44af0b MOV %R9D,%R12D |
0x44af0e LEA (%RDX,%R13,1),%RDI |
0x44af12 AND $-0x8,%ECX |
0x44af15 SHR $0x3,%R12D |
0x44af19 ADD %RSI,%RDI |
0x44af1c ADD %RDX,%RSI |
0x44af1f MOV %ECX,0x168(%RSP) |
0x44af26 SAL $0x6,%R12 |
0x44af2a ADD %R15D,%ECX |
0x44af2d LEA 0x5(%R15,%R11,1),%EDX |
0x44af32 CMP %R8D,%R15D |
0x44af35 MOV %ECX,0x128(%RSP) |
0x44af3c LEA -0x10(%R10,%RDI,8),%RDI |
0x44af41 CMOVGE %R15D,%EDX |
0x44af45 AND $0x7,%R9D |
0x44af49 MOV %R9D,0x140(%RSP) |
0x44af51 MOV %EDX,0x178(%RSP) |
0x44af58 NOPL (%RAX,%RAX,1) |
(234) 0x44af60 CMP %R8D,%R15D |
(234) 0x44af63 JGE 44b133 |
(234) 0x44af69 CMPL $0x6,0x150(%RSP) |
(234) 0x44af71 JBE 44bd50 |
(234) 0x44af77 LEA -0x40(%R12),%R9 |
(234) 0x44af7c LEA (%R12,%RDI,1),%R11 |
(234) 0x44af80 MOV %RDI,%RDX |
(234) 0x44af83 SHR $0x6,%R9 |
(234) 0x44af87 INC %R9 |
(234) 0x44af8a AND $0x7,%R9D |
(234) 0x44af8e JE 44b027 |
(234) 0x44af94 CMP $0x1,%R9 |
(234) 0x44af98 JE 44b011 |
(234) 0x44af9a CMP $0x2,%R9 |
(234) 0x44af9e JE 44b000 |
(234) 0x44afa0 CMP $0x3,%R9 |
(234) 0x44afa4 JE 44afef |
(234) 0x44afa6 CMP $0x4,%R9 |
(234) 0x44afaa JE 44afde |
(234) 0x44afac CMP $0x5,%R9 |
(234) 0x44afb0 JE 44afcd |
(234) 0x44afb2 CMP $0x6,%R9 |
(234) 0x44afb6 JNE 44bc91 |
(234) 0x44afbc VBROADCASTSD (%RAX),%ZMM7 |
(234) 0x44afc2 ADD $0x40,%RDX |
(234) 0x44afc6 VMOVUPD %ZMM7,-0x40(%RDX) |
(234) 0x44afcd VBROADCASTSD (%RAX),%ZMM8 |
(234) 0x44afd3 ADD $0x40,%RDX |
(234) 0x44afd7 VMOVUPD %ZMM8,-0x40(%RDX) |
(234) 0x44afde VBROADCASTSD (%RAX),%ZMM9 |
(234) 0x44afe4 ADD $0x40,%RDX |
(234) 0x44afe8 VMOVUPD %ZMM9,-0x40(%RDX) |
(234) 0x44afef VBROADCASTSD (%RAX),%ZMM10 |
(234) 0x44aff5 ADD $0x40,%RDX |
(234) 0x44aff9 VMOVUPD %ZMM10,-0x40(%RDX) |
(234) 0x44b000 VBROADCASTSD (%RAX),%ZMM11 |
(234) 0x44b006 ADD $0x40,%RDX |
(234) 0x44b00a VMOVUPD %ZMM11,-0x40(%RDX) |
(234) 0x44b011 VBROADCASTSD (%RAX),%ZMM12 |
(234) 0x44b017 ADD $0x40,%RDX |
(234) 0x44b01b VMOVUPD %ZMM12,-0x40(%RDX) |
(234) 0x44b022 CMP %R11,%RDX |
(234) 0x44b025 JE 44b09b |
(235) 0x44b027 VBROADCASTSD (%RAX),%ZMM13 |
(235) 0x44b02d ADD $0x200,%RDX |
(235) 0x44b034 VMOVUPD %ZMM13,-0x200(%RDX) |
(235) 0x44b03b VBROADCASTSD (%RAX),%ZMM14 |
(235) 0x44b041 VMOVUPD %ZMM14,-0x1c0(%RDX) |
(235) 0x44b048 VBROADCASTSD (%RAX),%ZMM15 |
(235) 0x44b04e VMOVUPD %ZMM15,-0x180(%RDX) |
(235) 0x44b055 VBROADCASTSD (%RAX),%ZMM0 |
(235) 0x44b05b VMOVUPD %ZMM0,-0x140(%RDX) |
(235) 0x44b062 VBROADCASTSD (%RAX),%ZMM1 |
(235) 0x44b068 VMOVUPD %ZMM1,-0x100(%RDX) |
(235) 0x44b06f VBROADCASTSD (%RAX),%ZMM2 |
(235) 0x44b075 VMOVUPD %ZMM2,-0xc0(%RDX) |
(235) 0x44b07c VBROADCASTSD (%RAX),%ZMM3 |
(235) 0x44b082 VMOVUPD %ZMM3,-0x80(%RDX) |
(235) 0x44b089 VBROADCASTSD (%RAX),%ZMM4 |
(235) 0x44b08f VMOVUPD %ZMM4,-0x40(%RDX) |
(235) 0x44b096 CMP %R11,%RDX |
(235) 0x44b099 JNE 44b027 |
(234) 0x44b09b MOV 0x140(%RSP),%ECX |
(234) 0x44b0a2 TEST %ECX,%ECX |
(234) 0x44b0a4 JE 44b133 |
(234) 0x44b0aa MOV 0x168(%RSP),%ECX |
(234) 0x44b0b1 MOV 0x128(%RSP),%EDX |
(234) 0x44b0b8 MOV 0x148(%RSP),%R11D |
(234) 0x44b0c0 SUB %ECX,%R11D |
(234) 0x44b0c3 LEA 0x5(%R11),%R9D |
(234) 0x44b0c7 ADD $0x4,%R11D |
(234) 0x44b0cb CMP $0x2,%R11D |
(234) 0x44b0cf JBE 44b0f7 |
(234) 0x44b0d1 MOV %ECX,%R11D |
(234) 0x44b0d4 LEA (%RSI,%R13,1),%RCX |
(234) 0x44b0d8 VBROADCASTSD (%RAX),%YMM5 |
(234) 0x44b0dd ADD %R11,%RCX |
(234) 0x44b0e0 MOV %R9D,%R11D |
(234) 0x44b0e3 AND $-0x4,%R11D |
(234) 0x44b0e7 VMOVUPD %YMM5,-0x10(%R10,%RCX,8) |
(234) 0x44b0ee ADD %R11D,%EDX |
(234) 0x44b0f1 AND $0x3,%R9D |
(234) 0x44b0f5 JE 44b133 |
(234) 0x44b0f7 VMOVSD (%RAX),%XMM6 |
(234) 0x44b0fb MOVSXD %EDX,%R9 |
(234) 0x44b0fe LEA 0x1(%RDX),%ECX |
(234) 0x44b101 ADD %RSI,%R9 |
(234) 0x44b104 VMOVSD %XMM6,(%R10,%R9,8) |
(234) 0x44b10a CMP %R8D,%ECX |
(234) 0x44b10d JGE 44b133 |
(234) 0x44b10f MOVSXD %ECX,%R11 |
(234) 0x44b112 ADD $0x2,%EDX |
(234) 0x44b115 ADD %RSI,%R11 |
(234) 0x44b118 VMOVSD %XMM6,(%R10,%R11,8) |
(234) 0x44b11e CMP %EDX,%R8D |
(234) 0x44b121 JLE 44b133 |
(234) 0x44b123 VMOVSD (%RAX),%XMM7 |
(234) 0x44b127 MOVSXD %EDX,%RDX |
(234) 0x44b12a ADD %RSI,%RDX |
(234) 0x44b12d VMOVSD %XMM7,(%R10,%RDX,8) |
(234) 0x44b133 MOV 0x178(%RSP),%R9D |
(234) 0x44b13b INC %EBX |
(234) 0x44b13d MOV 0x158(%RSP),%RCX |
(234) 0x44b145 CMP %R9D,%R8D |
(234) 0x44b148 JE 44b897 |
(234) 0x44b14e MOV 0x160(%RSP),%R11 |
(234) 0x44b156 ADD %RCX,%RDI |
(234) 0x44b159 ADD %R11,%RSI |
(234) 0x44b15c CMP %EBX,0x16c(%RSP) |
(234) 0x44b163 JG 44af60 |
0x44b169 KORTESTB %K1,%K1 |
0x44b16d JNE 44bd81 |
0x44b173 VZEROUPPER |
0x44b176 CALL 402220 <@plt_start@+0x200> |
0x44b17b MOV 0x60(%R14),%R15 |
0x44b17f MOV (%R15),%R8D |
0x44b182 CMP $0x1,%R8D |
0x44b186 JLE 44b7f1 |
0x44b18c MOV 0x118(%RSP),%RAX |
0x44b194 MOV 0x40(%RSP),%R10 |
0x44b199 MOV %R8,0x68(%RSP) |
0x44b19e MOV $0x1,%R15D |
0x44b1a4 MOV 0x48(%RSP),%RDI |
0x44b1a9 MOV %R14,%R12 |
0x44b1ac SUB %R10,%RAX |
0x44b1af LEA (,%RAX,8),%RSI |
0x44b1b7 DEC %RDI |
0x44b1ba MOV %RSI,0x20(%RSP) |
0x44b1bf MOV %RDI,0x18(%RSP) |
0x44b1c4 JMP 44b1e3 |
0x44b1c6 NOPW %CS:(%RAX,%RAX,1) |
(230) 0x44b1d0 CALL 402220 <@plt_start@+0x200> |
(230) 0x44b1d5 INC %R15 |
(230) 0x44b1d8 CMP %R15,0x68(%RSP) |
(230) 0x44b1dd JE 44b7f1 |
(230) 0x44b1e3 MOV 0x10(%R12),%RCX |
(230) 0x44b1e8 MOV 0x18(%R12),%RBX |
(230) 0x44b1ed MOV 0x88(%R12),%R14 |
(230) 0x44b1f5 MOV 0x98(%R12),%R9 |
(230) 0x44b1fd MOV (%RCX),%R11D |
(230) 0x44b200 MOV (%RBX),%EAX |
(230) 0x44b202 VMOVSD (%R14,%R15,8),%XMM2 |
(230) 0x44b208 VMOVSD (%R9,%R15,8),%XMM3 |
(230) 0x44b20e MOV %R14,0xb0(%RSP) |
(230) 0x44b216 SUB $0x2,%R11D |
(230) 0x44b21a ADD $0x3,%EAX |
(230) 0x44b21d MOV %R9,0x78(%RSP) |
(230) 0x44b222 SUB %R11D,%EAX |
(230) 0x44b225 VUNPCKLPD %XMM2,%XMM3,%XMM8 |
(230) 0x44b229 CLTD |
(230) 0x44b22a VMOVUPD %XMM8,0x130(%R12) |
(230) 0x44b234 IDIVL 0xb8(%RSP) |
(230) 0x44b23b CMP %EDX,0x124(%RSP) |
(230) 0x44b242 JL 44bc88 |
(230) 0x44b248 MOV 0x124(%RSP),%R13D |
(230) 0x44b250 IMUL %EAX,%R13D |
(230) 0x44b254 ADD %R13D,%EDX |
(230) 0x44b257 ADD %EDX,%EAX |
(230) 0x44b259 CMP %EAX,%EDX |
(230) 0x44b25b JGE 44b1d0 |
(230) 0x44b261 MOV 0x8(%R12),%RSI |
(230) 0x44b266 MOV 0xb8(%R12),%R9 |
(230) 0x44b26e ADD %R11D,%EAX |
(230) 0x44b271 LEA (%R11,%RDX,1),%EBX |
(230) 0x44b275 KXORB %K0,%K0,%K0 |
(230) 0x44b279 MOV (%R12),%R8 |
(230) 0x44b27d MOV 0xb0(%R12),%R14 |
(230) 0x44b285 MOV %EAX,0x120(%RSP) |
(230) 0x44b28c MOV $0x1,%R10D |
(230) 0x44b292 MOV (%RSI),%ESI |
(230) 0x44b294 MOV 0xc0(%R12),%R11 |
(230) 0x44b29c MOV %R9,0xd0(%RSP) |
(230) 0x44b2a4 MOV 0xc8(%R12),%RAX |
(230) 0x44b2ac MOV 0x138(%RSP),%R9 |
(230) 0x44b2b4 MOV %R14,0xd8(%RSP) |
(230) 0x44b2bc MOVSXD (%R8),%RCX |
(230) 0x44b2bf MOV 0xa8(%R12),%RDX |
(230) 0x44b2c7 LEA 0x3(%RSI),%EDI |
(230) 0x44b2ca MOV %R11,0xa0(%RSP) |
(230) 0x44b2d2 MOV 0x18(%RSP),%R14 |
(230) 0x44b2d7 LEA 0x4(%RSI),%R11D |
(230) 0x44b2db MOV 0x90(%R12),%R13 |
(230) 0x44b2e3 MOV %RAX,0x158(%RSP) |
(230) 0x44b2eb MOVSXD %EBX,%RAX |
(230) 0x44b2ee MOV %EDI,0x16c(%RSP) |
(230) 0x44b2f5 MOV %R11D,%EDI |
(230) 0x44b2f8 LEA -0x2(%RCX),%R8D |
(230) 0x44b2fc IMUL %RAX,%R9 |
(230) 0x44b300 SUB %ECX,%EDI |
(230) 0x44b302 MOV %RDX,0x110(%RSP) |
(230) 0x44b30a ADD %RCX,%R14 |
(230) 0x44b30d MOV 0x40(%RSP),%RDX |
(230) 0x44b312 ADD %RDI,%R14 |
(230) 0x44b315 MOV %R13,0x70(%RSP) |
(230) 0x44b31a SUB %RCX,%R10 |
(230) 0x44b31d MOV %R8D,0x168(%RSP) |
(230) 0x44b325 MOV 0x50(%RSP),%R11 |
(230) 0x44b32a LEA (%R14,%R9,1),%R13 |
(230) 0x44b32e LEA (%RAX,%RDX,1),%R14 |
(230) 0x44b332 MOVSXD %R8D,%RDX |
(230) 0x44b335 MOV 0x130(%RSP),%R8 |
(230) 0x44b33d ADD %RDX,%R11 |
(230) 0x44b340 MOV %RDI,0x178(%RSP) |
(230) 0x44b348 ADD %RDX,%R10 |
(230) 0x44b34b IMUL %RAX,%R8 |
(230) 0x44b34f LEA (%R11,%R8,1),%RDI |
(230) 0x44b353 MOV 0x38(%RSP),%R11 |
(230) 0x44b358 MOV %RDI,0x148(%RSP) |
(230) 0x44b360 MOV 0x160(%RSP),%RDI |
(230) 0x44b368 ADD %RDX,%R11 |
(230) 0x44b36b IMUL %RAX,%RDI |
(230) 0x44b36f MOV %R11,0xc8(%RSP) |
(230) 0x44b377 ADD %RDI,%R11 |
(230) 0x44b37a MOV 0x60(%RSP),%RDI |
(230) 0x44b37f MOV %R11,0x150(%RSP) |
(230) 0x44b387 MOV 0x170(%RSP),%R11 |
(230) 0x44b38f IMUL %R11,%RAX |
(230) 0x44b393 LEA 0x1(%RDI,%RDX,1),%R11 |
(230) 0x44b398 LEA (%R11,%RAX,1),%RDI |
(230) 0x44b39c MOV %RDI,0x140(%RSP) |
(230) 0x44b3a4 MOV 0x170(%RSP),%R11 |
(230) 0x44b3ac MOV 0x138(%RSP),%RDI |
(230) 0x44b3b4 SUB %R11,%RDI |
(230) 0x44b3b7 MOV 0x48(%RSP),%R11 |
(230) 0x44b3bc MOV %RDI,0xe8(%RSP) |
(230) 0x44b3c4 MOV 0x60(%RSP),%RDI |
(230) 0x44b3c9 SUB %RDI,%R11 |
(230) 0x44b3cc MOV 0x130(%RSP),%RDI |
(230) 0x44b3d4 ADD %R9,%R11 |
(230) 0x44b3d7 MOV %R11,%R9 |
(230) 0x44b3da MOV 0x170(%RSP),%R11 |
(230) 0x44b3e2 SUB %RAX,%R9 |
(230) 0x44b3e5 SUB %R11,%RDI |
(230) 0x44b3e8 MOV %R9,0xf8(%RSP) |
(230) 0x44b3f0 MOV 0x60(%RSP),%R9 |
(230) 0x44b3f5 MOV %RDI,0xe0(%RSP) |
(230) 0x44b3fd MOV 0x50(%RSP),%RDI |
(230) 0x44b402 SUB %R9,%RDI |
(230) 0x44b405 ADD %RDX,%R9 |
(230) 0x44b408 ADD %R8,%RDI |
(230) 0x44b40b MOV 0x20(%R12),%R8 |
(230) 0x44b410 MOV %R9,0xc0(%RSP) |
(230) 0x44b418 SUB %RAX,%RDI |
(230) 0x44b41b MOV 0x168(%RSP),%R9D |
(230) 0x44b423 MOV %RDI,0xf0(%RSP) |
(230) 0x44b42b MOV 0x30(%RSP),%RDI |
(230) 0x44b430 LEA 0x5(%R9,%RSI,1),%ESI |
(230) 0x44b435 LEA (%RDI,%RCX,1),%RAX |
(230) 0x44b439 SUB %ECX,%ESI |
(230) 0x44b43b ADD %RDX,%RDI |
(230) 0x44b43e MOV 0x178(%RSP),%RCX |
(230) 0x44b446 LEA -0x10(%R8,%RAX,8),%R11 |
(230) 0x44b44b MOV 0x178(%RSP),%R8 |
(230) 0x44b453 MOV %ESI,0xbc(%RSP) |
(230) 0x44b45a MOV %R11,0xa8(%RSP) |
(230) 0x44b462 MOV 0x20(%R12),%R11 |
(230) 0x44b467 SUB %RCX,%R10 |
(230) 0x44b46a ADD %R8,%RAX |
(230) 0x44b46d MOV 0x30(%R12),%R8 |
(230) 0x44b472 MOV %R10,0x98(%RSP) |
(230) 0x44b47a LEA -0x8(%R11,%RAX,8),%RAX |
(230) 0x44b47f MOV 0x20(%RSP),%R11 |
(230) 0x44b484 MOV %EBX,0x178(%RSP) |
(230) 0x44b48b MOV %RAX,0x80(%RSP) |
(230) 0x44b493 MOV 0x28(%RSP),%RAX |
(230) 0x44b498 ADD 0x38(%R12),%R11 |
(230) 0x44b49d ADD %RDX,%RAX |
(230) 0x44b4a0 MOV 0x20(%R12),%RDX |
(230) 0x44b4a5 MOV %R11,0x108(%RSP) |
(230) 0x44b4ad LEA 0x8(%R8,%RAX,8),%RAX |
(230) 0x44b4b2 LEA 0x8(%RDX,%RDI,8),%RDI |
(230) 0x44b4b7 MOV %RAX,0x88(%RSP) |
(230) 0x44b4bf MOV %RDI,0x90(%RSP) |
(230) 0x44b4c7 MOV 0x140(%RSP),%RBX |
(230) 0x44b4cf NOP |
(231) 0x44b4d0 MOV 0x168(%RSP),%R8D |
(231) 0x44b4d8 INCL 0x178(%RSP) |
(231) 0x44b4df CMP %R8D,0x16c(%RSP) |
(231) 0x44b4e7 JLE 44bc78 |
(231) 0x44b4ed MOV 0xd8(%RSP),%R11 |
(231) 0x44b4f5 MOV 0xd0(%RSP),%RSI |
(231) 0x44b4fd MOV (%R11,%R15,4),%R9D |
(231) 0x44b501 CMP (%RSI),%R9D |
(231) 0x44b504 JE 44ba80 |
(231) 0x44b50a MOV 0x98(%RSP),%RDX |
(231) 0x44b512 MOVSXD 0x178(%RSP),%RAX |
(231) 0x44b51a MOV %RBX,%R8 |
(231) 0x44b51d MOV %RBX,0x118(%RSP) |
(231) 0x44b525 MOV 0xc0(%RSP),%RCX |
(231) 0x44b52d MOV 0x160(%RSP),%R11 |
(231) 0x44b535 NEG %R8 |
(231) 0x44b538 LEA (%RDX,%R13,1),%RSI |
(231) 0x44b53c MOV 0x170(%RSP),%RDX |
(231) 0x44b544 SAL $0x3,%R8 |
(231) 0x44b548 MOV 0xc8(%RSP),%R10 |
(231) 0x44b550 MOV 0xa0(%RSP),%RDI |
(231) 0x44b558 IMUL %RAX,%RDX |
(231) 0x44b55c IMUL %R11,%RAX |
(231) 0x44b560 MOV 0x88(%RSP),%R11 |
(231) 0x44b568 ADD %RCX,%RDX |
(231) 0x44b56b MOV 0x90(%RSP),%RCX |
(231) 0x44b573 ADD %R8,%R11 |
(231) 0x44b576 ADD %R10,%RAX |
(231) 0x44b579 MOV %R11,0x140(%RSP) |
(231) 0x44b581 MOV (%RDI),%R10D |
(231) 0x44b584 MOV %RBX,%RDI |
(231) 0x44b587 ADD %R8,%RCX |
(231) 0x44b58a MOV %R14,%RBX |
(231) 0x44b58d MOV 0x148(%RSP),%R8 |
(231) 0x44b595 MOV %R15,%R14 |
(231) 0x44b598 MOV %RCX,0x128(%RSP) |
(231) 0x44b5a0 MOV 0x150(%RSP),%RCX |
(231) 0x44b5a8 JMP 44b5dc |
0x44b5aa NOPW (%RAX,%RAX,1) |
(233) 0x44b5b0 MOV 0x158(%RSP),%R15 |
(233) 0x44b5b8 CMP (%R15),%R9D |
(233) 0x44b5bb JE 44b8d0 |
(233) 0x44b5c1 INC %RCX |
(233) 0x44b5c4 INC %RDX |
(233) 0x44b5c7 INC %RAX |
(233) 0x44b5ca INC %RSI |
(233) 0x44b5cd INC %R8 |
(233) 0x44b5d0 INC %RDI |
(233) 0x44b5d3 CMP %RSI,%R13 |
(233) 0x44b5d6 JE 44b730 |
(233) 0x44b5dc CMP %R10D,%R9D |
(233) 0x44b5df JNE 44b5b0 |
(233) 0x44b5e1 MOV 0x140(%RSP),%R15 |
(233) 0x44b5e9 MOV 0x108(%RSP),%R11 |
(233) 0x44b5f1 VMOVSD -0x8(%R15,%RDI,8),%XMM5 |
(233) 0x44b5f8 VMOVSD (%R11,%RBX,8),%XMM7 |
(233) 0x44b5fe MOV 0x110(%RSP),%R15 |
(233) 0x44b606 VSUBSD %XMM2,%XMM5,%XMM6 |
(233) 0x44b60a VSUBSD %XMM3,%XMM7,%XMM8 |
(233) 0x44b60e VUNPCKLPD %XMM8,%XMM6,%XMM9 |
(233) 0x44b613 VMULPD %XMM9,%XMM9,%XMM10 |
(233) 0x44b618 VUNPCKHPD %XMM10,%XMM10,%XMM11 |
(233) 0x44b61d VADDPD %XMM10,%XMM11,%XMM12 |
(233) 0x44b622 VSQRTSD %XMM12,%XMM12,%XMM12 |
(233) 0x44b627 VCOMISD (%R15,%R14,8),%XMM12 |
(233) 0x44b62d JA 44b5c1 |
(233) 0x44b62f MOV 0x70(%R12),%R11 |
(233) 0x44b634 MOV 0x48(%R12),%R15 |
(233) 0x44b639 VMOVSD (%R11,%R14,8),%XMM13 |
(233) 0x44b63f MOV 0x68(%R12),%R11 |
(233) 0x44b644 VMOVSD %XMM13,(%R15,%RSI,8) |
(233) 0x44b64a MOV 0x40(%R12),%R15 |
(233) 0x44b64f INC %RSI |
(233) 0x44b652 VMOVSD (%R11,%R14,8),%XMM14 |
(233) 0x44b658 LEA (,%R14,8),%R11 |
(233) 0x44b660 VMOVSD %XMM14,(%R15,%R8,8) |
(233) 0x44b666 MOV 0x78(%R12),%R15 |
(233) 0x44b66b INC %R8 |
(233) 0x44b66e ADD %R11,%R15 |
(233) 0x44b671 ADD 0x80(%R12),%R11 |
(233) 0x44b679 VMOVSD (%R15),%XMM15 |
(233) 0x44b67e MOV %R15,0x100(%RSP) |
(233) 0x44b686 MOV 0x50(%R12),%R15 |
(233) 0x44b68b VMOVSD %XMM15,-0x8(%R15,%RDI,8) |
(233) 0x44b692 MOV 0x58(%R12),%R15 |
(233) 0x44b697 VMOVSD (%R11),%XMM0 |
(233) 0x44b69c VMOVSD %XMM0,(%R15,%RCX,8) |
(233) 0x44b6a2 MOV 0x100(%RSP),%R15 |
(233) 0x44b6aa INC %RCX |
(233) 0x44b6ad VMOVSD (%R15),%XMM1 |
(233) 0x44b6b2 MOV 0x50(%R12),%R15 |
(233) 0x44b6b7 VMOVSD %XMM1,(%R15,%RDI,8) |
(233) 0x44b6bd MOV 0x58(%R12),%R15 |
(233) 0x44b6c2 INC %RDI |
(233) 0x44b6c5 VMOVSD (%R11),%XMM4 |
(233) 0x44b6ca VMOVSD %XMM4,(%R15,%RCX,8) |
(233) 0x44b6d0 MOV 0x100(%RSP),%R15 |
(233) 0x44b6d8 VMOVSD (%R15),%XMM5 |
(233) 0x44b6dd MOV 0x50(%R12),%R15 |
(233) 0x44b6e2 VMOVSD %XMM5,(%R15,%RDX,8) |
(233) 0x44b6e8 MOV 0x58(%R12),%R15 |
(233) 0x44b6ed INC %RDX |
(233) 0x44b6f0 VMOVSD (%R11),%XMM6 |
(233) 0x44b6f5 VMOVSD %XMM6,(%R15,%RAX,8) |
(233) 0x44b6fb MOV 0x100(%RSP),%R15 |
(233) 0x44b703 INC %RAX |
(233) 0x44b706 VMOVSD (%R15),%XMM7 |
(233) 0x44b70b MOV 0x50(%R12),%R15 |
(233) 0x44b710 VMOVSD %XMM7,(%R15,%RDX,8) |
(233) 0x44b716 VMOVSD (%R11),%XMM8 |
(233) 0x44b71b MOV 0x58(%R12),%R11 |
(233) 0x44b720 VMOVSD %XMM8,(%R11,%RAX,8) |
(233) 0x44b726 CMP %RSI,%R13 |
(233) 0x44b729 JNE 44b5dc |
(231) 0x44b72f NOP |
(231) 0x44b730 MOV %RBX,%R9 |
(231) 0x44b733 MOV 0xbc(%RSP),%R11D |
(231) 0x44b73b MOV 0x118(%RSP),%RBX |
(231) 0x44b743 MOV %R14,%R15 |
(231) 0x44b746 LEA 0x1(%R9),%R10 |
(231) 0x44b74a CMP %R11D,0x16c(%RSP) |
(231) 0x44b752 JE 44b9f0 |
(231) 0x44b758 MOV 0x138(%RSP),%RSI |
(231) 0x44b760 MOV 0x130(%RSP),%RAX |
(231) 0x44b768 MOV %R10,%R14 |
(231) 0x44b76b MOV 0x160(%RSP),%RDX |
(231) 0x44b773 MOV 0x170(%RSP),%R10 |
(231) 0x44b77b MOV 0xe8(%RSP),%RDI |
(231) 0x44b783 MOV 0xe0(%RSP),%RCX |
(231) 0x44b78b ADD %RSI,%R13 |
(231) 0x44b78e MOV 0x178(%RSP),%R8D |
(231) 0x44b796 ADD %RAX,0x148(%RSP) |
(231) 0x44b79e ADD %R10,%RBX |
(231) 0x44b7a1 ADD %RDX,0x150(%RSP) |
(231) 0x44b7a9 ADD %RDI,0xf8(%RSP) |
(231) 0x44b7b1 ADD %RCX,0xf0(%RSP) |
(231) 0x44b7b9 CMP %R8D,0x120(%RSP) |
(231) 0x44b7c1 JG 44b4d0 |
(230) 0x44b7c7 KORTESTB %K0,%K0 |
(230) 0x44b7cb JE 44b1d0 |
(230) 0x44b7d1 MOV 0x5c(%RSP),%R11D |
(230) 0x44b7d6 MOV %R11D,0x140(%R12) |
(230) 0x44b7de INC %R15 |
(230) 0x44b7e1 CALL 402220 <@plt_start@+0x200> |
(230) 0x44b7e6 CMP %R15,0x68(%RSP) |
(230) 0x44b7eb JNE 44b1e3 |
0x44b7f1 LEA -0x28(%RBP),%RSP |
0x44b7f5 POP %RBX |
0x44b7f6 POP %R12 |
0x44b7f8 POP %R13 |
0x44b7fa POP %R14 |
0x44b7fc POP %R15 |
0x44b7fe POP %RBP |
0x44b7ff RET |
(240) 0x44b800 MOV 0x138(%RSP),%RDX |
(240) 0x44b808 ADD %RCX,%RDI |
(240) 0x44b80b ADD %RDX,%RSI |
(240) 0x44b80e CMP %EBX,0x16c(%RSP) |
(240) 0x44b815 JLE 44bddb |
(240) 0x44b81b MOV $0x1,%R9D |
(240) 0x44b821 MOV %R8D,0x110(%RSP) |
(240) 0x44b829 KMOVB %R9D,%K4 |
(240) 0x44b82e JMP 44a5f8 |
(238) 0x44b833 MOV 0x130(%RSP),%RDX |
(238) 0x44b83b ADD %RCX,%RDI |
(238) 0x44b83e ADD %RDX,%RSI |
(238) 0x44b841 CMP %R11D,0x16c(%RSP) |
(238) 0x44b849 JLE 44bdb6 |
(238) 0x44b84f MOV $0x1,%R10D |
(238) 0x44b855 MOV %EBX,0x108(%RSP) |
(238) 0x44b85c KMOVB %R10D,%K3 |
(238) 0x44b861 JMP 44a918 |
(236) 0x44b866 MOV 0x170(%RSP),%RDX |
(236) 0x44b86e ADD %RCX,%RDI |
(236) 0x44b871 ADD %RDX,%RSI |
(236) 0x44b874 CMP %R11D,0x16c(%RSP) |
(236) 0x44b87c JLE 44bd6a |
(236) 0x44b882 MOV $0x1,%EDX |
(236) 0x44b887 MOV %EBX,0x100(%RSP) |
(236) 0x44b88e KMOVB %EDX,%K2 |
(236) 0x44b892 JMP 44ac38 |
(234) 0x44b897 MOV 0x160(%RSP),%RDX |
(234) 0x44b89f ADD %RCX,%RDI |
(234) 0x44b8a2 ADD %RDX,%RSI |
(234) 0x44b8a5 CMP %EBX,0x16c(%RSP) |
(234) 0x44b8ac JLE 44bd8f |
(234) 0x44b8b2 MOV $0x1,%R11D |
(234) 0x44b8b8 MOV %R8D,0xf8(%RSP) |
(234) 0x44b8c0 KMOVB %R11D,%K1 |
(234) 0x44b8c5 JMP 44af60 |
0x44b8ca NOPW (%RAX,%RAX,1) |
(233) 0x44b8d0 MOV 0x128(%RSP),%R11 |
(233) 0x44b8d8 VCOMISD -0x8(%R11,%RDI,8),%XMM2 |
(233) 0x44b8df JNE 44b5c1 |
(233) 0x44b8e5 MOV 0x28(%R12),%R15 |
(233) 0x44b8ea VCOMISD (%R15,%RBX,8),%XMM3 |
(233) 0x44b8f0 JNE 44b5c1 |
(233) 0x44b8f6 MOV 0x70(%R12),%R11 |
(233) 0x44b8fb MOV 0x48(%R12),%R15 |
(233) 0x44b900 VMOVSD (%R11,%R14,8),%XMM9 |
(233) 0x44b906 MOV 0x68(%R12),%R11 |
(233) 0x44b90b VMOVSD %XMM9,(%R15,%RSI,8) |
(233) 0x44b911 MOV 0x40(%R12),%R15 |
(233) 0x44b916 VMOVSD (%R11,%R14,8),%XMM10 |
(233) 0x44b91c LEA (,%R14,8),%R11 |
(233) 0x44b924 VMOVSD %XMM10,(%R15,%R8,8) |
(233) 0x44b92a MOV 0x78(%R12),%R15 |
(233) 0x44b92f ADD %R11,%R15 |
(233) 0x44b932 ADD 0x80(%R12),%R11 |
(233) 0x44b93a VMOVSD (%R15),%XMM11 |
(233) 0x44b93f MOV %R15,0x100(%RSP) |
(233) 0x44b947 MOV 0x50(%R12),%R15 |
(233) 0x44b94c VMOVSD %XMM11,-0x8(%R15,%RDI,8) |
(233) 0x44b953 MOV 0x58(%R12),%R15 |
(233) 0x44b958 VMOVSD (%R11),%XMM12 |
(233) 0x44b95d VMOVSD %XMM12,(%R15,%RCX,8) |
(233) 0x44b963 MOV 0x100(%RSP),%R15 |
(233) 0x44b96b INC %RCX |
(233) 0x44b96e VMOVSD (%R15),%XMM13 |
(233) 0x44b973 MOV 0x50(%R12),%R15 |
(233) 0x44b978 VMOVSD %XMM13,(%R15,%RDI,8) |
(233) 0x44b97e MOV 0x58(%R12),%R15 |
(233) 0x44b983 VMOVSD (%R11),%XMM14 |
(233) 0x44b988 VMOVSD %XMM14,(%R15,%RCX,8) |
(233) 0x44b98e MOV 0x100(%RSP),%R15 |
(233) 0x44b996 VMOVSD (%R15),%XMM15 |
(233) 0x44b99b MOV 0x50(%R12),%R15 |
(233) 0x44b9a0 VMOVSD %XMM15,(%R15,%RDX,8) |
(233) 0x44b9a6 MOV 0x58(%R12),%R15 |
(233) 0x44b9ab INC %RDX |
(233) 0x44b9ae VMOVSD (%R11),%XMM0 |
(233) 0x44b9b3 VMOVSD %XMM0,(%R15,%RAX,8) |
(233) 0x44b9b9 MOV 0x100(%RSP),%R15 |
(233) 0x44b9c1 INC %RAX |
(233) 0x44b9c4 VMOVSD (%R15),%XMM1 |
(233) 0x44b9c9 MOV 0x50(%R12),%R15 |
(233) 0x44b9ce VMOVSD %XMM1,(%R15,%RDX,8) |
(233) 0x44b9d4 VMOVSD (%R11),%XMM4 |
(233) 0x44b9d9 MOV 0x58(%R12),%R11 |
(233) 0x44b9de VMOVSD %XMM4,(%R11,%RAX,8) |
(233) 0x44b9e4 JMP 44b5ca |
0x44b9e9 NOPL (%RAX) |
(231) 0x44b9f0 MOV 0x138(%RSP),%R14 |
(231) 0x44b9f8 MOV 0x130(%RSP),%R9 |
(231) 0x44ba00 MOV 0x160(%RSP),%RSI |
(231) 0x44ba08 MOV 0x170(%RSP),%RAX |
(231) 0x44ba10 MOV 0xe8(%RSP),%RDX |
(231) 0x44ba18 ADD %R14,%R13 |
(231) 0x44ba1b MOV 0x178(%RSP),%EDI |
(231) 0x44ba22 MOV %R10,%R14 |
(231) 0x44ba25 MOV 0xe0(%RSP),%R10 |
(231) 0x44ba2d ADD %R9,0x148(%RSP) |
(231) 0x44ba35 ADD %RAX,%RBX |
(231) 0x44ba38 ADD %RSI,0x150(%RSP) |
(231) 0x44ba40 ADD %RDX,0xf8(%RSP) |
(231) 0x44ba48 ADD %R10,0xf0(%RSP) |
(231) 0x44ba50 CMP %EDI,0x120(%RSP) |
(231) 0x44ba57 JLE 44b7d6 |
(231) 0x44ba5d MOV 0x16c(%RSP),%ECX |
(231) 0x44ba64 MOV $0x1,%R8D |
(231) 0x44ba6a KMOVB %R8D,%K0 |
(231) 0x44ba6f MOV %ECX,0x5c(%RSP) |
(231) 0x44ba73 JMP 44b4d0 |
0x44ba78 NOPL (%RAX,%RAX,1) |
(231) 0x44ba80 MOVSXD 0x178(%RSP),%R10 |
(231) 0x44ba88 MOV 0x160(%RSP),%RDI |
(231) 0x44ba90 LEA -0x1(%RBX),%RDX |
(231) 0x44ba94 MOV 0x170(%RSP),%RAX |
(231) 0x44ba9c MOV 0x80(%RSP),%R9 |
(231) 0x44baa4 MOV 0xc0(%RSP),%RCX |
(231) 0x44baac MOV 0xc8(%RSP),%R8 |
(231) 0x44bab4 IMUL %R10,%RAX |
(231) 0x44bab8 MOV %R9,%RSI |
(231) 0x44babb IMUL %RDI,%R10 |
(231) 0x44babf MOV 0xa8(%RSP),%RDI |
(231) 0x44bac7 SUB %RDI,%RSI |
(231) 0x44baca ADD %RCX,%RAX |
(231) 0x44bacd MOV 0x150(%RSP),%RCX |
(231) 0x44bad5 AND $0x8,%ESI |
(231) 0x44bad8 LEA (%R10,%R8,1),%R11 |
(231) 0x44badc LEA 0x1(%R14),%R10 |
(231) 0x44bae0 MOV %RDI,%R8 |
(231) 0x44bae3 JNE 44bc00 |
(231) 0x44bae9 MOV %R14,0x140(%RSP) |
(231) 0x44baf1 MOV 0xb0(%RSP),%RSI |
(231) 0x44baf9 NOPL (%RAX) |
(232) 0x44bb00 VMOVSD 0x8(%R8),%XMM9 |
(232) 0x44bb06 VCOMISD (%RSI,%R15,8),%XMM9 |
(232) 0x44bb0c JB 44bb60 |
(232) 0x44bb0e MOV 0x70(%RSP),%R14 |
(232) 0x44bb13 VMOVSD (%R14,%R15,8),%XMM10 |
(232) 0x44bb19 VCOMISD (%R8),%XMM10 |
(232) 0x44bb1e JBE 44bb60 |
(232) 0x44bb20 MOV 0x28(%R12),%RDI |
(232) 0x44bb25 MOV 0x78(%RSP),%R14 |
(232) 0x44bb2a VMOVSD (%RDI,%R10,8),%XMM11 |
(232) 0x44bb30 VCOMISD (%R14,%R15,8),%XMM11 |
(232) 0x44bb36 JB 44bb60 |
(232) 0x44bb38 MOV 0xa0(%R12),%R14 |
(232) 0x44bb40 VMOVSD (%R14,%R15,8),%XMM12 |
(232) 0x44bb46 MOV 0x140(%RSP),%R14 |
(232) 0x44bb4e VCOMISD (%RDI,%R14,8),%XMM12 |
(232) 0x44bb54 JA 44bf23 |
(232) 0x44bb5a NOPW (%RAX,%RAX,1) |
(232) 0x44bb60 INC %RDX |
(232) 0x44bb63 INC %RCX |
(232) 0x44bb66 INC %RAX |
(232) 0x44bb69 INC %R11 |
(232) 0x44bb6c VMOVSD 0x10(%R8),%XMM9 |
(232) 0x44bb72 LEA 0x8(%R8),%RDI |
(232) 0x44bb76 VCOMISD (%RSI,%R15,8),%XMM9 |
(232) 0x44bb7c JB 44bbd0 |
(232) 0x44bb7e MOV 0x70(%RSP),%R14 |
(232) 0x44bb83 VMOVSD (%R14,%R15,8),%XMM10 |
(232) 0x44bb89 VCOMISD 0x8(%R8),%XMM10 |
(232) 0x44bb8f JBE 44bbd0 |
(232) 0x44bb91 MOV 0x28(%R12),%R8 |
(232) 0x44bb96 MOV 0x78(%RSP),%R14 |
(232) 0x44bb9b VMOVSD (%R8,%R10,8),%XMM11 |
(232) 0x44bba1 VCOMISD (%R14,%R15,8),%XMM11 |
(232) 0x44bba7 JB 44bbd0 |
(232) 0x44bba9 MOV 0xa0(%R12),%R14 |
(232) 0x44bbb1 VMOVSD (%R14,%R15,8),%XMM12 |
(232) 0x44bbb7 MOV 0x140(%RSP),%R14 |
(232) 0x44bbbf VCOMISD (%R8,%R14,8),%XMM12 |
(232) 0x44bbc5 JA 44be16 |
(232) 0x44bbcb NOPL (%RAX,%RAX,1) |
(232) 0x44bbd0 INC %RDX |
(232) 0x44bbd3 INC %RCX |
(232) 0x44bbd6 INC %RAX |
(232) 0x44bbd9 INC %R11 |
(232) 0x44bbdc LEA 0x8(%RDI),%R8 |
(232) 0x44bbe0 CMP %R8,%R9 |
(232) 0x44bbe3 JNE 44bb00 |
(231) 0x44bbe9 MOV 0xbc(%RSP),%R11D |
(231) 0x44bbf1 JMP 44b74a |
0x44bbf6 NOPW %CS:(%RAX,%RAX,1) |
(231) 0x44bc00 VMOVSD 0x8(%RDI),%XMM9 |
(231) 0x44bc05 MOV 0xb0(%RSP),%R8 |
(231) 0x44bc0d MOV %RDI,%R9 |
(231) 0x44bc10 VCOMISD (%R8,%R15,8),%XMM9 |
(231) 0x44bc16 JB 44bc30 |
(231) 0x44bc18 MOV 0x70(%RSP),%RDI |
(231) 0x44bc1d VMOVSD (%RDI,%R15,8),%XMM10 |
(231) 0x44bc23 VCOMISD (%R9),%XMM10 |
(231) 0x44bc28 JA 44bce5 |
(231) 0x44bc2e XCHG %AX,%AX |
(231) 0x44bc30 MOV %RBX,%RDX |
(231) 0x44bc33 LEA 0x1(%RCX),%RCX |
(231) 0x44bc37 LEA 0x1(%R11),%R11 |
(231) 0x44bc3b INC %RAX |
(231) 0x44bc3e MOV 0xa8(%RSP),%RSI |
(231) 0x44bc46 LEA 0x8(%RSI),%R8 |
(231) 0x44bc4a CMP %R8,0x80(%RSP) |
(231) 0x44bc52 JE 44bbe9 |
(231) 0x44bc54 MOV 0xb0(%RSP),%RSI |
(231) 0x44bc5c MOV 0x80(%RSP),%R9 |
(231) 0x44bc64 MOV %R14,0x140(%RSP) |
(231) 0x44bc6c JMP 44bb00 |
0x44bc71 NOPL (%RAX) |
(231) 0x44bc78 MOV %R8D,%R11D |
(231) 0x44bc7b LEA 0x1(%R14),%R10 |
(231) 0x44bc7f JMP 44b74a |
0x44bc84 NOPL (%RAX) |
(230) 0x44bc88 INC %EAX |
(230) 0x44bc8a XOR %EDX,%EDX |
(230) 0x44bc8c JMP 44b248 |
(234) 0x44bc91 VBROADCASTSD (%RAX),%ZMM6 |
(234) 0x44bc97 LEA 0x40(%RDI),%RDX |
(234) 0x44bc9b VMOVUPD %ZMM6,(%RDI) |
(234) 0x44bca1 JMP 44afbc |
(236) 0x44bca6 VBROADCASTSD (%RAX),%ZMM4 |
(236) 0x44bcac LEA 0x40(%RDI),%RDX |
(236) 0x44bcb0 VMOVUPD %ZMM4,(%RDI) |
(236) 0x44bcb6 JMP 44ac94 |
(238) 0x44bcbb VBROADCASTSD (%RAX),%ZMM2 |
(238) 0x44bcc1 LEA 0x40(%RDI),%RDX |
(238) 0x44bcc5 VMOVUPD %ZMM2,(%RDI) |
(238) 0x44bccb JMP 44a974 |
(240) 0x44bcd0 VBROADCASTSD (%RAX),%ZMM0 |
(240) 0x44bcd6 LEA 0x40(%RDI),%RDX |
(240) 0x44bcda VMOVUPD %ZMM0,(%RDI) |
(240) 0x44bce0 JMP 44a654 |
(231) 0x44bce5 MOV 0x28(%R12),%R9 |
(231) 0x44bcea MOV 0x78(%RSP),%RSI |
(231) 0x44bcef VMOVSD (%R9,%R10,8),%XMM11 |
(231) 0x44bcf5 VCOMISD (%RSI,%R15,8),%XMM11 |
(231) 0x44bcfb JB 44bd17 |
(231) 0x44bcfd MOV 0xa0(%R12),%R8 |
(231) 0x44bd05 VMOVSD (%R8,%R15,8),%XMM12 |
(231) 0x44bd0b VCOMISD (%R9,%R14,8),%XMM12 |
(231) 0x44bd11 JA 44c024 |
(231) 0x44bd17 MOV 0x150(%RSP),%RDI |
(231) 0x44bd1f MOV %RBX,%RDX |
(231) 0x44bd22 INC %RAX |
(231) 0x44bd25 LEA 0x1(%R11),%R11 |
(231) 0x44bd29 LEA 0x1(%RDI),%RCX |
(231) 0x44bd2d JMP 44bc3e |
(238) 0x44bd32 MOV %R15D,%EDX |
(238) 0x44bd35 XOR %ECX,%ECX |
(238) 0x44bd37 JMP 44aa70 |
(236) 0x44bd3c MOV %R15D,%EDX |
(236) 0x44bd3f XOR %ECX,%ECX |
(236) 0x44bd41 JMP 44ad90 |
(240) 0x44bd46 MOV %R15D,%EDX |
(240) 0x44bd49 XOR %ECX,%ECX |
(240) 0x44bd4b JMP 44a750 |
(234) 0x44bd50 MOV %R15D,%EDX |
(234) 0x44bd53 XOR %ECX,%ECX |
(234) 0x44bd55 JMP 44b0b8 |
0x44bd5a MOV 0x100(%RSP),%R11D |
0x44bd62 MOV %R11D,0x178(%RSP) |
0x44bd6a MOV 0x178(%RSP),%R13D |
0x44bd72 MOV %R13D,0x140(%R14) |
0x44bd79 VZEROUPPER |
0x44bd7c JMP 44ae4e |
0x44bd81 MOV 0xf8(%RSP),%EBX |
0x44bd88 MOV %EBX,0x178(%RSP) |
0x44bd8f MOV 0x178(%RSP),%R13D |
0x44bd97 MOV %R13D,0x140(%R14) |
0x44bd9e VZEROUPPER |
0x44bda1 JMP 44b176 |
0x44bda6 MOV 0x108(%RSP),%R11D |
0x44bdae MOV %R11D,0x178(%RSP) |
0x44bdb6 MOV 0x178(%RSP),%R13D |
0x44bdbe MOV %R13D,0x140(%R14) |
0x44bdc5 VZEROUPPER |
0x44bdc8 JMP 44ab2e |
0x44bdcd MOV 0x110(%RSP),%EBX |
0x44bdd4 MOV %EBX,0x178(%RSP) |
0x44bddb MOV 0x178(%RSP),%R13D |
0x44bde3 MOV %R13D,0x140(%R14) |
0x44bdea VZEROUPPER |
0x44bded JMP 44a80e |
0x44bdf2 INC %EAX |
0x44bdf4 XOR %EDX,%EDX |
0x44bdf6 JMP 44ae7f |
0x44bdfb INC %EAX |
0x44bdfd XOR %EDX,%EDX |
0x44bdff JMP 44a83f |
0x44be04 INC %EAX |
0x44be06 XOR %EDX,%EDX |
0x44be08 JMP 44ab5d |
0x44be0d INC %EAX |
0x44be0f XOR %EDX,%EDX |
0x44be11 JMP 44a518 |
(232) 0x44be16 MOV 0x70(%R12),%R8 |
(232) 0x44be1b MOV 0xf8(%RSP),%R14 |
(232) 0x44be23 VMOVSD (%R8,%R15,8),%XMM13 |
(232) 0x44be29 LEA (%R14,%RDX,1),%R8 |
(232) 0x44be2d MOV 0x48(%R12),%R14 |
(232) 0x44be32 VMOVSD %XMM13,(%R14,%R8,8) |
(232) 0x44be38 MOV 0x68(%R12),%R8 |
(232) 0x44be3d MOV 0xf0(%RSP),%R14 |
(232) 0x44be45 VMOVSD (%R8,%R15,8),%XMM14 |
(232) 0x44be4b LEA (%RDX,%R14,1),%R8 |
(232) 0x44be4f MOV 0x40(%R12),%R14 |
(232) 0x44be54 VMOVSD %XMM14,(%R14,%R8,8) |
(232) 0x44be5a MOV 0x78(%R12),%R8 |
(232) 0x44be5f LEA (,%R15,8),%R14 |
(232) 0x44be67 ADD %R14,%R8 |
(232) 0x44be6a ADD 0x80(%R12),%R14 |
(232) 0x44be72 VMOVSD (%R8),%XMM15 |
(232) 0x44be77 MOV %R8,0x128(%RSP) |
(232) 0x44be7f MOV 0x50(%R12),%R8 |
(232) 0x44be84 VMOVSD %XMM15,(%R8,%RDX,8) |
(232) 0x44be8a MOV 0x58(%R12),%R8 |
(232) 0x44be8f INC %RDX |
(232) 0x44be92 VMOVSD (%R14),%XMM0 |
(232) 0x44be97 VMOVSD %XMM0,(%R8,%RCX,8) |
(232) 0x44be9d MOV 0x128(%RSP),%R8 |
(232) 0x44bea5 INC %RCX |
(232) 0x44bea8 VMOVSD (%R8),%XMM1 |
(232) 0x44bead MOV 0x50(%R12),%R8 |
(232) 0x44beb2 VMOVSD %XMM1,(%R8,%RDX,8) |
(232) 0x44beb8 MOV 0x58(%R12),%R8 |
(232) 0x44bebd VMOVSD (%R14),%XMM4 |
(232) 0x44bec2 VMOVSD %XMM4,(%R8,%RCX,8) |
(232) 0x44bec8 MOV 0x128(%RSP),%R8 |
(232) 0x44bed0 VMOVSD (%R8),%XMM5 |
(232) 0x44bed5 MOV 0x50(%R12),%R8 |
(232) 0x44beda VMOVSD %XMM5,(%R8,%RAX,8) |
(232) 0x44bee0 MOV 0x58(%R12),%R8 |
(232) 0x44bee5 INC %RAX |
(232) 0x44bee8 VMOVSD (%R14),%XMM6 |
(232) 0x44beed VMOVSD %XMM6,(%R8,%R11,8) |
(232) 0x44bef3 MOV 0x128(%RSP),%R8 |
(232) 0x44befb INC %R11 |
(232) 0x44befe VMOVSD (%R8),%XMM7 |
(232) 0x44bf03 MOV 0x50(%R12),%R8 |
(232) 0x44bf08 VMOVSD %XMM7,(%R8,%RAX,8) |
(232) 0x44bf0e VMOVSD (%R14),%XMM8 |
(232) 0x44bf13 MOV 0x58(%R12),%R14 |
(232) 0x44bf18 VMOVSD %XMM8,(%R14,%R11,8) |
(232) 0x44bf1e JMP 44bbdc |
(232) 0x44bf23 MOV 0x70(%R12),%RDI |
(232) 0x44bf28 MOV 0x48(%R12),%R14 |
(232) 0x44bf2d VMOVSD (%RDI,%R15,8),%XMM13 |
(232) 0x44bf33 MOV 0xf8(%RSP),%RDI |
(232) 0x44bf3b ADD %RDX,%RDI |
(232) 0x44bf3e VMOVSD %XMM13,(%R14,%RDI,8) |
(232) 0x44bf44 MOV 0x68(%R12),%RDI |
(232) 0x44bf49 MOV 0x40(%R12),%R14 |
(232) 0x44bf4e VMOVSD (%RDI,%R15,8),%XMM14 |
(232) 0x44bf54 MOV 0xf0(%RSP),%RDI |
(232) 0x44bf5c ADD %RDX,%RDI |
(232) 0x44bf5f VMOVSD %XMM14,(%R14,%RDI,8) |
(232) 0x44bf65 MOV 0x78(%R12),%RDI |
(232) 0x44bf6a LEA (,%R15,8),%R14 |
(232) 0x44bf72 ADD %R14,%RDI |
(232) 0x44bf75 ADD 0x80(%R12),%R14 |
(232) 0x44bf7d VMOVSD (%RDI),%XMM15 |
(232) 0x44bf81 MOV %RDI,0x128(%RSP) |
(232) 0x44bf89 MOV 0x50(%R12),%RDI |
(232) 0x44bf8e VMOVSD %XMM15,(%RDI,%RDX,8) |
(232) 0x44bf93 MOV 0x58(%R12),%RDI |
(232) 0x44bf98 INC %RDX |
(232) 0x44bf9b VMOVSD (%R14),%XMM0 |
(232) 0x44bfa0 VMOVSD %XMM0,(%RDI,%RCX,8) |
(232) 0x44bfa5 MOV 0x128(%RSP),%RDI |
(232) 0x44bfad INC %RCX |
(232) 0x44bfb0 VMOVSD (%RDI),%XMM1 |
(232) 0x44bfb4 MOV 0x50(%R12),%RDI |
(232) 0x44bfb9 VMOVSD %XMM1,(%RDI,%RDX,8) |
(232) 0x44bfbe MOV 0x58(%R12),%RDI |
(232) 0x44bfc3 VMOVSD (%R14),%XMM4 |
(232) 0x44bfc8 VMOVSD %XMM4,(%RDI,%RCX,8) |
(232) 0x44bfcd MOV 0x128(%RSP),%RDI |
(232) 0x44bfd5 VMOVSD (%RDI),%XMM5 |
(232) 0x44bfd9 MOV 0x50(%R12),%RDI |
(232) 0x44bfde VMOVSD %XMM5,(%RDI,%RAX,8) |
(232) 0x44bfe3 MOV 0x58(%R12),%RDI |
(232) 0x44bfe8 INC %RAX |
(232) 0x44bfeb VMOVSD (%R14),%XMM6 |
(232) 0x44bff0 VMOVSD %XMM6,(%RDI,%R11,8) |
(232) 0x44bff6 MOV 0x128(%RSP),%RDI |
(232) 0x44bffe INC %R11 |
(232) 0x44c001 VMOVSD (%RDI),%XMM7 |
(232) 0x44c005 MOV 0x50(%R12),%RDI |
(232) 0x44c00a VMOVSD %XMM7,(%RDI,%RAX,8) |
(232) 0x44c00f VMOVSD (%R14),%XMM8 |
(232) 0x44c014 MOV 0x58(%R12),%R14 |
(232) 0x44c019 VMOVSD %XMM8,(%R14,%R11,8) |
(232) 0x44c01f JMP 44bb6c |
(231) 0x44c024 MOV 0x70(%R12),%RCX |
(231) 0x44c029 MOV 0xf8(%RSP),%RSI |
(231) 0x44c031 MOV 0x48(%R12),%R9 |
(231) 0x44c036 MOV 0x68(%R12),%R8 |
(231) 0x44c03b VMOVSD (%RCX,%R15,8),%XMM13 |
(231) 0x44c041 ADD %RDX,%RSI |
(231) 0x44c044 MOV 0xf0(%RSP),%RCX |
(231) 0x44c04c MOV 0x40(%R12),%RDI |
(231) 0x44c051 VMOVSD %XMM13,(%R9,%RSI,8) |
(231) 0x44c057 MOV 0x78(%R12),%RSI |
(231) 0x44c05c ADD %RDX,%RCX |
(231) 0x44c05f LEA (,%R15,8),%R9 |
(231) 0x44c067 VMOVSD (%R8,%R15,8),%XMM14 |
(231) 0x44c06d MOV 0x50(%R12),%R8 |
(231) 0x44c072 ADD %R9,%RSI |
(231) 0x44c075 VMOVSD %XMM14,(%RDI,%RCX,8) |
(231) 0x44c07a MOV 0x80(%R12),%RDI |
(231) 0x44c082 MOV 0x150(%RSP),%RCX |
(231) 0x44c08a VMOVSD (%RSI),%XMM15 |
(231) 0x44c08e ADD %R9,%RDI |
(231) 0x44c091 MOV 0x58(%R12),%R9 |
(231) 0x44c096 VMOVSD %XMM15,(%R8,%RDX,8) |
(231) 0x44c09c MOV %RBX,%RDX |
(231) 0x44c09f VMOVSD (%RDI),%XMM0 |
(231) 0x44c0a3 VMOVSD %XMM0,(%R9,%RCX,8) |
(231) 0x44c0a9 INC %RCX |
(231) 0x44c0ac VMOVSD (%RSI),%XMM1 |
(231) 0x44c0b0 VMOVSD %XMM1,(%R8,%RBX,8) |
(231) 0x44c0b6 VMOVSD (%RDI),%XMM4 |
(231) 0x44c0ba VMOVSD %XMM4,(%R9,%RCX,8) |
(231) 0x44c0c0 VMOVSD (%RSI),%XMM5 |
(231) 0x44c0c4 VMOVSD %XMM5,(%R8,%RAX,8) |
(231) 0x44c0ca INC %RAX |
(231) 0x44c0cd VMOVSD (%RDI),%XMM6 |
(231) 0x44c0d1 VMOVSD %XMM6,(%R9,%R11,8) |
(231) 0x44c0d7 LEA 0x1(%R11),%R11 |
(231) 0x44c0db VMOVSD (%RSI),%XMM7 |
(231) 0x44c0df VMOVSD %XMM7,(%R8,%RAX,8) |
(231) 0x44c0e5 VMOVSD (%RDI),%XMM8 |
(231) 0x44c0e9 VMOVSD %XMM8,(%R9,%R11,8) |
(231) 0x44c0ef JMP 44bc3e |
0x44c0f4 NOPW %CS:(%RAX,%RAX,1) |
0x44c0ff NOP |
Path / |
Source file and lines | generate_chunk_kernel.f90:85-161 |
Module | exec |
nb instructions | 365 |
nb uops | 394 |
loop length | 1683 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 30 |
micro-operation queue | 65.67 cycles |
front end | 65.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 31.80 | 31.80 | 30.00 | 30.00 | 34.50 | 31.80 | 31.80 | 34.50 | 34.50 | 34.50 | 31.80 | 30.00 |
cycles | 31.80 | 47.13 | 30.00 | 30.00 | 34.50 | 31.80 | 31.80 | 34.50 | 34.50 | 34.50 | 31.80 | 30.00 |
Cycles executing div or sqrt instructions | 24.00 |
FE+BE cycles | 62.35-62.44 |
Stall cycles | 0.00 |
Front-end | 65.67 |
Dispatch | 47.13 |
DIV/SQRT | 24.00 |
Overall L1 | 65.67 |
all | 9% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 32% |
all | 9% |
load | 6% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x180,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x120(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x118(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x108(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf8(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf0(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x128(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x110(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd8(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x130(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x118(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%R12D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 402080 <@plt_start@+0x60> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EAX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x2,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 402180 <@plt_start@+0x160> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,0x124(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%R14),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R12D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %EBX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 44be0d <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x19ed> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x124(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EAX,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ESI,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 44a80e <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x3ee> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x138(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R12,%RDX,1),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV (%R14),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R12D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
KXORB %K4,%K4,%K4 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV 0x8(%R14),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EBX,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV 0x48(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x16c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %RDI,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOVSXD (%R8),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%RDI,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x48(%R14),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R9),%R12D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x70(%R14),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R13,%RDX,1),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x2(%R13),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x3(%R12),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R13D,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RSI,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R12D,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x5(%R12),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R12D,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x4(%R12),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R12D,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x10(%R10,%R9,8),%RDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
AND $-0x8,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x3,%R12D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA 0x5(%R15,%R11,1),%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %ECX,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x6,%R12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %R15D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R8D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVGE %R15D,%R9D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ECX,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9D,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
KORTESTB %K4,%K4 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JNE 44bdcd <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x19ad> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 402220 <@plt_start@+0x200> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x10(%R14),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R14),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R15),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x2,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD $0x3,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIVL 0xb8(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
CMP %EDX,0x124(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JL 44bdfb <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x19db> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x124(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EAX,%R10D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 44ab2e <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x70e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R14),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R14),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%R8,%RDX,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
KXORB %K3,%K3,%K3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV 0x130(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x50(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x16c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD (%RSI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %R11D,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
IMUL %R8,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (,%R8,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x40(%R14),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%R14),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x3(%RCX),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R13D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x2(%R13),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x5(%RCX),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x4(%RCX),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ECX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %ECX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12D,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EDX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%R10,%R13,1),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $-0x8,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x3,%R12D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %RSI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R10,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x6,%R12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %R15D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x5(%R15,%R8,1),%R10D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMP %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x10(%R9,%RDI,8),%RDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMOVLE %R15D,%R10D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10D,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
KORTESTB %K3,%K3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JNE 44bda6 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1986> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 402220 <@plt_start@+0x200> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x10(%R14),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R14),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R15),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x2,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD $0x3,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %EBX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIVL 0xb8(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
CMP %EDX,0x124(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JL 44be04 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x19e4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x124(%RSP),%R9D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EAX,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R9D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 44ae4e <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xa2e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R14),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R14),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RBX,%RDX,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %EBX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
KXORB %K2,%K2,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV 0x170(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x16c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD (%RSI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %R11D,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
IMUL %RCX,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (,%RCX,8),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x50(%R14),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%R14),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x3(%R8),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R13D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x2(%R13),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x5(%R8),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x4(%R8),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R8D,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10D,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R12D,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%R13,%RDX,1),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $-0x8,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x3,%R12D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %RSI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x6,%R12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %R15D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x5(%R15,%R8,1),%EDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMP %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x10(%R9,%RDI,8),%RDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMOVLE %R15D,%EDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
AND $0x7,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
KORTESTB %K2,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JNE 44bd5a <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x193a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 402220 <@plt_start@+0x200> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x10(%R14),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R14),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R15),%R9D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x2,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD $0x3,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R9D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIVL 0xb8(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
CMP %EDX,0x124(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JL 44bdf2 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x19d2> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x124(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EAX,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ESI,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 44b176 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xd56> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R14),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R14),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R9,%RDX,1),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %R9D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
KXORB %K1,%K1,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV 0x160(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EBX,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV 0x38(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x16c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD (%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R8),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R11,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (,%R11,8),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x58(%R14),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x80(%R14),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x3(%RCX),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R13D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R9,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x2(%R13),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x5(%RCX),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x4(%RCX),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ECX,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %ECX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12D,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9D,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R9D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%RDX,%R13,1),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $-0x8,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x3,%R12D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %RSI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x6,%R12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %R15D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x5(%R15,%R11,1),%EDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMP %R8D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x10(%R10,%RDI,8),%RDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMOVGE %R15D,%EDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
AND $0x7,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
KORTESTB %K1,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JNE 44bd81 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1961> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 402220 <@plt_start@+0x200> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x60(%R14),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R15),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP $0x1,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 44b7f1 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x13d1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x118(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x1,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x48(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R10,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (,%RAX,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
DEC %RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 44b1e3 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xdc3> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x100(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x178(%RSP),%R13D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13D,0x140(%R14) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 44ae4e <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xa2e> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0xf8(%RSP),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EBX,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x178(%RSP),%R13D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13D,0x140(%R14) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 44b176 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xd56> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0x108(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x178(%RSP),%R13D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13D,0x140(%R14) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 44ab2e <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x70e> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0x110(%RSP),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EBX,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x178(%RSP),%R13D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13D,0x140(%R14) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 44a80e <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x3ee> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 44ae7f <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xa5f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 44a83f <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x41f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 44ab5d <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x73d> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 44a518 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xf8> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | generate_chunk_kernel.f90:85-161 |
Module | exec |
nb instructions | 365 |
nb uops | 394 |
loop length | 1683 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 30 |
micro-operation queue | 65.67 cycles |
front end | 65.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 31.80 | 31.80 | 30.00 | 30.00 | 34.50 | 31.80 | 31.80 | 34.50 | 34.50 | 34.50 | 31.80 | 30.00 |
cycles | 31.80 | 47.13 | 30.00 | 30.00 | 34.50 | 31.80 | 31.80 | 34.50 | 34.50 | 34.50 | 31.80 | 30.00 |
Cycles executing div or sqrt instructions | 24.00 |
FE+BE cycles | 62.35-62.44 |
Stall cycles | 0.00 |
Front-end | 65.67 |
Dispatch | 47.13 |
DIV/SQRT | 24.00 |
Overall L1 | 65.67 |
all | 9% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 32% |
all | 9% |
load | 6% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x180,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x120(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x118(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x108(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf8(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf0(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x128(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x110(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd8(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x130(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x118(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%R12D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 402080 <@plt_start@+0x60> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EAX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x2,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 402180 <@plt_start@+0x160> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,0x124(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x18(%R14),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x3,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R12D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %EBX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 44be0d <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x19ed> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x124(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EAX,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ESI,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 44a80e <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x3ee> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x138(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R12,%RDX,1),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV (%R14),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R12D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
KXORB %K4,%K4,%K4 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV 0x8(%R14),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EBX,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV 0x48(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x16c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %RDI,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOVSXD (%R8),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%RDI,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x48(%R14),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R9),%R12D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x70(%R14),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R13,%RDX,1),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x2(%R13),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x3(%R12),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R13D,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RSI,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R12D,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x5(%R12),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R12D,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x4(%R12),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R12D,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x10(%R10,%R9,8),%RDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
AND $-0x8,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x3,%R12D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA 0x5(%R15,%R11,1),%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %ECX,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x6,%R12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %R15D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R8D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVGE %R15D,%R9D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ECX,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9D,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
KORTESTB %K4,%K4 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JNE 44bdcd <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x19ad> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 402220 <@plt_start@+0x200> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x10(%R14),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R14),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R15),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x2,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD $0x3,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIVL 0xb8(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
CMP %EDX,0x124(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JL 44bdfb <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x19db> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x124(%RSP),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EAX,%R10D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R10D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 44ab2e <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x70e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R14),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R14),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%R8,%RDX,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
KXORB %K3,%K3,%K3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV 0x130(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x50(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x16c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD (%RSI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %R11D,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
IMUL %R8,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (,%R8,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x40(%R14),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%R14),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x3(%RCX),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R13D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x2(%R13),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x5(%RCX),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x4(%RCX),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ECX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %ECX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12D,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EDX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%R10,%R13,1),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $-0x8,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x3,%R12D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %RSI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R10,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x6,%R12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %R15D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x5(%R15,%R8,1),%R10D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMP %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x10(%R9,%RDI,8),%RDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMOVLE %R15D,%R10D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10D,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
KORTESTB %K3,%K3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JNE 44bda6 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1986> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 402220 <@plt_start@+0x200> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x10(%R14),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R14),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R15),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x2,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD $0x3,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %EBX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIVL 0xb8(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
CMP %EDX,0x124(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JL 44be04 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x19e4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x124(%RSP),%R9D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EAX,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R9D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 44ae4e <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xa2e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R14),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R14),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RBX,%RDX,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %EBX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
KXORB %K2,%K2,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV 0x170(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x16c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD (%RSI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %R11D,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
IMUL %RCX,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (,%RCX,8),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x50(%R14),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%R14),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x3(%R8),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R13D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R10,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x2(%R13),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x5(%R8),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x4(%R8),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R8D,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10D,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R12D,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%R13,%RDX,1),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $-0x8,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x3,%R12D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %RSI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x6,%R12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %R15D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x5(%R15,%R8,1),%EDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMP %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x10(%R9,%RDI,8),%RDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMOVLE %R15D,%EDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
AND $0x7,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R10D,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
KORTESTB %K2,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JNE 44bd5a <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x193a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 402220 <@plt_start@+0x200> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x10(%R14),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R14),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R15),%R9D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RBX),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB $0x2,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD $0x3,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R9D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIVL 0xb8(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 6 |
CMP %EDX,0x124(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JL 44bdf2 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x19d2> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x124(%RSP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %EAX,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ESI,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 44b176 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xd56> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%R14),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R14),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R9,%RDX,1),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %R9D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
KXORB %K1,%K1,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV 0x160(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EBX,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV 0x38(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0x16c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVSXD (%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R8),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R11,%RSI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (,%R11,8),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x58(%R14),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x80(%R14),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x3(%RCX),%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB %R13D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R9,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x2(%R13),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x5(%RCX),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
LEA 0x4(%RCX),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ECX,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %ECX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12D,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9D,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R9D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%RDX,%R13,1),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $-0x8,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x3,%R12D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %RSI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x6,%R12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
ADD %R15D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x5(%R15,%R11,1),%EDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMP %R8D,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ECX,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x10(%R10,%RDI,8),%RDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMOVGE %R15D,%EDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
AND $0x7,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R9D,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EDX,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
KORTESTB %K1,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JNE 44bd81 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1961> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CALL 402220 <@plt_start@+0x200> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x60(%R14),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R15),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP $0x1,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 44b7f1 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x13d1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x118(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x1,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x48(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %R10,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (,%RAX,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
DEC %RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 44b1e3 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xdc3> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x100(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x178(%RSP),%R13D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13D,0x140(%R14) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 44ae4e <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xa2e> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0xf8(%RSP),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EBX,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x178(%RSP),%R13D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13D,0x140(%R14) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 44b176 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xd56> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0x108(%RSP),%R11D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11D,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x178(%RSP),%R13D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13D,0x140(%R14) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 44ab2e <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x70e> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0x110(%RSP),%EBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EBX,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x178(%RSP),%R13D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13D,0x140(%R14) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 44a80e <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x3ee> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 44ae7f <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xa5f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 44a83f <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x41f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 44ab5d <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x73d> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 44a518 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xf8> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼generate_chunk_kernel._omp_fn.0– | 0.03 | 0.01 |
▼Loop 240 - generate_chunk_kernel.f90:85-90 - exec– | 0 | 0 |
○Loop 241 - generate_chunk_kernel.f90:90-90 - exec | 0 | 0 |
▼Loop 236 - generate_chunk_kernel.f90:98-106 - exec– | 0 | 0 |
○Loop 237 - generate_chunk_kernel.f90:106-106 - exec | 0.01 | 0 |
▼Loop 234 - generate_chunk_kernel.f90:106-114 - exec– | 0 | 0 |
○Loop 235 - generate_chunk_kernel.f90:114-114 - exec | 0 | 0 |
▼Loop 230 - generate_chunk_kernel.f90:119-161 - exec– | 0 | 0 |
▼Loop 231 - generate_chunk_kernel.f90:129-161 - exec– | 0 | 0 |
○Loop 232 - generate_chunk_kernel.f90:130-137 - exec | 0.02 | 0.01 |
○Loop 233 - generate_chunk_kernel.f90:142-161 - exec | 0 | 0 |
▼Loop 238 - generate_chunk_kernel.f90:90-98 - exec– | 0 | 0 |
○Loop 239 - generate_chunk_kernel.f90:98-98 - exec | 0.01 | 0 |