Function: clover_pack_message_right._omp_fn.0 | Module: exec | Source: pack_kernel.f90:155-160 | Coverage: 0.04% |
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Function: clover_pack_message_right._omp_fn.0 | Module: exec | Source: pack_kernel.f90:155-160 | Coverage: 0.04% |
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/scratch_na/users/xoserete/qaas_runs/171-322-0339/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/pack_kernel.f90: 155 - 160 |
-------------------------------------------------------------------------------- |
155: !$OMP PARALLEL DO PRIVATE(index) |
156: DO k=y_min-depth,y_max+y_inc+depth |
157: !$OMP SIMD |
158: DO j=1,depth |
159: index= buffer_offset + j+(k+depth-1)*depth |
160: right_snd_buffer(index)=field(x_max+1-j,k) |
0x456e70 PUSH %RBP |
0x456e71 MOV %RSP,%RBP |
0x456e74 PUSH %R15 |
0x456e76 PUSH %R14 |
0x456e78 MOV %RDI,%R14 |
0x456e7b PUSH %R13 |
0x456e7d PUSH %R12 |
0x456e7f PUSH %RBX |
0x456e80 AND $-0x40,%RSP |
0x456e84 SUB $0xc0,%RSP |
0x456e8b MOV 0x20(%RDI),%RDX |
0x456e8f MOV 0x54(%RDI),%ESI |
0x456e92 MOV 0x28(%RDI),%RAX |
0x456e96 MOV 0x48(%RDI),%R15 |
0x456e9a MOV 0x40(%RDI),%RBX |
0x456e9e MOV 0x30(%RDI),%R12 |
0x456ea2 MOV %RDX,0x90(%RSP) |
0x456eaa MOV %ESI,0xbc(%RSP) |
0x456eb1 MOV %RAX,0xb0(%RSP) |
0x456eb9 CALL 402080 <@plt_start@+0x60> |
0x456ebe MOV %EAX,%R13D |
0x456ec1 CALL 402180 <@plt_start@+0x160> |
0x456ec6 MOV 0xbc(%RSP),%R8D |
0x456ece MOV %EAX,%ECX |
0x456ed0 MOV 0x58(%R14),%EAX |
0x456ed4 INC %EAX |
0x456ed6 SUB %R8D,%EAX |
0x456ed9 CLTD |
0x456eda IDIV %R13D |
0x456edd CMP %EDX,%ECX |
0x456edf JL 457357 |
0x456ee5 IMUL %EAX,%ECX |
0x456ee8 ADD %EDX,%ECX |
0x456eea ADD %ECX,%EAX |
0x456eec CMP %EAX,%ECX |
0x456eee JGE 4572f3 |
0x456ef4 ADD %R8D,%EAX |
0x456ef7 CMPQ $0x1,0x90(%RSP) |
0x456f00 LEA (%R8,%RCX,1),%EDI |
0x456f04 MOV 0x8(%R14),%R9 |
0x456f08 SETNE %SIL |
0x456f0c CMP $0x1,%RBX |
0x456f10 MOV 0x10(%R14),%R10 |
0x456f14 MOV (%R14),%R11 |
0x456f17 SETNE %CL |
0x456f1a MOV 0x18(%R14),%R13 |
0x456f1e MOV 0x38(%R14),%R8 |
0x456f22 MOV %EAX,0xb8(%RSP) |
0x456f29 OR %CL,%SIL |
0x456f2c MOV %EDI,0xbc(%RSP) |
0x456f33 MOV (%R9),%EAX |
0x456f36 MOV %R10,0xa8(%RSP) |
0x456f3e MOV %R11,0xa0(%RSP) |
0x456f46 MOV %SIL,0x63(%RSP) |
0x456f4b JNE 457360 |
0x456f51 MOVSXD 0xbc(%RSP),%R9 |
0x456f59 MOV 0xb0(%RSP),%R10 |
0x456f61 MOV %EAX,%ECX |
0x456f63 MOV %EAX,%R11D |
0x456f66 AND $-0x8,%R11D |
0x456f6a SHR $0x3,%ECX |
0x456f6d XOR %ESI,%ESI |
0x456f6f LEA 0x1(%R15),%RDI |
0x456f73 MOV %R9,%RBX |
0x456f76 IMUL %R10,%R9 |
0x456f7a SAL $0x6,%RCX |
0x456f7e MOV %R11D,0x90(%RSP) |
0x456f86 INC %R11D |
0x456f89 MOV %RCX,0x88(%RSP) |
0x456f91 VMOVDQA64 0x55d25(%RIP),%ZMM15 |
0x456f9b MOV %R11D,0x78(%RSP) |
0x456fa0 ADD %R12,%R9 |
0x456fa3 LEA -0x1(%RAX),%R12D |
0x456fa7 MOV %RDI,0x80(%RSP) |
0x456faf LEA (%RBX,%R12,1),%R10D |
0x456fb3 MOV %R12D,0x98(%RSP) |
0x456fbb IMUL %EAX,%R10D |
0x456fbf TEST %EAX,%EAX |
0x456fc1 CMOVNS %EAX,%ESI |
0x456fc4 LEA 0x1(%RSI),%EDX |
0x456fc7 MOV %EDX,0x54(%RSP) |
0x456fcb NOPL (%RAX,%RAX,1) |
(314) 0x456fd0 TEST %EAX,%EAX |
(314) 0x456fd2 JLE 4572bc |
(314) 0x456fd8 MOV 0xa8(%RSP),%RBX |
(314) 0x456fe0 MOV 0xa0(%RSP),%R12 |
(314) 0x456fe8 CMPL $0x6,0x98(%RSP) |
(314) 0x456ff0 MOV (%RBX),%EBX |
(314) 0x456ff2 MOV (%R12),%EDI |
(314) 0x456ff6 JBE 45734b |
(314) 0x456ffc MOV 0x80(%RSP),%RSI |
(314) 0x457004 MOVSXD %EDI,%R11 |
(314) 0x457007 MOVSXD %EBX,%RCX |
(314) 0x45700a MOVSXD %R10D,%RDX |
(314) 0x45700d ADD %R9,%R11 |
(314) 0x457010 ADD %RSI,%RCX |
(314) 0x457013 LEA -0x38(%R13,%R11,8),%R12 |
(314) 0x457018 MOV 0x88(%RSP),%RSI |
(314) 0x457020 MOV %R12,%R11 |
(314) 0x457023 ADD %RDX,%RCX |
(314) 0x457026 SUB %RSI,%R11 |
(314) 0x457029 SUB $0x40,%RSI |
(314) 0x45702d LEA (%R8,%RCX,8),%RCX |
(314) 0x457031 SHR $0x6,%RSI |
(314) 0x457035 INC %RSI |
(314) 0x457038 AND $0x7,%ESI |
(314) 0x45703b JE 45712c |
(314) 0x457041 CMP $0x1,%RSI |
(314) 0x457045 JE 457109 |
(314) 0x45704b CMP $0x2,%RSI |
(314) 0x45704f JE 4570ef |
(314) 0x457055 CMP $0x3,%RSI |
(314) 0x457059 JE 4570d5 |
(314) 0x45705b CMP $0x4,%RSI |
(314) 0x45705f JE 4570bb |
(314) 0x457061 CMP $0x5,%RSI |
(314) 0x457065 JE 4570a1 |
(314) 0x457067 CMP $0x6,%RSI |
(314) 0x45706b JE 457087 |
(314) 0x45706d VXORPS %XMM7,%XMM7,%XMM7 |
(314) 0x457071 VPERMPD (%R12),%ZMM15,%ZMM7 |
(314) 0x457078 ADD $0x40,%RCX |
(314) 0x45707c SUB $0x40,%R12 |
(314) 0x457080 VMOVUPD %ZMM7,-0x40(%RCX) |
(314) 0x457087 VXORPS %XMM6,%XMM6,%XMM6 |
(314) 0x45708b VPERMPD (%R12),%ZMM15,%ZMM6 |
(314) 0x457092 ADD $0x40,%RCX |
(314) 0x457096 SUB $0x40,%R12 |
(314) 0x45709a VMOVUPD %ZMM6,-0x40(%RCX) |
(314) 0x4570a1 VXORPS %XMM5,%XMM5,%XMM5 |
(314) 0x4570a5 VPERMPD (%R12),%ZMM15,%ZMM5 |
(314) 0x4570ac ADD $0x40,%RCX |
(314) 0x4570b0 SUB $0x40,%R12 |
(314) 0x4570b4 VMOVUPD %ZMM5,-0x40(%RCX) |
(314) 0x4570bb VXORPS %XMM4,%XMM4,%XMM4 |
(314) 0x4570bf VPERMPD (%R12),%ZMM15,%ZMM4 |
(314) 0x4570c6 ADD $0x40,%RCX |
(314) 0x4570ca SUB $0x40,%R12 |
(314) 0x4570ce VMOVUPD %ZMM4,-0x40(%RCX) |
(314) 0x4570d5 VXORPS %XMM3,%XMM3,%XMM3 |
(314) 0x4570d9 VPERMPD (%R12),%ZMM15,%ZMM3 |
(314) 0x4570e0 ADD $0x40,%RCX |
(314) 0x4570e4 SUB $0x40,%R12 |
(314) 0x4570e8 VMOVUPD %ZMM3,-0x40(%RCX) |
(314) 0x4570ef VXORPS %XMM2,%XMM2,%XMM2 |
(314) 0x4570f3 VPERMPD (%R12),%ZMM15,%ZMM2 |
(314) 0x4570fa ADD $0x40,%RCX |
(314) 0x4570fe SUB $0x40,%R12 |
(314) 0x457102 VMOVUPD %ZMM2,-0x40(%RCX) |
(314) 0x457109 VXORPS %XMM1,%XMM1,%XMM1 |
(314) 0x45710d VPERMPD (%R12),%ZMM15,%ZMM1 |
(314) 0x457114 SUB $0x40,%R12 |
(314) 0x457118 ADD $0x40,%RCX |
(314) 0x45711c VMOVUPD %ZMM1,-0x40(%RCX) |
(314) 0x457123 CMP %R12,%R11 |
(314) 0x457126 JE 4571e1 |
(315) 0x45712c VXORPS %XMM0,%XMM0,%XMM0 |
(315) 0x457130 VPERMPD (%R12),%ZMM15,%ZMM0 |
(315) 0x457137 SUB $0x200,%R12 |
(315) 0x45713e ADD $0x200,%RCX |
(315) 0x457145 VMOVUPD %ZMM0,-0x200(%RCX) |
(315) 0x45714c VXORPS %XMM8,%XMM8,%XMM8 |
(315) 0x457151 VPERMPD 0x1c0(%R12),%ZMM15,%ZMM8 |
(315) 0x457159 VMOVUPD %ZMM8,-0x1c0(%RCX) |
(315) 0x457160 VXORPS %XMM9,%XMM9,%XMM9 |
(315) 0x457165 VPERMPD 0x180(%R12),%ZMM15,%ZMM9 |
(315) 0x45716d VMOVUPD %ZMM9,-0x180(%RCX) |
(315) 0x457174 VXORPS %XMM10,%XMM10,%XMM10 |
(315) 0x457179 VPERMPD 0x140(%R12),%ZMM15,%ZMM10 |
(315) 0x457181 VMOVUPD %ZMM10,-0x140(%RCX) |
(315) 0x457188 VXORPS %XMM11,%XMM11,%XMM11 |
(315) 0x45718d VPERMPD 0x100(%R12),%ZMM15,%ZMM11 |
(315) 0x457195 VMOVUPD %ZMM11,-0x100(%RCX) |
(315) 0x45719c VXORPS %XMM12,%XMM12,%XMM12 |
(315) 0x4571a1 VPERMPD 0xc0(%R12),%ZMM15,%ZMM12 |
(315) 0x4571a9 VMOVUPD %ZMM12,-0xc0(%RCX) |
(315) 0x4571b0 VXORPS %XMM13,%XMM13,%XMM13 |
(315) 0x4571b5 VPERMPD 0x80(%R12),%ZMM15,%ZMM13 |
(315) 0x4571bd VMOVUPD %ZMM13,-0x80(%RCX) |
(315) 0x4571c4 VXORPS %XMM14,%XMM14,%XMM14 |
(315) 0x4571c9 VPERMPD 0x40(%R12),%ZMM15,%ZMM14 |
(315) 0x4571d1 VMOVUPD %ZMM14,-0x40(%RCX) |
(315) 0x4571d8 CMP %R12,%R11 |
(315) 0x4571db JNE 45712c |
(314) 0x4571e1 MOV 0x90(%RSP),%R12D |
(314) 0x4571e9 CMP %R12D,%EAX |
(314) 0x4571ec JE 4572bc |
(314) 0x4571f2 MOV 0x78(%RSP),%EDX |
(314) 0x4571f6 MOV %R12D,%ECX |
(314) 0x4571f9 MOV %EAX,%R12D |
(314) 0x4571fc SUB %ECX,%R12D |
(314) 0x4571ff LEA -0x1(%R12),%R11D |
(314) 0x457204 CMP $0x2,%R11D |
(314) 0x457208 JBE 457244 |
(314) 0x45720a MOVSXD %EDI,%RSI |
(314) 0x45720d MOVSXD %R10D,%R11 |
(314) 0x457210 ADD %R9,%RSI |
(314) 0x457213 SUB %RCX,%RSI |
(314) 0x457216 ADD %R15,%RCX |
(314) 0x457219 VXORPS %XMM7,%XMM7,%XMM7 |
(314) 0x45721d VPERMPD $0x1b,-0x18(%R13,%RSI,8),%YMM7 |
(314) 0x457225 MOVSXD %EBX,%RSI |
(314) 0x457228 ADD %RCX,%RSI |
(314) 0x45722b LEA 0x1(%R11,%RSI,1),%RCX |
(314) 0x457230 MOV %R12D,%ESI |
(314) 0x457233 AND $-0x4,%ESI |
(314) 0x457236 VMOVUPD %YMM7,(%R8,%RCX,8) |
(314) 0x45723c ADD %ESI,%EDX |
(314) 0x45723e AND $0x3,%R12D |
(314) 0x457242 JE 4572bc |
(314) 0x457244 LEA 0x1(%RDI),%R12D |
(314) 0x457248 LEA (%RBX,%RDX,1),%ESI |
(314) 0x45724b MOV %R12D,%R11D |
(314) 0x45724e ADD %R10D,%ESI |
(314) 0x457251 SUB %EDX,%R11D |
(314) 0x457254 MOVSXD %R11D,%RCX |
(314) 0x457257 MOVSXD %ESI,%R11 |
(314) 0x45725a ADD %R9,%RCX |
(314) 0x45725d ADD %R15,%R11 |
(314) 0x457260 VMOVSD (%R13,%RCX,8),%XMM6 |
(314) 0x457267 LEA 0x1(%RDX),%ECX |
(314) 0x45726a VMOVSD %XMM6,(%R8,%R11,8) |
(314) 0x457270 CMP %ECX,%EAX |
(314) 0x457272 JL 4572bc |
(314) 0x457274 SUB %EDX,%EDI |
(314) 0x457276 ADD %EBX,%ECX |
(314) 0x457278 ADD $0x2,%EDX |
(314) 0x45727b MOVSXD %EDI,%RDI |
(314) 0x45727e ADD %R10D,%ECX |
(314) 0x457281 ADD %R9,%RDI |
(314) 0x457284 MOVSXD %ECX,%RSI |
(314) 0x457287 VMOVSD (%R13,%RDI,8),%XMM5 |
(314) 0x45728e ADD %R15,%RSI |
(314) 0x457291 VMOVSD %XMM5,(%R8,%RSI,8) |
(314) 0x457297 CMP %EDX,%EAX |
(314) 0x457299 JL 4572bc |
(314) 0x45729b SUB %EDX,%R12D |
(314) 0x45729e ADD %EBX,%EDX |
(314) 0x4572a0 MOVSXD %R12D,%R12 |
(314) 0x4572a3 ADD %R10D,%EDX |
(314) 0x4572a6 ADD %R9,%R12 |
(314) 0x4572a9 MOVSXD %EDX,%RBX |
(314) 0x4572ac VMOVSD (%R13,%R12,8),%XMM4 |
(314) 0x4572b3 ADD %R15,%RBX |
(314) 0x4572b6 VMOVSD %XMM4,(%R8,%RBX,8) |
(314) 0x4572bc INCL 0xbc(%RSP) |
(314) 0x4572c3 MOV 0xb0(%RSP),%R11 |
(314) 0x4572cb ADD %EAX,%R10D |
(314) 0x4572ce ADD %R11,%R9 |
(314) 0x4572d1 MOV 0xbc(%RSP),%EDX |
(314) 0x4572d8 TEST %EAX,%EAX |
(314) 0x4572da JNS 457330 |
(314) 0x4572dc CMP %EDX,0xb8(%RSP) |
(314) 0x4572e3 JG 456fd0 |
0x4572e9 VZEROUPPER |
0x4572ec CMPB $0,0x63(%RSP) |
0x4572f1 JNE 45730f |
0x4572f3 LEA -0x28(%RBP),%RSP |
0x4572f7 POP %RBX |
0x4572f8 POP %R12 |
0x4572fa POP %R13 |
0x4572fc POP %R14 |
0x4572fe POP %R15 |
0x457300 POP %RBP |
0x457301 RET |
0x457302 VZEROUPPER |
0x457305 MOV 0x54(%RSP),%R13D |
0x45730a MOV %R13D,0x50(%RSP) |
0x45730f MOV 0x50(%RSP),%R15D |
0x457314 MOV %R15D,0x50(%R14) |
0x457318 LEA -0x28(%RBP),%RSP |
0x45731c POP %RBX |
0x45731d POP %R12 |
0x45731f POP %R13 |
0x457321 POP %R14 |
0x457323 POP %R15 |
0x457325 POP %RBP |
0x457326 RET |
0x457327 NOPW (%RAX,%RAX,1) |
(314) 0x457330 CMP %EDX,0xb8(%RSP) |
(314) 0x457337 JLE 457302 |
(314) 0x457339 MOV 0x54(%RSP),%ECX |
(314) 0x45733d MOVB $0x1,0x63(%RSP) |
(314) 0x457342 MOV %ECX,0x50(%RSP) |
(314) 0x457346 JMP 456fd0 |
(314) 0x45734b XOR %ECX,%ECX |
(314) 0x45734d MOV $0x1,%EDX |
(314) 0x457352 JMP 4571f9 |
0x457357 INC %EAX |
0x457359 XOR %EDX,%EDX |
0x45735b JMP 456ee5 |
0x457360 MOVSXD 0xbc(%RSP),%RDX |
0x457368 MOV 0xb0(%RSP),%R9 |
0x457370 LEA -0x1(%RAX),%R10D |
0x457374 MOV %EAX,%ESI |
0x457376 KXORB %K0,%K0,%K0 |
0x45737a MOV %R10D,0x2c(%RSP) |
0x45737f SHR $0x3,%ESI |
0x457382 MOV %RBX,%RCX |
0x457385 MOV %RDX,%RDI |
0x457388 IMUL %R9,%RDX |
0x45738c MOV %ESI,0x6c(%RSP) |
0x457390 SAL $0x6,%RCX |
0x457394 LEA (%RDI,%R10,1),%R11D |
0x457398 MOV 0x90(%RSP),%RDI |
0x4573a0 MOV %R8,0x70(%RSP) |
0x4573a5 IMUL %EAX,%R11D |
0x4573a9 MOV %RCX,0x58(%RSP) |
0x4573ae IMUL $-0x28,%RDI,%R10 |
0x4573b2 LEA (%RDX,%R12,1),%R12 |
0x4573b6 MOV %RDI,%RDX |
0x4573b9 MOV %R14,0x8(%RSP) |
0x4573be NEG %RDX |
0x4573c1 MOV %R12,0x98(%RSP) |
0x4573c9 LEA (,%RBX,8),%R12 |
0x4573d1 MOV %R11D,0x88(%RSP) |
0x4573d9 MOV %RBX,%R11 |
0x4573dc MOV %RDX,%RSI |
0x4573df LEA (,%RDX,8),%R9 |
0x4573e7 MOV %R10,0x20(%RSP) |
0x4573ec SAL $0x5,%R11 |
0x4573f0 MOV %RDX,%R10 |
0x4573f3 SAL $0x5,%RDX |
0x4573f7 SAL $0x4,%R10 |
0x4573fb MOV %R11,0x18(%RSP) |
0x457400 MOV %RBX,%R11 |
0x457403 SAL $0x6,%RSI |
0x457407 MOV %R10,%RDI |
0x45740a MOV %RDX,0x30(%RSP) |
0x45740f LEA (%RBX,%RBX,2),%RDX |
0x457413 SAL $0x4,%R11 |
0x457417 NEG %RDI |
0x45741a MOV %R12,0x48(%RSP) |
0x45741f LEA (,%RDX,8),%R12 |
0x457427 XOR %EDX,%EDX |
0x457429 MOV %RDI,0x38(%RSP) |
0x45742e MOV %EAX,%EDI |
0x457430 AND $-0x8,%EDI |
0x457433 MOV %R15,0x80(%RSP) |
0x45743b MOV %RSI,%R15 |
0x45743e MOV %EDI,0x28(%RSP) |
0x457442 INC %EDI |
0x457444 TEST %EAX,%EAX |
0x457446 CMOVNS %EAX,%EDX |
0x457449 MOV %EDI,0x14(%RSP) |
0x45744d MOV %R13,0x78(%RSP) |
0x457452 MOV %R11,%R13 |
0x457455 LEA 0x1(%RDX),%EDI |
0x457458 MOV %EDI,0x54(%RSP) |
0x45745c NOPL (%RAX) |
(312) 0x457460 TEST %EAX,%EAX |
(312) 0x457462 JLE 457851 |
(312) 0x457468 MOV 0xa8(%RSP),%R14 |
(312) 0x457470 MOV 0xa0(%RSP),%RSI |
(312) 0x457478 CMPL $0x6,0x2c(%RSP) |
(312) 0x45747d MOV (%R14),%R8D |
(312) 0x457480 MOV (%RSI),%ECX |
(312) 0x457482 MOV %R8D,0x68(%RSP) |
(312) 0x457487 MOV %ECX,0x64(%RSP) |
(312) 0x45748b JBE 4578cd |
(312) 0x457491 MOV 0x90(%RSP),%RDX |
(312) 0x457499 MOVSXD %ECX,%R11 |
(312) 0x45749c MOVSXD %R8D,%RSI |
(312) 0x45749f MOVSXD 0x88(%RSP),%R8 |
(312) 0x4574a7 MOV 0x98(%RSP),%RDI |
(312) 0x4574af MOV 0x78(%RSP),%R14 |
(312) 0x4574b4 IMUL %RDX,%R11 |
(312) 0x4574b8 LEA 0x1(%RSI,%R8,1),%RCX |
(312) 0x4574bd MOV 0x70(%RSP),%RDX |
(312) 0x4574c2 MOV 0x20(%RSP),%R8 |
(312) 0x4574c7 IMUL %RBX,%RCX |
(312) 0x4574cb ADD %RDI,%R11 |
(312) 0x4574ce LEA (%R14,%R11,8),%RDI |
(312) 0x4574d2 MOV 0x80(%RSP),%R11 |
(312) 0x4574da MOV %RDI,0x40(%RSP) |
(312) 0x4574df ADD %R11,%RCX |
(312) 0x4574e2 XOR %R11D,%R11D |
(312) 0x4574e5 LEA (%RDX,%RCX,8),%R14 |
(312) 0x4574e9 MOV 0x18(%RSP),%RDX |
(312) 0x4574ee LEA (%RDI,%R8,1),%RCX |
(312) 0x4574f2 MOV %R14,%RSI |
(312) 0x4574f5 ADD %R14,%RDX |
(312) 0x4574f8 TESTB $0x1,0x6c(%RSP) |
(312) 0x4574fd JE 45758a |
(312) 0x457503 MOV 0x38(%RSP),%R11 |
(312) 0x457508 VMOVSD (%RDI),%XMM7 |
(312) 0x45750c VMOVSD (%RDI,%R9,1),%XMM6 |
(312) 0x457512 VMOVSD (%RDI,%R10,1),%XMM5 |
(312) 0x457518 VMOVSD (%RCX,%R11,1),%XMM4 |
(312) 0x45751e MOV 0x30(%RSP),%R11 |
(312) 0x457523 VMOVSD (%RCX),%XMM2 |
(312) 0x457527 VMOVSD (%RCX,%R9,1),%XMM1 |
(312) 0x45752d VMOVSD (%RDI,%R11,1),%XMM3 |
(312) 0x457533 VMOVSD (%RCX,%R10,1),%XMM0 |
(312) 0x457539 VMOVSD %XMM7,(%R14) |
(312) 0x45753e MOV $0x1,%R11D |
(312) 0x457544 VMOVSD %XMM6,(%R14,%RBX,8) |
(312) 0x45754a MOV 0x6c(%RSP),%R8D |
(312) 0x45754f ADD %R15,%RDI |
(312) 0x457552 ADD %R15,%RCX |
(312) 0x457555 VMOVSD %XMM5,(%R14,%R13,1) |
(312) 0x45755b VMOVSD %XMM4,(%R14,%R12,1) |
(312) 0x457561 MOV 0x58(%RSP),%R14 |
(312) 0x457566 VMOVSD %XMM3,(%RDX) |
(312) 0x45756a ADD %R14,%RSI |
(312) 0x45756d VMOVSD %XMM2,(%RDX,%RBX,8) |
(312) 0x457572 VMOVSD %XMM1,(%RDX,%R13,1) |
(312) 0x457578 VMOVSD %XMM0,(%RDX,%R12,1) |
(312) 0x45757e ADD %R14,%RDX |
(312) 0x457581 CMP %R8D,%R11D |
(312) 0x457584 JE 457683 |
(312) 0x45758a MOV 0x58(%RSP),%R8 |
(312) 0x45758f MOV 0x30(%RSP),%R14 |
(312) 0x457594 MOV %EAX,0x40(%RSP) |
(312) 0x457598 MOV 0x38(%RSP),%RAX |
(312) 0x45759d MOV %RAX,0x58(%RSP) |
(313) 0x4575a2 MOV 0x58(%RSP),%RAX |
(313) 0x4575a7 VMOVSD (%RDI),%XMM8 |
(313) 0x4575ab ADD $0x2,%R11D |
(313) 0x4575af VMOVSD (%RDI,%R9,1),%XMM9 |
(313) 0x4575b5 VMOVSD (%RDI,%R10,1),%XMM10 |
(313) 0x4575bb VMOVSD (%RCX,%RAX,1),%XMM11 |
(313) 0x4575c0 VMOVSD (%RDI,%R14,1),%XMM12 |
(313) 0x4575c6 ADD %R15,%RDI |
(313) 0x4575c9 VMOVSD (%RCX),%XMM13 |
(313) 0x4575cd VMOVSD (%RCX,%R9,1),%XMM14 |
(313) 0x4575d3 VMOVSD (%RCX,%R10,1),%XMM15 |
(313) 0x4575d9 VMOVSD %XMM8,(%RSI) |
(313) 0x4575dd ADD %R15,%RCX |
(313) 0x4575e0 VMOVSD %XMM9,(%RSI,%RBX,8) |
(313) 0x4575e5 VMOVSD %XMM10,(%RSI,%R13,1) |
(313) 0x4575eb VMOVSD %XMM11,(%RSI,%R12,1) |
(313) 0x4575f1 ADD %R8,%RSI |
(313) 0x4575f4 VMOVSD %XMM12,(%RDX) |
(313) 0x4575f8 VMOVSD %XMM13,(%RDX,%RBX,8) |
(313) 0x4575fd VMOVSD %XMM14,(%RDX,%R13,1) |
(313) 0x457603 VMOVSD %XMM15,(%RDX,%R12,1) |
(313) 0x457609 ADD %R8,%RDX |
(313) 0x45760c VMOVSD (%RCX,%RAX,1),%XMM4 |
(313) 0x457611 VMOVSD (%RDI),%XMM7 |
(313) 0x457615 VMOVSD (%RDI,%R9,1),%XMM6 |
(313) 0x45761b VMOVSD (%RDI,%R10,1),%XMM5 |
(313) 0x457621 VMOVSD (%RDI,%R14,1),%XMM3 |
(313) 0x457627 VMOVSD (%RCX),%XMM2 |
(313) 0x45762b ADD %R15,%RDI |
(313) 0x45762e VMOVSD (%RCX,%R9,1),%XMM1 |
(313) 0x457634 VMOVSD (%RCX,%R10,1),%XMM0 |
(313) 0x45763a VMOVSD %XMM7,(%RSI) |
(313) 0x45763e ADD %R15,%RCX |
(313) 0x457641 VMOVSD %XMM6,(%RSI,%RBX,8) |
(313) 0x457646 VMOVSD %XMM5,(%RSI,%R13,1) |
(313) 0x45764c VMOVSD %XMM4,(%RSI,%R12,1) |
(313) 0x457652 ADD %R8,%RSI |
(313) 0x457655 VMOVSD %XMM3,(%RDX) |
(313) 0x457659 VMOVSD %XMM2,(%RDX,%RBX,8) |
(313) 0x45765e VMOVSD %XMM1,(%RDX,%R13,1) |
(313) 0x457664 VMOVSD %XMM0,(%RDX,%R12,1) |
(313) 0x45766a MOV 0x6c(%RSP),%EAX |
(313) 0x45766e ADD %R8,%RDX |
(313) 0x457671 CMP %EAX,%R11D |
(313) 0x457674 JNE 4575a2 |
(312) 0x45767a MOV %R8,0x58(%RSP) |
(312) 0x45767f MOV 0x40(%RSP),%EAX |
(312) 0x457683 MOV 0x28(%RSP),%EDI |
(312) 0x457687 CMP %EAX,%EDI |
(312) 0x457689 JE 457851 |
(312) 0x45768f MOV 0x14(%RSP),%ECX |
(312) 0x457693 MOV %EDI,%R8D |
(312) 0x457696 MOV %EAX,%R11D |
(312) 0x457699 SUB %R8D,%R11D |
(312) 0x45769c LEA -0x1(%R11),%ESI |
(312) 0x4576a0 CMP $0x2,%ESI |
(312) 0x4576a3 JBE 45774f |
(312) 0x4576a9 MOV 0x90(%RSP),%R14 |
(312) 0x4576b1 MOVSXD 0x64(%RSP),%RDX |
(312) 0x4576b6 MOV %R9,%RSI |
(312) 0x4576b9 IMUL %R8,%RSI |
(312) 0x4576bd MOV 0x98(%RSP),%RDI |
(312) 0x4576c5 IMUL %R14,%RDX |
(312) 0x4576c9 MOV 0x78(%RSP),%R14 |
(312) 0x4576ce IMUL %RBX,%R8 |
(312) 0x4576d2 ADD %RDI,%RDX |
(312) 0x4576d5 MOVSXD 0x68(%RSP),%RDI |
(312) 0x4576da LEA (%RSI,%RDX,8),%RDX |
(312) 0x4576de MOVSXD 0x88(%RSP),%RSI |
(312) 0x4576e6 ADD %R14,%RDX |
(312) 0x4576e9 MOV 0x80(%RSP),%R14 |
(312) 0x4576f1 LEA 0x1(%RDI,%RSI,1),%RDI |
(312) 0x4576f6 VMOVSD (%RDX),%XMM8 |
(312) 0x4576fa ADD %R9,%RDX |
(312) 0x4576fd IMUL %RBX,%RDI |
(312) 0x457701 VMOVSD (%RDX),%XMM9 |
(312) 0x457705 ADD %R9,%RDX |
(312) 0x457708 VMOVSD (%RDX),%XMM10 |
(312) 0x45770c VMOVSD (%RDX,%R9,1),%XMM11 |
(312) 0x457712 MOV 0x48(%RSP),%RDX |
(312) 0x457717 ADD %R14,%RDI |
(312) 0x45771a ADD %R8,%RDI |
(312) 0x45771d MOV 0x70(%RSP),%R8 |
(312) 0x457722 LEA (%R8,%RDI,8),%RSI |
(312) 0x457726 MOV %R11D,%EDI |
(312) 0x457729 VMOVSD %XMM8,(%RSI) |
(312) 0x45772d AND $-0x4,%EDI |
(312) 0x457730 ADD %RDX,%RSI |
(312) 0x457733 VMOVSD %XMM9,(%RSI) |
(312) 0x457737 ADD %EDI,%ECX |
(312) 0x457739 ADD %RDX,%RSI |
(312) 0x45773c AND $0x3,%R11D |
(312) 0x457740 VMOVSD %XMM10,(%RSI) |
(312) 0x457744 VMOVSD %XMM11,(%RSI,%RDX,1) |
(312) 0x457749 JE 457851 |
(312) 0x45774f MOV 0x64(%RSP),%EDI |
(312) 0x457753 MOV 0x98(%RSP),%R14 |
(312) 0x45775b MOV 0x78(%RSP),%R8 |
(312) 0x457760 LEA 0x1(%RDI),%ESI |
(312) 0x457763 MOV %ESI,%R11D |
(312) 0x457766 SUB %ECX,%R11D |
(312) 0x457769 MOVSXD %R11D,%RDX |
(312) 0x45776c MOV 0x90(%RSP),%R11 |
(312) 0x457774 IMUL %R11,%RDX |
(312) 0x457778 ADD %R14,%RDX |
(312) 0x45777b MOV 0x68(%RSP),%R14D |
(312) 0x457780 VMOVSD (%R8,%RDX,8),%XMM12 |
(312) 0x457786 MOV 0x88(%RSP),%R8D |
(312) 0x45778e LEA (%R14,%RCX,1),%EDX |
(312) 0x457792 ADD %R8D,%EDX |
(312) 0x457795 MOV 0x80(%RSP),%R8 |
(312) 0x45779d MOVSXD %EDX,%RDX |
(312) 0x4577a0 IMUL %RBX,%RDX |
(312) 0x4577a4 ADD %R8,%RDX |
(312) 0x4577a7 MOV 0x70(%RSP),%R8 |
(312) 0x4577ac VMOVSD %XMM12,(%R8,%RDX,8) |
(312) 0x4577b2 LEA 0x1(%RCX),%EDX |
(312) 0x4577b5 CMP %EDX,%EAX |
(312) 0x4577b7 JL 457851 |
(312) 0x4577bd SUB %ECX,%EDI |
(312) 0x4577bf MOV 0x98(%RSP),%R8 |
(312) 0x4577c7 ADD %R14D,%EDX |
(312) 0x4577ca ADD $0x2,%ECX |
(312) 0x4577cd MOVSXD %EDI,%RDI |
(312) 0x4577d0 IMUL %R11,%RDI |
(312) 0x4577d4 ADD %R8,%RDI |
(312) 0x4577d7 MOV 0x78(%RSP),%R8 |
(312) 0x4577dc VMOVSD (%R8,%RDI,8),%XMM13 |
(312) 0x4577e2 MOV %R14D,%EDI |
(312) 0x4577e5 MOV 0x88(%RSP),%R14D |
(312) 0x4577ed MOV 0x80(%RSP),%R8 |
(312) 0x4577f5 ADD %R14D,%EDX |
(312) 0x4577f8 MOVSXD %EDX,%RDX |
(312) 0x4577fb IMUL %RBX,%RDX |
(312) 0x4577ff ADD %R8,%RDX |
(312) 0x457802 MOV 0x70(%RSP),%R8 |
(312) 0x457807 VMOVSD %XMM13,(%R8,%RDX,8) |
(312) 0x45780d CMP %ECX,%EAX |
(312) 0x45780f JL 457851 |
(312) 0x457811 SUB %ECX,%ESI |
(312) 0x457813 ADD %ECX,%EDI |
(312) 0x457815 MOV 0x78(%RSP),%RDX |
(312) 0x45781a MOV 0x70(%RSP),%R8 |
(312) 0x45781f MOVSXD %ESI,%RSI |
(312) 0x457822 ADD %R14D,%EDI |
(312) 0x457825 MOV 0x80(%RSP),%R14 |
(312) 0x45782d IMUL %R11,%RSI |
(312) 0x457831 MOVSXD %EDI,%RCX |
(312) 0x457834 MOV 0x98(%RSP),%R11 |
(312) 0x45783c IMUL %RBX,%RCX |
(312) 0x457840 ADD %R11,%RSI |
(312) 0x457843 VMOVSD (%RDX,%RSI,8),%XMM14 |
(312) 0x457848 ADD %R14,%RCX |
(312) 0x45784b VMOVSD %XMM14,(%R8,%RCX,8) |
(312) 0x457851 INCL 0xbc(%RSP) |
(312) 0x457858 MOV 0xbc(%RSP),%R11D |
(312) 0x457860 TEST %EAX,%EAX |
(312) 0x457862 JNS 457899 |
(312) 0x457864 MOV 0xb0(%RSP),%RSI |
(312) 0x45786c ADD %EAX,0x88(%RSP) |
(312) 0x457873 ADD %RSI,0x98(%RSP) |
(312) 0x45787b CMP %R11D,0xb8(%RSP) |
(312) 0x457883 JG 457460 |
0x457889 MOV 0x8(%RSP),%R14 |
0x45788e KMOVB %K0,0x63(%RSP) |
0x457894 JMP 4572ec |
(312) 0x457899 MOV 0xb0(%RSP),%RDX |
(312) 0x4578a1 ADD %EAX,0x88(%RSP) |
(312) 0x4578a8 ADD %RDX,0x98(%RSP) |
(312) 0x4578b0 CMP %R11D,0xb8(%RSP) |
(312) 0x4578b8 JLE 4578da |
(312) 0x4578ba MOV 0x54(%RSP),%EDI |
(312) 0x4578be KMOVB 0x63(%RSP),%K0 |
(312) 0x4578c4 MOV %EDI,0x50(%RSP) |
(312) 0x4578c8 JMP 457460 |
(312) 0x4578cd XOR %R8D,%R8D |
(312) 0x4578d0 MOV $0x1,%ECX |
(312) 0x4578d5 JMP 457696 |
0x4578da MOV 0x8(%RSP),%R14 |
0x4578df JMP 457305 |
0x4578e4 NOPW %CS:(%RAX,%RAX,1) |
0x4578ef NOP |
Path / |
Source file and lines | pack_kernel.f90:155-160 |
Module | exec |
nb instructions | 176 |
nb uops | 183 |
loop length | 726 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 1 |
nb stack references | 26 |
micro-operation queue | 30.50 cycles |
front end | 30.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 12.10 | 12.00 | 13.33 | 13.33 | 21.00 | 12.00 | 11.90 | 21.00 | 21.00 | 21.00 | 12.00 | 13.33 |
cycles | 12.10 | 15.00 | 13.33 | 13.33 | 21.00 | 12.00 | 11.90 | 21.00 | 21.00 | 21.00 | 12.00 | 13.33 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 29.78-29.82 |
Stall cycles | 0.00 |
Front-end | 30.50 |
Dispatch | 21.00 |
DIV/SQRT | 6.00 |
Overall L1 | 30.50 |
all | 5% |
load | 16% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 11% |
load | 24% |
store | 9% |
mul | 6% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x20(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x54(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x48(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0xbc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 402080 <@plt_start@+0x60> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 402180 <@plt_start@+0x160> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xbc(%RSP),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x58(%R14),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 457357 <__pack_kernel_module_MOD_clover_pack_message_right._omp_fn.0+0x4e7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %ECX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4572f3 <__pack_kernel_module_MOD_clover_pack_message_right._omp_fn.0+0x483> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMPQ $0x1,0x90(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA (%R8,%RCX,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV 0x8(%R14),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SETNE %SIL | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP $0x1,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x10(%R14),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R14),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SETNE %CL | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%R14),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%R14),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
OR %CL,%SIL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDI,0xbc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%R9),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %SIL,0x63(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JNE 457360 <__pack_kernel_module_MOD_clover_pack_message_right._omp_fn.0+0x4f0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD 0xbc(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EAX,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x3,%ECX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x1(%R15),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R9,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R10,%R9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SAL $0x6,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R11D,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVDQA64 0x55d25(%RIP),%ZMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
MOV %R11D,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R12,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %RDI,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RBX,%R12,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R12D,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %EAX,%R10D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
TEST %EAX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVNS %EAX,%ESI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LEA 0x1(%RSI),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CMPB $0,0x63(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 45730f <__pack_kernel_module_MOD_clover_pack_message_right._omp_fn.0+0x49f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV 0x54(%RSP),%R13D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13D,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RSP),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15D,0x50(%R14) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 456ee5 <__pack_kernel_module_MOD_clover_pack_message_right._omp_fn.0+0x75> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOVSXD 0xbc(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x1(%RAX),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
KXORB %K0,%K0,%K0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV %R10D,0x2c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SHR $0x3,%ESI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RBX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R9,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %ESI,0x6c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x6,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%RDI,%R10,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV 0x90(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %EAX,%R11D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %RCX,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL $-0x28,%RDI,%R10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RDX,%R12,1),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDI,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NEG %RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R12,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%RBX,8),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R11D,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (,%RDX,8),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R10,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x5,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RDX,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x5,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
SAL $0x4,%R10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R11,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x6,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R10,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RBX,%RBX,2),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SAL $0x4,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
NEG %RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R12,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%RDX,8),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R15,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EDI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
TEST %EAX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVNS %EAX,%EDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x1(%RDX),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x8(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
KMOVB %K0,0x63(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
JMP 4572ec <__pack_kernel_module_MOD_clover_pack_message_right._omp_fn.0+0x47c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0x8(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 457305 <__pack_kernel_module_MOD_clover_pack_message_right._omp_fn.0+0x495> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | pack_kernel.f90:155-160 |
Module | exec |
nb instructions | 176 |
nb uops | 183 |
loop length | 726 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 1 |
nb stack references | 26 |
micro-operation queue | 30.50 cycles |
front end | 30.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 12.10 | 12.00 | 13.33 | 13.33 | 21.00 | 12.00 | 11.90 | 21.00 | 21.00 | 21.00 | 12.00 | 13.33 |
cycles | 12.10 | 15.00 | 13.33 | 13.33 | 21.00 | 12.00 | 11.90 | 21.00 | 21.00 | 21.00 | 12.00 | 13.33 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 29.78-29.82 |
Stall cycles | 0.00 |
Front-end | 30.50 |
Dispatch | 21.00 |
DIV/SQRT | 6.00 |
Overall L1 | 30.50 |
all | 5% |
load | 16% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 11% |
load | 24% |
store | 9% |
mul | 6% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0xc0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x20(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x54(%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x48(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,0xbc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 402080 <@plt_start@+0x60> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 402180 <@plt_start@+0x160> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xbc(%RSP),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x58(%R14),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R13D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 457357 <__pack_kernel_module_MOD_clover_pack_message_right._omp_fn.0+0x4e7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %ECX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4572f3 <__pack_kernel_module_MOD_clover_pack_message_right._omp_fn.0+0x483> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMPQ $0x1,0x90(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA (%R8,%RCX,1),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV 0x8(%R14),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SETNE %SIL | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP $0x1,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x10(%R14),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R14),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SETNE %CL | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%R14),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%R14),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
OR %CL,%SIL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDI,0xbc(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%R9),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %SIL,0x63(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JNE 457360 <__pack_kernel_module_MOD_clover_pack_message_right._omp_fn.0+0x4f0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD 0xbc(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EAX,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SHR $0x3,%ECX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x1(%R15),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R9,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R10,%R9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SAL $0x6,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R11D,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVDQA64 0x55d25(%RIP),%ZMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
MOV %R11D,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R12,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA -0x1(%RAX),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %RDI,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RBX,%R12,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R12D,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %EAX,%R10D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
TEST %EAX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVNS %EAX,%ESI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LEA 0x1(%RSI),%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDX,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
CMPB $0,0x63(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 45730f <__pack_kernel_module_MOD_clover_pack_message_right._omp_fn.0+0x49f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV 0x54(%RSP),%R13D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13D,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RSP),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15D,0x50(%R14) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 456ee5 <__pack_kernel_module_MOD_clover_pack_message_right._omp_fn.0+0x75> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOVSXD 0xbc(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x1(%RAX),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
KXORB %K0,%K0,%K0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV %R10D,0x2c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SHR $0x3,%ESI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RBX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R9,%RDX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %ESI,0x6c(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x6,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%RDI,%R10,1),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV 0x90(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL %EAX,%R11D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %RCX,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IMUL $-0x28,%RDI,%R10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
LEA (%RDX,%R12,1),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDI,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R14,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NEG %RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R12,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%RBX,8),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R11D,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (,%RDX,8),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R10,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x5,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RDX,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x5,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
SAL $0x4,%R10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R11,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x6,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R10,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RBX,%RBX,2),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SAL $0x4,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
NEG %RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R12,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%RDX,8),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDI,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R15,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EDI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
TEST %EAX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
CMOVNS %EAX,%EDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %EDI,0x14(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x1(%RDX),%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %EDI,0x54(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x8(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
KMOVB %K0,0x63(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
JMP 4572ec <__pack_kernel_module_MOD_clover_pack_message_right._omp_fn.0+0x47c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0x8(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 457305 <__pack_kernel_module_MOD_clover_pack_message_right._omp_fn.0+0x495> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼clover_pack_message_right._omp_fn.0– | 0.04 | 0.01 |
▼Loop 314 - pack_kernel.f90:155-160 - exec– | 0.04 | 0.03 |
○Loop 315 - pack_kernel.f90:160-160 - exec | 0 | 0 |
▼Loop 312 - pack_kernel.f90:159-160 - exec– | 0 | 0 |
○Loop 313 - pack_kernel.f90:160-160 - exec | 0 | 0 |