Loop Id: 283 | Module: exec | Source: generate_chunk_kernel.f90:87-163 [...] | Coverage: 0.03% |
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Loop Id: 283 | Module: exec | Source: generate_chunk_kernel.f90:87-163 [...] | Coverage: 0.03% |
---|
0x437f00 MOV -0xf0(%RBP),%ECX |
0x437f06 INC %ECX |
0x437f08 MOV -0x170(%RBP),%R8 |
0x437f0f INC %R8 |
0x437f12 MOV -0x178(%RBP),%RAX |
0x437f19 INC %RAX |
0x437f1c CMP -0x168(%RBP),%R8 |
0x437f23 MOV -0xec(%RBP),%EDI |
0x437f29 JE 437e40 |
0x437f2f MOVSXD %ECX,%RSI |
0x437f32 LEA (,%RSI,8),%R9 |
0x437f3a CMP %RSI,%RAX |
0x437f3d MOV %RSI,%RDX |
0x437f40 MOV %RAX,-0x178(%RBP) |
0x437f47 CMOVG %RAX,%RDX |
0x437f4b SUB %RSI,%RDX |
0x437f4e INC %RDX |
0x437f51 SHR $0x3,%RDX |
0x437f55 NEG %RDX |
0x437f58 MOV %RDX,-0x78(%RBP) |
0x437f5c MOV -0x160(%RBP),%RAX |
0x437f63 LEA (%R8,%RAX,1),%R10 |
0x437f67 CMP -0xe8(%RBP),%EDI |
0x437f6d MOV %ECX,-0xf0(%RBP) |
0x437f73 MOV %R8,-0x170(%RBP) |
0x437f7a JNE 438110 |
0x437f80 LEA 0x1(%R10),%RAX |
0x437f84 MOV %RAX,%R12 |
0x437f87 SUB -0x50(%RBP),%RAX |
0x437f8b MOV 0xd0(%RBP),%RCX |
0x437f92 VMOVSD (%RCX,%RAX,8),%XMM0 |
0x437f97 MOV 0x68(%RBP),%RAX |
0x437f9b MOV -0x48(%RBP),%RCX |
0x437f9f VUCOMISD -0x8(%RAX,%RCX,8),%XMM0 |
0x437fa5 JB 437f00 |
0x437fab MOV %R10,%RDI |
0x437fae SUB -0x50(%RBP),%RDI |
0x437fb2 MOV 0x60(%RBP),%RAX |
0x437fb6 MOV -0x48(%RBP),%RCX |
0x437fba VMOVSD -0x8(%RAX,%RCX,8),%XMM0 |
0x437fc0 MOV 0xd0(%RBP),%RAX |
0x437fc7 VUCOMISD (%RAX,%RDI,8),%XMM0 |
0x437fcc JBE 437f00 |
0x437fd2 MOV 0xc8(%RBP),%RAX |
0x437fd9 MOV -0x158(%RBP),%RCX |
0x437fe0 VMOVSD (%RAX,%RCX,8),%XMM0 |
0x437fe5 MOV 0x58(%RBP),%RAX |
0x437fe9 MOV -0x48(%RBP),%RCX |
0x437fed VUCOMISD -0x8(%RAX,%RCX,8),%XMM0 |
0x437ff3 JB 437f00 |
0x437ff9 MOV 0x50(%RBP),%RAX |
0x437ffd MOV -0x48(%RBP),%RCX |
0x438001 VMOVSD -0x8(%RAX,%RCX,8),%XMM0 |
0x438007 MOV 0xc8(%RBP),%RAX |
0x43800e MOV -0x60(%RBP),%RCX |
0x438012 VUCOMISD (%RAX,%RCX,8),%XMM0 |
0x438017 JBE 437f00 |
0x43801d MOV %RDI,%R10 |
0x438020 MOV 0xf8(%RBP),%RAX |
0x438027 MOV (%RAX),%RAX |
0x43802a MOV -0x60(%RBP),%R8 |
0x43802e IMUL %R8,%RAX |
0x438032 ADD 0xa8(%RBP),%RAX |
0x438039 MOV 0x80(%RBP),%RCX |
0x438040 MOV -0x48(%RBP),%RDI |
0x438044 VMOVSD -0x8(%RCX,%RDI,8),%XMM0 |
0x43804a VMOVSD %XMM0,(%RAX,%R10,8) |
0x438050 MOV 0x108(%RBP),%RAX |
0x438057 MOV (%RAX),%RAX |
0x43805a IMUL %R8,%RAX |
0x43805e ADD 0xb0(%RBP),%RAX |
0x438065 MOV 0x88(%RBP),%RCX |
0x43806c VMOVSD -0x8(%RCX,%RDI,8),%XMM0 |
0x438072 VMOVSD %XMM0,(%RAX,%R10,8) |
0x438078 MOV 0x78(%RBP),%RAX |
0x43807c VMOVSD -0x8(%RAX,%RDI,8),%XMM0 |
0x438082 MOV 0x70(%RBP),%RAX |
0x438086 VMOVSD -0x8(%RAX,%RDI,8),%XMM1 |
0x43808c MOV 0x118(%RBP),%RAX |
0x438093 MOV (%RAX),%R10 |
0x438096 MOV 0x128(%RBP),%RAX |
0x43809d MOV (%RAX),%R11 |
0x4380a0 CMP %RSI,%R12 |
0x4380a3 CMOVLE %RSI,%R12 |
0x4380a7 SUB %RSI,%R12 |
0x4380aa LEA 0x1(%R12),%RDX |
0x4380af MOV %RDX,%RAX |
0x4380b2 AND $-0x8,%RAX |
0x4380b6 MOV %R12,-0x70(%RBP) |
0x4380ba SUB %RAX,%R12 |
0x4380bd MOV %RAX,-0x68(%RBP) |
0x4380c1 ADD %RAX,%RSI |
0x4380c4 SUB -0x50(%RBP),%RSI |
0x4380c8 LEA 0x6(%RSI),%RAX |
0x4380cc MOV %RAX,-0xd0(%RBP) |
0x4380d3 MOV -0xc8(%RBP),%RCX |
0x4380da MOV %RCX,%RBX |
0x4380dd IMUL %R11,%RBX |
0x4380e1 MOV -0xc0(%RBP),%RAX |
0x4380e8 ADD %R9,%RAX |
0x4380eb ADD %RAX,%RBX |
0x4380ee MOV %RCX,%RAX |
0x4380f1 IMUL %R10,%RAX |
0x4380f5 ADD -0xb8(%RBP),%R9 |
0x4380fc ADD %RAX,%R9 |
0x4380ff XOR %EAX,%EAX |
0x438101 JMP 43850b |
0x438110 MOV 0x30(%RBP),%RAX |
0x438114 CMP (%RAX),%EDI |
0x438116 JNE 438680 |
0x43811c MOV %R10,%RAX |
0x43811f SUB -0x50(%RBP),%RAX |
0x438123 MOV 0xc0(%RBP),%RCX |
0x43812a VMOVSD (%RCX,%RAX,8),%XMM0 |
0x43812f VSUBSD %XMM2,%XMM0,%XMM0 |
0x438133 VMULSD %XMM0,%XMM0,%XMM0 |
0x438137 MOV 0xb8(%RBP),%RCX |
0x43813e MOV -0x60(%RBP),%RDI |
0x438142 VMOVSD (%RCX,%RDI,8),%XMM1 |
0x438147 VSUBSD %XMM3,%XMM1,%XMM1 |
0x43814b VFMADD213SD %XMM0,%XMM1,%XMM1 |
0x438150 VSQRTSD %XMM1,%XMM1,%XMM0 |
0x438154 MOV 0x48(%RBP),%RCX |
0x438158 MOV -0x48(%RBP),%RDI |
0x43815c VMOVSD -0x8(%RCX,%RDI,8),%XMM1 |
0x438162 VUCOMISD %XMM0,%XMM1 |
0x438166 JB 437f00 |
0x43816c MOV %R10,%R11 |
0x43816f MOV 0xf8(%RBP),%RCX |
0x438176 MOV (%RCX),%RCX |
0x438179 MOV -0x60(%RBP),%R10 |
0x43817d IMUL %R10,%RCX |
0x438181 ADD 0xa8(%RBP),%RCX |
0x438188 MOV 0x80(%RBP),%RDI |
0x43818f MOV -0x48(%RBP),%R8 |
0x438193 VMOVSD -0x8(%RDI,%R8,8),%XMM0 |
0x43819a VMOVSD %XMM0,(%RCX,%RAX,8) |
0x43819f MOV 0x108(%RBP),%RCX |
0x4381a6 MOV (%RCX),%RCX |
0x4381a9 IMUL %R10,%RCX |
0x4381ad ADD 0xb0(%RBP),%RCX |
0x4381b4 MOV 0x88(%RBP),%RDI |
0x4381bb VMOVSD -0x8(%RDI,%R8,8),%XMM0 |
0x4381c2 VMOVSD %XMM0,(%RCX,%RAX,8) |
0x4381c7 MOV 0x78(%RBP),%RAX |
0x4381cb VMOVSD -0x8(%RAX,%R8,8),%XMM0 |
0x4381d2 MOV 0x118(%RBP),%RAX |
0x4381d9 MOV (%RAX),%RDI |
0x4381dc MOV 0x70(%RBP),%RAX |
0x4381e0 VMOVSD -0x8(%RAX,%R8,8),%XMM1 |
0x4381e7 MOV 0x128(%RBP),%RAX |
0x4381ee MOV (%RAX),%R10 |
0x4381f1 MOV %R11,%RAX |
0x4381f4 INC %RAX |
0x4381f7 CMP %RSI,%RAX |
0x4381fa CMOVLE %RSI,%RAX |
0x4381fe SUB %RSI,%RAX |
0x438201 LEA 0x1(%RAX),%RDX |
0x438205 MOV %RDX,%RCX |
0x438208 AND $-0x8,%RCX |
0x43820c MOV %RAX,-0x70(%RBP) |
0x438210 SUB %RCX,%RAX |
0x438213 MOV %RCX,-0x68(%RBP) |
0x438217 ADD %RCX,%RSI |
0x43821a SUB -0x50(%RBP),%RSI |
0x43821e LEA 0x6(%RSI),%RCX |
0x438222 MOV %RCX,-0xd0(%RBP) |
0x438229 MOV -0xc8(%RBP),%R8 |
0x438230 MOV %R8,%RBX |
0x438233 IMUL %R10,%RBX |
0x438237 MOV -0xc0(%RBP),%RCX |
0x43823e ADD %R9,%RCX |
0x438241 ADD %RCX,%RBX |
0x438244 MOV %R8,%RCX |
0x438247 IMUL %RDI,%RCX |
0x43824b ADD -0xb8(%RBP),%R9 |
0x438252 ADD %RCX,%R9 |
0x438255 XOR %R8D,%R8D |
0x438258 MOV -0xd0(%RBP),%R15 |
0x43825f JMP 438310 |
(286) 0x438264 MOV -0x38(%RBP),%RCX |
(286) 0x438268 ADD %R8,%RCX |
(286) 0x43826b SUB -0x30(%RBP),%RCX |
(286) 0x43826f MOV %RDI,%R12 |
(286) 0x438272 IMUL %RCX,%R12 |
(286) 0x438276 IMUL %R10,%RCX |
(286) 0x43827a LEA (%R14,%R12,1),%R11 |
(286) 0x43827e VMOVSD %XMM0,0x28(%R11,%RSI,8) |
(286) 0x438285 LEA (%RCX,%R13,1),%R11 |
(286) 0x438289 VMOVSD %XMM1,0x28(%R11,%RSI,8) |
(286) 0x438290 LEA (%R14,%R12,1),%R11 |
(286) 0x438294 VMOVSD %XMM0,0x20(%R11,%RSI,8) |
(286) 0x43829b LEA (%RCX,%R13,1),%R11 |
(286) 0x43829f VMOVSD %XMM1,0x20(%R11,%RSI,8) |
(286) 0x4382a6 LEA (%R14,%R12,1),%R11 |
(286) 0x4382aa VMOVSD %XMM0,0x18(%R11,%RSI,8) |
(286) 0x4382b1 LEA (%RCX,%R13,1),%R11 |
(286) 0x4382b5 VMOVSD %XMM1,0x18(%R11,%RSI,8) |
(286) 0x4382bc LEA (%R14,%R12,1),%R11 |
(286) 0x4382c0 VMOVSD %XMM0,0x10(%R11,%RSI,8) |
(286) 0x4382c7 LEA (%RCX,%R13,1),%R11 |
(286) 0x4382cb VMOVSD %XMM1,0x10(%R11,%RSI,8) |
(286) 0x4382d2 LEA (%R14,%R12,1),%R11 |
(286) 0x4382d6 VMOVSD %XMM0,0x8(%R11,%RSI,8) |
(286) 0x4382dd LEA (%RCX,%R13,1),%R11 |
(286) 0x4382e1 VMOVSD %XMM1,0x8(%R11,%RSI,8) |
(286) 0x4382e8 ADD %R14,%R12 |
(286) 0x4382eb VMOVSD %XMM0,(%R12,%RSI,8) |
(286) 0x4382f1 ADD %R13,%RCX |
(286) 0x4382f4 VMOVSD %XMM1,(%RCX,%RSI,8) |
(286) 0x4382f9 LEA 0x1(%R8),%RCX |
(286) 0x4382fd ADD %R10,%RBX |
(286) 0x438300 ADD %RDI,%R9 |
(286) 0x438303 CMP $0x1,%R8 |
(286) 0x438307 MOV %RCX,%R8 |
(286) 0x43830a JE 437f00 |
(286) 0x438310 CMP $0x8,%RDX |
(286) 0x438314 JB 43838f |
(286) 0x438316 MOV $0x48,%ECX |
(286) 0x43831b MOV -0x78(%RBP),%R12 |
(286) 0x43831f NOP |
(287) 0x438320 VMOVSD %XMM0,-0x38(%R9,%RCX,1) |
(287) 0x438327 VMOVSD %XMM1,-0x38(%RBX,%RCX,1) |
(287) 0x43832d VMOVSD %XMM0,-0x30(%R9,%RCX,1) |
(287) 0x438334 VMOVSD %XMM1,-0x30(%RBX,%RCX,1) |
(287) 0x43833a VMOVSD %XMM0,-0x28(%R9,%RCX,1) |
(287) 0x438341 VMOVSD %XMM1,-0x28(%RBX,%RCX,1) |
(287) 0x438347 VMOVSD %XMM0,-0x20(%R9,%RCX,1) |
(287) 0x43834e VMOVSD %XMM1,-0x20(%RBX,%RCX,1) |
(287) 0x438354 VMOVSD %XMM0,-0x18(%R9,%RCX,1) |
(287) 0x43835b VMOVSD %XMM1,-0x18(%RBX,%RCX,1) |
(287) 0x438361 VMOVSD %XMM0,-0x10(%R9,%RCX,1) |
(287) 0x438368 VMOVSD %XMM1,-0x10(%RBX,%RCX,1) |
(287) 0x43836e VMOVSD %XMM0,-0x8(%R9,%RCX,1) |
(287) 0x438375 VMOVSD %XMM1,-0x8(%RBX,%RCX,1) |
(287) 0x43837b VMOVSD %XMM0,(%R9,%RCX,1) |
(287) 0x438381 VMOVSD %XMM1,(%RBX,%RCX,1) |
(287) 0x438386 ADD $0x40,%RCX |
(287) 0x43838a INC %R12 |
(287) 0x43838d JNE 438320 |
(286) 0x43838f CMP $0x3,%RAX |
(286) 0x438393 JGE 4383d0 |
(286) 0x438395 TEST %RAX,%RAX |
(286) 0x438398 JLE 43843f |
(286) 0x43839e MOV -0x38(%RBP),%RCX |
(286) 0x4383a2 ADD %R8,%RCX |
(286) 0x4383a5 SUB -0x30(%RBP),%RCX |
(286) 0x4383a9 MOV %RDI,%R12 |
(286) 0x4383ac IMUL %RCX,%R12 |
(286) 0x4383b0 IMUL %R10,%RCX |
(286) 0x4383b4 CMP $0x1,%RAX |
(286) 0x4383b8 JNE 4382bc |
(286) 0x4383be JMP 4382d2 |
(286) 0x4383d0 CMP $0x5,%RAX |
(286) 0x4383d4 JGE 438400 |
(286) 0x4383d6 MOV -0x38(%RBP),%RCX |
(286) 0x4383da ADD %R8,%RCX |
(286) 0x4383dd SUB -0x30(%RBP),%RCX |
(286) 0x4383e1 MOV %RDI,%R12 |
(286) 0x4383e4 IMUL %RCX,%R12 |
(286) 0x4383e8 IMUL %R10,%RCX |
(286) 0x4383ec CMP $0x4,%RAX |
(286) 0x4383f0 JE 438290 |
(286) 0x4383f6 JMP 4382a6 |
(286) 0x438400 JE 438264 |
(286) 0x438406 CMP $0x6,%RAX |
(286) 0x43840a JNE 4382f9 |
(286) 0x438410 MOV -0x38(%RBP),%RCX |
(286) 0x438414 ADD %R8,%RCX |
(286) 0x438417 SUB -0x30(%RBP),%RCX |
(286) 0x43841b MOV %RDI,%R12 |
(286) 0x43841e IMUL %RCX,%R12 |
(286) 0x438422 LEA (%R14,%R12,1),%R11 |
(286) 0x438426 VMOVSD %XMM0,(%R11,%R15,8) |
(286) 0x43842c IMUL %R10,%RCX |
(286) 0x438430 LEA (%RCX,%R13,1),%R11 |
(286) 0x438434 VMOVSD %XMM1,(%R11,%R15,8) |
(286) 0x43843a JMP 43827a |
(286) 0x43843f MOV -0x68(%RBP),%RCX |
(286) 0x438443 CMP %RCX,-0x70(%RBP) |
(286) 0x438447 JNE 4382f9 |
(286) 0x43844d MOV -0x38(%RBP),%RCX |
(286) 0x438451 ADD %R8,%RCX |
(286) 0x438454 SUB -0x30(%RBP),%RCX |
(286) 0x438458 MOV %RDI,%R12 |
(286) 0x43845b IMUL %RCX,%R12 |
(286) 0x43845f IMUL %R10,%RCX |
(286) 0x438463 JMP 4382e8 |
(288) 0x438468 MOV -0x38(%RBP),%RCX |
(288) 0x43846c LEA (%RAX,%RCX,1),%R8 |
(288) 0x438470 SUB -0x30(%RBP),%R8 |
(288) 0x438474 MOV %R10,%RCX |
(288) 0x438477 IMUL %R8,%RCX |
(288) 0x43847b IMUL %R11,%R8 |
(288) 0x43847f LEA (%R14,%RCX,1),%RDI |
(288) 0x438483 VMOVSD %XMM0,0x28(%RDI,%RSI,8) |
(288) 0x438489 LEA (%R8,%R13,1),%RDI |
(288) 0x43848d VMOVSD %XMM1,0x28(%RDI,%RSI,8) |
(288) 0x438493 LEA (%R14,%RCX,1),%RDI |
(288) 0x438497 VMOVSD %XMM0,0x20(%RDI,%RSI,8) |
(288) 0x43849d LEA (%R8,%R13,1),%RDI |
(288) 0x4384a1 VMOVSD %XMM1,0x20(%RDI,%RSI,8) |
(288) 0x4384a7 LEA (%R14,%RCX,1),%RDI |
(288) 0x4384ab VMOVSD %XMM0,0x18(%RDI,%RSI,8) |
(288) 0x4384b1 LEA (%R8,%R13,1),%RDI |
(288) 0x4384b5 VMOVSD %XMM1,0x18(%RDI,%RSI,8) |
(288) 0x4384bb LEA (%R14,%RCX,1),%RDI |
(288) 0x4384bf VMOVSD %XMM0,0x10(%RDI,%RSI,8) |
(288) 0x4384c5 LEA (%R8,%R13,1),%RDI |
(288) 0x4384c9 VMOVSD %XMM1,0x10(%RDI,%RSI,8) |
(288) 0x4384cf LEA (%R14,%RCX,1),%RDI |
(288) 0x4384d3 VMOVSD %XMM0,0x8(%RDI,%RSI,8) |
(288) 0x4384d9 LEA (%R8,%R13,1),%RDI |
(288) 0x4384dd VMOVSD %XMM1,0x8(%RDI,%RSI,8) |
(288) 0x4384e3 ADD %R14,%RCX |
(288) 0x4384e6 VMOVSD %XMM0,(%RCX,%RSI,8) |
(288) 0x4384eb ADD %R13,%R8 |
(288) 0x4384ee VMOVSD %XMM1,(%R8,%RSI,8) |
(288) 0x4384f4 LEA 0x1(%RAX),%RCX |
(288) 0x4384f8 ADD %R11,%RBX |
(288) 0x4384fb ADD %R10,%R9 |
(288) 0x4384fe CMP $0x1,%RAX |
(288) 0x438502 MOV %RCX,%RAX |
(288) 0x438505 JE 437f00 |
(288) 0x43850b CMP $0x8,%RDX |
(288) 0x43850f JB 43858f |
(288) 0x438515 MOV $0x48,%ECX |
(288) 0x43851a MOV -0x78(%RBP),%RDI |
(288) 0x43851e XCHG %AX,%AX |
(289) 0x438520 VMOVSD %XMM0,-0x38(%R9,%RCX,1) |
(289) 0x438527 VMOVSD %XMM1,-0x38(%RBX,%RCX,1) |
(289) 0x43852d VMOVSD %XMM0,-0x30(%R9,%RCX,1) |
(289) 0x438534 VMOVSD %XMM1,-0x30(%RBX,%RCX,1) |
(289) 0x43853a VMOVSD %XMM0,-0x28(%R9,%RCX,1) |
(289) 0x438541 VMOVSD %XMM1,-0x28(%RBX,%RCX,1) |
(289) 0x438547 VMOVSD %XMM0,-0x20(%R9,%RCX,1) |
(289) 0x43854e VMOVSD %XMM1,-0x20(%RBX,%RCX,1) |
(289) 0x438554 VMOVSD %XMM0,-0x18(%R9,%RCX,1) |
(289) 0x43855b VMOVSD %XMM1,-0x18(%RBX,%RCX,1) |
(289) 0x438561 VMOVSD %XMM0,-0x10(%R9,%RCX,1) |
(289) 0x438568 VMOVSD %XMM1,-0x10(%RBX,%RCX,1) |
(289) 0x43856e VMOVSD %XMM0,-0x8(%R9,%RCX,1) |
(289) 0x438575 VMOVSD %XMM1,-0x8(%RBX,%RCX,1) |
(289) 0x43857b VMOVSD %XMM0,(%R9,%RCX,1) |
(289) 0x438581 VMOVSD %XMM1,(%RBX,%RCX,1) |
(289) 0x438586 ADD $0x40,%RCX |
(289) 0x43858a INC %RDI |
(289) 0x43858d JNE 438520 |
(288) 0x43858f CMP $0x3,%R12 |
(288) 0x438593 JGE 4385d0 |
(288) 0x438595 TEST %R12,%R12 |
(288) 0x438598 JLE 43864d |
(288) 0x43859e MOV -0x38(%RBP),%RCX |
(288) 0x4385a2 LEA (%RAX,%RCX,1),%R8 |
(288) 0x4385a6 SUB -0x30(%RBP),%R8 |
(288) 0x4385aa MOV %R10,%RCX |
(288) 0x4385ad IMUL %R8,%RCX |
(288) 0x4385b1 IMUL %R11,%R8 |
(288) 0x4385b5 CMP $0x1,%R12 |
(288) 0x4385b9 JNE 4384bb |
(288) 0x4385bf JMP 4384cf |
(288) 0x4385d0 CMP $0x5,%R12 |
(288) 0x4385d4 JGE 438600 |
(288) 0x4385d6 MOV -0x38(%RBP),%RCX |
(288) 0x4385da LEA (%RAX,%RCX,1),%R8 |
(288) 0x4385de SUB -0x30(%RBP),%R8 |
(288) 0x4385e2 MOV %R10,%RCX |
(288) 0x4385e5 IMUL %R8,%RCX |
(288) 0x4385e9 IMUL %R11,%R8 |
(288) 0x4385ed CMP $0x4,%R12 |
(288) 0x4385f1 JE 438493 |
(288) 0x4385f7 JMP 4384a7 |
(288) 0x438600 JE 438468 |
(288) 0x438606 CMP $0x6,%R12 |
(288) 0x43860a JNE 4384f4 |
(288) 0x438610 MOV -0x38(%RBP),%RCX |
(288) 0x438614 LEA (%RAX,%RCX,1),%R8 |
(288) 0x438618 SUB -0x30(%RBP),%R8 |
(288) 0x43861c MOV %R10,%RCX |
(288) 0x43861f IMUL %R8,%RCX |
(288) 0x438623 LEA (%R14,%RCX,1),%RDI |
(288) 0x438627 MOV %R14,%R15 |
(288) 0x43862a MOV -0xd0(%RBP),%R14 |
(288) 0x438631 VMOVSD %XMM0,(%RDI,%R14,8) |
(288) 0x438637 IMUL %R11,%R8 |
(288) 0x43863b LEA (%R8,%R13,1),%RDI |
(288) 0x43863f VMOVSD %XMM1,(%RDI,%R14,8) |
(288) 0x438645 MOV %R15,%R14 |
(288) 0x438648 JMP 43847f |
(288) 0x43864d MOV -0x68(%RBP),%RCX |
(288) 0x438651 CMP %RCX,-0x70(%RBP) |
(288) 0x438655 JNE 4384f4 |
(288) 0x43865b MOV -0x38(%RBP),%RCX |
(288) 0x43865f LEA (%RAX,%RCX,1),%R8 |
(288) 0x438663 SUB -0x30(%RBP),%R8 |
(288) 0x438667 MOV %R10,%RCX |
(288) 0x43866a IMUL %R8,%RCX |
(288) 0x43866e IMUL %R11,%R8 |
(288) 0x438672 JMP 4384e3 |
0x438680 MOV 0x28(%RBP),%RAX |
0x438684 CMP (%RAX),%EDI |
0x438686 JNE 437f00 |
0x43868c MOV %R10,%R11 |
0x43868f MOV %R10,%RAX |
0x438692 SUB -0x50(%RBP),%RAX |
0x438696 MOV 0xd0(%RBP),%RCX |
0x43869d VMOVSD (%RCX,%RAX,8),%XMM0 |
0x4386a2 VUCOMISD %XMM2,%XMM0 |
0x4386a6 JNE 437f00 |
0x4386ac JP 437f00 |
0x4386b2 MOV 0xc8(%RBP),%RCX |
0x4386b9 MOV -0x60(%RBP),%RDI |
0x4386bd VMOVSD (%RCX,%RDI,8),%XMM0 |
0x4386c2 VUCOMISD %XMM3,%XMM0 |
0x4386c6 JNE 437f00 |
0x4386cc JP 437f00 |
0x4386d2 MOV 0xf8(%RBP),%RCX |
0x4386d9 MOV (%RCX),%RCX |
0x4386dc MOV -0x60(%RBP),%R10 |
0x4386e0 IMUL %R10,%RCX |
0x4386e4 ADD 0xa8(%RBP),%RCX |
0x4386eb MOV 0x80(%RBP),%RDI |
0x4386f2 MOV -0x48(%RBP),%R8 |
0x4386f6 VMOVSD -0x8(%RDI,%R8,8),%XMM0 |
0x4386fd VMOVSD %XMM0,(%RCX,%RAX,8) |
0x438702 MOV 0x108(%RBP),%RCX |
0x438709 MOV (%RCX),%RCX |
0x43870c IMUL %R10,%RCX |
0x438710 ADD 0xb0(%RBP),%RCX |
0x438717 MOV 0x88(%RBP),%RDI |
0x43871e VMOVSD -0x8(%RDI,%R8,8),%XMM0 |
0x438725 VMOVSD %XMM0,(%RCX,%RAX,8) |
0x43872a MOV 0x78(%RBP),%RAX |
0x43872e VMOVSD -0x8(%RAX,%R8,8),%XMM0 |
0x438735 MOV 0x118(%RBP),%RAX |
0x43873c MOV (%RAX),%R12 |
0x43873f MOV 0x70(%RBP),%RAX |
0x438743 VMOVSD -0x8(%RAX,%R8,8),%XMM1 |
0x43874a MOV 0x128(%RBP),%RAX |
0x438751 MOV (%RAX),%R10 |
0x438754 MOV %R11,%RAX |
0x438757 INC %RAX |
0x43875a CMP %RSI,%RAX |
0x43875d CMOVLE %RSI,%RAX |
0x438761 SUB %RSI,%RAX |
0x438764 LEA 0x1(%RAX),%R15 |
0x438768 MOV %R15,%RCX |
0x43876b AND $-0x8,%RCX |
0x43876f MOV %RAX,-0x70(%RBP) |
0x438773 SUB %RCX,%RAX |
0x438776 MOV %RCX,-0x68(%RBP) |
0x43877a ADD %RCX,%RSI |
0x43877d SUB -0x50(%RBP),%RSI |
0x438781 LEA 0x6(%RSI),%RDX |
0x438785 MOV -0xc8(%RBP),%RDI |
0x43878c MOV %RDI,%RBX |
0x43878f IMUL %R10,%RBX |
0x438793 MOV -0xc0(%RBP),%RCX |
0x43879a ADD %R9,%RCX |
0x43879d ADD %RCX,%RBX |
0x4387a0 MOV %RDI,%RCX |
0x4387a3 IMUL %R12,%RCX |
0x4387a7 ADD -0xb8(%RBP),%R9 |
0x4387ae ADD %RCX,%R9 |
0x4387b1 XOR %R8D,%R8D |
0x4387b4 JMP 438864 |
(284) 0x4387b9 MOV -0x38(%RBP),%RCX |
(284) 0x4387bd ADD %R8,%RCX |
(284) 0x4387c0 SUB -0x30(%RBP),%RCX |
(284) 0x4387c4 MOV %R12,%RDI |
(284) 0x4387c7 IMUL %RCX,%RDI |
(284) 0x4387cb IMUL %R10,%RCX |
(284) 0x4387cf LEA (%R14,%RDI,1),%R11 |
(284) 0x4387d3 VMOVSD %XMM0,0x28(%R11,%RSI,8) |
(284) 0x4387da LEA (%RCX,%R13,1),%R11 |
(284) 0x4387de VMOVSD %XMM1,0x28(%R11,%RSI,8) |
(284) 0x4387e5 LEA (%R14,%RDI,1),%R11 |
(284) 0x4387e9 VMOVSD %XMM0,0x20(%R11,%RSI,8) |
(284) 0x4387f0 LEA (%RCX,%R13,1),%R11 |
(284) 0x4387f4 VMOVSD %XMM1,0x20(%R11,%RSI,8) |
(284) 0x4387fb LEA (%R14,%RDI,1),%R11 |
(284) 0x4387ff VMOVSD %XMM0,0x18(%R11,%RSI,8) |
(284) 0x438806 LEA (%RCX,%R13,1),%R11 |
(284) 0x43880a VMOVSD %XMM1,0x18(%R11,%RSI,8) |
(284) 0x438811 LEA (%R14,%RDI,1),%R11 |
(284) 0x438815 VMOVSD %XMM0,0x10(%R11,%RSI,8) |
(284) 0x43881c LEA (%RCX,%R13,1),%R11 |
(284) 0x438820 VMOVSD %XMM1,0x10(%R11,%RSI,8) |
(284) 0x438827 LEA (%R14,%RDI,1),%R11 |
(284) 0x43882b VMOVSD %XMM0,0x8(%R11,%RSI,8) |
(284) 0x438832 LEA (%RCX,%R13,1),%R11 |
(284) 0x438836 VMOVSD %XMM1,0x8(%R11,%RSI,8) |
(284) 0x43883d ADD %R14,%RDI |
(284) 0x438840 VMOVSD %XMM0,(%RDI,%RSI,8) |
(284) 0x438845 ADD %R13,%RCX |
(284) 0x438848 VMOVSD %XMM1,(%RCX,%RSI,8) |
(284) 0x43884d LEA 0x1(%R8),%RCX |
(284) 0x438851 ADD %R10,%RBX |
(284) 0x438854 ADD %R12,%R9 |
(284) 0x438857 CMP $0x1,%R8 |
(284) 0x43885b MOV %RCX,%R8 |
(284) 0x43885e JE 437f00 |
(284) 0x438864 CMP $0x8,%R15 |
(284) 0x438868 JB 4388ef |
(284) 0x43886e MOV $0x48,%ECX |
(284) 0x438873 MOV -0x78(%RBP),%RDI |
(284) 0x438877 NOPW (%RAX,%RAX,1) |
(285) 0x438880 VMOVSD %XMM0,-0x38(%R9,%RCX,1) |
(285) 0x438887 VMOVSD %XMM1,-0x38(%RBX,%RCX,1) |
(285) 0x43888d VMOVSD %XMM0,-0x30(%R9,%RCX,1) |
(285) 0x438894 VMOVSD %XMM1,-0x30(%RBX,%RCX,1) |
(285) 0x43889a VMOVSD %XMM0,-0x28(%R9,%RCX,1) |
(285) 0x4388a1 VMOVSD %XMM1,-0x28(%RBX,%RCX,1) |
(285) 0x4388a7 VMOVSD %XMM0,-0x20(%R9,%RCX,1) |
(285) 0x4388ae VMOVSD %XMM1,-0x20(%RBX,%RCX,1) |
(285) 0x4388b4 VMOVSD %XMM0,-0x18(%R9,%RCX,1) |
(285) 0x4388bb VMOVSD %XMM1,-0x18(%RBX,%RCX,1) |
(285) 0x4388c1 VMOVSD %XMM0,-0x10(%R9,%RCX,1) |
(285) 0x4388c8 VMOVSD %XMM1,-0x10(%RBX,%RCX,1) |
(285) 0x4388ce VMOVSD %XMM0,-0x8(%R9,%RCX,1) |
(285) 0x4388d5 VMOVSD %XMM1,-0x8(%RBX,%RCX,1) |
(285) 0x4388db VMOVSD %XMM0,(%R9,%RCX,1) |
(285) 0x4388e1 VMOVSD %XMM1,(%RBX,%RCX,1) |
(285) 0x4388e6 ADD $0x40,%RCX |
(285) 0x4388ea INC %RDI |
(285) 0x4388ed JNE 438880 |
(284) 0x4388ef CMP $0x3,%RAX |
(284) 0x4388f3 JGE 438930 |
(284) 0x4388f5 TEST %RAX,%RAX |
(284) 0x4388f8 JLE 43899f |
(284) 0x4388fe MOV -0x38(%RBP),%RCX |
(284) 0x438902 ADD %R8,%RCX |
(284) 0x438905 SUB -0x30(%RBP),%RCX |
(284) 0x438909 MOV %R12,%RDI |
(284) 0x43890c IMUL %RCX,%RDI |
(284) 0x438910 IMUL %R10,%RCX |
(284) 0x438914 CMP $0x1,%RAX |
(284) 0x438918 JNE 438811 |
(284) 0x43891e JMP 438827 |
(284) 0x438930 CMP $0x5,%RAX |
(284) 0x438934 JGE 438960 |
(284) 0x438936 MOV -0x38(%RBP),%RCX |
(284) 0x43893a ADD %R8,%RCX |
(284) 0x43893d SUB -0x30(%RBP),%RCX |
(284) 0x438941 MOV %R12,%RDI |
(284) 0x438944 IMUL %RCX,%RDI |
(284) 0x438948 IMUL %R10,%RCX |
(284) 0x43894c CMP $0x4,%RAX |
(284) 0x438950 JE 4387e5 |
(284) 0x438956 JMP 4387fb |
(284) 0x438960 JE 4387b9 |
(284) 0x438966 CMP $0x6,%RAX |
(284) 0x43896a JNE 43884d |
(284) 0x438970 MOV -0x38(%RBP),%RCX |
(284) 0x438974 ADD %R8,%RCX |
(284) 0x438977 SUB -0x30(%RBP),%RCX |
(284) 0x43897b MOV %R12,%RDI |
(284) 0x43897e IMUL %RCX,%RDI |
(284) 0x438982 LEA (%R14,%RDI,1),%R11 |
(284) 0x438986 VMOVSD %XMM0,(%R11,%RDX,8) |
(284) 0x43898c IMUL %R10,%RCX |
(284) 0x438990 LEA (%RCX,%R13,1),%R11 |
(284) 0x438994 VMOVSD %XMM1,(%R11,%RDX,8) |
(284) 0x43899a JMP 4387cf |
(284) 0x43899f MOV -0x68(%RBP),%RCX |
(284) 0x4389a3 CMP %RCX,-0x70(%RBP) |
(284) 0x4389a7 JNE 43884d |
(284) 0x4389ad MOV -0x38(%RBP),%RCX |
(284) 0x4389b1 ADD %R8,%RCX |
(284) 0x4389b4 SUB -0x30(%RBP),%RCX |
(284) 0x4389b8 MOV %R12,%RDI |
(284) 0x4389bb IMUL %RCX,%RDI |
(284) 0x4389bf IMUL %R10,%RCX |
(284) 0x4389c3 JMP 43883d |
/scratch_na/users/xoserete/qaas_runs/171-419-3245/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90: 87 - 163 |
-------------------------------------------------------------------------------- |
87: DO k=y_min-2,y_max+2 |
[...] |
128: DO j=x_min-2,x_max+2 |
129: IF(state_geometry(state).EQ.g_rect ) THEN |
130: IF(vertexx(j+1).GE.state_xmin(state).AND.vertexx(j).LT.state_xmax(state)) THEN |
131: IF(vertexy(k+1).GE.state_ymin(state).AND.vertexy(k).LT.state_ymax(state)) THEN |
132: energy0(j,k)=state_energy(state) |
133: density0(j,k)=state_density(state) |
134: DO kt=k,k+1 |
135: DO jt=j,j+1 |
136: xvel0(jt,kt)=state_xvel(state) |
137: yvel0(jt,kt)=state_yvel(state) |
138: ENDDO |
139: ENDDO |
140: ENDIF |
141: ENDIF |
142: ELSEIF(state_geometry(state).EQ.g_circ ) THEN |
143: radius=SQRT((cellx(j)-x_cent)*(cellx(j)-x_cent)+(celly(k)-y_cent)*(celly(k)-y_cent)) |
144: IF(radius.LE.state_radius(state))THEN |
145: energy0(j,k)=state_energy(state) |
146: density0(j,k)=state_density(state) |
147: DO kt=k,k+1 |
148: DO jt=j,j+1 |
149: xvel0(jt,kt)=state_xvel(state) |
150: yvel0(jt,kt)=state_yvel(state) |
151: ENDDO |
152: ENDDO |
153: ENDIF |
154: ELSEIF(state_geometry(state).EQ.g_point) THEN |
155: IF(vertexx(j).EQ.x_cent .AND. vertexy(k).EQ.y_cent) THEN |
156: energy0(j,k)=state_energy(state) |
157: density0(j,k)=state_density(state) |
158: DO kt=k,k+1 |
159: DO jt=j,j+1 |
160: xvel0(jt,kt)=state_xvel(state) |
161: yvel0(jt,kt)=state_yvel(state) |
162: ENDDO |
163: ENDDO |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_invoke_task_func | libiomp5.so |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.20 |
CQA speedup if FP arith vectorized | 2.79 |
CQA speedup if fully vectorized | 12.59 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.02 |
Bottlenecks | micro-operation queue, |
Function | generate_chunk_kernel_.DIR.OMP.PARALLEL.2 |
Source | generate_chunk_kernel.f90:87-87,generate_chunk_kernel.f90:128-133,generate_chunk_kernel.f90:136-137,generate_chunk_kernel.f90:142-146,generate_chunk_kernel.f90:149-150,generate_chunk_kernel.f90:154-157,generate_chunk_kernel.f90:160-161 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 41.83 |
CQA cycles if no scalar integer | 19.00 |
CQA cycles if FP arith vectorized | 15.01 |
CQA cycles if fully vectorized | 3.32 |
Front-end cycles | 41.83 |
DIV/SQRT cycles | 18.20 |
P0 cycles | 21.93 |
P1 cycles | 41.00 |
P2 cycles | 41.00 |
P3 cycles | 9.00 |
P4 cycles | 18.20 |
P5 cycles | 18.20 |
P6 cycles | 9.00 |
P7 cycles | 9.00 |
P8 cycles | 9.00 |
P9 cycles | 18.20 |
P10 cycles | 41.00 |
P11 cycles | 4.50 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 48.01 - 48.40 |
Stall cycles (UFS) | 5.89 - 6.22 |
Nb insns | 247.00 |
Nb uops | 251.00 |
Nb loads | 123.00 |
Nb stores | 18.00 |
Nb stack references | 39.00 |
FLOP/cycle | 0.14 |
Nb FLOP add-sub | 2.00 |
Nb FLOP mul | 1.00 |
Nb FLOP fma | 1.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 1.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 26.39 |
Bytes prefetched | 0.00 |
Bytes loaded | 964.00 |
Bytes stored | 140.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | 0.00 |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.18 |
Vector-efficiency ratio load | 11.90 |
Vector-efficiency ratio store | 12.15 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | 12.50 |
Vector-efficiency ratio div_sqrt | 12.50 |
Vector-efficiency ratio other | 11.72 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.20 |
CQA speedup if FP arith vectorized | 2.79 |
CQA speedup if fully vectorized | 12.59 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.02 |
Bottlenecks | micro-operation queue, |
Function | generate_chunk_kernel_.DIR.OMP.PARALLEL.2 |
Source | generate_chunk_kernel.f90:87-87,generate_chunk_kernel.f90:128-133,generate_chunk_kernel.f90:136-137,generate_chunk_kernel.f90:142-146,generate_chunk_kernel.f90:149-150,generate_chunk_kernel.f90:154-157,generate_chunk_kernel.f90:160-161 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 41.83 |
CQA cycles if no scalar integer | 19.00 |
CQA cycles if FP arith vectorized | 15.01 |
CQA cycles if fully vectorized | 3.32 |
Front-end cycles | 41.83 |
DIV/SQRT cycles | 18.20 |
P0 cycles | 21.93 |
P1 cycles | 41.00 |
P2 cycles | 41.00 |
P3 cycles | 9.00 |
P4 cycles | 18.20 |
P5 cycles | 18.20 |
P6 cycles | 9.00 |
P7 cycles | 9.00 |
P8 cycles | 9.00 |
P9 cycles | 18.20 |
P10 cycles | 41.00 |
P11 cycles | 4.50 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 48.01 - 48.40 |
Stall cycles (UFS) | 5.89 - 6.22 |
Nb insns | 247.00 |
Nb uops | 251.00 |
Nb loads | 123.00 |
Nb stores | 18.00 |
Nb stack references | 39.00 |
FLOP/cycle | 0.14 |
Nb FLOP add-sub | 2.00 |
Nb FLOP mul | 1.00 |
Nb FLOP fma | 1.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 1.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 26.39 |
Bytes prefetched | 0.00 |
Bytes loaded | 964.00 |
Bytes stored | 140.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | 0.00 |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.18 |
Vector-efficiency ratio load | 11.90 |
Vector-efficiency ratio store | 12.15 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | 12.50 |
Vector-efficiency ratio div_sqrt | 12.50 |
Vector-efficiency ratio other | 11.72 |
Path / |
Function | generate_chunk_kernel_.DIR.OMP.PARALLEL.2 |
Source file and lines | generate_chunk_kernel.f90:87-163 |
Module | exec |
nb instructions | 247 |
nb uops | 251 |
loop length | 1171 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 39 |
ADD-SUB / MUL ratio | 2.00 |
micro-operation queue | 41.83 cycles |
front end | 41.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 18.20 | 18.20 | 41.00 | 41.00 | 9.00 | 18.20 | 18.20 | 9.00 | 9.00 | 9.00 | 18.20 | 41.00 |
cycles | 18.20 | 21.93 | 41.00 | 41.00 | 9.00 | 18.20 | 18.20 | 9.00 | 9.00 | 9.00 | 18.20 | 41.00 |
Cycles executing div or sqrt instructions | 4.50 |
FE+BE cycles | 48.01-48.40 |
Stall cycles | 5.89-6.22 |
LM full (events) | 10.78-13.10 |
Front-end | 41.83 |
Dispatch | 41.00 |
DIV/SQRT | 4.50 |
Overall L1 | 41.83 |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
all | 11% |
load | 9% |
store | 11% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | 12% |
other | 12% |
all | 12% |
load | 11% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | 12% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0xf0(%RBP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x170(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x178(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP -0x168(%RBP),%R8 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV -0xec(%RBP),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 437e40 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x4e0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD %ECX,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
LEA (,%RSI,8),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RSI,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,-0x178(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMOVG %RAX,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB %RSI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
INC %RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
NEG %RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x160(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R8,%RAX,1),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP -0xe8(%RBP),%EDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %ECX,-0xf0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,-0x170(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JNE 438110 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x7b0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA 0x1(%R10),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB -0x50(%RBP),%RAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RCX,%RAX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD -0x8(%RAX,%RCX,8),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JB 437f00 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x5a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R10,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB -0x50(%RBP),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x60(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD (%RAX,%RDI,8),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE 437f00 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x5a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xc8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x158(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RAX,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD -0x8(%RAX,%RCX,8),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JB 437f00 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x5a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x60(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD (%RAX,%RCX,8),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE 437f00 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x5a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xf8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x60(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R8,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0xa8(%RBP),%RAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x80(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RCX,%RDI,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RAX,%R10,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x108(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R8,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0xb0(%RBP),%RAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x88(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RCX,%RDI,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RAX,%R10,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x78(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%RDI,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x70(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%RDI,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x118(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x128(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RSI,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVLE %RSI,%R12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB %RSI,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%R12),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R12,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %RAX,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB -0x50(%RBP),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA 0x6(%RSI),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0xd0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0xc8(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R11,%RBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV -0xc0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R9,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RAX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R10,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD -0xb8(%RBP),%R9 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
ADD %RAX,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43850b <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0xbab> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP (%RAX),%EDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 438680 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0xd20> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R10,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB -0x50(%RBP),%RAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RCX,%RAX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VSUBSD %XMM2,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULSD %XMM0,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV 0xb8(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x60(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RCX,%RDI,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VSUBSD %XMM3,%XMM1,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD213SD %XMM0,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VSQRTSD %XMM1,%XMM1,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-19 | 4.50 |
MOV 0x48(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RCX,%RDI,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD %XMM0,%XMM1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JB 437f00 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x5a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R10,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xf8(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x60(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R10,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0xa8(%RBP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x80(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RDI,%R8,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RCX,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x108(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R10,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0xb0(%RBP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x88(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RDI,%R8,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RCX,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x78(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%R8,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x118(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x70(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%R8,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x128(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVLE %RSI,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %RAX,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RCX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB -0x50(%RBP),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA 0x6(%RSI),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,-0xd0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0xc8(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R10,%RBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV -0xc0(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R9,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RCX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RDI,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD -0xb8(%RBP),%R9 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
ADD %RCX,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %R8D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0xd0(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 438310 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x9b0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0x28(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP (%RAX),%EDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 437f00 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x5a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R10,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB -0x50(%RBP),%RAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RCX,%RAX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD %XMM2,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JNE 437f00 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x5a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JP 437f00 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x5a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xc8(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x60(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RCX,%RDI,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD %XMM3,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JNE 437f00 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x5a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JP 437f00 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x5a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xf8(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x60(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R10,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0xa8(%RBP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x80(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RDI,%R8,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RCX,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x108(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R10,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0xb0(%RBP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x88(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RDI,%R8,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RCX,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x78(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%R8,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x118(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x70(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%R8,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x128(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVLE %RSI,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R15,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %RAX,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RCX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB -0x50(%RBP),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA 0x6(%RSI),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0xc8(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R10,%RBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV -0xc0(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R9,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RCX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R12,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD -0xb8(%RBP),%R9 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
ADD %RCX,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %R8D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 438864 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0xf04> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Function | generate_chunk_kernel_.DIR.OMP.PARALLEL.2 |
Source file and lines | generate_chunk_kernel.f90:87-163 |
Module | exec |
nb instructions | 247 |
nb uops | 251 |
loop length | 1171 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 39 |
ADD-SUB / MUL ratio | 2.00 |
micro-operation queue | 41.83 cycles |
front end | 41.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 18.20 | 18.20 | 41.00 | 41.00 | 9.00 | 18.20 | 18.20 | 9.00 | 9.00 | 9.00 | 18.20 | 41.00 |
cycles | 18.20 | 21.93 | 41.00 | 41.00 | 9.00 | 18.20 | 18.20 | 9.00 | 9.00 | 9.00 | 18.20 | 41.00 |
Cycles executing div or sqrt instructions | 4.50 |
FE+BE cycles | 48.01-48.40 |
Stall cycles | 5.89-6.22 |
LM full (events) | 10.78-13.10 |
Front-end | 41.83 |
Dispatch | 41.00 |
DIV/SQRT | 4.50 |
Overall L1 | 41.83 |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
all | 11% |
load | 9% |
store | 11% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | 12% |
other | 12% |
all | 12% |
load | 11% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | 12% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0xf0(%RBP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x170(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x178(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP -0x168(%RBP),%R8 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV -0xec(%RBP),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JE 437e40 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x4e0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD %ECX,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
LEA (,%RSI,8),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RSI,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,-0x178(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMOVG %RAX,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB %RSI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
INC %RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
NEG %RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x160(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R8,%RAX,1),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP -0xe8(%RBP),%EDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %ECX,-0xf0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,-0x170(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JNE 438110 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x7b0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA 0x1(%R10),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB -0x50(%RBP),%RAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RCX,%RAX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD -0x8(%RAX,%RCX,8),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JB 437f00 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x5a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R10,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB -0x50(%RBP),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x60(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD (%RAX,%RDI,8),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE 437f00 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x5a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xc8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x158(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RAX,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x58(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD -0x8(%RAX,%RCX,8),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JB 437f00 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x5a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x60(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD (%RAX,%RCX,8),%XMM0 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE 437f00 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x5a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDI,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xf8(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x60(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R8,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0xa8(%RBP),%RAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x80(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RCX,%RDI,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RAX,%R10,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x108(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R8,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0xb0(%RBP),%RAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x88(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RCX,%RDI,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RAX,%R10,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x78(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%RDI,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x70(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%RDI,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x118(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x128(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RSI,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVLE %RSI,%R12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB %RSI,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%R12),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %R12,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %RAX,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB -0x50(%RBP),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA 0x6(%RSI),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,-0xd0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0xc8(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R11,%RBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV -0xc0(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R9,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RAX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R10,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD -0xb8(%RBP),%R9 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
ADD %RAX,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 43850b <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0xbab> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP (%RAX),%EDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 438680 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0xd20> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R10,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB -0x50(%RBP),%RAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RCX,%RAX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VSUBSD %XMM2,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULSD %XMM0,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV 0xb8(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x60(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RCX,%RDI,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VSUBSD %XMM3,%XMM1,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD213SD %XMM0,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VSQRTSD %XMM1,%XMM1,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-19 | 4.50 |
MOV 0x48(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RCX,%RDI,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD %XMM0,%XMM1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JB 437f00 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x5a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R10,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xf8(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x60(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R10,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0xa8(%RBP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x80(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RDI,%R8,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RCX,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x108(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R10,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0xb0(%RBP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x88(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RDI,%R8,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RCX,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x78(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%R8,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x118(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x70(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%R8,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x128(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVLE %RSI,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RDX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %RAX,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RCX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB -0x50(%RBP),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA 0x6(%RSI),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,-0xd0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0xc8(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R10,%RBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV -0xc0(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R9,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RCX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RDI,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD -0xb8(%RBP),%R9 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
ADD %RCX,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %R8D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0xd0(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 438310 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x9b0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0x28(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP (%RAX),%EDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 437f00 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x5a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R10,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB -0x50(%RBP),%RAX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RCX,%RAX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD %XMM2,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JNE 437f00 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x5a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JP 437f00 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x5a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xc8(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x60(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RCX,%RDI,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VUCOMISD %XMM3,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JNE 437f00 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x5a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JP 437f00 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0x5a0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xf8(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x60(%RBP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R10,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0xa8(%RBP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x80(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x48(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RDI,%R8,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RCX,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x108(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %R10,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD 0xb0(%RBP),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV 0x88(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RDI,%R8,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%RCX,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x78(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%R8,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x118(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x70(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x8(%RAX,%R8,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x128(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVLE %RSI,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x1(%RAX),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R15,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %RAX,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RCX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB -0x50(%RBP),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
LEA 0x6(%RSI),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0xc8(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R10,%RBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV -0xc0(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R9,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RCX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %R12,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD -0xb8(%RBP),%R9 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
ADD %RCX,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %R8D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 438864 <generate_chunk_kernel_module_mp_generate_chunk_kernel_.DIR.OMP.PARALLEL.2+0xf04> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |