Loop Id: 99 | Module: exec | Source: ljForce.c:191-216 [...] | Coverage: 55.21% |
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Loop Id: 99 | Module: exec | Source: ljForce.c:191-216 [...] | Coverage: 55.21% |
---|
0x409208 ADD X26, X26, #1 |
0x40920c ADD X7, X7, #24 |
0x409210 CMP X26, X2 |
0x409214 B.GE 4091e8 |
0x409218 LDR Q6, [X5] [1] |
0x40921c LDUR Q7, [X7, #496] [2] |
0x409220 MOVI D16, #0 |
0x409224 LDR D17, [X7] [2] |
0x409228 FSUB V6.2D, V6.2D, V7.2D |
0x40922c FMLA D16, D6, V6.D[0] |
0x409230 MOV D7, V6.D[1] |
0x409234 FMLA D16, D7, V6.D[1] |
0x409238 LDR D7, [X6] [9] |
0x40923c FSUB D7, D7, S17 |
0x409240 LDR D17, [X23] [8] |
0x409244 FMADD D16, D7, D7, D16 |
0x409248 FCMP D16, #0 |
0x40924c FCCMP D16, D17, #2, #12 |
0x409250 B.HI 409208 |
0x409254 FDIV D16, D0, D16 |
0x409258 LDR D17, [X22] [7] |
0x40925c LDR D19, [X21] [5] |
0x409260 LDR X27, [X18, #48] [11] |
0x409264 FMUL D18, D16, D16 |
0x409268 FMUL D18, D16, D18 |
0x40926c FMUL D17, D18, D17 |
0x409270 FADD D18, D17, D1 |
0x409274 FNMSUB D18, D17, D18, D19 |
0x409278 LDR D19, [X27, X4,LSL #3] [6] |
0x40927c FMADD D19, D18, D2, D19 |
0x409280 STR D19, [X27, X4,LSL #3] [6] |
0x409284 LDR D19, [SP, #16] [4] |
0x409288 LDR X27, [X18, #40] [11] |
0x40928c MADD X27, X4, X13, X27 |
0x409290 FMADD D18, D18, D2, D19 |
0x409294 STR D18, [SP, #16] [4] |
0x409298 LDR D18, [X9] [3] |
0x40929c FMUL D18, D18, D3 |
0x4092a0 FMUL D18, D17, D18 |
0x4092a4 FMADD D17, D17, D5, D4 |
0x4092a8 FMUL D16, D16, D18 |
0x4092ac FMUL D16, D17, D16 |
0x4092b0 LDR Q17, [X27] [10] |
0x4092b4 FMLS V17.2D, V6.2D, V16.D[0] |
0x4092b8 LDR D6, [X27, #16] [10] |
0x4092bc STR Q17, [X27] [10] |
0x4092c0 FMSUB D6, D7, D16, D6 |
0x4092c4 STR D6, [X27, #16] [10] |
0x4092c8 B 409208 |
/home/hbollore/qaas-runs/170-265-5545/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 191 - 216 |
-------------------------------------------------------------------------------- |
191: for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++) |
[...] |
197: dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m]; |
198: r2+=dr[m]*dr[m]; |
199: } |
200: |
201: if ( r2 <= rCut2 && r2 > 0.0) |
202: { |
203: |
204: // Important note: |
205: // from this point on r actually refers to 1.0/r |
206: r2 = 1.0/r2; |
207: real_t r6 = s6 * (r2*r2*r2); |
208: real_t eLocal = r6 * (r6 - 1.0) - eShift; |
209: s->atoms->U[iOff] += 0.5*eLocal; |
210: ePot += 0.5*eLocal; |
211: |
212: // different formulation to avoid sqrt computation |
213: real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0); |
214: for (int m=0; m<3; m++) |
215: { |
216: s->atoms->f[iOff][m] -= dr[m]*fr; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○100.00 | __kmp_invoke_microtask | libomp.so |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.28 |
CQA speedup if FP arith vectorized | 1.28 |
CQA speedup if fully vectorized | 3.57 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.12 |
Bottlenecks | |
Function | .omp_outlined..5#0x409080 |
Source | ljForce.c:191-191,ljForce.c:197-216 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 4.69 |
CQA cycles if no scalar integer | 3.67 |
CQA cycles if FP arith vectorized | 3.67 |
CQA cycles if fully vectorized | 1.31 |
Front-end cycles | 4.25 |
DIV/SQRT cycles | 1.25 |
P0 cycles | 1.25 |
P1 cycles | 0.88 |
P2 cycles | 0.88 |
P3 cycles | 0.88 |
P4 cycles | 0.88 |
P5 cycles | 4.63 |
P6 cycles | 4.63 |
P7 cycles | 4.63 |
P8 cycles | 4.63 |
P9 cycles | 3.83 |
P10 cycles | 3.83 |
P11 cycles | 3.83 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
P14 cycles | 0.50 - 0.25 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 34.00 |
Nb uops | 34.00 |
Nb loads | NA |
Nb stores | 2.00 |
Nb stack references | 0.00 |
FLOP/cycle | 4.37 |
Nb FLOP add-sub | 3.50 |
Nb FLOP mul | 3.50 |
Nb FLOP fma | 6.50 |
Nb FLOP div | 0.50 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.36 |
Bytes prefetched | 0.00 |
Bytes loaded | 96.00 |
Bytes stored | 20.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 30.30 |
Vectorization ratio load | 32.50 |
Vectorization ratio store | 25.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 50.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 32.58 |
Vector-efficiency ratio load | 33.13 |
Vector-efficiency ratio store | 31.25 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 37.50 |
Vector-efficiency ratio fma | 50.00 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 25.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.31 |
CQA speedup if FP arith vectorized | 1.24 |
CQA speedup if fully vectorized | 3.61 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.14 |
Bottlenecks | P6, P7, P8, P9, |
Function | .omp_outlined..5#0x409080 |
Source | ljForce.c:191-191,ljForce.c:197-216 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 7.00 |
CQA cycles if no scalar integer | 5.33 |
CQA cycles if FP arith vectorized | 5.67 |
CQA cycles if fully vectorized | 1.94 |
Front-end cycles | 6.13 |
DIV/SQRT cycles | 1.50 |
P0 cycles | 1.50 |
P1 cycles | 1.00 |
P2 cycles | 1.00 |
P3 cycles | 1.00 |
P4 cycles | 1.00 |
P5 cycles | 7.00 |
P6 cycles | 7.00 |
P7 cycles | 7.00 |
P8 cycles | 7.00 |
P9 cycles | 6.00 |
P10 cycles | 6.00 |
P11 cycles | 6.00 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
P14 cycles | 1.00 - 0.50 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 49.00 |
Nb uops | 49.00 |
Nb loads | NA |
Nb stores | 4.00 |
Nb stack references | 0.00 |
FLOP/cycle | 4.57 |
Nb FLOP add-sub | 4.00 |
Nb FLOP mul | 7.00 |
Nb FLOP fma | 10.00 |
Nb FLOP div | 1.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 25.14 |
Bytes prefetched | 0.00 |
Bytes loaded | 136.00 |
Bytes stored | 40.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 27.27 |
Vectorization ratio load | 25.00 |
Vectorization ratio store | 25.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 50.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 31.82 |
Vector-efficiency ratio load | 31.25 |
Vector-efficiency ratio store | 31.25 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 37.50 |
Vector-efficiency ratio fma | 50.00 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 25.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.19 |
CQA speedup if FP arith vectorized | 1.42 |
CQA speedup if fully vectorized | 3.45 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.06 |
Bottlenecks | micro-operation queue, |
Function | .omp_outlined..5#0x409080 |
Source | ljForce.c:191-191,ljForce.c:197-216 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 2.38 |
CQA cycles if no scalar integer | 2.00 |
CQA cycles if FP arith vectorized | 1.67 |
CQA cycles if fully vectorized | 0.69 |
Front-end cycles | 2.38 |
DIV/SQRT cycles | 1.00 |
P0 cycles | 1.00 |
P1 cycles | 0.75 |
P2 cycles | 0.75 |
P3 cycles | 0.75 |
P4 cycles | 0.75 |
P5 cycles | 2.25 |
P6 cycles | 2.25 |
P7 cycles | 2.25 |
P8 cycles | 2.25 |
P9 cycles | 1.67 |
P10 cycles | 1.67 |
P11 cycles | 1.67 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
P14 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 19.00 |
Nb uops | 19.00 |
Nb loads | NA |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 3.79 |
Nb FLOP add-sub | 3.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 3.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 23.58 |
Bytes prefetched | 0.00 |
Bytes loaded | 56.00 |
Bytes stored | 0.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 33.33 |
Vectorization ratio load | 40.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 50.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 33.33 |
Vector-efficiency ratio load | 35.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 37.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 25.00 |
Path / |
Function | .omp_outlined..5#0x409080 |
Source file and lines | ljForce.c:191-216 |
Module | exec |
nb instructions | 34 |
loop length | 136 |
nb stack references | 0 |
front end | 4.25 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.25 | 1.25 | 0.88 | 0.88 | 0.88 | 0.88 | 4.63 | 4.63 | 4.63 | 4.63 | 3.83 | 3.83 | 3.83 | 0.00 | 0.00 |
cycles | 1.25 | 1.25 | 0.88 | 0.88 | 0.88 | 0.88 | 4.63 | 4.63 | 4.63 | 4.63 | 3.83 | 3.83 | 3.83 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 0.50-0.25 |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 4.25 |
Data deps. | 1.00 |
Overall L1 | 4.69 |
all | 22% |
load | 32% |
store | 25% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 30% |
load | 32% |
store | 25% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Function | .omp_outlined..5#0x409080 |
Source file and lines | ljForce.c:191-216 |
Module | exec |
nb instructions | 49 |
loop length | 196 |
nb stack references | 0 |
front end | 6.13 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.50 | 1.50 | 1.00 | 1.00 | 1.00 | 1.00 | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 |
cycles | 1.50 | 1.50 | 1.00 | 1.00 | 1.00 | 1.00 | 7.00 | 7.00 | 7.00 | 7.00 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | 1.00-0.50 |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 6.13 |
Data deps. | 1.00 |
Overall L1 | 7.00 |
all | 20% |
load | 25% |
store | 25% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 27% |
load | 25% |
store | 25% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADD X26, X26, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X7, X7, #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X26, X2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 4091e8 <.omp_outlined..5+0x168> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR Q6, [X5] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDUR Q7, [X7, #496] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
MOVI D16, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
LDR D17, [X7] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
FSUB V6.2D, V6.2D, V7.2D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
FMLA D16, D6, V6.D[0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
MOV D7, V6.D[1] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
FMLA D16, D7, V6.D[1] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
LDR D7, [X6] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
FSUB D7, D7, S17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
LDR D17, [X23] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
FMADD D16, D7, D7, D16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
FCMP D16, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
FCCMP D16, D17, #2, #12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
B.HI 409208 <.omp_outlined..5+0x188> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
FDIV D16, D0, D16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 7-15 | 1-0.50 |
LDR D17, [X22] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDR D19, [X21] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDR X27, [X18, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
FMUL D18, D16, D16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
FMUL D18, D16, D18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
FMUL D17, D18, D17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
FADD D18, D17, D1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
FNMSUB D18, D17, D18, D19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
LDR D19, [X27, X4,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
FMADD D19, D18, D2, D19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
STR D19, [X27, X4,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
LDR D19, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDR X27, [X18, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
MADD X27, X4, X13, X27 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
FMADD D18, D18, D2, D19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
STR D18, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
LDR D18, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
FMUL D18, D18, D3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
FMUL D18, D17, D18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
FMADD D17, D17, D5, D4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
FMUL D16, D16, D18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
FMUL D16, D17, D16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
LDR Q17, [X27] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
FMLS V17.2D, V6.2D, V16.D[0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
LDR D6, [X27, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
STR Q17, [X27] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
FMSUB D6, D7, D16, D6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
STR D6, [X27, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
B 409208 <.omp_outlined..5+0x188> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Function | .omp_outlined..5#0x409080 |
Source file and lines | ljForce.c:191-216 |
Module | exec |
nb instructions | 19 |
loop length | 76 |
nb stack references | 0 |
front end | 2.38 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.00 | 1.00 | 0.75 | 0.75 | 0.75 | 0.75 | 2.25 | 2.25 | 2.25 | 2.25 | 1.67 | 1.67 | 1.67 | 0.00 | 0.00 |
cycles | 1.00 | 1.00 | 0.75 | 0.75 | 0.75 | 0.75 | 2.25 | 2.25 | 2.25 | 2.25 | 1.67 | 1.67 | 1.67 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 2.38 |
Data deps. | 1.00 |
Overall L1 | 2.38 |
all | 25% |
load | 40% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 33% |
load | 40% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADD X26, X26, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X7, X7, #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X26, X2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.GE 4091e8 <.omp_outlined..5+0x168> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR Q6, [X5] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDUR Q7, [X7, #496] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
MOVI D16, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
LDR D17, [X7] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
FSUB V6.2D, V6.2D, V7.2D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
FMLA D16, D6, V6.D[0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
MOV D7, V6.D[1] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
FMLA D16, D7, V6.D[1] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
LDR D7, [X6] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
FSUB D7, D7, S17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
LDR D17, [X23] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
FMADD D16, D7, D7, D16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
FCMP D16, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
FCCMP D16, D17, #2, #12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
B.HI 409208 <.omp_outlined..5+0x188> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |