Function: .omp_outlined..7 | Module: exec | Source: initAtoms.c:174-181 | Coverage: 0.01% |
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Function: .omp_outlined..7 | Module: exec | Source: initAtoms.c:174-181 | Coverage: 0.01% |
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/home/hbollore/qaas/qaas-runs/169-814-5713/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 174 - 181 |
-------------------------------------------------------------------------------- |
174: #pragma omp parallel for |
175: for (int iBox=0; iBox<s->boxes->nLocalBoxes; ++iBox) |
176: { |
177: for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff) |
178: { |
179: s->atoms->p[iOff][0] *= scaleFactor; |
180: s->atoms->p[iOff][1] *= scaleFactor; |
181: s->atoms->p[iOff][2] *= scaleFactor; |
0x4073e0 SUB SP, SP, #80 |
0x4073e4 STP X29, X30, [SP, #16] |
0x4073e8 STR X23, [SP, #32] |
0x4073ec STP X22, X21, [SP, #48] |
0x4073f0 STP X20, X19, [SP, #64] |
0x4073f4 ADD X29, SP, #16 |
0x4073f8 LDR X21, [X2] |
0x4073fc LDR X22, [X21, #24] |
0x407400 LDR W8, [X22, #12] |
0x407404 SUBS W23, W8, #1 |
0x407408 B.LT 407478 |
0x40740c LDR W20, [X0] |
0x407410 ORR X19, XZR, X3 |
0x407414 MOVZ W8, #1 |
0x407418 ADRP X0, |
0x40741c ADD X0, X0, #2808 |
0x407420 STP W23, WZR, [X29, #24] |
0x407424 STR WZR, [SP, #8] |
0x407428 ADD X3, SP, #8 |
0x40742c ADD X4, X29, #28 |
0x407430 ADD X5, X29, #24 |
0x407434 SUB X6, X29, #4 |
0x407438 STUR W8, [X29, #508] |
0x40743c STR W8, [SP] |
0x407440 MOVZ W2, #34 |
0x407444 MOVZ W7, #1 |
0x407448 ORR W1, WZR, W20 |
0x40744c BL 401f00 |
0x407450 LDR W8, [X29, #24] |
0x407454 CMP W8, W23 |
0x407458 CSEL W12, W8, W23, #11 |
0x40745c LDRSW X8, [X29, #28] |
0x407460 CMP W8, W12 |
0x407464 B.LE 407490 |
(103) 0x407468 ORR W1, WZR, W20 |
(103) 0x40746c ADRP X0, |
(103) 0x407470 ADD X0, X0, #2832 |
(103) 0x407474 BL 401df0 |
(103) 0x407478 LDP X20, X19, [SP, #64] |
(103) 0x40747c LDP X22, X21, [SP, #48] |
(103) 0x407480 LDR X23, [SP, #32] |
(103) 0x407484 LDP X29, X30, [SP, #16] |
(103) 0x407488 ADD SP, SP, #80 |
(103) 0x40748c RET |
(103) 0x407490 LDR X10, [X22, #120] |
(103) 0x407494 RDVL X15, #1 |
(103) 0x407498 ORR W9, WZR, WZR |
(103) 0x40749c UBFM W11, W8, #26, #25 |
(103) 0x4074a0 ADD W12, W12, #1 |
(103) 0x4074a4 ADD X13, X19, #8 |
(103) 0x4074a8 CNTD X16, ALL |
(103) 0x4074ac PTRUE P0.D, ALL |
(103) 0x4074b0 MOVZ W14, #24 |
(103) 0x4074b4 MOVZ W17, #4 |
(103) 0x4074b8 ORR X18, XZR, X8 |
(103) 0x4074bc UBFM X15, X15, #4, #63 |
(103) 0x4074c0 B 4074d8 |
(103) 0x4074c4 ADD X18, X18, #1 |
(103) 0x4074c8 ADD W11, W11, #64 |
(103) 0x4074cc ADD W9, W9, #1 |
(103) 0x4074d0 CMP W12, W18 |
(103) 0x4074d4 B.EQ 407468 |
(103) 0x4074d8 LDR W0, [X10, X18,LSL #2] |
(103) 0x4074dc SUBS W3, W0, #1 |
(103) 0x4074e0 B.LT 4074c4 |
(103) 0x4074e4 LDR X2, [X21, #32] |
(103) 0x4074e8 CMP X16, #4 |
(103) 0x4074ec ADD X4, X3, #1 |
(103) 0x4074f0 SBFM X1, X11, #0, #31 |
(103) 0x4074f4 CSEL X5, X16, X17, #8 |
(103) 0x4074f8 CMP X4, X5 |
(103) 0x4074fc LDR X2, [X2, #32] |
(103) 0x407500 B.CC 40758c |
(103) 0x407504 ADD W5, W8, W9 |
(103) 0x407508 UBFM W5, W5, #26, #25 |
(103) 0x40750c SBFM X6, X5, #0, #31 |
(103) 0x407510 ADD X5, X6, W5,SXTW #1 |
(103) 0x407514 ADD X3, X6, X3 |
(103) 0x407518 UBFM X5, X5, #61, #60 |
(103) 0x40751c MADD X3, X3, X14, X2 |
(103) 0x407520 ADD X5, X2, X5 |
(103) 0x407524 ADD X3, X3, #24 |
(103) 0x407528 CMP X5, X13 |
(103) 0x40752c CCMP X3, X19, #0, #3 |
(103) 0x407530 B.HI 40758c |
(103) 0x407534 UDIV X3, X4, X16 |
(103) 0x407538 SMADDL X5, W11, W14, XZR |
(103) 0x40753c ADD X6, X15, X15,LSL #1 |
(103) 0x407540 ADD X5, X2, X5 |
(103) 0x407544 UBFM X6, X6, #60, #59 |
(103) 0x407548 MADD X3, X3, X16, XZR |
(103) 0x40754c SUB X4, X4, X3 |
(103) 0x407550 ADD X1, X3, X1 |
(103) 0x407554 ORR X7, XZR, X3 |
(103) 0x407558 HINT #0 |
(103) 0x40755c HINT #0 |
(105) 0x407560 LD1RD {Z0.D}, P0/Z, [X19] |
(105) 0x407564 LD3D {Z1.D, Z2.D, Z3.D}, P0/Z, [X5, MUL VL] |
(105) 0x407568 SUBS X7, X7, X16 |
(105) 0x40756c FMUL Z4.D, Z0.D, Z1.D |
(105) 0x407570 FMUL Z5.D, Z0.D, Z2.D |
(105) 0x407574 FMUL Z6.D, Z0.D, Z3.D |
(105) 0x407578 ST3D {Z4.D, Z5.D, Z6.D}, P0, [X5, MUL VL] |
(105) 0x40757c ADD X5, X5, X6 |
(105) 0x407580 B.NE 407560 |
(103) 0x407584 CBNZ X4, 407590 |
0x407588 B 4074c4 |
(103) 0x40758c ORR W3, WZR, WZR |
(103) 0x407590 MADD X1, X1, X14, X2 |
(103) 0x407594 SUB W0, W0, W3 |
(103) 0x407598 ADD X1, X1, #16 |
(103) 0x40759c HINT #0 |
(104) 0x4075a0 LDR D0, [X19] |
(104) 0x4075a4 LDP D1, D2, [X1, #1008] |
(104) 0x4075a8 SUBS W0, W0, #1 |
(104) 0x4075ac FMUL D0, D0, D1 |
(104) 0x4075b0 LDR D1, [X1] |
(104) 0x4075b4 STUR D0, [X1, #496] |
(104) 0x4075b8 LDR D0, [X19] |
(104) 0x4075bc FMUL D0, D0, D2 |
(104) 0x4075c0 STUR D0, [X1, #504] |
(104) 0x4075c4 LDR D0, [X19] |
(104) 0x4075c8 FMUL D0, D0, D1 |
(104) 0x4075cc STR D0, [X1], #24 |
(104) 0x4075d0 B.NE 4075a0 |
(103) 0x4075d4 B 4074c4 |
0x4075d8 HINT #0 |
0x4075dc HINT #0 |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○100.00 | __kmp_invoke_microtask | libomp.so |
Path / |
Source file and lines | initAtoms.c:174-181 |
Module | exec |
nb instructions | 37 |
loop length | 148 |
nb stack references | 0 |
front end | 4.38 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.00 | 2.00 | 4.50 | 4.50 | 4.50 | 4.50 | 0.00 | 0.00 | 0.00 | 0.00 | 4.67 | 4.67 | 4.67 | 4.00 | 4.00 |
cycles | 2.00 | 2.00 | 4.50 | 4.50 | 4.50 | 4.50 | 0.00 | 0.00 | 0.00 | 0.00 | 4.67 | 4.67 | 4.67 | 4.00 | 4.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 4.38 |
Overall L1 | 4.67 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SUB SP, SP, #80 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X29, X30, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X23, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X22, X21, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X20, X19, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X21, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X22, [X21, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR W8, [X22, #12] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUBS W23, W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LT 407478 <.omp_outlined..7+0x98> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR W20, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ORR X19, XZR, X3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X0, <420418> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #2808 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP W23, WZR, [X29, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR WZR, [SP, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X3, SP, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X4, X29, #28 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X5, X29, #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X6, X29, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STUR W8, [X29, #508] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR W8, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR W1, WZR, W20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 401f00 <@plt_start@+0x1c0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR W8, [X29, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP W8, W23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CSEL W12, W8, W23, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDRSW X8, [X29, #28] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP W8, W12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LE 407490 <.omp_outlined..7+0xb0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
B 4074c4 <.omp_outlined..7+0xe4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 |
Source file and lines | initAtoms.c:174-181 |
Module | exec |
nb instructions | 37 |
loop length | 148 |
nb stack references | 0 |
front end | 4.38 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.00 | 2.00 | 4.50 | 4.50 | 4.50 | 4.50 | 0.00 | 0.00 | 0.00 | 0.00 | 4.67 | 4.67 | 4.67 | 4.00 | 4.00 |
cycles | 2.00 | 2.00 | 4.50 | 4.50 | 4.50 | 4.50 | 0.00 | 0.00 | 0.00 | 0.00 | 4.67 | 4.67 | 4.67 | 4.00 | 4.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 4.38 |
Overall L1 | 4.67 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SUB SP, SP, #80 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X29, X30, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X23, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X22, X21, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X20, X19, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X21, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X22, [X21, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR W8, [X22, #12] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUBS W23, W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LT 407478 <.omp_outlined..7+0x98> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR W20, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ORR X19, XZR, X3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X0, <420418> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #2808 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP W23, WZR, [X29, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR WZR, [SP, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X3, SP, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X4, X29, #28 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X5, X29, #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X6, X29, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STUR W8, [X29, #508] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR W8, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR W1, WZR, W20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 401f00 <@plt_start@+0x1c0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR W8, [X29, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP W8, W23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CSEL W12, W8, W23, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDRSW X8, [X29, #28] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP W8, W12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LE 407490 <.omp_outlined..7+0xb0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
B 4074c4 <.omp_outlined..7+0xe4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼.omp_outlined..7– | 0.01 | 0 |
▼Loop 103 - initAtoms.c:174-181 - exec– | 0 | 0 |
○Loop 105 - initAtoms.c:177-179 - exec | 0.01 | 0 |
○Loop 104 - initAtoms.c:177-181 - exec | 0 | 0 |