Function: loadAtomsBuffer | Module: exec | Source: haloExchange.c:373-393 | Coverage: 0.19% |
---|
Function: loadAtomsBuffer | Module: exec | Source: haloExchange.c:373-393 | Coverage: 0.19% |
---|
/home/hbollore/qaas/qaas-runs/169-814-5713/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 373 - 393 |
-------------------------------------------------------------------------------- |
373: int nCells = parms->nCells[face]; |
374: int* cellList = parms->cellList[face]; |
375: int nBuf = 0; |
376: for (int iCell=0; iCell<nCells; ++iCell) |
377: { |
378: int iBox = cellList[iCell]; |
379: int iOff = iBox*MAXATOMS; |
380: for (int ii=iOff; ii<iOff+s->boxes->nAtoms[iBox]; ++ii) |
381: { |
382: buf[nBuf].gid = s->atoms->gid[ii]; |
383: buf[nBuf].type = s->atoms->iSpecies[ii]; |
384: buf[nBuf].rx = s->atoms->r[ii][0] + shift[0]; |
385: buf[nBuf].ry = s->atoms->r[ii][1] + shift[1]; |
386: buf[nBuf].rz = s->atoms->r[ii][2] + shift[2]; |
387: buf[nBuf].px = s->atoms->p[ii][0]; |
388: buf[nBuf].py = s->atoms->p[ii][1]; |
389: buf[nBuf].pz = s->atoms->p[ii][2]; |
390: ++nBuf; |
391: } |
392: } |
393: return nBuf*sizeof(AtomMsg); |
0x405400 LDR W9, [X0, X2,SXTW #2] |
0x405404 CMP W9, #1 |
0x405408 B.LT 405530 |
0x40540c ADD X11, X0, W2,SXTW #3 |
0x405410 LDP X13, X14, [X1, #16] |
0x405414 ORR X10, XZR, XZR |
0x405418 LDR X12, [X11, #72] |
0x40541c LDR X11, [X11, #24] |
0x405420 ORR W8, WZR, WZR |
0x405424 LDP D2, D3, [X13, #72] |
0x405428 LDP D0, D1, [X12] |
0x40542c FMUL D1, D1, D3 |
0x405430 LDR D3, [X13, #88] |
0x405434 ADD X13, X3, #24 |
0x405438 FMUL D0, D0, D2 |
0x40543c LDR D2, [X12, #16] |
0x405440 LDR X12, [X14, #120] |
0x405444 MOVZ W14, #56 |
0x405448 FMUL D2, D2, D3 |
0x40544c B 40546c |
0x405450 HINT #0 |
0x405454 HINT #0 |
0x405458 HINT #0 |
0x40545c HINT #0 |
(66) 0x405460 ADD X10, X10, #1 |
(66) 0x405464 CMP X10, X9 |
(66) 0x405468 B.EQ 405534 |
(66) 0x40546c LDRSW X15, [X11, X10,LSL #2] |
(66) 0x405470 LDR W16, [X12, X15,LSL #2] |
(66) 0x405474 CMP W16, #1 |
(66) 0x405478 B.LT 405460 |
(66) 0x40547c LDR X0, [X1, #32] |
(66) 0x405480 UBFM W17, W15, #26, #25 |
(66) 0x405484 ORR X16, XZR, XZR |
(66) 0x405488 SBFM X18, X17, #0, #31 |
(66) 0x40548c ADD X4, X18, W17,SXTW #1 |
(66) 0x405490 LDP X2, X3, [X0, #8] |
(66) 0x405494 LDP X5, X0, [X0, #24] |
(66) 0x405498 UBFM X4, X4, #61, #60 |
(66) 0x40549c ADD X6, X0, X4 |
(66) 0x4054a0 ADD X5, X5, X4 |
(66) 0x4054a4 SBFM X4, X17, #62, #31 |
(66) 0x4054a8 ADD X0, X3, X4 |
(66) 0x4054ac ADD X2, X2, X4 |
(66) 0x4054b0 SMADDL X3, W8, W14, X13 |
(66) 0x4054b4 ADD X4, X6, #16 |
(66) 0x4054b8 ADD X5, X5, #16 |
(66) 0x4054bc HINT #0 |
(67) 0x4054c0 LDUR D3, [X5, #496] |
(67) 0x4054c4 LDR W6, [X2, X16,LSL #2] |
(67) 0x4054c8 STUR W6, [X3, #488] |
(67) 0x4054cc LDR W6, [X0, X16,LSL #2] |
(67) 0x4054d0 ADD X16, X16, #1 |
(67) 0x4054d4 FADD D3, D0, D3 |
(67) 0x4054d8 ADD X7, X18, X16 |
(67) 0x4054dc STUR D3, [X3, #496] |
(67) 0x4054e0 LDUR D3, [X5, #504] |
(67) 0x4054e4 STUR W6, [X3, #492] |
(67) 0x4054e8 LDRSW X6, [X12, X15,LSL #2] |
(67) 0x4054ec ADD X6, X6, W17,SXTW |
(67) 0x4054f0 FADD D3, D1, D3 |
(67) 0x4054f4 CMP X7, X6 |
(67) 0x4054f8 STUR D3, [X3, #504] |
(67) 0x4054fc LDR D3, [X5], #24 |
(67) 0x405500 FADD D3, D2, D3 |
(67) 0x405504 STR D3, [X3] |
(67) 0x405508 LDUR D3, [X4, #496] |
(67) 0x40550c STR D3, [X3, #8] |
(67) 0x405510 LDUR D3, [X4, #504] |
(67) 0x405514 STR D3, [X3, #16] |
(67) 0x405518 LDR D3, [X4], #24 |
(67) 0x40551c STR D3, [X3, #24] |
(67) 0x405520 ADD X3, X3, #56 |
(67) 0x405524 B.LT 4054c0 |
(66) 0x405528 ADD W8, W8, W16 |
(66) 0x40552c B 405460 |
0x405530 ORR W8, WZR, WZR |
0x405534 UBFM W9, W8, #26, #25 |
0x405538 SUB W0, W9, W8,LSL #3 |
0x40553c RET |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | timestep | timestep.c:150 | exec |
○ | main | CoMD.c:125 | exec |
○ | __libc_start_main | libc-2.31.so | |
○ | _start | exec |
Path / |
Source file and lines | haloExchange.c:373-393 |
Module | exec |
nb instructions | 28 |
loop length | 112 |
nb stack references | 0 |
front end | 3.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.50 | 1.50 | 2.25 | 2.25 | 2.25 | 2.25 | 0.75 | 0.75 | 0.75 | 0.75 | 3.00 | 3.00 | 3.00 | 0.00 | 0.00 |
cycles | 1.50 | 1.50 | 2.25 | 2.25 | 2.25 | 2.25 | 0.75 | 0.75 | 0.75 | 0.75 | 3.00 | 3.00 | 3.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 3.00 |
Overall L1 | 3.00 |
all | 33% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LDR W9, [X0, X2,SXTW #2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LT 405530 <loadAtomsBuffer+0x130> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD X11, X0, W2,SXTW #3 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
LDP X13, X14, [X1, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
ORR X10, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X12, [X11, #72] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X11, [X11, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ORR W8, WZR, WZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDP D2, D3, [X13, #72] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDP D0, D1, [X12] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
FMUL D1, D1, D3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
LDR D3, [X13, #88] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
ADD X13, X3, #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
FMUL D0, D0, D2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
LDR D2, [X12, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDR X12, [X14, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
MOVZ W14, #56 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
FMUL D2, D2, D3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
B 40546c <loadAtomsBuffer+0x6c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
ORR W8, WZR, WZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
UBFM W9, W8, #26, #25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB W0, W9, W8,LSL #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
RET | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Source file and lines | haloExchange.c:373-393 |
Module | exec |
nb instructions | 28 |
loop length | 112 |
nb stack references | 0 |
front end | 3.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.50 | 1.50 | 2.25 | 2.25 | 2.25 | 2.25 | 0.75 | 0.75 | 0.75 | 0.75 | 3.00 | 3.00 | 3.00 | 0.00 | 0.00 |
cycles | 1.50 | 1.50 | 2.25 | 2.25 | 2.25 | 2.25 | 0.75 | 0.75 | 0.75 | 0.75 | 3.00 | 3.00 | 3.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 3.00 |
Overall L1 | 3.00 |
all | 33% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LDR W9, [X0, X2,SXTW #2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LT 405530 <loadAtomsBuffer+0x130> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADD X11, X0, W2,SXTW #3 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
LDP X13, X14, [X1, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
ORR X10, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X12, [X11, #72] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X11, [X11, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ORR W8, WZR, WZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDP D2, D3, [X13, #72] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDP D0, D1, [X12] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
FMUL D1, D1, D3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
LDR D3, [X13, #88] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
ADD X13, X3, #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
FMUL D0, D0, D2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
LDR D2, [X12, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDR X12, [X14, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
MOVZ W14, #56 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
FMUL D2, D2, D3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
B 40546c <loadAtomsBuffer+0x6c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
ORR W8, WZR, WZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
UBFM W9, W8, #26, #25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB W0, W9, W8,LSL #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
RET | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼loadAtomsBuffer– | 0.19 | 0.08 |
▼Loop 66 - haloExchange.c:376-389 - exec– | 0 | 0 |
○Loop 67 - haloExchange.c:380-389 - exec | 0.19 | 0.08 |