Function: .omp_outlined.#0x40b270 | Module: exec | Source: timestep.c:71-78 | Coverage: 0.56% |
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Function: .omp_outlined.#0x40b270 | Module: exec | Source: timestep.c:71-78 | Coverage: 0.56% |
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/home/hbollore/qaas/qaas-runs/169-814-5713/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 78 |
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71: #pragma omp parallel for |
72: for (int iBox=0; iBox<nBoxes; iBox++) |
73: { |
74: for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++) |
75: { |
76: s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0]; |
77: s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1]; |
78: s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2]; |
0x40b270 SUB SP, SP, #96 |
0x40b274 STP X29, X30, [SP, #32] |
0x40b278 STP X24, X23, [SP, #48] |
0x40b27c STP X22, X21, [SP, #64] |
0x40b280 STP X20, X19, [SP, #80] |
0x40b284 ADD X29, SP, #32 |
0x40b288 LDR W8, [X2] |
0x40b28c SUBS W22, W8, #1 |
0x40b290 B.LT 40b304 |
0x40b294 LDR W20, [X0] |
0x40b298 LDR X21, [X3] |
0x40b29c ORR X19, XZR, X4 |
0x40b2a0 MOVZ W8, #1 |
0x40b2a4 ADRP X0, |
0x40b2a8 ADD X0, X0, #3120 |
0x40b2ac STP W22, WZR, [X29, #504] |
0x40b2b0 STR WZR, [SP, #16] |
0x40b2b4 ADD X3, SP, #16 |
0x40b2b8 SUB X4, X29, #4 |
0x40b2bc SUB X5, X29, #8 |
0x40b2c0 SUB X6, X29, #12 |
0x40b2c4 STUR W8, [X29, #500] |
0x40b2c8 STR W8, [SP] |
0x40b2cc MOVZ W2, #34 |
0x40b2d0 MOVZ W7, #1 |
0x40b2d4 ORR W1, WZR, W20 |
0x40b2d8 BL 401f00 |
0x40b2dc LDUR W8, [X29, #504] |
0x40b2e0 CMP W8, W22 |
0x40b2e4 CSEL W12, W8, W22, #11 |
0x40b2e8 LDURSW X8, [X29, #508] |
0x40b2ec CMP W8, W12 |
0x40b2f0 B.LE 40b31c |
(34) 0x40b2f4 ORR W1, WZR, W20 |
(34) 0x40b2f8 ADRP X0, |
(34) 0x40b2fc ADD X0, X0, #3144 |
(34) 0x40b300 BL 401df0 |
(34) 0x40b304 LDP X20, X19, [SP, #80] |
(34) 0x40b308 LDP X22, X21, [SP, #64] |
(34) 0x40b30c LDP X24, X23, [SP, #48] |
(34) 0x40b310 LDP X29, X30, [SP, #32] |
(34) 0x40b314 ADD SP, SP, #96 |
(34) 0x40b318 RET |
(34) 0x40b31c LDR X10, [X21, #24] |
(34) 0x40b320 RDVL X15, #1 |
(34) 0x40b324 ORR W9, WZR, WZR |
(34) 0x40b328 UBFM W11, W8, #26, #25 |
(34) 0x40b32c ADD W12, W12, #1 |
(34) 0x40b330 ADD X13, X19, #8 |
(34) 0x40b334 LDR X10, [X10, #120] |
(34) 0x40b338 CNTD X16, ALL |
(34) 0x40b33c PTRUE P0.D, ALL |
(34) 0x40b340 ORR X18, XZR, X8 |
(34) 0x40b344 MOVZ W14, #24 |
(34) 0x40b348 UBFM X15, X15, #4, #63 |
(34) 0x40b34c MOVZ W17, #4 |
(34) 0x40b350 B 40b374 |
0x40b354 HINT #0 |
0x40b358 HINT #0 |
0x40b35c HINT #0 |
(34) 0x40b360 ADD X18, X18, #1 |
(34) 0x40b364 ADD W11, W11, #64 |
(34) 0x40b368 ADD W9, W9, #1 |
(34) 0x40b36c CMP W12, W18 |
(34) 0x40b370 B.EQ 40b2f4 |
(34) 0x40b374 LDR W0, [X10, X18,LSL #2] |
(34) 0x40b378 SUBS W5, W0, #1 |
(34) 0x40b37c B.LT 40b360 |
(34) 0x40b380 LDR X1, [X21, #32] |
(34) 0x40b384 CMP X16, #4 |
(34) 0x40b388 ADD X6, X5, #1 |
(34) 0x40b38c SBFM X2, X11, #0, #31 |
(34) 0x40b390 CSEL X4, X16, X17, #8 |
(34) 0x40b394 CMP X6, X4 |
(34) 0x40b398 LDP X1, X3, [X1, #32] |
(34) 0x40b39c B.CS 40b3a8 |
(34) 0x40b3a0 ORR W4, WZR, WZR |
(34) 0x40b3a4 B 40b460 |
(34) 0x40b3a8 ADD W7, W8, W9 |
(34) 0x40b3ac ORR W4, WZR, WZR |
(34) 0x40b3b0 UBFM W7, W7, #26, #25 |
(34) 0x40b3b4 SBFM X22, X7, #0, #31 |
(34) 0x40b3b8 ADD X5, X22, X5 |
(34) 0x40b3bc ADD X7, X22, W7,SXTW #1 |
(34) 0x40b3c0 ADD X5, X5, X5,LSL #1 |
(34) 0x40b3c4 UBFM X7, X7, #61, #60 |
(34) 0x40b3c8 ADD X23, X1, X7 |
(34) 0x40b3cc UBFM X5, X5, #61, #60 |
(34) 0x40b3d0 ADD X22, X3, X5 |
(34) 0x40b3d4 ADD X5, X1, X5 |
(34) 0x40b3d8 ADD X22, X22, #24 |
(34) 0x40b3dc CMP X23, X22 |
(34) 0x40b3e0 ADD X22, X5, #24 |
(34) 0x40b3e4 ADD X5, X3, X7 |
(34) 0x40b3e8 CCMP X5, X22, #2, #3 |
(34) 0x40b3ec CSINC W5, WZR, WZR, #2 |
(34) 0x40b3f0 CMP X22, X19 |
(34) 0x40b3f4 CCMP X23, X13, #2, #8 |
(34) 0x40b3f8 B.CC 40b460 |
(34) 0x40b3fc TBNZ W5, #0, 40b460 |
0x40b400 UDIV X4, X6, X16 |
0x40b404 ADD X7, X15, X15,LSL #1 |
0x40b408 SMADDL X5, W11, W14, XZR |
0x40b40c UBFM X7, X7, #60, #59 |
0x40b410 MADD X4, X4, X16, XZR |
0x40b414 SUB X6, X6, X4 |
0x40b418 ADD X2, X4, X2 |
0x40b41c ORR X22, XZR, X4 |
(33) 0x40b420 ADD X23, X3, X5 |
(33) 0x40b424 ADD X24, X1, X5 |
(33) 0x40b428 LD1RD {Z0.D}, P0/Z, [X19] |
(33) 0x40b42c LD3D {Z1.D, Z2.D, Z3.D}, P0/Z, [X23, MUL VL] |
(33) 0x40b430 ADD X5, X5, X7 |
(33) 0x40b434 SUBS X22, X22, X16 |
(33) 0x40b438 LD3D {Z4.D, Z5.D, Z6.D}, P0/Z, [X24, MUL VL] |
(33) 0x40b43c MOVPRFX Z16, Z4 |
(33) 0x40b440 FMLA Z16.D, P0/M, Z0.D, Z1.D |
(33) 0x40b444 MOVPRFX Z17, Z5 |
(33) 0x40b448 FMLA Z17.D, P0/M, Z0.D, Z2.D |
(33) 0x40b44c MOVPRFX Z18, Z6 |
(33) 0x40b450 FMLA Z18.D, P0/M, Z0.D, Z3.D |
(33) 0x40b454 ST3D {Z16.D, Z17.D, Z18.D}, P0, [X24, MUL VL] |
(33) 0x40b458 B.NE 40b420 |
0x40b45c CBZ X6, 40b360 |
(34) 0x40b460 ADD X2, X2, X2,LSL #1 |
(34) 0x40b464 SUB W0, W0, W4 |
(34) 0x40b468 UBFM X4, X2, #61, #60 |
(34) 0x40b46c ADD X2, X3, X4 |
(34) 0x40b470 ADD X1, X1, X4 |
(34) 0x40b474 ADD X2, X2, #8 |
(34) 0x40b478 ADD X1, X1, #8 |
(34) 0x40b47c HINT #0 |
(35) 0x40b480 LDR D0, [X19] |
(35) 0x40b484 LDUR D1, [X2, #504] |
(35) 0x40b488 LDUR D2, [X1, #504] |
(35) 0x40b48c SUBS W0, W0, #1 |
(35) 0x40b490 FMADD D0, D0, D1, D2 |
(35) 0x40b494 LDP D2, D3, [X1] |
(35) 0x40b498 STUR D0, [X1, #504] |
(35) 0x40b49c LDR D0, [X19] |
(35) 0x40b4a0 LDR D1, [X2] |
(35) 0x40b4a4 FMADD D0, D0, D1, D2 |
(35) 0x40b4a8 STR D0, [X1] |
(35) 0x40b4ac LDR D0, [X19] |
(35) 0x40b4b0 LDR D1, [X2, #8] |
(35) 0x40b4b4 ADD X2, X2, #24 |
(35) 0x40b4b8 FMADD D0, D0, D1, D3 |
(35) 0x40b4bc STR D0, [X1, #8] |
(35) 0x40b4c0 ADD X1, X1, #24 |
(35) 0x40b4c4 B.NE 40b480 |
(34) 0x40b4c8 B 40b360 |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○100.00 | __kmp_invoke_microtask | libomp.so |
Path / |
Source file and lines | timestep.c:71-78 |
Module | exec |
nb instructions | 45 |
loop length | 180 |
nb stack references | 0 |
front end | 5.25 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.00 | 2.00 | 6.50 | 6.50 | 6.50 | 6.50 | 0.00 | 0.00 | 0.00 | 0.00 | 4.33 | 4.33 | 4.33 | 4.00 | 4.00 |
cycles | 2.00 | 2.00 | 6.50 | 6.50 | 6.50 | 6.50 | 0.00 | 0.00 | 0.00 | 0.00 | 4.33 | 4.33 | 4.33 | 4.00 | 4.00 |
Cycles executing div or sqrt instructions | 1.00-0.50 |
Front-end | 5.25 |
Overall L1 | 6.50 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SUB SP, SP, #96 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X29, X30, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X24, X23, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X22, X21, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X20, X19, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #32 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W8, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUBS W22, W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LT 40b304 <.omp_outlined.+0x94> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR W20, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X21, [X3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ORR X19, XZR, X4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X0, <4202a4> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #3120 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP W22, WZR, [X29, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR WZR, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X3, SP, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X4, X29, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X5, X29, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X6, X29, #12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STUR W8, [X29, #500] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR W8, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR W1, WZR, W20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 401f00 <@plt_start@+0x1c0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDUR W8, [X29, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP W8, W22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CSEL W12, W8, W22, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDURSW X8, [X29, #508] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP W8, W12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LE 40b31c <.omp_outlined.+0xac> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
UDIV X4, X6, X16 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5-20 | 1-0.50 |
ADD X7, X15, X15,LSL #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SMADDL X5, W11, W14, XZR | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
UBFM X7, X7, #60, #59 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MADD X4, X4, X16, XZR | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
SUB X6, X6, X4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X2, X4, X2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X22, XZR, X4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CBZ X6, 40b360 <.omp_outlined.+0xf0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Source file and lines | timestep.c:71-78 |
Module | exec |
nb instructions | 45 |
loop length | 180 |
nb stack references | 0 |
front end | 5.25 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.00 | 2.00 | 6.50 | 6.50 | 6.50 | 6.50 | 0.00 | 0.00 | 0.00 | 0.00 | 4.33 | 4.33 | 4.33 | 4.00 | 4.00 |
cycles | 2.00 | 2.00 | 6.50 | 6.50 | 6.50 | 6.50 | 0.00 | 0.00 | 0.00 | 0.00 | 4.33 | 4.33 | 4.33 | 4.00 | 4.00 |
Cycles executing div or sqrt instructions | 1.00-0.50 |
Front-end | 5.25 |
Overall L1 | 6.50 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SUB SP, SP, #96 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X29, X30, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X24, X23, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X22, X21, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X20, X19, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #32 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR W8, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUBS W22, W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LT 40b304 <.omp_outlined.+0x94> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR W20, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X21, [X3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ORR X19, XZR, X4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X0, <4202a4> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #3120 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP W22, WZR, [X29, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR WZR, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X3, SP, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X4, X29, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X5, X29, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X6, X29, #12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STUR W8, [X29, #500] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR W8, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR W1, WZR, W20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 401f00 <@plt_start@+0x1c0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDUR W8, [X29, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP W8, W22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CSEL W12, W8, W22, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDURSW X8, [X29, #508] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP W8, W12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LE 40b31c <.omp_outlined.+0xac> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
UDIV X4, X6, X16 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5-20 | 1-0.50 |
ADD X7, X15, X15,LSL #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SMADDL X5, W11, W14, XZR | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
UBFM X7, X7, #60, #59 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MADD X4, X4, X16, XZR | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
SUB X6, X6, X4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X2, X4, X2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X22, XZR, X4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CBZ X6, 40b360 <.omp_outlined.+0xf0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼.omp_outlined.#0x40b270– | 0.56 | 0.24 |
○Loop 33 - timestep.c:74-76 - exec | 0.48 | 0.21 |
▼Loop 34 - timestep.c:71-78 - exec– | 0.02 | 0.01 |
○Loop 35 - timestep.c:74-78 - exec | 0.06 | 0.02 |