Loop Id: 59 | Module: exec | Source: haloExchange.c:633-642 | Coverage: 0.04% |
---|
Loop Id: 59 | Module: exec | Source: haloExchange.c:633-642 | Coverage: 0.04% |
---|
0x40a830 MOV (%RBX),%ECX [4] |
0x40a832 MOV %ECX,(%RDX,%R14,4) [2] |
0x40a836 MOV 0x4(%RBX),%ECX [4] |
0x40a839 MOV %ECX,(%RSI,%R14,4) [3] |
0x40a83d VMOVUPS 0x8(%RBX),%XMM0 [4] |
0x40a842 VMOVUPS %XMM0,-0x10(%R12,%RAX,1) [1] |
0x40a849 VMOVSD 0x18(%RBX),%XMM0 [4] |
0x40a84e VMOVSD %XMM0,(%R12,%RAX,1) [1] |
0x40a854 VMOVUPS 0x20(%RBX),%XMM0 [4] |
0x40a859 VMOVUPS %XMM0,-0x10(%R13,%RAX,1) [5] |
0x40a860 VMOVSD 0x30(%RBX),%XMM0 [4] |
0x40a865 VMOVSD %XMM0,(%R13,%RAX,1) [5] |
0x40a86c INC %R14 |
0x40a86f ADD $0x18,%RAX |
0x40a873 ADD $0x38,%RBX |
0x40a877 CMP %R15,%R14 |
0x40a87a JL 40a830 |
/scratch_na/users/xoserete/qaas_runs/171-172-4338/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 633 - 642 |
-------------------------------------------------------------------------------- |
633: for (int ii=begin, iTmp=0; ii<end; ++ii, ++iTmp) |
634: { |
635: atoms->gid[ii] = tmp[iTmp].gid; |
636: atoms->iSpecies[ii] = tmp[iTmp].type; |
637: atoms->r[ii][0] = tmp[iTmp].rx; |
638: atoms->r[ii][1] = tmp[iTmp].ry; |
639: atoms->r[ii][2] = tmp[iTmp].rz; |
640: atoms->p[ii][0] = tmp[iTmp].px; |
641: atoms->p[ii][1] = tmp[iTmp].py; |
642: atoms->p[ii][2] = tmp[iTmp].pz; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.50 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 6.86 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.12 |
Bottlenecks | P4, P7, P8, P9, |
Function | sortAtomsInCell |
Source | haloExchange.c:633-642 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 3.00 |
CQA cycles if no scalar integer | 2.00 |
CQA cycles if FP arith vectorized | 3.00 |
CQA cycles if fully vectorized | 0.44 |
Front-end cycles | 2.67 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.00 |
P1 cycles | 2.00 |
P2 cycles | 2.00 |
P3 cycles | 3.00 |
P4 cycles | 0.00 |
P5 cycles | 0.50 |
P6 cycles | 3.00 |
P7 cycles | 3.00 |
P8 cycles | 3.00 |
P9 cycles | 0.00 |
P10 cycles | 2.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 3.12 |
Stall cycles (UFS) | 0.00 |
Nb insns | 17.00 |
Nb uops | 16.00 |
Nb loads | 6.00 |
Nb stores | 6.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 37.33 |
Bytes prefetched | 0.00 |
Bytes loaded | 56.00 |
Bytes stored | 56.00 |
Stride 0 | 0.00 |
Stride 1 | 2.00 |
Stride n | 3.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 33.33 |
Vectorization ratio load | 33.33 |
Vectorization ratio store | 33.33 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 14.58 |
Vector-efficiency ratio load | 14.58 |
Vector-efficiency ratio store | 14.58 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.50 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 6.86 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.12 |
Bottlenecks | P4, P7, P8, P9, |
Function | sortAtomsInCell |
Source | haloExchange.c:633-642 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 3.00 |
CQA cycles if no scalar integer | 2.00 |
CQA cycles if FP arith vectorized | 3.00 |
CQA cycles if fully vectorized | 0.44 |
Front-end cycles | 2.67 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.00 |
P1 cycles | 2.00 |
P2 cycles | 2.00 |
P3 cycles | 3.00 |
P4 cycles | 0.00 |
P5 cycles | 0.50 |
P6 cycles | 3.00 |
P7 cycles | 3.00 |
P8 cycles | 3.00 |
P9 cycles | 0.00 |
P10 cycles | 2.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 3.12 |
Stall cycles (UFS) | 0.00 |
Nb insns | 17.00 |
Nb uops | 16.00 |
Nb loads | 6.00 |
Nb stores | 6.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 37.33 |
Bytes prefetched | 0.00 |
Bytes loaded | 56.00 |
Bytes stored | 56.00 |
Stride 0 | 0.00 |
Stride 1 | 2.00 |
Stride n | 3.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 33.33 |
Vectorization ratio load | 33.33 |
Vectorization ratio store | 33.33 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 14.58 |
Vector-efficiency ratio load | 14.58 |
Vector-efficiency ratio store | 14.58 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Path / |
Function | sortAtomsInCell |
Source file and lines | haloExchange.c:633-642 |
Module | exec |
nb instructions | 17 |
nb uops | 16 |
loop length | 76 |
used x86 registers | 9 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 2.67 cycles |
front end | 2.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.00 | 2.00 | 2.00 | 3.00 | 0.00 | 0.50 | 3.00 | 3.00 | 3.00 | 0.00 | 2.00 |
cycles | 0.50 | 0.00 | 2.00 | 2.00 | 3.00 | 0.00 | 0.50 | 3.00 | 3.00 | 3.00 | 0.00 | 2.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 3.12 |
Stall cycles | 0.00 |
Front-end | 2.67 |
Dispatch | 3.00 |
Data deps. | 1.00 |
Overall L1 | 3.00 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 50% |
load | 50% |
store | 50% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 33% |
load | 33% |
store | 33% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 6% |
load | 6% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 18% |
load | 18% |
store | 18% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 14% |
load | 14% |
store | 14% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV (%RBX),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %ECX,(%RDX,%R14,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x4(%RBX),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %ECX,(%RSI,%R14,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVUPS 0x8(%RBX),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPS %XMM0,-0x10(%R12,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVSD 0x18(%RBX),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%R12,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVUPS 0x20(%RBX),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPS %XMM0,-0x10(%R13,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVSD 0x30(%RBX),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%R13,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x18,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x38,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R15,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 40a830 <sortAtomsInCell+0xf0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | sortAtomsInCell |
Source file and lines | haloExchange.c:633-642 |
Module | exec |
nb instructions | 17 |
nb uops | 16 |
loop length | 76 |
used x86 registers | 9 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 2.67 cycles |
front end | 2.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.00 | 2.00 | 2.00 | 3.00 | 0.00 | 0.50 | 3.00 | 3.00 | 3.00 | 0.00 | 2.00 |
cycles | 0.50 | 0.00 | 2.00 | 2.00 | 3.00 | 0.00 | 0.50 | 3.00 | 3.00 | 3.00 | 0.00 | 2.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 3.12 |
Stall cycles | 0.00 |
Front-end | 2.67 |
Dispatch | 3.00 |
Data deps. | 1.00 |
Overall L1 | 3.00 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 50% |
load | 50% |
store | 50% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 33% |
load | 33% |
store | 33% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 6% |
load | 6% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 18% |
load | 18% |
store | 18% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 14% |
load | 14% |
store | 14% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV (%RBX),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %ECX,(%RDX,%R14,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x4(%RBX),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %ECX,(%RSI,%R14,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVUPS 0x8(%RBX),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPS %XMM0,-0x10(%R12,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVSD 0x18(%RBX),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%R12,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVUPS 0x20(%RBX),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPS %XMM0,-0x10(%R13,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVSD 0x30(%RBX),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM0,(%R13,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x18,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x38,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R15,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 40a830 <sortAtomsInCell+0xf0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |