Function: setTemperature.extracted.30 | Module: exec | Source: initAtoms.c:151-162 [...] | Coverage: 0.02% |
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Function: setTemperature.extracted.30 | Module: exec | Source: initAtoms.c:151-162 [...] | Coverage: 0.02% |
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/scratch_na/users/xoserete/qaas_runs/171-172-4338/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 151 - 162 |
-------------------------------------------------------------------------------- |
151: #pragma omp parallel for |
152: for (int iBox=0; iBox<s->boxes->nLocalBoxes; ++iBox) |
153: { |
154: for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff) |
155: { |
156: int iType = s->atoms->iSpecies[iOff]; |
157: real_t mass = s->species[iType].mass; |
158: real_t sigma = sqrt(kB_eV * temperature/mass); |
159: uint64_t seed = mkSeed(s->atoms->gid[iOff], 123); |
160: s->atoms->p[iOff][0] = mass * sigma * gasdev(&seed); |
161: s->atoms->p[iOff][1] = mass * sigma * gasdev(&seed); |
162: s->atoms->p[iOff][2] = mass * sigma * gasdev(&seed); |
/scratch_na/users/xoserete/qaas_runs/171-172-4338/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c: 27 - 70 |
-------------------------------------------------------------------------------- |
27: v2 = 2.0*lcg61(seed)-1.0; |
28: rsq = v1*v1+v2*v2; |
29: } while (rsq >= 1.0 || rsq == 0.0); |
30: |
31: return v2 * sqrt(-2.0*log(rsq)/rsq); |
[...] |
45: *seed *= UINT64_C(437799614237992725); |
46: *seed %= UINT64_C(2305843009213693951); |
47: |
48: return *seed*convertToDouble; |
[...] |
67: uint32_t s1 = id * UINT32_C(2654435761); |
68: uint32_t s2 = (id+callSite) * UINT32_C(2654435761); |
69: |
70: uint64_t iSeed = (UINT64_C(0x100000000) * s1) + s2; |
0x40be00 PUSH %RBP |
0x40be01 MOV %RSP,%RBP |
0x40be04 PUSH %R15 |
0x40be06 PUSH %R14 |
0x40be08 PUSH %R13 |
0x40be0a PUSH %R12 |
0x40be0c PUSH %RBX |
0x40be0d SUB $0x88,%RSP |
0x40be14 MOV %RCX,%R15 |
0x40be17 MOV %RDX,-0x78(%RBP) |
0x40be1b MOVL $0,-0x6c(%RBP) |
0x40be22 MOV (%RDI),%ESI |
0x40be24 MOVL $0,-0x44(%RBP) |
0x40be2b MOV %R9D,-0x40(%RBP) |
0x40be2f MOVL $0x1,-0x68(%RBP) |
0x40be36 SUB $0x8,%RSP |
0x40be3a LEA -0x68(%RBP),%RAX |
0x40be3e LEA -0x6c(%RBP),%RCX |
0x40be42 LEA -0x44(%RBP),%R8 |
0x40be46 LEA -0x40(%RBP),%R9 |
0x40be4a MOV $0x631690,%EDI |
0x40be4f MOV %ESI,-0x5c(%RBP) |
0x40be52 MOV $0x22,%EDX |
0x40be57 PUSH $0x1 |
0x40be59 PUSH $0x1 |
0x40be5b PUSH %RAX |
0x40be5c CALL 403120 <__kmpc_for_static_init_4@plt> |
0x40be61 ADD $0x20,%RSP |
0x40be65 MOV -0x44(%RBP),%ECX |
0x40be68 MOV -0x40(%RBP),%EAX |
0x40be6b MOV %RAX,-0x80(%RBP) |
0x40be6f CMP %EAX,%ECX |
0x40be71 JBE 40bec0 |
0x40be73 MOV $0x6316b0,%EDI |
0x40be78 MOV -0x5c(%RBP),%ESI |
0x40be7b ADD $0x88,%RSP |
0x40be82 POP %RBX |
0x40be83 POP %R12 |
0x40be85 POP %R13 |
0x40be87 POP %R14 |
0x40be89 POP %R15 |
0x40be8b POP %RBP |
0x40be8c JMP 402fe0 |
0x40be91 NOPW %CS:(%RAX,%RAX,1) |
0x40bea0 NOPW %CS:(%RAX,%RAX,1) |
0x40beaf NOPW %CS:(%RAX,%RAX,1) |
0x40bebe XCHG %AX,%AX |
0x40bec0 VMOVQ %R15,%XMM0 |
0x40bec5 MOV -0x78(%RBP),%RAX |
0x40bec9 MOV 0x18(%RAX),%RAX |
0x40becd VMULSD 0x1a043(%RIP),%XMM0,%XMM0 |
0x40bed5 VMOVSD %XMM0,-0x98(%RBP) |
0x40bedd MOV %ECX,%EDX |
0x40bedf SAL $0x6,%EDX |
0x40bee2 MOV %EDX,-0x3c(%RBP) |
0x40bee5 INCQ -0x80(%RBP) |
0x40bee9 MOV 0x78(%RAX),%RAX |
0x40beed MOV %RAX,-0x88(%RBP) |
0x40bef4 MOV $0x613606df9756715,%R13 |
0x40befe MOV $0x9,%EBX |
0x40bf03 VMOVSD 0x1ec65(%RIP),%XMM3 |
0x40bf0b VMOVSD 0x1a00d(%RIP),%XMM4 |
0x40bf13 VMOVSD 0x1ec5d(%RIP),%XMM5 |
0x40bf1b VXORPD %XMM6,%XMM6,%XMM6 |
0x40bf1f JMP 40bf58 |
0x40bf21 NOPW %CS:(%RAX,%RAX,1) |
0x40bf30 NOPW %CS:(%RAX,%RAX,1) |
0x40bf3f NOP |
(68) 0x40bf40 MOV -0x90(%RBP),%RCX |
(68) 0x40bf47 INC %RCX |
(68) 0x40bf4a ADDL $0x40,-0x3c(%RBP) |
(68) 0x40bf4e CMP -0x80(%RBP),%RCX |
(68) 0x40bf52 JE 40be73 |
(68) 0x40bf58 MOV %RCX,-0x90(%RBP) |
(68) 0x40bf5f MOV -0x88(%RBP),%RAX |
(68) 0x40bf66 MOV (%RAX,%RCX,4),%EAX |
(68) 0x40bf69 MOV %EAX,-0x60(%RBP) |
(68) 0x40bf6c TEST %EAX,%EAX |
(68) 0x40bf6e JLE 40bf40 |
(68) 0x40bf70 MOV -0x3c(%RBP),%R12D |
(68) 0x40bf74 MOV -0x78(%RBP),%RCX |
(68) 0x40bf78 MOV 0x20(%RCX),%RAX |
(68) 0x40bf7c MOV 0x28(%RCX),%RCX |
(68) 0x40bf80 MOV %RCX,-0xb0(%RBP) |
(68) 0x40bf87 MOV 0x8(%RAX),%RCX |
(68) 0x40bf8b MOV %RCX,-0xa8(%RBP) |
(68) 0x40bf92 MOV 0x10(%RAX),%RCX |
(68) 0x40bf96 MOV %RCX,-0xa0(%RBP) |
(68) 0x40bf9d MOV 0x20(%RAX),%RAX |
(68) 0x40bfa1 MOV %RAX,-0x50(%RBP) |
(68) 0x40bfa5 XOR %EAX,%EAX |
(68) 0x40bfa7 NOPW (%RAX,%RAX,1) |
(72) 0x40bfb0 MOV %EAX,-0x64(%RBP) |
(72) 0x40bfb3 MOV -0xa0(%RBP),%RAX |
(72) 0x40bfba MOVSXD (%RAX,%R12,4),%RAX |
(72) 0x40bfbe SAL $0x4,%RAX |
(72) 0x40bfc2 MOV -0xb0(%RBP),%RCX |
(72) 0x40bfc9 VMOVSD 0x8(%RCX,%RAX,1),%XMM7 |
(72) 0x40bfcf VMOVSD -0x98(%RBP),%XMM1 |
(72) 0x40bfd7 VDIVSD %XMM7,%XMM1,%XMM1 |
(72) 0x40bfdb VSQRTSD %XMM1,%XMM1,%XMM1 |
(72) 0x40bfdf MOV -0xa8(%RBP),%RAX |
(72) 0x40bfe6 IMUL $-0x61c8864f,(%RAX,%R12,4),%ECX |
(72) 0x40bfee MOV %ECX,%EAX |
(72) 0x40bff0 ADD $0x4a7780b,%EAX |
(72) 0x40bff5 SAL $0x20,%RCX |
(72) 0x40bff9 OR %RCX,%RAX |
(72) 0x40bffc IMUL %R13,%RAX |
(72) 0x40c000 MOV %RAX,%RDX |
(72) 0x40c003 MULX %RBX,%RCX,%RCX |
(72) 0x40c008 SUB %RCX,%RDX |
(72) 0x40c00b SHR $0x1,%RDX |
(72) 0x40c00e ADD %RCX,%RDX |
(72) 0x40c011 SHR $0x3c,%RDX |
(72) 0x40c015 MOV %RDX,%RCX |
(72) 0x40c018 SAL $0x3d,%RCX |
(72) 0x40c01c SUB %RCX,%RDX |
(72) 0x40c01f ADD %RAX,%RDX |
(72) 0x40c022 IMUL %R13,%RDX |
(72) 0x40c026 MULX %RBX,%RCX,%RCX |
(72) 0x40c02b MOV %RDX,%RAX |
(72) 0x40c02e SUB %RCX,%RAX |
(72) 0x40c031 SHR $0x1,%RAX |
(72) 0x40c034 ADD %RCX,%RAX |
(72) 0x40c037 SHR $0x3c,%RAX |
(72) 0x40c03b MOV %RAX,%RCX |
(72) 0x40c03e SAL $0x3d,%RCX |
(72) 0x40c042 SUB %RCX,%RAX |
(72) 0x40c045 ADD %RDX,%RAX |
(72) 0x40c048 IMUL %R13,%RAX |
(72) 0x40c04c MOV %RAX,%RDX |
(72) 0x40c04f MULX %RBX,%RCX,%RCX |
(72) 0x40c054 SUB %RCX,%RDX |
(72) 0x40c057 SHR $0x1,%RDX |
(72) 0x40c05a ADD %RCX,%RDX |
(72) 0x40c05d SHR $0x3c,%RDX |
(72) 0x40c061 MOV %RDX,%RCX |
(72) 0x40c064 SAL $0x3d,%RCX |
(72) 0x40c068 SUB %RCX,%RDX |
(72) 0x40c06b ADD %RAX,%RDX |
(72) 0x40c06e IMUL %R13,%RDX |
(72) 0x40c072 MULX %RBX,%RCX,%RCX |
(72) 0x40c077 MOV %RDX,%RAX |
(72) 0x40c07a SUB %RCX,%RAX |
(72) 0x40c07d SHR $0x1,%RAX |
(72) 0x40c080 ADD %RCX,%RAX |
(72) 0x40c083 SHR $0x3c,%RAX |
(72) 0x40c087 MOV %RAX,%RCX |
(72) 0x40c08a SAL $0x3d,%RCX |
(72) 0x40c08e SUB %RCX,%RAX |
(72) 0x40c091 ADD %RDX,%RAX |
(72) 0x40c094 IMUL %R13,%RAX |
(72) 0x40c098 MOV %RAX,%RDX |
(72) 0x40c09b MULX %RBX,%RCX,%RCX |
(72) 0x40c0a0 SUB %RCX,%RDX |
(72) 0x40c0a3 SHR $0x1,%RDX |
(72) 0x40c0a6 ADD %RCX,%RDX |
(72) 0x40c0a9 SHR $0x3c,%RDX |
(72) 0x40c0ad MOV %RDX,%RCX |
(72) 0x40c0b0 SAL $0x3d,%RCX |
(72) 0x40c0b4 SUB %RCX,%RDX |
(72) 0x40c0b7 ADD %RAX,%RDX |
(72) 0x40c0ba IMUL %R13,%RDX |
(72) 0x40c0be MULX %RBX,%RCX,%RCX |
(72) 0x40c0c3 MOV %RDX,%RAX |
(72) 0x40c0c6 SUB %RCX,%RAX |
(72) 0x40c0c9 SHR $0x1,%RAX |
(72) 0x40c0cc ADD %RCX,%RAX |
(72) 0x40c0cf SHR $0x3c,%RAX |
(72) 0x40c0d3 MOV %RAX,%RCX |
(72) 0x40c0d6 SAL $0x3d,%RCX |
(72) 0x40c0da SUB %RCX,%RAX |
(72) 0x40c0dd ADD %RDX,%RAX |
(72) 0x40c0e0 IMUL %R13,%RAX |
(72) 0x40c0e4 MOV %RAX,%RDX |
(72) 0x40c0e7 MULX %RBX,%RCX,%RCX |
(72) 0x40c0ec SUB %RCX,%RDX |
(72) 0x40c0ef SHR $0x1,%RDX |
(72) 0x40c0f2 ADD %RCX,%RDX |
(72) 0x40c0f5 SHR $0x3c,%RDX |
(72) 0x40c0f9 MOV %RDX,%RCX |
(72) 0x40c0fc SAL $0x3d,%RCX |
(72) 0x40c100 SUB %RCX,%RDX |
(72) 0x40c103 ADD %RAX,%RDX |
(72) 0x40c106 IMUL %R13,%RDX |
(72) 0x40c10a MULX %RBX,%RCX,%RCX |
(72) 0x40c10f MOV %RDX,%RAX |
(72) 0x40c112 SUB %RCX,%RAX |
(72) 0x40c115 SHR $0x1,%RAX |
(72) 0x40c118 ADD %RCX,%RAX |
(72) 0x40c11b SHR $0x3c,%RAX |
(72) 0x40c11f MOV %RAX,%RCX |
(72) 0x40c122 SAL $0x3d,%RCX |
(72) 0x40c126 SUB %RCX,%RAX |
(72) 0x40c129 ADD %RDX,%RAX |
(72) 0x40c12c IMUL %R13,%RAX |
(72) 0x40c130 MOV %RAX,%RDX |
(72) 0x40c133 MULX %RBX,%RCX,%RCX |
(72) 0x40c138 SUB %RCX,%RDX |
(72) 0x40c13b SHR $0x1,%RDX |
(72) 0x40c13e ADD %RCX,%RDX |
(72) 0x40c141 SHR $0x3c,%RDX |
(72) 0x40c145 MOV %RDX,%RCX |
(72) 0x40c148 SAL $0x3d,%RCX |
(72) 0x40c14c SUB %RCX,%RDX |
(72) 0x40c14f ADD %RAX,%RDX |
(72) 0x40c152 IMUL %R13,%RDX |
(72) 0x40c156 MULX %RBX,%RAX,%RAX |
(72) 0x40c15b MOV %RDX,%R15 |
(72) 0x40c15e SUB %RAX,%R15 |
(72) 0x40c161 SHR $0x1,%R15 |
(72) 0x40c164 ADD %RAX,%R15 |
(72) 0x40c167 SHR $0x3c,%R15 |
(72) 0x40c16b MOV %R15,%RAX |
(72) 0x40c16e SAL $0x3d,%RAX |
(72) 0x40c172 SUB %RAX,%R15 |
(72) 0x40c175 ADD %RDX,%R15 |
(72) 0x40c178 NOPL (%RAX,%RAX,1) |
(69) 0x40c180 IMUL %R13,%R15 |
(69) 0x40c184 MOV %R15,%RDX |
(69) 0x40c187 MULX %RBX,%RAX,%RAX |
(69) 0x40c18c SUB %RAX,%RDX |
(69) 0x40c18f SHR $0x1,%RDX |
(69) 0x40c192 ADD %RAX,%RDX |
(69) 0x40c195 SHR $0x3c,%RDX |
(69) 0x40c199 MOV %RDX,%RAX |
(69) 0x40c19c SAL $0x3d,%RAX |
(69) 0x40c1a0 SUB %RAX,%RDX |
(69) 0x40c1a3 ADD %R15,%RDX |
(69) 0x40c1a6 VCVTSI2SD %RDX,%XMM3,%XMM0 |
(69) 0x40c1ab IMUL %R13,%RDX |
(69) 0x40c1af MULX %RBX,%RAX,%RAX |
(69) 0x40c1b4 MOV %RDX,%R15 |
(69) 0x40c1b7 SUB %RAX,%R15 |
(69) 0x40c1ba SHR $0x1,%R15 |
(69) 0x40c1bd ADD %RAX,%R15 |
(69) 0x40c1c0 SHR $0x3c,%R15 |
(69) 0x40c1c4 MOV %R15,%RAX |
(69) 0x40c1c7 SAL $0x3d,%RAX |
(69) 0x40c1cb SUB %RAX,%R15 |
(69) 0x40c1ce ADD %RDX,%R15 |
(69) 0x40c1d1 VCVTSI2SD %R15,%XMM1,%XMM8 |
(69) 0x40c1d6 VFMADD213SD %XMM3,%XMM4,%XMM8 |
(69) 0x40c1db VMULSD %XMM8,%XMM8,%XMM2 |
(69) 0x40c1e0 VFMADD213SD %XMM3,%XMM4,%XMM0 |
(69) 0x40c1e5 VFMADD213SD %XMM2,%XMM0,%XMM0 |
(69) 0x40c1ea VUCOMISD %XMM5,%XMM0 |
(69) 0x40c1ee JAE 40c180 |
(69) 0x40c1f0 VUCOMISD %XMM6,%XMM0 |
(69) 0x40c1f4 JE 40c180 |
(72) 0x40c1f6 VMULSD %XMM7,%XMM1,%XMM1 |
(72) 0x40c1fa VMOVSD %XMM1,-0x58(%RBP) |
(72) 0x40c1ff VMOVSD %XMM0,-0x30(%RBP) |
(72) 0x40c204 VMOVSD %XMM8,-0x38(%RBP) |
(72) 0x40c209 CALL 413c70 <log> |
(72) 0x40c20e VXORPD %XMM5,%XMM5,%XMM5 |
(72) 0x40c212 VMOVSD 0x1e95e(%RIP),%XMM4 |
(72) 0x40c21a VMOVSD 0x19cfe(%RIP),%XMM3 |
(72) 0x40c222 VMOVSD 0x1e946(%RIP),%XMM2 |
(72) 0x40c22a VMULSD 0x19cf6(%RIP),%XMM0,%XMM0 |
(72) 0x40c232 VDIVSD -0x30(%RBP),%XMM0,%XMM0 |
(72) 0x40c237 VSQRTSD %XMM0,%XMM0,%XMM0 |
(72) 0x40c23b VMOVSD -0x38(%RBP),%XMM1 |
(72) 0x40c240 VMULSD -0x58(%RBP),%XMM1,%XMM1 |
(72) 0x40c245 VMULSD %XMM1,%XMM0,%XMM0 |
(72) 0x40c249 LEA (%R12,%R12,2),%R14 |
(72) 0x40c24d MOV -0x50(%RBP),%RAX |
(72) 0x40c251 VMOVSD %XMM0,(%RAX,%R14,8) |
(72) 0x40c257 NOPW (%RAX,%RAX,1) |
(70) 0x40c260 IMUL %R13,%R15 |
(70) 0x40c264 MOV %R15,%RDX |
(70) 0x40c267 MULX %RBX,%RAX,%RAX |
(70) 0x40c26c SUB %RAX,%RDX |
(70) 0x40c26f SHR $0x1,%RDX |
(70) 0x40c272 ADD %RAX,%RDX |
(70) 0x40c275 SHR $0x3c,%RDX |
(70) 0x40c279 MOV %RDX,%RAX |
(70) 0x40c27c SAL $0x3d,%RAX |
(70) 0x40c280 SUB %RAX,%RDX |
(70) 0x40c283 ADD %R15,%RDX |
(70) 0x40c286 VCVTSI2SD %RDX,%XMM7,%XMM0 |
(70) 0x40c28b IMUL %R13,%RDX |
(70) 0x40c28f MULX %RBX,%RAX,%RAX |
(70) 0x40c294 MOV %RDX,%R15 |
(70) 0x40c297 SUB %RAX,%R15 |
(70) 0x40c29a SHR $0x1,%R15 |
(70) 0x40c29d ADD %RAX,%R15 |
(70) 0x40c2a0 SHR $0x3c,%R15 |
(70) 0x40c2a4 MOV %R15,%RAX |
(70) 0x40c2a7 SAL $0x3d,%RAX |
(70) 0x40c2ab SUB %RAX,%R15 |
(70) 0x40c2ae ADD %RDX,%R15 |
(70) 0x40c2b1 VCVTSI2SD %R15,%XMM7,%XMM6 |
(70) 0x40c2b6 VFMADD213SD %XMM2,%XMM3,%XMM6 |
(70) 0x40c2bb VMULSD %XMM6,%XMM6,%XMM1 |
(70) 0x40c2bf VFMADD213SD %XMM2,%XMM3,%XMM0 |
(70) 0x40c2c4 VFMADD213SD %XMM1,%XMM0,%XMM0 |
(70) 0x40c2c9 VUCOMISD %XMM4,%XMM0 |
(70) 0x40c2cd JAE 40c260 |
(70) 0x40c2cf VUCOMISD %XMM5,%XMM0 |
(70) 0x40c2d3 JE 40c260 |
(72) 0x40c2d5 VMOVSD %XMM0,-0x30(%RBP) |
(72) 0x40c2da VMOVSD %XMM6,-0x38(%RBP) |
(72) 0x40c2df CALL 413c70 <log> |
(72) 0x40c2e4 VXORPD %XMM5,%XMM5,%XMM5 |
(72) 0x40c2e8 VMOVSD 0x1e888(%RIP),%XMM4 |
(72) 0x40c2f0 VMOVSD 0x19c28(%RIP),%XMM3 |
(72) 0x40c2f8 VMOVSD 0x1e870(%RIP),%XMM2 |
(72) 0x40c300 VMULSD 0x19c20(%RIP),%XMM0,%XMM0 |
(72) 0x40c308 VDIVSD -0x30(%RBP),%XMM0,%XMM0 |
(72) 0x40c30d VSQRTSD %XMM0,%XMM0,%XMM0 |
(72) 0x40c311 VMOVSD -0x38(%RBP),%XMM1 |
(72) 0x40c316 VMULSD -0x58(%RBP),%XMM1,%XMM1 |
(72) 0x40c31b VMULSD %XMM1,%XMM0,%XMM0 |
(72) 0x40c31f MOV -0x50(%RBP),%RAX |
(72) 0x40c323 VMOVSD %XMM0,0x8(%RAX,%R14,8) |
(72) 0x40c32a NOPW (%RAX,%RAX,1) |
(71) 0x40c330 IMUL %R13,%R15 |
(71) 0x40c334 MOV %R15,%RDX |
(71) 0x40c337 MULX %RBX,%RAX,%RAX |
(71) 0x40c33c SUB %RAX,%RDX |
(71) 0x40c33f SHR $0x1,%RDX |
(71) 0x40c342 ADD %RAX,%RDX |
(71) 0x40c345 SHR $0x3c,%RDX |
(71) 0x40c349 MOV %RDX,%RAX |
(71) 0x40c34c SAL $0x3d,%RAX |
(71) 0x40c350 SUB %RAX,%RDX |
(71) 0x40c353 ADD %R15,%RDX |
(71) 0x40c356 VCVTSI2SD %RDX,%XMM7,%XMM0 |
(71) 0x40c35b IMUL %R13,%RDX |
(71) 0x40c35f MULX %RBX,%RAX,%RAX |
(71) 0x40c364 MOV %RDX,%R15 |
(71) 0x40c367 SUB %RAX,%R15 |
(71) 0x40c36a SHR $0x1,%R15 |
(71) 0x40c36d ADD %RAX,%R15 |
(71) 0x40c370 SHR $0x3c,%R15 |
(71) 0x40c374 MOV %R15,%RAX |
(71) 0x40c377 SAL $0x3d,%RAX |
(71) 0x40c37b SUB %RAX,%R15 |
(71) 0x40c37e ADD %RDX,%R15 |
(71) 0x40c381 VCVTSI2SD %R15,%XMM7,%XMM6 |
(71) 0x40c386 VFMADD213SD %XMM2,%XMM3,%XMM6 |
(71) 0x40c38b VMULSD %XMM6,%XMM6,%XMM1 |
(71) 0x40c38f VFMADD213SD %XMM2,%XMM3,%XMM0 |
(71) 0x40c394 VFMADD213SD %XMM1,%XMM0,%XMM0 |
(71) 0x40c399 VUCOMISD %XMM4,%XMM0 |
(71) 0x40c39d JAE 40c330 |
(71) 0x40c39f VUCOMISD %XMM5,%XMM0 |
(71) 0x40c3a3 JE 40c330 |
(72) 0x40c3a5 VMOVSD %XMM0,-0x30(%RBP) |
(72) 0x40c3aa VMOVSD %XMM6,-0x38(%RBP) |
(72) 0x40c3af CALL 413c70 <log> |
(72) 0x40c3b4 VXORPD %XMM6,%XMM6,%XMM6 |
(72) 0x40c3b8 VMOVSD 0x1e7b8(%RIP),%XMM5 |
(72) 0x40c3c0 VMOVSD 0x19b58(%RIP),%XMM4 |
(72) 0x40c3c8 VMOVSD 0x1e7a0(%RIP),%XMM3 |
(72) 0x40c3d0 VMULSD 0x19b50(%RIP),%XMM0,%XMM0 |
(72) 0x40c3d8 VDIVSD -0x30(%RBP),%XMM0,%XMM0 |
(72) 0x40c3dd VSQRTSD %XMM0,%XMM0,%XMM0 |
(72) 0x40c3e1 VMOVSD -0x38(%RBP),%XMM1 |
(72) 0x40c3e6 VMULSD -0x58(%RBP),%XMM1,%XMM1 |
(72) 0x40c3eb VMULSD %XMM1,%XMM0,%XMM0 |
(72) 0x40c3ef MOV -0x50(%RBP),%RAX |
(72) 0x40c3f3 VMOVSD %XMM0,0x10(%RAX,%R14,8) |
(72) 0x40c3fa MOV -0x64(%RBP),%EAX |
(72) 0x40c3fd INC %EAX |
(72) 0x40c3ff INC %R12 |
(72) 0x40c402 CMP -0x60(%RBP),%EAX |
(72) 0x40c405 JNE 40bfb0 |
(68) 0x40c40b JMP 40bf40 |
0x40c410 NOPW %CS:(%RAX,%RAX,1) |
0x40c41a NOPW %CS:(%RAX,%RAX,1) |
0x40c424 NOPW %CS:(%RAX,%RAX,1) |
0x40c42e NOPW %CS:(%RAX,%RAX,1) |
0x40c438 NOPL (%RAX,%RAX,1) |
Path / |
Source file and lines | initAtoms.c:151-162 |
Module | exec |
nb instructions | 73 |
nb uops | 76 |
loop length | 368 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 5 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 12.67 cycles |
front end | 12.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 2.70 | 6.00 | 6.00 | 10.50 | 2.60 | 2.60 | 10.50 | 10.50 | 10.50 | 2.60 | 6.00 |
cycles | 2.50 | 2.70 | 6.00 | 6.00 | 10.50 | 2.60 | 2.60 | 10.50 | 10.50 | 10.50 | 2.60 | 6.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 12.69-12.74 |
Stall cycles | 0.00 |
Front-end | 12.67 |
Dispatch | 10.50 |
Overall L1 | 12.67 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 16% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 3% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
all | 8% |
load | 6% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 14% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 10% |
load | 9% |
store | 8% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x88,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0,-0x6c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,-0x44(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9D,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x68(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x6c(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x44(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x40(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x631690,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,-0x5c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 403120 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x44(%RBP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x80(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EAX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 40bec0 <setTemperature.extracted.30+0xc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x6316b0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x5c(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x88,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 402fe0 <__kmpc_for_static_fini@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVQ %R15,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV -0x78(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMULSD 0x1a043(%RIP),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM0,-0x98(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x6,%EDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %EDX,-0x3c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INCQ -0x80(%RBP) | 3 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV 0x78(%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x88(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x613606df9756715,%R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
MOV $0x9,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVSD 0x1ec65(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x1a00d(%RIP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x1ec5d(%RIP),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM6,%XMM6,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40bf58 <setTemperature.extracted.30+0x158> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | initAtoms.c:151-162 |
Module | exec |
nb instructions | 73 |
nb uops | 76 |
loop length | 368 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 5 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 12.67 cycles |
front end | 12.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 2.70 | 6.00 | 6.00 | 10.50 | 2.60 | 2.60 | 10.50 | 10.50 | 10.50 | 2.60 | 6.00 |
cycles | 2.50 | 2.70 | 6.00 | 6.00 | 10.50 | 2.60 | 2.60 | 10.50 | 10.50 | 10.50 | 2.60 | 6.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 12.69-12.74 |
Stall cycles | 0.00 |
Front-end | 12.67 |
Dispatch | 10.50 |
Overall L1 | 12.67 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 16% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 3% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
all | 8% |
load | 6% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 14% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 10% |
load | 9% |
store | 8% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x88,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,-0x78(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0,-0x6c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,-0x44(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9D,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x68(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x6c(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x44(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x40(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x631690,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,-0x5c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 403120 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x44(%RBP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x40(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x80(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EAX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 40bec0 <setTemperature.extracted.30+0xc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x6316b0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x5c(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x88,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 402fe0 <__kmpc_for_static_fini@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVQ %R15,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV -0x78(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMULSD 0x1a043(%RIP),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM0,-0x98(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x6,%EDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %EDX,-0x3c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INCQ -0x80(%RBP) | 3 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV 0x78(%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x88(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x613606df9756715,%R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
MOV $0x9,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVSD 0x1ec65(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x1a00d(%RIP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x1ec5d(%RIP),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM6,%XMM6,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40bf58 <setTemperature.extracted.30+0x158> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼setTemperature.extracted.30– | 0.02 | 0 |
▼Loop 68 - initAtoms.c:151-162 - exec– | 0 | 0 |
▼Loop 72 - initAtoms.c:154-162 - exec– | 0.01 | 0 |
○Loop 69 - random.c:27-48 - exec | 0.01 | 0 |
○Loop 71 - random.c:27-48 - exec | 0 | 0 |
○Loop 70 - random.c:27-48 - exec | 0 | 0 |