Loop Id: 98 | Module: exec | Source: timestep.c:71-78 | Coverage: 0.1% |
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Loop Id: 98 | Module: exec | Source: timestep.c:71-78 | Coverage: 0.1% |
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0x412ec0 SAL $0x3,%R9 |
0x412ec4 LEA (%R9,%R9,2),%R9 |
0x412ec8 VMOVSD (%R8,%R9,1),%XMM1 |
0x412ece VFMADD213SD (%RDI,%R9,1),%XMM0,%XMM1 |
0x412ed4 VMOVSD %XMM1,(%RDI,%R9,1) |
0x412eda VMOVSD 0x8(%R8,%R9,1),%XMM1 |
0x412ee1 VFMADD213SD 0x8(%RDI,%R9,1),%XMM0,%XMM1 |
0x412ee8 VMOVSD %XMM1,0x8(%RDI,%R9,1) |
0x412eef VMOVSD 0x10(%R8,%R9,1),%XMM1 |
0x412ef6 VFMADD213SD 0x10(%RDI,%R9,1),%XMM0,%XMM1 |
0x412efd VMOVSD %XMM1,0x10(%RDI,%R9,1) |
0x412f04 INC %RAX |
0x412f07 ADD $0x40,%ESI |
0x412f0a CMP %RCX,%RAX |
0x412f0d JE 412e68 |
0x412f13 MOV (%RDX,%RAX,4),%R10D |
0x412f17 TEST %R10D,%R10D |
0x412f1a JLE 412f04 |
0x412f1c MOV %ESI,%R9D |
0x412f1f MOV 0x20(%RBX),%R8 |
0x412f23 MOV 0x20(%R8),%RDI |
0x412f27 MOV 0x28(%R8),%R8 |
0x412f2b CMP $0x1,%R10D |
0x412f2f JE 412ec0 |
0x412f31 LEA (%R9,%R9,2),%R11 |
0x412f35 LEA 0x28(,%R11,8),%R11 |
0x412f3d MOV %R10D,%R15D |
0x412f40 AND $-0x2,%R15D |
0x412f44 NOPW %CS:(%RAX,%RAX,1) |
(99) 0x412f50 VMOVSD -0x28(%R8,%R11,1),%XMM1 |
(99) 0x412f57 VFMADD213SD -0x28(%RDI,%R11,1),%XMM0,%XMM1 |
(99) 0x412f5e VMOVSD %XMM1,-0x28(%RDI,%R11,1) |
(99) 0x412f65 VMOVSD -0x20(%R8,%R11,1),%XMM1 |
(99) 0x412f6c VFMADD213SD -0x20(%RDI,%R11,1),%XMM0,%XMM1 |
(99) 0x412f73 VMOVSD %XMM1,-0x20(%RDI,%R11,1) |
(99) 0x412f7a VMOVSD -0x18(%R8,%R11,1),%XMM1 |
(99) 0x412f81 VFMADD213SD -0x18(%RDI,%R11,1),%XMM0,%XMM1 |
(99) 0x412f88 VMOVSD %XMM1,-0x18(%RDI,%R11,1) |
(99) 0x412f8f VMOVSD -0x10(%R8,%R11,1),%XMM1 |
(99) 0x412f96 VFMADD213SD -0x10(%RDI,%R11,1),%XMM0,%XMM1 |
(99) 0x412f9d VMOVSD %XMM1,-0x10(%RDI,%R11,1) |
(99) 0x412fa4 VMOVSD -0x8(%R8,%R11,1),%XMM1 |
(99) 0x412fab VFMADD213SD -0x8(%RDI,%R11,1),%XMM0,%XMM1 |
(99) 0x412fb2 VMOVSD %XMM1,-0x8(%RDI,%R11,1) |
(99) 0x412fb9 VMOVSD (%R8,%R11,1),%XMM1 |
(99) 0x412fbf VFMADD213SD (%RDI,%R11,1),%XMM0,%XMM1 |
(99) 0x412fc5 VMOVSD %XMM1,(%RDI,%R11,1) |
(99) 0x412fcb ADD $0x2,%R9 |
(99) 0x412fcf ADD $0x30,%R11 |
(99) 0x412fd3 ADD $-0x2,%R15D |
(99) 0x412fd7 JNE 412f50 |
0x412fdd TEST $0x1,%R10B |
0x412fe1 JNE 412ec0 |
0x412fe7 JMP 412f04 |
/scratch_na/users/xoserete/qaas_runs/171-172-4338/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 78 |
-------------------------------------------------------------------------------- |
71: #pragma omp parallel for |
72: for (int iBox=0; iBox<nBoxes; iBox++) |
73: { |
74: for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++) |
75: { |
76: s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0]; |
77: s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1]; |
78: s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2]; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.41 |
CQA speedup if FP arith vectorized | 1.54 |
CQA speedup if fully vectorized | 12.43 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.49 |
Bottlenecks | |
Function | advanceVelocity.extracted |
Source | timestep.c:71-78 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 3.58 |
CQA cycles if no scalar integer | 2.54 |
CQA cycles if FP arith vectorized | 2.33 |
CQA cycles if fully vectorized | 0.29 |
Front-end cycles | 3.58 |
DIV/SQRT cycles | 2.38 |
P0 cycles | 1.60 |
P1 cycles | 2.08 |
P2 cycles | 2.08 |
P3 cycles | 0.75 |
P4 cycles | 1.60 |
P5 cycles | 2.13 |
P6 cycles | 0.75 |
P7 cycles | 0.75 |
P8 cycles | 0.75 |
P9 cycles | 1.55 |
P10 cycles | 2.08 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 3.98 - 3.95 |
Stall cycles (UFS) | 0.22 - 0.20 |
Nb insns | 20.75 |
Nb uops | 20.00 |
Nb loads | 6.25 |
Nb stores | 1.50 |
Nb stack references | 0.00 |
FLOP/cycle | 0.84 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 1.50 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 13.31 |
Bytes prefetched | 0.00 |
Bytes loaded | 46.00 |
Bytes stored | 12.00 |
Stride 0 | 0.75 |
Stride 1 | 2.00 |
Stride n | 1.00 |
Stride unknown | 0.00 |
Stride indirect | 0.75 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 9.82 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 6.25 |
Vector-efficiency ratio fma | 12.50 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 9.22 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 13.33 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.25 |
Bottlenecks | micro-operation queue, P0, P6, |
Function | advanceVelocity.extracted |
Source | timestep.c:71-78 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 1.00 |
CQA cycles if no scalar integer | 1.00 |
CQA cycles if FP arith vectorized | 1.00 |
CQA cycles if fully vectorized | 0.07 |
Front-end cycles | 1.00 |
DIV/SQRT cycles | 1.00 |
P0 cycles | 0.80 |
P1 cycles | 0.33 |
P2 cycles | 0.33 |
P3 cycles | 0.00 |
P4 cycles | 0.60 |
P5 cycles | 1.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.60 |
P10 cycles | 0.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 1.09 |
Stall cycles (UFS) | 0.00 |
Nb insns | 7.00 |
Nb uops | 6.00 |
Nb loads | 1.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 4.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 4.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 1.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 9.38 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 6.25 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.62 |
CQA speedup if FP arith vectorized | 1.97 |
CQA speedup if fully vectorized | 11.29 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.30 |
Bottlenecks | micro-operation queue, |
Function | advanceVelocity.extracted |
Source | timestep.c:71-78 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 4.33 |
CQA cycles if no scalar integer | 2.67 |
CQA cycles if FP arith vectorized | 2.20 |
CQA cycles if fully vectorized | 0.38 |
Front-end cycles | 4.33 |
DIV/SQRT cycles | 3.00 |
P0 cycles | 1.50 |
P1 cycles | 3.33 |
P2 cycles | 3.33 |
P3 cycles | 1.50 |
P4 cycles | 1.60 |
P5 cycles | 2.50 |
P6 cycles | 1.50 |
P7 cycles | 1.50 |
P8 cycles | 1.50 |
P9 cycles | 1.40 |
P10 cycles | 3.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 5.46 - 5.33 |
Stall cycles (UFS) | 0.89 - 0.79 |
Nb insns | 24.00 |
Nb uops | 23.00 |
Nb loads | 10.00 |
Nb stores | 3.00 |
Nb stack references | 0.00 |
FLOP/cycle | 1.38 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 3.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 23.08 |
Bytes prefetched | 0.00 |
Bytes loaded | 76.00 |
Bytes stored | 24.00 |
Stride 0 | 1.00 |
Stride 1 | 1.00 |
Stride n | 2.00 |
Stride unknown | 0.00 |
Stride indirect | 1.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 11.46 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 6.25 |
Vector-efficiency ratio fma | 12.50 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 9.38 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 14.61 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.75 |
Bottlenecks | micro-operation queue, |
Function | advanceVelocity.extracted |
Source | timestep.c:71-78 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 3.50 |
CQA cycles if no scalar integer | 3.50 |
CQA cycles if FP arith vectorized | 3.50 |
CQA cycles if fully vectorized | 0.24 |
Front-end cycles | 3.50 |
DIV/SQRT cycles | 2.00 |
P0 cycles | 2.00 |
P1 cycles | 1.33 |
P2 cycles | 1.33 |
P3 cycles | 0.00 |
P4 cycles | 2.00 |
P5 cycles | 2.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 2.00 |
P10 cycles | 1.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 3.63 |
Stall cycles (UFS) | 0.00 |
Nb insns | 21.00 |
Nb uops | 21.00 |
Nb loads | 4.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 8.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 28.00 |
Bytes stored | 0.00 |
Stride 0 | 1.00 |
Stride 1 | 3.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 1.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 8.04 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 6.25 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 7.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.83 |
CQA speedup if FP arith vectorized | 2.09 |
CQA speedup if fully vectorized | 12.10 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.57 |
Bottlenecks | micro-operation queue, |
Function | advanceVelocity.extracted |
Source | timestep.c:71-78 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 5.50 |
CQA cycles if no scalar integer | 3.00 |
CQA cycles if FP arith vectorized | 2.63 |
CQA cycles if fully vectorized | 0.45 |
Front-end cycles | 5.50 |
DIV/SQRT cycles | 3.50 |
P0 cycles | 2.10 |
P1 cycles | 3.33 |
P2 cycles | 3.33 |
P3 cycles | 1.50 |
P4 cycles | 2.20 |
P5 cycles | 3.00 |
P6 cycles | 1.50 |
P7 cycles | 1.50 |
P8 cycles | 1.50 |
P9 cycles | 2.20 |
P10 cycles | 3.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 5.75 - 5.76 |
Stall cycles (UFS) | 0.00 - 0.01 |
Nb insns | 31.00 |
Nb uops | 30.00 |
Nb loads | 10.00 |
Nb stores | 3.00 |
Nb stack references | 0.00 |
FLOP/cycle | 1.09 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 3.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 18.18 |
Bytes prefetched | 0.00 |
Bytes loaded | 76.00 |
Bytes stored | 24.00 |
Stride 0 | 1.00 |
Stride 1 | 3.00 |
Stride n | 2.00 |
Stride unknown | 0.00 |
Stride indirect | 1.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 10.42 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 6.25 |
Vector-efficiency ratio fma | 12.50 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 7.50 |
Path / |
Function | advanceVelocity.extracted |
Source file and lines | timestep.c:71-78 |
Module | exec |
nb instructions | 20.75 |
nb uops | 20 |
loop length | 95.50 |
used x86 registers | 9 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 3.58 cycles |
front end | 3.58 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.38 | 1.60 | 2.08 | 2.08 | 0.75 | 1.60 | 2.13 | 0.75 | 0.75 | 0.75 | 1.55 | 2.08 |
cycles | 2.38 | 1.60 | 2.08 | 2.08 | 0.75 | 1.60 | 2.13 | 0.75 | 0.75 | 0.75 | 1.55 | 2.08 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 3.98-3.95 |
Stall cycles | 0.22-0.20 |
LM full (events) | 0.35-0.32 |
Front-end | 3.58 |
Dispatch | 2.46 |
Data deps. | 1.00 |
Overall L1 | 3.58 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 8% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 12% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 9% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | 12% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 9% |
Function | advanceVelocity.extracted |
Source file and lines | timestep.c:71-78 |
Module | exec |
nb instructions | 7 |
nb uops | 6 |
loop length | 24 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 1.00 cycles |
front end | 1.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.00 | 0.80 | 0.33 | 0.33 | 0.00 | 0.60 | 1.00 | 0.00 | 0.00 | 0.00 | 0.60 | 0.33 |
cycles | 1.00 | 0.80 | 0.33 | 0.33 | 0.00 | 0.60 | 1.00 | 0.00 | 0.00 | 0.00 | 0.60 | 0.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 1.09 |
Stall cycles | 0.00 |
Front-end | 1.00 |
Dispatch | 1.00 |
Data deps. | 1.00 |
Overall L1 | 1.00 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 9% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x40,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 412e68 <advanceVelocity.extracted+0x68> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%RDX,%RAX,4),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R10D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 412f04 <advanceVelocity.extracted+0x104> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | advanceVelocity.extracted |
Source file and lines | timestep.c:71-78 |
Module | exec |
nb instructions | 24 |
nb uops | 23 |
loop length | 113 |
used x86 registers | 9 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 4.33 cycles |
front end | 4.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.00 | 1.50 | 3.33 | 3.33 | 1.50 | 1.60 | 2.50 | 1.50 | 1.50 | 1.50 | 1.40 | 3.33 |
cycles | 3.00 | 1.50 | 3.33 | 3.33 | 1.50 | 1.60 | 2.50 | 1.50 | 1.50 | 1.50 | 1.40 | 3.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 5.46-5.33 |
Stall cycles | 0.89-0.79 |
LM full (events) | 1.40-1.24 |
Front-end | 4.33 |
Dispatch | 3.33 |
Data deps. | 1.00 |
Overall L1 | 4.33 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 8% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 12% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 11% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | 12% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SAL $0x3,%R9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R9,%R9,2),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD (%R8,%R9,1),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VFMADD213SD (%RDI,%R9,1),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM1,(%RDI,%R9,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x8(%R8,%R9,1),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VFMADD213SD 0x8(%RDI,%R9,1),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM1,0x8(%RDI,%R9,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x10(%R8,%R9,1),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VFMADD213SD 0x10(%RDI,%R9,1),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM1,0x10(%RDI,%R9,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x40,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 412e68 <advanceVelocity.extracted+0x68> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%RDX,%RAX,4),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R10D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 412f04 <advanceVelocity.extracted+0x104> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ESI,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x20(%RBX),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R8),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%R8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP $0x1,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 412ec0 <advanceVelocity.extracted+0xc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | advanceVelocity.extracted |
Source file and lines | timestep.c:71-78 |
Module | exec |
nb instructions | 21 |
nb uops | 21 |
loop length | 91 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 3.50 cycles |
front end | 3.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.00 | 2.00 | 1.33 | 1.33 | 0.00 | 2.00 | 2.00 | 0.00 | 0.00 | 0.00 | 2.00 | 1.33 |
cycles | 2.00 | 2.00 | 1.33 | 1.33 | 0.00 | 2.00 | 2.00 | 0.00 | 0.00 | 0.00 | 2.00 | 1.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 3.63 |
Stall cycles | 0.00 |
Front-end | 3.50 |
Dispatch | 2.00 |
Data deps. | 1.00 |
Overall L1 | 3.50 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 8% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 7% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x40,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 412e68 <advanceVelocity.extracted+0x68> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%RDX,%RAX,4),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R10D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 412f04 <advanceVelocity.extracted+0x104> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ESI,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x20(%RBX),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R8),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%R8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP $0x1,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 412ec0 <advanceVelocity.extracted+0xc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%R9,%R9,2),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x28(,%R11,8),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R10D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x2,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
TEST $0x1,%R10B | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 412ec0 <advanceVelocity.extracted+0xc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 412f04 <advanceVelocity.extracted+0x104> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Function | advanceVelocity.extracted |
Source file and lines | timestep.c:71-78 |
Module | exec |
nb instructions | 31 |
nb uops | 30 |
loop length | 154 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 5.50 cycles |
front end | 5.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.50 | 2.10 | 3.33 | 3.33 | 1.50 | 2.20 | 3.00 | 1.50 | 1.50 | 1.50 | 2.20 | 3.33 |
cycles | 3.50 | 2.10 | 3.33 | 3.33 | 1.50 | 2.20 | 3.00 | 1.50 | 1.50 | 1.50 | 2.20 | 3.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 5.75-5.76 |
Stall cycles | 0.00-0.01 |
LM full (events) | 0.01-0.03 |
Front-end | 5.50 |
Dispatch | 3.50 |
Data deps. | 1.00 |
Overall L1 | 5.50 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 7% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 7% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 12% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 10% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | 12% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 7% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SAL $0x3,%R9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R9,%R9,2),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD (%R8,%R9,1),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VFMADD213SD (%RDI,%R9,1),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM1,(%RDI,%R9,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x8(%R8,%R9,1),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VFMADD213SD 0x8(%RDI,%R9,1),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM1,0x8(%RDI,%R9,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x10(%R8,%R9,1),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VFMADD213SD 0x10(%RDI,%R9,1),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM1,0x10(%RDI,%R9,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x40,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 412e68 <advanceVelocity.extracted+0x68> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%RDX,%RAX,4),%R10D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R10D,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 412f04 <advanceVelocity.extracted+0x104> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ESI,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x20(%RBX),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R8),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%R8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP $0x1,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 412ec0 <advanceVelocity.extracted+0xc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%R9,%R9,2),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x28(,%R11,8),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R10D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x2,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
TEST $0x1,%R10B | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 412ec0 <advanceVelocity.extracted+0xc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |