Loop Id: 67 | Module: exec | Source: initAtoms.c:221-228 | Coverage: 0.01% |
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Loop Id: 67 | Module: exec | Source: initAtoms.c:221-228 | Coverage: 0.01% |
---|
0x409070 LEA (%RSI,%RBX,1),%RDX |
0x409074 VMOVQ %RDX,%XMM9 |
0x409079 VPSLLQ $0x3,%XMM9,%XMM10 |
0x40907f VPSLLQ $0x4,%XMM9,%XMM9 |
0x409085 VPADDQ %XMM10,%XMM9,%XMM9 |
0x40908a VPADDQ %XMM6,%XMM9,%XMM9 |
0x40908e VMOVQ %XMM9,%RDX |
0x409093 VMOVUPD 0x20(%RDX),%YMM9 [2] |
0x409098 VBLENDPD $0x3,(%RDX),%YMM9,%YMM10 [2] |
0x40909e VMOVUPD 0x10(%RDX),%XMM11 [2] |
0x4090a3 VMOVUPD 0x20(%RDX),%XMM12 [2] |
0x4090a8 VINSERTF128 $0x1,0x40(%RDX),%YMM11,%YMM11 [2] |
0x4090af VBLENDPD $0xa,%YMM11,%YMM10,%YMM13 |
0x4090b5 VSHUFPD $0x5,%YMM9,%YMM10,%YMM9 |
0x4090bb VBROADCASTSD 0x50(%RDX),%YMM10 [2] |
0x4090c1 VBLENDPD $0x8,%YMM10,%YMM9,%YMM9 |
0x4090c7 VBLENDPD $0xc,0x40(%RDX),%YMM12,%YMM10 [2] |
0x4090ce VBLENDPD $0xa,%YMM10,%YMM11,%YMM10 |
0x4090d4 VPMOVSXDQ (%R13,%RBX,4),%YMM11 [1] |
0x4090db VPSLLQ $0x4,%YMM11,%YMM11 |
0x4090e1 VXORPD %XMM12,%XMM12,%XMM12 |
0x4090e6 KXNORW %K0,%K0,%K1 |
0x4090ea VGATHERQPD 0x8(%R9,%YMM11,1),%YMM12{%K1} [3] |
0x4090f2 VADDPD %YMM8,%YMM13,%YMM8 |
0x4090f7 VADDPD %YMM7,%YMM9,%YMM7 |
0x4090fb VADDPD %YMM5,%YMM10,%YMM5 |
0x4090ff VADDPD %YMM4,%YMM12,%YMM4 |
0x409103 ADD $0x4,%RBX |
0x409107 CMP %R15D,%EBX |
0x40910a JLE 409070 |
/scratch_na/users/xoserete/qaas_runs/171-172-4338/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 221 - 228 |
-------------------------------------------------------------------------------- |
221: for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff) |
222: { |
223: v0 += s->atoms->p[iOff][0]; |
224: v1 += s->atoms->p[iOff][1]; |
225: v2 += s->atoms->p[iOff][2]; |
226: |
227: int iSpecies = s->atoms->iSpecies[iOff]; |
228: v3 += s->species[iSpecies].mass; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.04 |
CQA speedup if FP arith vectorized | 1.19 |
CQA speedup if fully vectorized | 2.58 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.02 |
Bottlenecks | P0, |
Function | computeVcm.extracted |
Source | initAtoms.c:221-228 |
Source loop unroll info | unrolled by 4 |
Source loop unroll confidence level | medium |
Unroll/vectorization loop type | main |
Unroll factor | 4 |
CQA cycles | 7.83 |
CQA cycles if no scalar integer | 7.50 |
CQA cycles if FP arith vectorized | 6.58 |
CQA cycles if fully vectorized | 3.04 |
Front-end cycles | 6.17 |
DIV/SQRT cycles | 7.83 |
P0 cycles | 7.67 |
P1 cycles | 4.00 |
P2 cycles | 4.00 |
P3 cycles | 0.00 |
P4 cycles | 7.50 |
P5 cycles | 1.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 4.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 3 |
FE+BE cycles (UFS) | 11.29 - 14.12 |
Stall cycles (UFS) | 5.21 - 7.66 |
Nb insns | 30.00 |
Nb uops | 37.00 |
Nb loads | 9.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 2.04 |
Nb FLOP add-sub | 16.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 25.53 |
Bytes prefetched | 0.00 |
Bytes loaded | 200.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 1.00 |
Stride n | 1.00 |
Stride unknown | 0.00 |
Stride indirect | 1.00 |
Vectorization ratio all | 88.00 |
Vectorization ratio load | 88.89 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 80.00 |
Vector-efficiency ratio all | 36.50 |
Vector-efficiency ratio load | 34.72 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 41.67 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 35.83 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.04 |
CQA speedup if FP arith vectorized | 1.19 |
CQA speedup if fully vectorized | 2.58 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.02 |
Bottlenecks | P0, |
Function | computeVcm.extracted |
Source | initAtoms.c:221-228 |
Source loop unroll info | unrolled by 4 |
Source loop unroll confidence level | medium |
Unroll/vectorization loop type | main |
Unroll factor | 4 |
CQA cycles | 7.83 |
CQA cycles if no scalar integer | 7.50 |
CQA cycles if FP arith vectorized | 6.58 |
CQA cycles if fully vectorized | 3.04 |
Front-end cycles | 6.17 |
DIV/SQRT cycles | 7.83 |
P0 cycles | 7.67 |
P1 cycles | 4.00 |
P2 cycles | 4.00 |
P3 cycles | 0.00 |
P4 cycles | 7.50 |
P5 cycles | 1.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 4.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 3 |
FE+BE cycles (UFS) | 11.29 - 14.12 |
Stall cycles (UFS) | 5.21 - 7.66 |
Nb insns | 30.00 |
Nb uops | 37.00 |
Nb loads | 9.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 2.04 |
Nb FLOP add-sub | 16.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 25.53 |
Bytes prefetched | 0.00 |
Bytes loaded | 200.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 1.00 |
Stride n | 1.00 |
Stride unknown | 0.00 |
Stride indirect | 1.00 |
Vectorization ratio all | 88.00 |
Vectorization ratio load | 88.89 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 80.00 |
Vector-efficiency ratio all | 36.50 |
Vector-efficiency ratio load | 34.72 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 41.67 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 35.83 |
Path / |
Function | computeVcm.extracted |
Source file and lines | initAtoms.c:221-228 |
Module | exec |
nb instructions | 30 |
nb uops | 37 |
loop length | 160 |
used x86 registers | 6 |
used mmx registers | 0 |
used xmm registers | 5 |
used ymm registers | 9 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 6.17 cycles |
front end | 6.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.83 | 7.67 | 4.00 | 4.00 | 0.00 | 7.50 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 4.00 |
cycles | 7.83 | 7.67 | 4.00 | 4.00 | 0.00 | 7.50 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 4.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 3.00 |
FE+BE cycles | 11.29-14.12 |
Stall cycles | 5.21-7.66 |
LM full (events) | 6.83-9.61 |
Front-end | 6.17 |
Dispatch | 7.83 |
Data deps. | 3.00 |
Overall L1 | 7.83 |
all | 75% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 60% |
all | 94% |
load | 87% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 90% |
all | 88% |
load | 88% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 80% |
all | 25% |
load | 25% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 25% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 25% |
all | 41% |
load | 35% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 41% |
all | 36% |
load | 34% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 41% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 35% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LEA (%RSI,%RBX,1),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVQ %RDX,%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VPSLLQ $0x3,%XMM9,%XMM10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 |
VPSLLQ $0x4,%XMM9,%XMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 |
VPADDQ %XMM10,%XMM9,%XMM9 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPADDQ %XMM6,%XMM9,%XMM9 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMOVQ %XMM9,%RDX | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VMOVUPD 0x20(%RDX),%YMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VBLENDPD $0x3,(%RDX),%YMM9,%YMM10 | 2 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVUPD 0x10(%RDX),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x20(%RDX),%XMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VINSERTF128 $0x1,0x40(%RDX),%YMM11,%YMM11 | 2 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBLENDPD $0xa,%YMM11,%YMM10,%YMM13 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VSHUFPD $0x5,%YMM9,%YMM10,%YMM9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD 0x50(%RDX),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBLENDPD $0x8,%YMM10,%YMM9,%YMM9 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VBLENDPD $0xc,0x40(%RDX),%YMM12,%YMM10 | 2 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VBLENDPD $0xa,%YMM10,%YMM11,%YMM10 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPMOVSXDQ (%R13,%RBX,4),%YMM11 | 2 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
VPSLLQ $0x4,%YMM11,%YMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 |
VXORPD %XMM12,%XMM12,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD 0x8(%R9,%YMM11,1),%YMM12{%K1} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VADDPD %YMM8,%YMM13,%YMM8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPD %YMM7,%YMM9,%YMM7 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPD %YMM5,%YMM10,%YMM5 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPD %YMM4,%YMM12,%YMM4 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
ADD $0x4,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 409070 <computeVcm.extracted+0x1f0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | computeVcm.extracted |
Source file and lines | initAtoms.c:221-228 |
Module | exec |
nb instructions | 30 |
nb uops | 37 |
loop length | 160 |
used x86 registers | 6 |
used mmx registers | 0 |
used xmm registers | 5 |
used ymm registers | 9 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 6.17 cycles |
front end | 6.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 7.83 | 7.67 | 4.00 | 4.00 | 0.00 | 7.50 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 4.00 |
cycles | 7.83 | 7.67 | 4.00 | 4.00 | 0.00 | 7.50 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 4.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 3.00 |
FE+BE cycles | 11.29-14.12 |
Stall cycles | 5.21-7.66 |
LM full (events) | 6.83-9.61 |
Front-end | 6.17 |
Dispatch | 7.83 |
Data deps. | 3.00 |
Overall L1 | 7.83 |
all | 75% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 60% |
all | 94% |
load | 87% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 90% |
all | 88% |
load | 88% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 80% |
all | 25% |
load | 25% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 25% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 25% |
all | 41% |
load | 35% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 41% |
all | 36% |
load | 34% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 41% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 35% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LEA (%RSI,%RBX,1),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVQ %RDX,%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VPSLLQ $0x3,%XMM9,%XMM10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 |
VPSLLQ $0x4,%XMM9,%XMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 |
VPADDQ %XMM10,%XMM9,%XMM9 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPADDQ %XMM6,%XMM9,%XMM9 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMOVQ %XMM9,%RDX | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VMOVUPD 0x20(%RDX),%YMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VBLENDPD $0x3,(%RDX),%YMM9,%YMM10 | 2 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVUPD 0x10(%RDX),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x20(%RDX),%XMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VINSERTF128 $0x1,0x40(%RDX),%YMM11,%YMM11 | 2 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBLENDPD $0xa,%YMM11,%YMM10,%YMM13 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VSHUFPD $0x5,%YMM9,%YMM10,%YMM9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD 0x50(%RDX),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBLENDPD $0x8,%YMM10,%YMM9,%YMM9 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VBLENDPD $0xc,0x40(%RDX),%YMM12,%YMM10 | 2 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VBLENDPD $0xa,%YMM10,%YMM11,%YMM10 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPMOVSXDQ (%R13,%RBX,4),%YMM11 | 2 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
VPSLLQ $0x4,%YMM11,%YMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 |
VXORPD %XMM12,%XMM12,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VGATHERQPD 0x8(%R9,%YMM11,1),%YMM12{%K1} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VADDPD %YMM8,%YMM13,%YMM8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPD %YMM7,%YMM9,%YMM7 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPD %YMM5,%YMM10,%YMM5 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPD %YMM4,%YMM12,%YMM4 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
ADD $0x4,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 409070 <computeVcm.extracted+0x1f0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |