Function: ljForce._omp_fn.1 | Module: exec | Source: ljForce.c:172-216 [...] | Coverage: 62.91% |
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Function: ljForce._omp_fn.1 | Module: exec | Source: ljForce.c:172-216 [...] | Coverage: 62.91% |
---|
/scratch_na/users/xoserete/qaas_runs/171-172-4338/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 172 - 216 |
-------------------------------------------------------------------------------- |
172: #pragma omp parallel for reduction(+:ePot) |
173: for (int iBox=0; iBox<s->boxes->nLocalBoxes; iBox++) |
174: { |
175: int nIBox = s->boxes->nAtoms[iBox]; |
176: |
177: // loop over neighbors of iBox |
178: for (int jTmp=0; jTmp<nNbrBoxes; jTmp++) |
179: { |
180: int jBox = s->boxes->nbrBoxes[iBox][jTmp]; |
181: |
182: assert(jBox>=0); |
183: |
184: int nJBox = s->boxes->nAtoms[jBox]; |
185: |
186: // loop over atoms in iBox |
187: for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++) |
188: { |
189: |
190: // loop over atoms in jBox |
191: for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++) |
[...] |
197: dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m]; |
198: r2+=dr[m]*dr[m]; |
199: } |
200: |
201: if ( r2 <= rCut2 && r2 > 0.0) |
202: { |
203: |
204: // Important note: |
205: // from this point on r actually refers to 1.0/r |
206: r2 = 1.0/r2; |
207: real_t r6 = s6 * (r2*r2*r2); |
208: real_t eLocal = r6 * (r6 - 1.0) - eShift; |
209: s->atoms->U[iOff] += 0.5*eLocal; |
210: ePot += 0.5*eLocal; |
211: |
212: // different formulation to avoid sqrt computation |
213: real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0); |
214: for (int m=0; m<3; m++) |
215: { |
216: s->atoms->f[iOff][m] -= dr[m]*fr; |
0x406120 PUSH %RBP |
0x406121 MOV %RSP,%RBP |
0x406124 PUSH %R15 |
0x406126 PUSH %R14 |
0x406128 PUSH %R13 |
0x40612a PUSH %R12 |
0x40612c MOV %RDI,%R12 |
0x40612f PUSH %RBX |
0x406130 SUB $0x58,%RSP |
0x406134 VMOVSD 0x20(%RDI),%XMM10 |
0x406139 VMOVSD 0x18(%RDI),%XMM11 |
0x40613e VMOVSD 0x10(%RDI),%XMM4 |
0x406143 MOV 0x30(%RDI),%EAX |
0x406146 VMOVSD 0x8(%RDI),%XMM9 |
0x40614b MOV (%RDI),%R15 |
0x40614e VMOVSD %XMM10,-0x50(%RBP) |
0x406153 VMOVSD %XMM11,-0x48(%RBP) |
0x406158 VMOVSD %XMM4,-0x40(%RBP) |
0x40615d MOV 0x18(%R15),%R13 |
0x406161 VMOVSD %XMM9,-0x38(%RBP) |
0x406166 MOV %EAX,-0x60(%RBP) |
0x406169 CALL 403070 <omp_get_num_threads@plt> |
0x40616e MOV %EAX,%EBX |
0x406170 CALL 403150 <omp_get_thread_num@plt> |
0x406175 VMOVSD -0x38(%RBP),%XMM0 |
0x40617a VMOVSD -0x40(%RBP),%XMM4 |
0x40617f MOV %EAX,%ECX |
0x406181 MOV 0xc(%R13),%EAX |
0x406185 VMOVSD -0x48(%RBP),%XMM11 |
0x40618a VMOVSD -0x50(%RBP),%XMM10 |
0x40618f CLTD |
0x406190 IDIV %EBX |
0x406192 CMP %EDX,%ECX |
0x406194 JL 406572 |
0x40619a IMUL %EAX,%ECX |
0x40619d ADD %ECX,%EDX |
0x40619f ADD %EDX,%EAX |
0x4061a1 MOV %EAX,-0x64(%RBP) |
0x4061a4 CMP %EAX,%EDX |
0x4061a6 JGE 406588 |
0x4061ac VMULSD 0xba3c(%RIP),%XMM0,%XMM9 |
0x4061b4 MOVSXD -0x60(%RBP),%RSI |
0x4061b8 MOVSXD %EDX,%RAX |
0x4061bb SAL $0x6,%EDX |
0x4061be MOV 0x78(%R13),%R14 |
0x4061c2 VMOVSD 0xbaf6(%RIP),%XMM8 |
0x4061ca MOV %EDX,%ECX |
0x4061cc VXORPD %XMM6,%XMM6,%XMM6 |
0x4061d0 VMOVSD 0xba20(%RIP),%XMM7 |
0x4061d8 VMOVSD 0xba20(%RIP),%XMM12 |
0x4061e0 LEA (,%RSI,4),%R11 |
(21) 0x4061e8 MOV -0x60(%RBP),%R8D |
(21) 0x4061ec MOV (%R14,%RAX,4),%EDI |
(21) 0x4061f0 TEST %R8D,%R8D |
(21) 0x4061f3 JLE 406529 |
(21) 0x4061f9 MOV 0x80(%R13),%R10 |
(21) 0x406200 MOV %EAX,%ESI |
(21) 0x406202 LEA (%RDI,%RCX,1),%R9D |
(21) 0x406206 MOV %R13,-0x70(%RBP) |
(21) 0x40620a SAL $0x6,%ESI |
(21) 0x40620d MOV %R9D,-0x48(%RBP) |
(21) 0x406211 DEC %R9D |
(21) 0x406214 VMOVSD 0xb9ec(%RIP),%XMM13 |
(21) 0x40621c MOVSXD %ESI,%RDI |
(21) 0x40621f MOV (%R10,%RAX,8),%RDX |
(21) 0x406223 SUB %ESI,%R9D |
(21) 0x406226 MOV %R14,-0x40(%RBP) |
(21) 0x40622a LEA (,%RDI,8),%R8 |
(21) 0x406232 MOV %R11,-0x78(%RBP) |
(21) 0x406236 LEA (%RDX,%R11,1),%RBX |
(21) 0x40623a MOV %R8,-0x50(%RBP) |
(21) 0x40623e MOV %RAX,-0x80(%RBP) |
(21) 0x406242 MOV %ECX,-0x68(%RBP) |
(21) 0x406245 MOV %ESI,-0x5c(%RBP) |
(21) 0x406248 MOV %RBX,-0x58(%RBP) |
(21) 0x40624c LEA 0x1(%RDI,%R9,1),%RBX |
(21) 0x406251 MOV %R12,%RDI |
(21) 0x406254 SAL $0x3,%RBX |
(23) 0x406258 MOV (%RDX),%R11D |
(23) 0x40625b TEST %R11D,%R11D |
(23) 0x40625e JS 40658e |
(23) 0x406264 MOV -0x40(%RBP),%R12 |
(23) 0x406268 MOV -0x5c(%RBP),%R13D |
(23) 0x40626c MOVSXD %R11D,%R14 |
(23) 0x40626f MOV (%R12,%R14,4),%EAX |
(23) 0x406273 CMP %R13D,-0x48(%RBP) |
(23) 0x406277 JLE 406502 |
(23) 0x40627d SAL $0x6,%R11D |
(23) 0x406281 LEA (%R14,%R14,2),%R10 |
(23) 0x406285 MOV %RDX,-0x38(%RBP) |
(23) 0x406289 LEA (%RAX,%RAX,2),%R9 |
(23) 0x40628d MOVSXD %R11D,%RCX |
(23) 0x406290 SAL $0x9,%R10 |
(23) 0x406294 MOV -0x50(%RBP),%R8 |
(23) 0x406298 LEA (%RAX,%R11,1),%R13D |
(23) 0x40629c LEA (%RCX,%RCX,2),%R12 |
(23) 0x4062a0 LEA (%R10,%R9,8),%R14 |
(23) 0x4062a4 VXORPD %XMM5,%XMM5,%XMM5 |
(23) 0x4062a8 SAL $0x3,%R12 |
(23) 0x4062ac NOPL (%RAX) |
(24) 0x4062b0 CMP %R13D,%R11D |
(24) 0x4062b3 JGE 4064f1 |
(24) 0x4062b9 MOV 0x20(%R15),%R9 |
(24) 0x4062bd LEA (%R8,%R8,2),%R10 |
(24) 0x4062c1 MOV 0x18(%R9),%RCX |
(24) 0x4062c5 LEA (%RCX,%R12,1),%RAX |
(24) 0x4062c9 LEA (%RCX,%R10,1),%RDX |
(24) 0x4062cd ADD %R14,%RCX |
(24) 0x4062d0 MOV %RCX,%RSI |
(24) 0x4062d3 SUB %RAX,%RSI |
(24) 0x4062d6 AND $0x8,%ESI |
(24) 0x4062d9 JE 406398 |
(24) 0x4062df VMOVSD 0x10(%RDX),%XMM2 |
(24) 0x4062e4 VMOVSD (%RDX),%XMM1 |
(24) 0x4062e8 VMOVUPD (%RDX),%XMM3 |
(24) 0x4062ec VSUBSD 0x10(%RAX),%XMM2,%XMM2 |
(24) 0x4062f1 VSUBSD (%RAX),%XMM1,%XMM0 |
(24) 0x4062f5 VSUBPD (%RAX),%XMM3,%XMM3 |
(24) 0x4062f9 VMULSD %XMM2,%XMM2,%XMM14 |
(24) 0x4062fd VUNPCKHPD %XMM3,%XMM3,%XMM15 |
(24) 0x406301 VFMADD132SD %XMM0,%XMM14,%XMM0 |
(24) 0x406306 VFMADD132SD %XMM15,%XMM0,%XMM15 |
(24) 0x40630b VCOMISD %XMM15,%XMM4 |
(24) 0x406310 JB 406385 |
(24) 0x406312 VCOMISD %XMM5,%XMM15 |
(24) 0x406316 JBE 406385 |
(24) 0x406318 VDIVSD %XMM15,%XMM8,%XMM15 |
(24) 0x40631d MOV 0x30(%R9),%RSI |
(24) 0x406321 ADD %R8,%RSI |
(24) 0x406324 VMULSD %XMM15,%XMM15,%XMM1 |
(24) 0x406329 VMULSD %XMM15,%XMM11,%XMM0 |
(24) 0x40632e VMULSD %XMM9,%XMM15,%XMM14 |
(24) 0x406333 VMULSD %XMM0,%XMM1,%XMM0 |
(24) 0x406337 VSUBSD %XMM8,%XMM0,%XMM1 |
(24) 0x40633c VFMSUB132SD %XMM0,%XMM10,%XMM1 |
(24) 0x406341 VMOVSD %XMM1,%XMM1,%XMM15 |
(24) 0x406345 VFMADD231SD %XMM7,%XMM1,%XMM6 |
(24) 0x40634a VMOVSD %XMM0,%XMM0,%XMM1 |
(24) 0x40634e VFMADD132SD %XMM12,%XMM13,%XMM1 |
(24) 0x406353 VFMADD213SD (%RSI),%XMM7,%XMM15 |
(24) 0x406358 VMULSD %XMM1,%XMM0,%XMM0 |
(24) 0x40635c VMOVSD %XMM15,(%RSI) |
(24) 0x406360 MOV 0x28(%R9),%RSI |
(24) 0x406364 ADD %R10,%RSI |
(24) 0x406367 VMULSD %XMM14,%XMM0,%XMM14 |
(24) 0x40636c VMOVDDUP %XMM14,%XMM15 |
(24) 0x406371 VFNMADD213SD 0x10(%RSI),%XMM2,%XMM14 |
(24) 0x406377 VFNMADD213PD (%RSI),%XMM3,%XMM15 |
(24) 0x40637c VMOVSD %XMM14,0x10(%RSI) |
(24) 0x406381 VMOVUPD %XMM15,(%RSI) |
(24) 0x406385 ADD $0x18,%RAX |
(24) 0x406389 CMP %RAX,%RCX |
(24) 0x40638c JE 4064f1 |
(24) 0x406392 NOPW (%RAX,%RAX,1) |
(25) 0x406398 VMOVSD (%RDX),%XMM2 |
(25) 0x40639c VMOVSD 0x10(%RDX),%XMM14 |
(25) 0x4063a1 VMOVUPD (%RDX),%XMM3 |
(25) 0x4063a5 VSUBSD (%RAX),%XMM2,%XMM1 |
(25) 0x4063a9 VSUBSD 0x10(%RAX),%XMM14,%XMM2 |
(25) 0x4063ae VSUBPD (%RAX),%XMM3,%XMM3 |
(25) 0x4063b2 VMULSD %XMM2,%XMM2,%XMM15 |
(25) 0x4063b6 VUNPCKHPD %XMM3,%XMM3,%XMM0 |
(25) 0x4063ba VFMADD132SD %XMM1,%XMM15,%XMM1 |
(25) 0x4063bf VFMADD132SD %XMM0,%XMM1,%XMM0 |
(25) 0x4063c4 VCOMISD %XMM0,%XMM4 |
(25) 0x4063c8 JB 40643b |
(25) 0x4063ca VCOMISD %XMM5,%XMM0 |
(25) 0x4063ce JBE 40643b |
(25) 0x4063d0 VDIVSD %XMM0,%XMM8,%XMM0 |
(25) 0x4063d4 MOV 0x30(%R9),%RSI |
(25) 0x4063d8 ADD %R8,%RSI |
(25) 0x4063db VMULSD %XMM0,%XMM0,%XMM1 |
(25) 0x4063df VMULSD %XMM0,%XMM11,%XMM15 |
(25) 0x4063e3 VMULSD %XMM9,%XMM0,%XMM14 |
(25) 0x4063e8 VMULSD %XMM15,%XMM1,%XMM0 |
(25) 0x4063ed VSUBSD %XMM8,%XMM0,%XMM1 |
(25) 0x4063f2 VFMSUB132SD %XMM0,%XMM10,%XMM1 |
(25) 0x4063f7 VMOVSD %XMM1,%XMM1,%XMM15 |
(25) 0x4063fb VFMADD231SD %XMM7,%XMM1,%XMM6 |
(25) 0x406400 VMOVSD %XMM0,%XMM0,%XMM1 |
(25) 0x406404 VFMADD132SD %XMM12,%XMM13,%XMM1 |
(25) 0x406409 VFMADD213SD (%RSI),%XMM7,%XMM15 |
(25) 0x40640e VMULSD %XMM1,%XMM0,%XMM0 |
(25) 0x406412 VMOVSD %XMM15,(%RSI) |
(25) 0x406416 MOV 0x28(%R9),%RSI |
(25) 0x40641a ADD %R10,%RSI |
(25) 0x40641d VMULSD %XMM14,%XMM0,%XMM14 |
(25) 0x406422 VMOVDDUP %XMM14,%XMM15 |
(25) 0x406427 VFNMADD213SD 0x10(%RSI),%XMM2,%XMM14 |
(25) 0x40642d VFNMADD213PD (%RSI),%XMM3,%XMM15 |
(25) 0x406432 VMOVSD %XMM14,0x10(%RSI) |
(25) 0x406437 VMOVUPD %XMM15,(%RSI) |
(25) 0x40643b VMOVSD (%RDX),%XMM2 |
(25) 0x40643f VMOVSD 0x10(%RDX),%XMM14 |
(25) 0x406444 LEA 0x18(%RAX),%RSI |
(25) 0x406448 VMOVUPD (%RDX),%XMM3 |
(25) 0x40644c VSUBSD 0x18(%RAX),%XMM2,%XMM1 |
(25) 0x406451 VSUBSD 0x28(%RAX),%XMM14,%XMM2 |
(25) 0x406456 VSUBPD 0x18(%RAX),%XMM3,%XMM3 |
(25) 0x40645b VMULSD %XMM2,%XMM2,%XMM15 |
(25) 0x40645f VUNPCKHPD %XMM3,%XMM3,%XMM0 |
(25) 0x406463 VFMADD132SD %XMM1,%XMM15,%XMM1 |
(25) 0x406468 VFMADD132SD %XMM0,%XMM1,%XMM0 |
(25) 0x40646d VCOMISD %XMM0,%XMM4 |
(25) 0x406471 JB 4064e4 |
(25) 0x406473 VCOMISD %XMM5,%XMM0 |
(25) 0x406477 JBE 4064e4 |
(25) 0x406479 VDIVSD %XMM0,%XMM8,%XMM0 |
(25) 0x40647d MOV 0x30(%R9),%RAX |
(25) 0x406481 ADD %R8,%RAX |
(25) 0x406484 VMULSD %XMM0,%XMM0,%XMM1 |
(25) 0x406488 VMULSD %XMM0,%XMM11,%XMM15 |
(25) 0x40648c VMULSD %XMM9,%XMM0,%XMM14 |
(25) 0x406491 VMULSD %XMM15,%XMM1,%XMM0 |
(25) 0x406496 VSUBSD %XMM8,%XMM0,%XMM1 |
(25) 0x40649b VFMSUB132SD %XMM0,%XMM10,%XMM1 |
(25) 0x4064a0 VMOVSD %XMM1,%XMM1,%XMM15 |
(25) 0x4064a4 VFMADD231SD %XMM7,%XMM1,%XMM6 |
(25) 0x4064a9 VMOVSD %XMM0,%XMM0,%XMM1 |
(25) 0x4064ad VFMADD132SD %XMM12,%XMM13,%XMM1 |
(25) 0x4064b2 VFMADD213SD (%RAX),%XMM7,%XMM15 |
(25) 0x4064b7 VMULSD %XMM1,%XMM0,%XMM0 |
(25) 0x4064bb VMOVSD %XMM15,(%RAX) |
(25) 0x4064bf MOV 0x28(%R9),%RAX |
(25) 0x4064c3 ADD %R10,%RAX |
(25) 0x4064c6 VMULSD %XMM14,%XMM0,%XMM14 |
(25) 0x4064cb VMOVDDUP %XMM14,%XMM15 |
(25) 0x4064d0 VFNMADD213SD 0x10(%RAX),%XMM2,%XMM14 |
(25) 0x4064d6 VFNMADD213PD (%RAX),%XMM3,%XMM15 |
(25) 0x4064db VMOVSD %XMM14,0x10(%RAX) |
(25) 0x4064e0 VMOVUPD %XMM15,(%RAX) |
(25) 0x4064e4 LEA 0x18(%RSI),%RAX |
(25) 0x4064e8 CMP %RAX,%RCX |
(25) 0x4064eb JNE 406398 |
(24) 0x4064f1 ADD $0x8,%R8 |
(24) 0x4064f5 CMP %RBX,%R8 |
(24) 0x4064f8 JNE 4062b0 |
(23) 0x4064fe MOV -0x38(%RBP),%RDX |
(23) 0x406502 MOV -0x58(%RBP),%R11 |
(23) 0x406506 ADD $0x4,%RDX |
(23) 0x40650a CMP %R11,%RDX |
(23) 0x40650d JNE 406258 |
(21) 0x406513 MOV -0x70(%RBP),%R13 |
(21) 0x406517 MOV -0x40(%RBP),%R14 |
(21) 0x40651b MOV %RDI,%R12 |
(21) 0x40651e MOV -0x78(%RBP),%R11 |
(21) 0x406522 MOV -0x80(%RBP),%RAX |
(21) 0x406526 MOV -0x68(%RBP),%ECX |
(21) 0x406529 INC %RAX |
(21) 0x40652c ADD $0x40,%ECX |
(21) 0x40652f CMP %EAX,-0x64(%RBP) |
(21) 0x406532 JG 4061e8 |
0x406538 MOV 0x28(%R12),%R8 |
0x40653d LEA 0x28(%R12),%R15 |
(22) 0x406542 VMOVQ %R8,%XMM4 |
(22) 0x406547 MOV %R8,%RAX |
(22) 0x40654a VADDSD %XMM4,%XMM6,%XMM11 |
(22) 0x40654e VMOVQ %XMM11,%RBX |
(22) 0x406553 LOCK CMPXCHG %RBX,(%R15) |
(22) 0x406558 MOV %R8,%RDI |
(22) 0x40655b MOV %RAX,%R8 |
(22) 0x40655e CMP %RAX,%RDI |
(22) 0x406561 JNE 406542 |
0x406563 ADD $0x58,%RSP |
0x406567 POP %RBX |
0x406568 POP %R12 |
0x40656a POP %R13 |
0x40656c POP %R14 |
0x40656e POP %R15 |
0x406570 POP %RBP |
0x406571 RET |
0x406572 INC %EAX |
0x406574 XOR %EDX,%EDX |
0x406576 IMUL %EAX,%ECX |
0x406579 ADD %ECX,%EDX |
0x40657b ADD %EDX,%EAX |
0x40657d MOV %EAX,-0x64(%RBP) |
0x406580 CMP %EAX,%EDX |
0x406582 JL 4061ac |
0x406588 VXORPD %XMM6,%XMM6,%XMM6 |
0x40658c JMP 406538 |
0x40658e MOV $0x411a58,%ECX |
0x406593 MOV $0xb6,%EDX |
0x406598 MOV $0x410bd8,%ESI |
0x40659d MOV $0x410136,%EDI |
0x4065a2 CALL 4030c0 <__assert_fail@plt> |
0x4065a7 NOPW (%RAX,%RAX,1) |
Path / |
Source file and lines | ljForce.c:172-216 |
Module | exec |
nb instructions | 77 |
nb uops | 83 |
loop length | 287 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 9 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 13.83 cycles |
front end | 13.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.10 | 5.00 | 8.67 | 8.67 | 8.00 | 5.07 | 4.90 | 8.00 | 8.00 | 8.00 | 4.93 | 8.67 |
cycles | 5.10 | 7.73 | 8.67 | 8.67 | 8.00 | 5.07 | 4.90 | 8.00 | 8.00 | 8.00 | 4.93 | 8.67 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 13.41-13.40 |
Stall cycles | 0.00 |
Front-end | 13.83 |
Dispatch | 8.67 |
DIV/SQRT | 6.00 |
Overall L1 | 13.83 |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 11% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 5% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 22% |
all | 7% |
load | 12% |
store | 6% |
mul | 6% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 13% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 10% |
load | 12% |
store | 9% |
mul | 8% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x58,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVSD 0x20(%RDI),%XMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x18(%RDI),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x10(%RDI),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x8(%RDI),%XMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM10,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM11,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM4,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%R15),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM9,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 403070 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 403150 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD -0x38(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x40(%RBP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xc(%R13),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x48(%RBP),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x50(%RBP),%XMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %EBX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 406572 <ljForce._omp_fn.1+0x452> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ECX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,-0x64(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 406588 <ljForce._omp_fn.1+0x468> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMULSD 0xba3c(%RIP),%XMM0,%XMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
MOVSXD -0x60(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDX,%RAX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
SAL $0x6,%EDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV 0x78(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xbaf6(%RIP),%XMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VXORPD %XMM6,%XMM6,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0xba20(%RIP),%XMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xba20(%RIP),%XMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%RSI,4),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x28(%R12),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x28(%R12),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x58,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %EAX,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ECX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,-0x64(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 4061ac <ljForce._omp_fn.1+0x8c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VXORPD %XMM6,%XMM6,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 406538 <ljForce._omp_fn.1+0x418> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV $0x411a58,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0xb6,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x410bd8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x410136,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4030c0 <__assert_fail@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | ljForce.c:172-216 |
Module | exec |
nb instructions | 77 |
nb uops | 83 |
loop length | 287 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 9 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 13.83 cycles |
front end | 13.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.10 | 5.00 | 8.67 | 8.67 | 8.00 | 5.07 | 4.90 | 8.00 | 8.00 | 8.00 | 4.93 | 8.67 |
cycles | 5.10 | 7.73 | 8.67 | 8.67 | 8.00 | 5.07 | 4.90 | 8.00 | 8.00 | 8.00 | 4.93 | 8.67 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 13.41-13.40 |
Stall cycles | 0.00 |
Front-end | 13.83 |
Dispatch | 8.67 |
DIV/SQRT | 6.00 |
Overall L1 | 13.83 |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 11% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 5% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 22% |
all | 7% |
load | 12% |
store | 6% |
mul | 6% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 13% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 10% |
load | 12% |
store | 9% |
mul | 8% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x58,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVSD 0x20(%RDI),%XMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x18(%RDI),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x10(%RDI),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x8(%RDI),%XMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM10,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM11,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM4,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%R15),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM9,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 403070 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 403150 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD -0x38(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x40(%RBP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xc(%R13),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x48(%RBP),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x50(%RBP),%XMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %EBX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 406572 <ljForce._omp_fn.1+0x452> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ECX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,-0x64(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 406588 <ljForce._omp_fn.1+0x468> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMULSD 0xba3c(%RIP),%XMM0,%XMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
MOVSXD -0x60(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDX,%RAX | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
SAL $0x6,%EDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV 0x78(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xbaf6(%RIP),%XMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VXORPD %XMM6,%XMM6,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0xba20(%RIP),%XMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xba20(%RIP),%XMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%RSI,4),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x28(%R12),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x28(%R12),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x58,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %EAX,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ECX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,-0x64(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 4061ac <ljForce._omp_fn.1+0x8c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VXORPD %XMM6,%XMM6,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 406538 <ljForce._omp_fn.1+0x418> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV $0x411a58,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0xb6,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x410bd8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x410136,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4030c0 <__assert_fail@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼ljForce._omp_fn.1– | 62.91 | 12.82 |
▼Loop 21 - ljForce.c:175-216 - exec– | 0.02 | 0 |
▼Loop 23 - ljForce.c:178-216 - exec– | 0.3 | 0.04 |
▼Loop 24 - ljForce.c:187-216 - exec– | 4.83 | 0.67 |
○Loop 25 - ljForce.c:191-216 - exec | 57.76 | 7.97 |
○Loop 22 - ljForce.c:172-172 - exec | 0 | 0 |