Function: setTemperature.extracted.30 | Module: exec | Source: initAtoms.c:151-162 [...] | Coverage: 0.02% |
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Function: setTemperature.extracted.30 | Module: exec | Source: initAtoms.c:151-162 [...] | Coverage: 0.02% |
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/scratch_na/users/xoserete/qaas_runs/171-172-2581/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 151 - 162 |
-------------------------------------------------------------------------------- |
151: #pragma omp parallel for |
152: for (int iBox=0; iBox<s->boxes->nLocalBoxes; ++iBox) |
153: { |
154: for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff) |
155: { |
156: int iType = s->atoms->iSpecies[iOff]; |
157: real_t mass = s->species[iType].mass; |
158: real_t sigma = sqrt(kB_eV * temperature/mass); |
159: uint64_t seed = mkSeed(s->atoms->gid[iOff], 123); |
160: s->atoms->p[iOff][0] = mass * sigma * gasdev(&seed); |
161: s->atoms->p[iOff][1] = mass * sigma * gasdev(&seed); |
162: s->atoms->p[iOff][2] = mass * sigma * gasdev(&seed); |
/scratch_na/users/xoserete/qaas_runs/171-172-2581/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c: 27 - 70 |
-------------------------------------------------------------------------------- |
27: v2 = 2.0*lcg61(seed)-1.0; |
28: rsq = v1*v1+v2*v2; |
29: } while (rsq >= 1.0 || rsq == 0.0); |
30: |
31: return v2 * sqrt(-2.0*log(rsq)/rsq); |
[...] |
45: *seed *= UINT64_C(437799614237992725); |
46: *seed %= UINT64_C(2305843009213693951); |
47: |
48: return *seed*convertToDouble; |
[...] |
67: uint32_t s1 = id * UINT32_C(2654435761); |
68: uint32_t s2 = (id+callSite) * UINT32_C(2654435761); |
69: |
70: uint64_t iSeed = (UINT64_C(0x100000000) * s1) + s2; |
0x40a510 PUSH %RBP |
0x40a511 MOV %RSP,%RBP |
0x40a514 PUSH %R15 |
0x40a516 PUSH %R14 |
0x40a518 PUSH %R13 |
0x40a51a PUSH %R12 |
0x40a51c PUSH %RBX |
0x40a51d SUB $0x98,%RSP |
0x40a524 MOV %RCX,%R15 |
0x40a527 MOV %RDX,-0x88(%RBP) |
0x40a52e MOVL $0,-0x5c(%RBP) |
0x40a535 MOV (%RDI),%ESI |
0x40a537 MOVL $0,-0x34(%RBP) |
0x40a53e MOV %R9D,-0x30(%RBP) |
0x40a542 MOVL $0x1,-0x58(%RBP) |
0x40a549 SUB $0x8,%RSP |
0x40a54d LEA -0x58(%RBP),%RAX |
0x40a551 LEA -0x5c(%RBP),%RCX |
0x40a555 LEA -0x34(%RBP),%R8 |
0x40a559 LEA -0x30(%RBP),%R9 |
0x40a55d MOV $0x62f690,%EDI |
0x40a562 MOV %ESI,-0x4c(%RBP) |
0x40a565 MOV $0x22,%EDX |
0x40a56a PUSH $0x1 |
0x40a56c PUSH $0x1 |
0x40a56e PUSH %RAX |
0x40a56f CALL 403120 <__kmpc_for_static_init_4@plt> |
0x40a574 ADD $0x20,%RSP |
0x40a578 MOV -0x34(%RBP),%ECX |
0x40a57b MOV -0x30(%RBP),%EAX |
0x40a57e MOV %RAX,-0x90(%RBP) |
0x40a585 CMP %EAX,%ECX |
0x40a587 JBE 40a5a7 |
0x40a589 MOV $0x62f6b0,%EDI |
0x40a58e MOV -0x4c(%RBP),%ESI |
0x40a591 ADD $0x98,%RSP |
0x40a598 POP %RBX |
0x40a599 POP %R12 |
0x40a59b POP %R13 |
0x40a59d POP %R14 |
0x40a59f POP %R15 |
0x40a5a1 POP %RBP |
0x40a5a2 JMP 402fe0 |
0x40a5a7 VMOVQ %R15,%XMM0 |
0x40a5ac MOV -0x88(%RBP),%RAX |
0x40a5b3 MOV 0x18(%RAX),%RAX |
0x40a5b7 VMULSD 0x19829(%RIP),%XMM0,%XMM0 |
0x40a5bf VMOVSD %XMM0,-0xa8(%RBP) |
0x40a5c7 MOV %ECX,%EDX |
0x40a5c9 SAL $0x6,%EDX |
0x40a5cc MOV %EDX,-0x2c(%RBP) |
0x40a5cf INCQ -0x90(%RBP) |
0x40a5d6 MOV 0x78(%RAX),%RAX |
0x40a5da MOV %RAX,-0x98(%RBP) |
0x40a5e1 MOV $0x613606df9756715,%R13 |
0x40a5eb MOV $0x9,%EBX |
0x40a5f0 VMOVDDUP 0x19800(%RIP),%XMM4 |
0x40a5f8 VMOVDDUP 0x1e480(%RIP),%XMM5 |
0x40a600 VMOVSD 0x1e480(%RIP),%XMM6 |
0x40a608 VXORPD %XMM7,%XMM7,%XMM7 |
0x40a60c JMP 40a62b |
0x40a60e XCHG %AX,%AX |
(70) 0x40a610 MOV -0xa0(%RBP),%RCX |
(70) 0x40a617 INC %RCX |
(70) 0x40a61a ADDL $0x40,-0x2c(%RBP) |
(70) 0x40a61e CMP -0x90(%RBP),%RCX |
(70) 0x40a625 JE 40a589 |
(70) 0x40a62b MOV %RCX,-0xa0(%RBP) |
(70) 0x40a632 MOV -0x98(%RBP),%RAX |
(70) 0x40a639 MOV (%RAX,%RCX,4),%EAX |
(70) 0x40a63c MOV %EAX,-0x50(%RBP) |
(70) 0x40a63f TEST %EAX,%EAX |
(70) 0x40a641 JLE 40a610 |
(70) 0x40a643 MOV -0x2c(%RBP),%R12D |
(70) 0x40a647 MOV -0x88(%RBP),%RCX |
(70) 0x40a64e MOV 0x20(%RCX),%RAX |
(70) 0x40a652 MOV 0x28(%RCX),%RCX |
(70) 0x40a656 MOV %RCX,-0xc0(%RBP) |
(70) 0x40a65d MOV 0x8(%RAX),%RCX |
(70) 0x40a661 MOV %RCX,-0xb8(%RBP) |
(70) 0x40a668 MOV 0x10(%RAX),%RCX |
(70) 0x40a66c MOV %RCX,-0xb0(%RBP) |
(70) 0x40a673 MOV 0x20(%RAX),%RAX |
(70) 0x40a677 MOV %RAX,-0x40(%RBP) |
(70) 0x40a67b XOR %EAX,%EAX |
(70) 0x40a67d NOPL (%RAX) |
(74) 0x40a680 MOV %EAX,-0x54(%RBP) |
(74) 0x40a683 MOV -0xb0(%RBP),%RAX |
(74) 0x40a68a MOVSXD (%RAX,%R12,4),%RAX |
(74) 0x40a68e SAL $0x4,%RAX |
(74) 0x40a692 MOV -0xc0(%RBP),%RCX |
(74) 0x40a699 VMOVSD 0x8(%RCX,%RAX,1),%XMM9 |
(74) 0x40a69f VMOVSD -0xa8(%RBP),%XMM1 |
(74) 0x40a6a7 VDIVSD %XMM9,%XMM1,%XMM1 |
(74) 0x40a6ac MOV -0xb8(%RBP),%RAX |
(74) 0x40a6b3 IMUL $-0x61c8864f,(%RAX,%R12,4),%ECX |
(74) 0x40a6bb MOV %ECX,%EAX |
(74) 0x40a6bd ADD $0x4a7780b,%EAX |
(74) 0x40a6c2 SAL $0x20,%RCX |
(74) 0x40a6c6 OR %RCX,%RAX |
(74) 0x40a6c9 IMUL %R13,%RAX |
(74) 0x40a6cd MOV %RAX,%RDX |
(74) 0x40a6d0 MULX %RBX,%RCX,%RCX |
(74) 0x40a6d5 SUB %RCX,%RDX |
(74) 0x40a6d8 SHR $0x1,%RDX |
(74) 0x40a6db ADD %RCX,%RDX |
(74) 0x40a6de SHR $0x3c,%RDX |
(74) 0x40a6e2 MOV %RDX,%RCX |
(74) 0x40a6e5 SAL $0x3d,%RCX |
(74) 0x40a6e9 SUB %RCX,%RDX |
(74) 0x40a6ec ADD %RAX,%RDX |
(74) 0x40a6ef IMUL %R13,%RDX |
(74) 0x40a6f3 MULX %RBX,%RCX,%RCX |
(74) 0x40a6f8 MOV %RDX,%RAX |
(74) 0x40a6fb SUB %RCX,%RAX |
(74) 0x40a6fe SHR $0x1,%RAX |
(74) 0x40a701 ADD %RCX,%RAX |
(74) 0x40a704 SHR $0x3c,%RAX |
(74) 0x40a708 MOV %RAX,%RCX |
(74) 0x40a70b SAL $0x3d,%RCX |
(74) 0x40a70f SUB %RCX,%RAX |
(74) 0x40a712 ADD %RDX,%RAX |
(74) 0x40a715 IMUL %R13,%RAX |
(74) 0x40a719 MOV %RAX,%RDX |
(74) 0x40a71c MULX %RBX,%RCX,%RCX |
(74) 0x40a721 SUB %RCX,%RDX |
(74) 0x40a724 SHR $0x1,%RDX |
(74) 0x40a727 ADD %RCX,%RDX |
(74) 0x40a72a SHR $0x3c,%RDX |
(74) 0x40a72e MOV %RDX,%RCX |
(74) 0x40a731 SAL $0x3d,%RCX |
(74) 0x40a735 SUB %RCX,%RDX |
(74) 0x40a738 ADD %RAX,%RDX |
(74) 0x40a73b IMUL %R13,%RDX |
(74) 0x40a73f MULX %RBX,%RCX,%RCX |
(74) 0x40a744 MOV %RDX,%RAX |
(74) 0x40a747 SUB %RCX,%RAX |
(74) 0x40a74a SHR $0x1,%RAX |
(74) 0x40a74d ADD %RCX,%RAX |
(74) 0x40a750 SHR $0x3c,%RAX |
(74) 0x40a754 MOV %RAX,%RCX |
(74) 0x40a757 SAL $0x3d,%RCX |
(74) 0x40a75b SUB %RCX,%RAX |
(74) 0x40a75e ADD %RDX,%RAX |
(74) 0x40a761 IMUL %R13,%RAX |
(74) 0x40a765 MOV %RAX,%RDX |
(74) 0x40a768 MULX %RBX,%RCX,%RCX |
(74) 0x40a76d SUB %RCX,%RDX |
(74) 0x40a770 SHR $0x1,%RDX |
(74) 0x40a773 ADD %RCX,%RDX |
(74) 0x40a776 SHR $0x3c,%RDX |
(74) 0x40a77a MOV %RDX,%RCX |
(74) 0x40a77d SAL $0x3d,%RCX |
(74) 0x40a781 SUB %RCX,%RDX |
(74) 0x40a784 ADD %RAX,%RDX |
(74) 0x40a787 IMUL %R13,%RDX |
(74) 0x40a78b MULX %RBX,%RCX,%RCX |
(74) 0x40a790 MOV %RDX,%RAX |
(74) 0x40a793 SUB %RCX,%RAX |
(74) 0x40a796 SHR $0x1,%RAX |
(74) 0x40a799 ADD %RCX,%RAX |
(74) 0x40a79c SHR $0x3c,%RAX |
(74) 0x40a7a0 MOV %RAX,%RCX |
(74) 0x40a7a3 SAL $0x3d,%RCX |
(74) 0x40a7a7 SUB %RCX,%RAX |
(74) 0x40a7aa ADD %RDX,%RAX |
(74) 0x40a7ad IMUL %R13,%RAX |
(74) 0x40a7b1 MOV %RAX,%RDX |
(74) 0x40a7b4 MULX %RBX,%RCX,%RCX |
(74) 0x40a7b9 SUB %RCX,%RDX |
(74) 0x40a7bc SHR $0x1,%RDX |
(74) 0x40a7bf ADD %RCX,%RDX |
(74) 0x40a7c2 SHR $0x3c,%RDX |
(74) 0x40a7c6 MOV %RDX,%RCX |
(74) 0x40a7c9 SAL $0x3d,%RCX |
(74) 0x40a7cd SUB %RCX,%RDX |
(74) 0x40a7d0 ADD %RAX,%RDX |
(74) 0x40a7d3 IMUL %R13,%RDX |
(74) 0x40a7d7 MULX %RBX,%RCX,%RCX |
(74) 0x40a7dc MOV %RDX,%RAX |
(74) 0x40a7df SUB %RCX,%RAX |
(74) 0x40a7e2 SHR $0x1,%RAX |
(74) 0x40a7e5 ADD %RCX,%RAX |
(74) 0x40a7e8 SHR $0x3c,%RAX |
(74) 0x40a7ec MOV %RAX,%RCX |
(74) 0x40a7ef SAL $0x3d,%RCX |
(74) 0x40a7f3 SUB %RCX,%RAX |
(74) 0x40a7f6 ADD %RDX,%RAX |
(74) 0x40a7f9 IMUL %R13,%RAX |
(74) 0x40a7fd MOV %RAX,%RDX |
(74) 0x40a800 MULX %RBX,%RCX,%RCX |
(74) 0x40a805 SUB %RCX,%RDX |
(74) 0x40a808 SHR $0x1,%RDX |
(74) 0x40a80b ADD %RCX,%RDX |
(74) 0x40a80e SHR $0x3c,%RDX |
(74) 0x40a812 MOV %RDX,%RCX |
(74) 0x40a815 SAL $0x3d,%RCX |
(74) 0x40a819 SUB %RCX,%RDX |
(74) 0x40a81c ADD %RAX,%RDX |
(74) 0x40a81f IMUL %R13,%RDX |
(74) 0x40a823 MULX %RBX,%RAX,%RAX |
(74) 0x40a828 VSQRTSD %XMM1,%XMM1,%XMM1 |
(74) 0x40a82c MOV %RDX,%R15 |
(74) 0x40a82f SUB %RAX,%R15 |
(74) 0x40a832 SHR $0x1,%R15 |
(74) 0x40a835 ADD %RAX,%R15 |
(74) 0x40a838 SHR $0x3c,%R15 |
(74) 0x40a83c MOV %R15,%RAX |
(74) 0x40a83f SAL $0x3d,%RAX |
(74) 0x40a843 SUB %RAX,%R15 |
(74) 0x40a846 ADD %RDX,%R15 |
(74) 0x40a849 NOPL (%RAX) |
(71) 0x40a850 IMUL %R13,%R15 |
(71) 0x40a854 MOV %R15,%RDX |
(71) 0x40a857 MULX %RBX,%RAX,%RAX |
(71) 0x40a85c SUB %RAX,%RDX |
(71) 0x40a85f SHR $0x1,%RDX |
(71) 0x40a862 ADD %RAX,%RDX |
(71) 0x40a865 SHR $0x3c,%RDX |
(71) 0x40a869 MOV %RDX,%RAX |
(71) 0x40a86c SAL $0x3d,%RAX |
(71) 0x40a870 SUB %RAX,%RDX |
(71) 0x40a873 ADD %R15,%RDX |
(71) 0x40a876 VCVTSI2SD %RDX,%XMM4,%XMM2 |
(71) 0x40a87b IMUL %R13,%RDX |
(71) 0x40a87f MULX %RBX,%RAX,%RAX |
(71) 0x40a884 MOV %RDX,%R15 |
(71) 0x40a887 SUB %RAX,%R15 |
(71) 0x40a88a SHR $0x1,%R15 |
(71) 0x40a88d ADD %RAX,%R15 |
(71) 0x40a890 SHR $0x3c,%R15 |
(71) 0x40a894 MOV %R15,%RAX |
(71) 0x40a897 SAL $0x3d,%RAX |
(71) 0x40a89b SUB %RAX,%R15 |
(71) 0x40a89e ADD %RDX,%R15 |
(71) 0x40a8a1 VCVTSI2SD %R15,%XMM4,%XMM3 |
(71) 0x40a8a6 VUNPCKLPD %XMM2,%XMM3,%XMM8 |
(71) 0x40a8aa VFMADD213PD %XMM5,%XMM4,%XMM8 |
(71) 0x40a8af VMULPD %XMM8,%XMM8,%XMM2 |
(71) 0x40a8b4 VSHUFPD $0x1,%XMM2,%XMM2,%XMM3 |
(71) 0x40a8b9 VADDSD %XMM3,%XMM2,%XMM0 |
(71) 0x40a8bd VUCOMISD %XMM6,%XMM0 |
(71) 0x40a8c1 JAE 40a850 |
(71) 0x40a8c3 VUCOMISD %XMM7,%XMM0 |
(71) 0x40a8c7 JE 40a850 |
(74) 0x40a8c9 VMULSD %XMM1,%XMM9,%XMM1 |
(74) 0x40a8cd VMOVSD %XMM1,-0x48(%RBP) |
(74) 0x40a8d2 VMOVUPD %XMM8,-0x80(%RBP) |
(74) 0x40a8d7 VMOVSD %XMM0,-0x70(%RBP) |
(74) 0x40a8dc CALL 411d30 <log> |
(74) 0x40a8e1 VXORPD %XMM5,%XMM5,%XMM5 |
(74) 0x40a8e5 VMOVSD 0x1e19b(%RIP),%XMM4 |
(74) 0x40a8ed VMOVDDUP 0x1e18b(%RIP),%XMM3 |
(74) 0x40a8f5 VMOVDDUP 0x194fb(%RIP),%XMM2 |
(74) 0x40a8fd VMULSD 0x194eb(%RIP),%XMM0,%XMM0 |
(74) 0x40a905 VDIVSD -0x70(%RBP),%XMM0,%XMM0 |
(74) 0x40a90a VSQRTSD %XMM0,%XMM0,%XMM0 |
(74) 0x40a90e VMOVUPD -0x80(%RBP),%XMM1 |
(74) 0x40a913 VMULSD -0x48(%RBP),%XMM1,%XMM1 |
(74) 0x40a918 VMULSD %XMM1,%XMM0,%XMM0 |
(74) 0x40a91c LEA (%R12,%R12,2),%R14 |
(74) 0x40a920 MOV -0x40(%RBP),%RAX |
(74) 0x40a924 VMOVSD %XMM0,(%RAX,%R14,8) |
(74) 0x40a92a NOPW (%RAX,%RAX,1) |
(72) 0x40a930 IMUL %R13,%R15 |
(72) 0x40a934 MOV %R15,%RDX |
(72) 0x40a937 MULX %RBX,%RAX,%RAX |
(72) 0x40a93c SUB %RAX,%RDX |
(72) 0x40a93f SHR $0x1,%RDX |
(72) 0x40a942 ADD %RAX,%RDX |
(72) 0x40a945 SHR $0x3c,%RDX |
(72) 0x40a949 MOV %RDX,%RAX |
(72) 0x40a94c SAL $0x3d,%RAX |
(72) 0x40a950 SUB %RAX,%RDX |
(72) 0x40a953 ADD %R15,%RDX |
(72) 0x40a956 VCVTSI2SD %RDX,%XMM7,%XMM0 |
(72) 0x40a95b IMUL %R13,%RDX |
(72) 0x40a95f MULX %RBX,%RAX,%RAX |
(72) 0x40a964 MOV %RDX,%R15 |
(72) 0x40a967 SUB %RAX,%R15 |
(72) 0x40a96a SHR $0x1,%R15 |
(72) 0x40a96d ADD %RAX,%R15 |
(72) 0x40a970 SHR $0x3c,%R15 |
(72) 0x40a974 MOV %R15,%RAX |
(72) 0x40a977 SAL $0x3d,%RAX |
(72) 0x40a97b SUB %RAX,%R15 |
(72) 0x40a97e ADD %RDX,%R15 |
(72) 0x40a981 VCVTSI2SD %R15,%XMM7,%XMM1 |
(72) 0x40a986 VUNPCKLPD %XMM0,%XMM1,%XMM6 |
(72) 0x40a98a VFMADD213PD %XMM3,%XMM2,%XMM6 |
(72) 0x40a98f VMULPD %XMM6,%XMM6,%XMM0 |
(72) 0x40a993 VSHUFPD $0x1,%XMM0,%XMM0,%XMM1 |
(72) 0x40a998 VADDSD %XMM1,%XMM0,%XMM0 |
(72) 0x40a99c VUCOMISD %XMM4,%XMM0 |
(72) 0x40a9a0 JAE 40a930 |
(72) 0x40a9a2 VUCOMISD %XMM5,%XMM0 |
(72) 0x40a9a6 JE 40a930 |
(74) 0x40a9a8 VMOVSD %XMM0,-0x80(%RBP) |
(74) 0x40a9ad VMOVUPD %XMM6,-0x70(%RBP) |
(74) 0x40a9b2 CALL 411d30 <log> |
(74) 0x40a9b7 VXORPD %XMM5,%XMM5,%XMM5 |
(74) 0x40a9bb VMOVSD 0x1e0c5(%RIP),%XMM4 |
(74) 0x40a9c3 VMOVDDUP 0x1e0b5(%RIP),%XMM3 |
(74) 0x40a9cb VMOVDDUP 0x19425(%RIP),%XMM2 |
(74) 0x40a9d3 VMULSD 0x19415(%RIP),%XMM0,%XMM0 |
(74) 0x40a9db VDIVSD -0x80(%RBP),%XMM0,%XMM0 |
(74) 0x40a9e0 VSQRTSD %XMM0,%XMM0,%XMM0 |
(74) 0x40a9e4 VMOVUPD -0x70(%RBP),%XMM1 |
(74) 0x40a9e9 VMULSD -0x48(%RBP),%XMM1,%XMM1 |
(74) 0x40a9ee VMULSD %XMM1,%XMM0,%XMM0 |
(74) 0x40a9f2 MOV -0x40(%RBP),%RAX |
(74) 0x40a9f6 VMOVSD %XMM0,0x8(%RAX,%R14,8) |
(74) 0x40a9fd NOPL (%RAX) |
(73) 0x40aa00 IMUL %R13,%R15 |
(73) 0x40aa04 MOV %R15,%RDX |
(73) 0x40aa07 MULX %RBX,%RAX,%RAX |
(73) 0x40aa0c SUB %RAX,%RDX |
(73) 0x40aa0f SHR $0x1,%RDX |
(73) 0x40aa12 ADD %RAX,%RDX |
(73) 0x40aa15 SHR $0x3c,%RDX |
(73) 0x40aa19 MOV %RDX,%RAX |
(73) 0x40aa1c SAL $0x3d,%RAX |
(73) 0x40aa20 SUB %RAX,%RDX |
(73) 0x40aa23 ADD %R15,%RDX |
(73) 0x40aa26 VCVTSI2SD %RDX,%XMM7,%XMM0 |
(73) 0x40aa2b IMUL %R13,%RDX |
(73) 0x40aa2f MULX %RBX,%RAX,%RAX |
(73) 0x40aa34 MOV %RDX,%R15 |
(73) 0x40aa37 SUB %RAX,%R15 |
(73) 0x40aa3a SHR $0x1,%R15 |
(73) 0x40aa3d ADD %RAX,%R15 |
(73) 0x40aa40 SHR $0x3c,%R15 |
(73) 0x40aa44 MOV %R15,%RAX |
(73) 0x40aa47 SAL $0x3d,%RAX |
(73) 0x40aa4b SUB %RAX,%R15 |
(73) 0x40aa4e ADD %RDX,%R15 |
(73) 0x40aa51 VCVTSI2SD %R15,%XMM7,%XMM1 |
(73) 0x40aa56 VUNPCKLPD %XMM0,%XMM1,%XMM6 |
(73) 0x40aa5a VFMADD213PD %XMM3,%XMM2,%XMM6 |
(73) 0x40aa5f VMULPD %XMM6,%XMM6,%XMM0 |
(73) 0x40aa63 VSHUFPD $0x1,%XMM0,%XMM0,%XMM1 |
(73) 0x40aa68 VADDSD %XMM1,%XMM0,%XMM0 |
(73) 0x40aa6c VUCOMISD %XMM4,%XMM0 |
(73) 0x40aa70 JAE 40aa00 |
(73) 0x40aa72 VUCOMISD %XMM5,%XMM0 |
(73) 0x40aa76 JE 40aa00 |
(74) 0x40aa78 VMOVSD %XMM0,-0x80(%RBP) |
(74) 0x40aa7d VMOVUPD %XMM6,-0x70(%RBP) |
(74) 0x40aa82 CALL 411d30 <log> |
(74) 0x40aa87 VXORPD %XMM7,%XMM7,%XMM7 |
(74) 0x40aa8b VMOVSD 0x1dff5(%RIP),%XMM6 |
(74) 0x40aa93 VMOVDDUP 0x1dfe5(%RIP),%XMM5 |
(74) 0x40aa9b VMOVDDUP 0x19355(%RIP),%XMM4 |
(74) 0x40aaa3 VMULSD 0x19345(%RIP),%XMM0,%XMM0 |
(74) 0x40aaab VDIVSD -0x80(%RBP),%XMM0,%XMM0 |
(74) 0x40aab0 VSQRTSD %XMM0,%XMM0,%XMM0 |
(74) 0x40aab4 VMOVUPD -0x70(%RBP),%XMM1 |
(74) 0x40aab9 VMULSD -0x48(%RBP),%XMM1,%XMM1 |
(74) 0x40aabe VMULSD %XMM1,%XMM0,%XMM0 |
(74) 0x40aac2 MOV -0x40(%RBP),%RAX |
(74) 0x40aac6 VMOVSD %XMM0,0x10(%RAX,%R14,8) |
(74) 0x40aacd MOV -0x54(%RBP),%EAX |
(74) 0x40aad0 INC %EAX |
(74) 0x40aad2 INC %R12 |
(74) 0x40aad5 CMP -0x50(%RBP),%EAX |
(74) 0x40aad8 JNE 40a680 |
(70) 0x40aade JMP 40a610 |
0x40aae3 NOPW %CS:(%RAX,%RAX,1) |
0x40aaed NOPL (%RAX) |
Path / |
Source file and lines | initAtoms.c:151-162 |
Module | exec |
nb instructions | 64 |
nb uops | 67 |
loop length | 269 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 5 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 11.17 cycles |
front end | 11.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 2.70 | 6.00 | 6.00 | 10.50 | 2.60 | 2.60 | 10.50 | 10.50 | 10.50 | 2.60 | 6.00 |
cycles | 2.50 | 2.70 | 6.00 | 6.00 | 10.50 | 2.60 | 2.60 | 10.50 | 10.50 | 10.50 | 2.60 | 6.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 11.21-11.26 |
Stall cycles | 0.00 |
Front-end | 11.17 |
Dispatch | 10.50 |
Overall L1 | 11.17 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 16% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 3% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
all | 8% |
load | 6% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 14% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 10% |
load | 9% |
store | 8% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x98,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,-0x88(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0,-0x5c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,-0x34(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9D,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x58(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x5c(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x34(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x30(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x62f690,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,-0x4c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 403120 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x34(%RBP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x30(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x90(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EAX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 40a5a7 <setTemperature.extracted.30+0x97> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x62f6b0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x4c(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x98,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 402fe0 <__kmpc_for_static_fini@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VMOVQ %R15,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV -0x88(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMULSD 0x19829(%RIP),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM0,-0xa8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x6,%EDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %EDX,-0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INCQ -0x90(%RBP) | 3 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV 0x78(%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x98(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x613606df9756715,%R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
MOV $0x9,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVDDUP 0x19800(%RIP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVDDUP 0x1e480(%RIP),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x1e480(%RIP),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM7,%XMM7,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40a62b <setTemperature.extracted.30+0x11b> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | initAtoms.c:151-162 |
Module | exec |
nb instructions | 64 |
nb uops | 67 |
loop length | 269 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 5 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 11.17 cycles |
front end | 11.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 2.70 | 6.00 | 6.00 | 10.50 | 2.60 | 2.60 | 10.50 | 10.50 | 10.50 | 2.60 | 6.00 |
cycles | 2.50 | 2.70 | 6.00 | 6.00 | 10.50 | 2.60 | 2.60 | 10.50 | 10.50 | 10.50 | 2.60 | 6.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 11.21-11.26 |
Stall cycles | 0.00 |
Front-end | 11.17 |
Dispatch | 10.50 |
Overall L1 | 11.17 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 16% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 3% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
all | 8% |
load | 6% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 14% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 10% |
load | 9% |
store | 8% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x98,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,-0x88(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0,-0x5c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,-0x34(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9D,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x58(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x5c(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x34(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x30(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x62f690,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,-0x4c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 403120 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x34(%RBP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x30(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x90(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EAX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 40a5a7 <setTemperature.extracted.30+0x97> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x62f6b0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x4c(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x98,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 402fe0 <__kmpc_for_static_fini@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VMOVQ %R15,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV -0x88(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMULSD 0x19829(%RIP),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM0,-0xa8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x6,%EDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %EDX,-0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INCQ -0x90(%RBP) | 3 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV 0x78(%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x98(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x613606df9756715,%R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
MOV $0x9,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVDDUP 0x19800(%RIP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVDDUP 0x1e480(%RIP),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x1e480(%RIP),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM7,%XMM7,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40a62b <setTemperature.extracted.30+0x11b> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼setTemperature.extracted.30– | 0.02 | 0 |
▼Loop 70 - initAtoms.c:151-162 - exec– | 0 | 0 |
▼Loop 74 - initAtoms.c:154-162 - exec– | 0.01 | 0 |
○Loop 71 - random.c:27-48 - exec | 0 | 0 |
○Loop 73 - random.c:27-48 - exec | 0 | 0 |
○Loop 72 - random.c:27-48 - exec | 0 | 0 |