Function: advancePosition.extracted | Module: exec | Source: timestep.c:85-94 | Coverage: 1.42% |
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Function: advancePosition.extracted | Module: exec | Source: timestep.c:85-94 | Coverage: 1.42% |
---|
/scratch_na/users/xoserete/qaas_runs/171-172-2581/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 85 - 94 |
-------------------------------------------------------------------------------- |
85: #pragma omp parallel for |
86: for (int iBox=0; iBox<nBoxes; iBox++) |
87: { |
88: for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++) |
89: { |
90: int iSpecies = s->atoms->iSpecies[iOff]; |
91: real_t invMass = 1.0/s->species[iSpecies].mass; |
92: s->atoms->r[iOff][0] += dt*s->atoms->p[iOff][0]*invMass; |
93: s->atoms->r[iOff][1] += dt*s->atoms->p[iOff][1]*invMass; |
94: s->atoms->r[iOff][2] += dt*s->atoms->p[iOff][2]*invMass; |
0x40edb0 PUSH %RBP |
0x40edb1 MOV %RSP,%RBP |
0x40edb4 PUSH %R15 |
0x40edb6 PUSH %R14 |
0x40edb8 PUSH %R13 |
0x40edba PUSH %R12 |
0x40edbc PUSH %RBX |
0x40edbd SUB $0x38,%RSP |
0x40edc1 MOV %RCX,%R15 |
0x40edc4 MOV %RDX,-0x50(%RBP) |
0x40edc8 MOVL $0,-0x44(%RBP) |
0x40edcf MOV (%RDI),%ESI |
0x40edd1 MOVL $0,-0x30(%RBP) |
0x40edd8 MOV %R9D,-0x2c(%RBP) |
0x40eddc MOVL $0x1,-0x40(%RBP) |
0x40ede3 SUB $0x8,%RSP |
0x40ede7 LEA -0x40(%RBP),%RAX |
0x40edeb LEA -0x44(%RBP),%RCX |
0x40edef LEA -0x30(%RBP),%R8 |
0x40edf3 LEA -0x2c(%RBP),%R9 |
0x40edf7 MOV $0x62c950,%EDI |
0x40edfc MOV %ESI,-0x3c(%RBP) |
0x40edff MOV $0x22,%EDX |
0x40ee04 PUSH $0x1 |
0x40ee06 PUSH $0x1 |
0x40ee08 PUSH %RAX |
0x40ee09 CALL 402d40 <__kmpc_for_static_init_4@plt> |
0x40ee0e ADD $0x20,%RSP |
0x40ee12 MOV -0x30(%RBP),%EAX |
0x40ee15 MOV -0x2c(%RBP),%ECX |
0x40ee18 MOV %RCX,-0x38(%RBP) |
0x40ee1c CMP %ECX,%EAX |
0x40ee1e JBE 40ee3e |
0x40ee20 MOV $0x62c970,%EDI |
0x40ee25 MOV -0x3c(%RBP),%ESI |
0x40ee28 ADD $0x38,%RSP |
0x40ee2c POP %RBX |
0x40ee2d POP %R12 |
0x40ee2f POP %R13 |
0x40ee31 POP %R14 |
0x40ee33 POP %R15 |
0x40ee35 POP %RBP |
0x40ee36 VZEROUPPER |
0x40ee39 JMP 402c00 |
0x40ee3e VMOVQ %R15,%XMM0 |
0x40ee43 MOV -0x50(%RBP),%RCX |
0x40ee47 MOV 0x18(%RCX),%RCX |
0x40ee4b MOV 0x78(%RCX),%RCX |
0x40ee4f MOV %RCX,-0x58(%RBP) |
0x40ee53 MOV -0x38(%RBP),%RCX |
0x40ee57 SUB %RAX,%RCX |
0x40ee5a MOV %RCX,-0x38(%RBP) |
0x40ee5e VPBROADCASTQ %XMM0,%YMM1 |
0x40ee63 MOV %EAX,%ESI |
0x40ee65 SAL $0x6,%ESI |
0x40ee68 XOR %EDI,%EDI |
0x40ee6a VMOVUPD 0x133ce(%RIP),%YMM2 |
0x40ee72 VMOVUPD 0x133e6(%RIP),%YMM3 |
0x40ee7a VBROADCASTF128 0x1345d(%RIP),%YMM4 |
0x40ee83 VMOVUPD 0x13415(%RIP),%YMM5 |
0x40ee8b VMOVUPD 0x133ed(%RIP),%YMM6 |
0x40ee93 JMP 40eeb4 |
0x40ee95 NOPW %CS:(%RAX,%RAX,1) |
(97) 0x40eea0 LEA 0x1(%RDI),%RCX |
(97) 0x40eea4 ADD $0x40,%ESI |
(97) 0x40eea7 CMP -0x38(%RBP),%RDI |
(97) 0x40eeab MOV %RCX,%RDI |
(97) 0x40eeae JE 40ee20 |
(97) 0x40eeb4 MOV %ESI,%ESI |
(97) 0x40eeb6 LEA (%RDI,%RAX,1),%RCX |
(97) 0x40eeba MOV -0x58(%RBP),%RDX |
(97) 0x40eebe MOV (%RDX,%RCX,4),%R8D |
(97) 0x40eec2 TEST %R8D,%R8D |
(97) 0x40eec5 JLE 40eea0 |
(97) 0x40eec7 LEA (,%RSI,8),%RCX |
(97) 0x40eecf LEA (,%RSI,4),%R12 |
(97) 0x40eed7 LEA (%RDI,%RAX,1),%EBX |
(97) 0x40eeda SAL $0x6,%EBX |
(97) 0x40eedd MOV -0x50(%RBP),%R9 |
(97) 0x40eee1 MOV 0x20(%R9),%RDX |
(97) 0x40eee5 MOV 0x28(%R9),%R9 |
(97) 0x40eee9 MOV 0x10(%RDX),%R15 |
(97) 0x40eeed MOV 0x18(%RDX),%R10 |
(97) 0x40eef1 MOV 0x20(%RDX),%R11 |
(97) 0x40eef5 LEA -0x1(%R8),%EDX |
(97) 0x40eef9 MOVSXD %EDX,%RDX |
(97) 0x40eefc ADD %RBX,%RDX |
(97) 0x40eeff SAL $0x3,%RDX |
(97) 0x40ef03 LEA (%RDX,%RDX,2),%RDX |
(97) 0x40ef07 LEA 0x10(%R11,%RDX,1),%R14 |
(97) 0x40ef0c SAL $0x3,%RBX |
(97) 0x40ef10 LEA (%RBX,%RBX,2),%RBX |
(97) 0x40ef14 LEA (%R10,%RBX,1),%R13 |
(97) 0x40ef18 CMP %R13,%R14 |
(97) 0x40ef1b JB 40efa0 |
(97) 0x40ef21 ADD %R11,%RBX |
(97) 0x40ef24 LEA 0x10(%R10,%RDX,1),%RDX |
(97) 0x40ef29 CMP %RBX,%RDX |
(97) 0x40ef2c JB 40efa0 |
(97) 0x40ef2e LEA 0x10(%RCX,%RCX,2),%RCX |
(97) 0x40ef33 ADD %R12,%R15 |
(97) 0x40ef36 XOR %EDX,%EDX |
(97) 0x40ef38 NOPL (%RAX,%RAX,1) |
(100) 0x40ef40 MOVSXD (%R15,%RDX,4),%RBX |
(100) 0x40ef44 SAL $0x4,%RBX |
(100) 0x40ef48 VDIVSD 0x8(%R9,%RBX,1),%XMM0,%XMM7 |
(100) 0x40ef4f VMOVSD -0x10(%R11,%RCX,1),%XMM8 |
(100) 0x40ef56 VFMADD213SD -0x10(%R10,%RCX,1),%XMM7,%XMM8 |
(100) 0x40ef5d VMOVSD %XMM8,-0x10(%R10,%RCX,1) |
(100) 0x40ef64 VMOVSD -0x8(%R11,%RCX,1),%XMM8 |
(100) 0x40ef6b VFMADD213SD -0x8(%R10,%RCX,1),%XMM7,%XMM8 |
(100) 0x40ef72 VMOVSD %XMM8,-0x8(%R10,%RCX,1) |
(100) 0x40ef79 VMOVSD (%R11,%RCX,1),%XMM8 |
(100) 0x40ef7f VFMADD213SD (%R10,%RCX,1),%XMM7,%XMM8 |
(100) 0x40ef85 VMOVSD %XMM8,(%R10,%RCX,1) |
(100) 0x40ef8b ADD $0x18,%RCX |
(100) 0x40ef8f INC %RDX |
(100) 0x40ef92 CMP %EDX,%R8D |
(100) 0x40ef95 JNE 40ef40 |
(97) 0x40ef97 JMP 40eea0 |
0x40ef9c NOPL (%RAX) |
(97) 0x40efa0 LEA (%RCX,%RCX,2),%RCX |
(97) 0x40efa4 MOV %R8D,%R14D |
(97) 0x40efa7 AND $-0x4,%R14D |
(97) 0x40efab JE 40f0e2 |
(97) 0x40efb1 LEA -0x1(%R14),%EDX |
(97) 0x40efb5 ADD %R15,%R12 |
(97) 0x40efb8 MOV %RCX,%R13 |
(97) 0x40efbb XOR %EBX,%EBX |
(97) 0x40efbd NOPL (%RAX) |
(99) 0x40efc0 VPMOVSXDQ (%R12,%RBX,4),%YMM7 |
(99) 0x40efc6 KXNORW %K0,%K0,%K1 |
(99) 0x40efca VXORPD %XMM8,%XMM8,%XMM8 |
(99) 0x40efcf VPSLLQ $0x4,%YMM7,%YMM7 |
(99) 0x40efd4 VGATHERQPD 0x8(%R9,%YMM7,1),%YMM8{%K1} |
(99) 0x40efdc VDIVPD %YMM8,%YMM1,%YMM7 |
(99) 0x40efe1 VMOVUPD 0x20(%R11,%R13,1),%YMM8 |
(99) 0x40efe8 VMOVUPD 0x20(%R10,%R13,1),%YMM9 |
(99) 0x40efef VMOVUPD 0x10(%R11,%R13,1),%XMM10 |
(99) 0x40eff6 VMOVUPD 0x10(%R10,%R13,1),%XMM11 |
(99) 0x40effd VBLENDPD $0x3,(%R11,%R13,1),%YMM8,%YMM12 |
(99) 0x40f004 VBLENDPD $0x3,(%R10,%R13,1),%YMM9,%YMM13 |
(99) 0x40f00b VINSERTF128 $0x1,0x40(%R11,%R13,1),%YMM10,%YMM10 |
(99) 0x40f013 VINSERTF128 $0x1,0x40(%R10,%R13,1),%YMM11,%YMM11 |
(99) 0x40f01b VBROADCASTSD 0x50(%R11,%R13,1),%YMM14 |
(99) 0x40f022 VBROADCASTSD 0x50(%R10,%R13,1),%YMM15 |
(99) 0x40f029 VSHUFPD $0x5,%YMM8,%YMM12,%YMM8 |
(99) 0x40f02f VBLENDPD $0x8,%YMM14,%YMM8,%YMM8 |
(99) 0x40f035 VMOVUPD 0x20(%R11,%R13,1),%XMM14 |
(99) 0x40f03c VSHUFPD $0x5,%YMM9,%YMM13,%YMM9 |
(99) 0x40f042 VBLENDPD $0x8,%YMM15,%YMM9,%YMM9 |
(99) 0x40f048 VMOVUPD 0x20(%R10,%R13,1),%XMM15 |
(99) 0x40f04f VBLENDPD $0xc,0x40(%R11,%R13,1),%YMM14,%YMM14 |
(99) 0x40f057 VBLENDPD $0xc,0x40(%R10,%R13,1),%YMM15,%YMM15 |
(99) 0x40f05f VBLENDPD $0xa,%YMM10,%YMM12,%YMM12 |
(99) 0x40f065 VBLENDPD $0xa,%YMM11,%YMM13,%YMM13 |
(99) 0x40f06b VFMADD231PD %YMM12,%YMM7,%YMM13 |
(99) 0x40f070 VFMADD231PD %YMM8,%YMM7,%YMM9 |
(99) 0x40f075 VBLENDPD $0xa,%YMM14,%YMM10,%YMM8 |
(99) 0x40f07b VBLENDPD $0xa,%YMM15,%YMM11,%YMM10 |
(99) 0x40f081 VFMADD231PD %YMM8,%YMM7,%YMM10 |
(99) 0x40f086 VMOVAPD %YMM9,%YMM7 |
(99) 0x40f08a VPERMT2PD %YMM13,%YMM2,%YMM7 |
(99) 0x40f090 VMOVAPD %YMM13,%YMM8 |
(99) 0x40f095 VPERMT2PD %YMM9,%YMM3,%YMM8 |
(99) 0x40f09b VPERMT2PD %YMM13,%YMM4,%YMM9 |
(99) 0x40f0a1 VPERMT2PD %YMM10,%YMM6,%YMM8 |
(99) 0x40f0a7 VBLENDPD $0x2,%YMM10,%YMM7,%YMM7 |
(99) 0x40f0ad VMOVUPD %YMM7,0x20(%R10,%R13,1) |
(99) 0x40f0b4 VMOVUPD %YMM8,(%R10,%R13,1) |
(99) 0x40f0ba VPERMT2PD %YMM9,%YMM5,%YMM10 |
(99) 0x40f0c0 VMOVUPD %YMM10,0x40(%R10,%R13,1) |
(99) 0x40f0c7 ADD $0x4,%RBX |
(99) 0x40f0cb ADD $0x60,%R13 |
(99) 0x40f0cf CMP %EDX,%EBX |
(99) 0x40f0d1 JLE 40efc0 |
(97) 0x40f0d7 CMP %R14D,%R8D |
(97) 0x40f0da JE 40eea0 |
(97) 0x40f0e0 JMP 40f0e5 |
(97) 0x40f0e2 XOR %R14D,%R14D |
(97) 0x40f0e5 SUB %R14D,%R8D |
(97) 0x40f0e8 MOVSXD %R14D,%RDX |
(97) 0x40f0eb LEA (%RDX,%RDX,2),%RBX |
(97) 0x40f0ef LEA (%RCX,%RBX,8),%RCX |
(97) 0x40f0f3 ADD %RCX,%R10 |
(97) 0x40f0f6 ADD %RCX,%R11 |
(97) 0x40f0f9 ADD %RSI,%RDX |
(97) 0x40f0fc LEA (%R15,%RDX,4),%RCX |
(97) 0x40f100 XOR %EDX,%EDX |
(97) 0x40f102 XOR %EBX,%EBX |
(97) 0x40f104 NOPW %CS:(%RAX,%RAX,1) |
(98) 0x40f110 MOVSXD (%RCX,%RBX,4),%R14 |
(98) 0x40f114 SAL $0x4,%R14 |
(98) 0x40f118 VDIVSD 0x8(%R9,%R14,1),%XMM0,%XMM7 |
(98) 0x40f11f VMOVUPD (%R11,%RDX,1),%XMM8 |
(98) 0x40f125 VMOVDDUP %XMM7,%XMM9 |
(98) 0x40f129 VFMADD213PD (%R10,%RDX,1),%XMM8,%XMM9 |
(98) 0x40f12f VMOVUPD %XMM9,(%R10,%RDX,1) |
(98) 0x40f135 VMOVSD 0x10(%R11,%RDX,1),%XMM8 |
(98) 0x40f13c VFMADD213SD 0x10(%R10,%RDX,1),%XMM7,%XMM8 |
(98) 0x40f143 VMOVSD %XMM8,0x10(%R10,%RDX,1) |
(98) 0x40f14a INC %RBX |
(98) 0x40f14d ADD $0x18,%RDX |
(98) 0x40f151 CMP %EBX,%R8D |
(98) 0x40f154 JNE 40f110 |
(97) 0x40f156 JMP 40eea0 |
0x40f15b NOPL (%RAX,%RAX,1) |
Path / |
Source file and lines | timestep.c:85-94 |
Module | exec |
nb instructions | 65 |
nb uops | 67 |
loop length | 249 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 6 |
used zmm registers | 0 |
nb stack references | 8 |
micro-operation queue | 11.17 cycles |
front end | 11.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.80 | 1.80 | 6.33 | 6.33 | 9.50 | 2.00 | 1.80 | 9.50 | 9.50 | 9.50 | 1.60 | 6.33 |
cycles | 1.80 | 1.80 | 6.33 | 6.33 | 9.50 | 2.00 | 1.80 | 9.50 | 9.50 | 9.50 | 1.60 | 6.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 11.04-11.11 |
Stall cycles | 0.00 |
Front-end | 11.17 |
Dispatch | 9.50 |
Overall L1 | 11.17 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 21% |
load | 71% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 22% |
all | 10% |
load | 6% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 45% |
load | 45% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 16% |
load | 33% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x38,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0,-0x44(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9D,-0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x40(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x44(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x30(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x2c(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x62c950,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,-0x3c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 402d40 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x30(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x2c(%RBP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 40ee3e <advancePosition.extracted+0x8e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x62c970,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x3c(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x38,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 402c00 <__kmpc_for_static_fini@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VMOVQ %R15,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV -0x50(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RCX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RCX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x38(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VPBROADCASTQ %XMM0,%YMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x6,%ESI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVUPD 0x133ce(%RIP),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x133e6(%RIP),%YMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VBROADCASTF128 0x1345d(%RIP),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 5-8 | 0.33 |
VMOVUPD 0x13415(%RIP),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x133ed(%RIP),%YMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
JMP 40eeb4 <advancePosition.extracted+0x104> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | timestep.c:85-94 |
Module | exec |
nb instructions | 65 |
nb uops | 67 |
loop length | 249 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 6 |
used zmm registers | 0 |
nb stack references | 8 |
micro-operation queue | 11.17 cycles |
front end | 11.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.80 | 1.80 | 6.33 | 6.33 | 9.50 | 2.00 | 1.80 | 9.50 | 9.50 | 9.50 | 1.60 | 6.33 |
cycles | 1.80 | 1.80 | 6.33 | 6.33 | 9.50 | 2.00 | 1.80 | 9.50 | 9.50 | 9.50 | 1.60 | 6.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 11.04-11.11 |
Stall cycles | 0.00 |
Front-end | 11.17 |
Dispatch | 9.50 |
Overall L1 | 11.17 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 21% |
load | 71% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 22% |
all | 10% |
load | 6% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 45% |
load | 45% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 16% |
load | 33% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x38,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0,-0x44(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9D,-0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x40(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x44(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x30(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x2c(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x62c950,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,-0x3c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 402d40 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x30(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x2c(%RBP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 40ee3e <advancePosition.extracted+0x8e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x62c970,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x3c(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x38,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 402c00 <__kmpc_for_static_fini@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VMOVQ %R15,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV -0x50(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RCX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RCX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x38(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VPBROADCASTQ %XMM0,%YMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x6,%ESI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVUPD 0x133ce(%RIP),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x133e6(%RIP),%YMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VBROADCASTF128 0x1345d(%RIP),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 5-8 | 0.33 |
VMOVUPD 0x13415(%RIP),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x133ed(%RIP),%YMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
JMP 40eeb4 <advancePosition.extracted+0x104> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advancePosition.extracted– | 1.42 | 0.37 |
▼Loop 97 - timestep.c:85-94 - exec– | 0.03 | 0.01 |
○Loop 99 - timestep.c:88-94 - exec | 1.33 | 0.35 |
○Loop 98 - timestep.c:88-94 - exec | 0.07 | 0.02 |
○Loop 100 - timestep.c:88-94 - exec | 0 | 0 |