Loop Id: 83 | Module: exec | Source: ljForce.c:187-216 [...] | Coverage: 4.96% |
---|
Loop Id: 83 | Module: exec | Source: ljForce.c:187-216 [...] | Coverage: 4.96% |
---|
0x40b1b0 CMP %R13D,%R11D |
0x40b1b3 JGE 40b3f1 |
0x40b1b9 MOV 0x20(%R15),%R9 |
0x40b1bd LEA (%R8,%R8,2),%R10 |
0x40b1c1 MOV 0x18(%R9),%RCX |
0x40b1c5 LEA (%RCX,%R12,1),%RAX |
0x40b1c9 LEA (%RCX,%R10,1),%RDX |
0x40b1cd ADD %R14,%RCX |
0x40b1d0 MOV %RCX,%RSI |
0x40b1d3 SUB %RAX,%RSI |
0x40b1d6 AND $0x8,%ESI |
0x40b1d9 JE 40b298 |
0x40b1df VMOVUPD (%RDX),%XMM2 |
0x40b1e3 VMOVSD 0x10(%RDX),%XMM14 |
0x40b1e8 VMOVSD (%RDX),%XMM1 |
0x40b1ec VSUBPD (%RAX),%XMM2,%XMM3 |
0x40b1f0 VSUBSD 0x10(%RAX),%XMM14,%XMM2 |
0x40b1f5 VSUBSD (%RAX),%XMM1,%XMM0 |
0x40b1f9 VMULSD %XMM2,%XMM2,%XMM1 |
0x40b1fd VUNPCKHPD %XMM3,%XMM3,%XMM15 |
0x40b201 VFMADD132SD %XMM0,%XMM1,%XMM0 |
0x40b206 VFMADD132SD %XMM15,%XMM0,%XMM15 |
0x40b20b VCOMISD %XMM15,%XMM4 |
0x40b210 JB 40b285 |
0x40b212 VCOMISD %XMM5,%XMM15 |
0x40b216 JBE 40b285 |
0x40b218 VDIVSD %XMM15,%XMM8,%XMM15 |
0x40b21d MOV 0x30(%R9),%RSI |
0x40b221 ADD %R8,%RSI |
0x40b224 VMULSD %XMM15,%XMM15,%XMM1 |
0x40b229 VMULSD %XMM15,%XMM11,%XMM0 |
0x40b22e VMULSD %XMM9,%XMM15,%XMM14 |
0x40b233 VMULSD %XMM0,%XMM1,%XMM0 |
0x40b237 VSUBSD %XMM8,%XMM0,%XMM1 |
0x40b23c VFMSUB132SD %XMM0,%XMM10,%XMM1 |
0x40b241 VMOVSD %XMM1,%XMM1,%XMM15 |
0x40b245 VFMADD231SD %XMM7,%XMM1,%XMM6 |
0x40b24a VMOVSD %XMM0,%XMM0,%XMM1 |
0x40b24e VFMADD132SD %XMM12,%XMM13,%XMM1 |
0x40b253 VFMADD213SD (%RSI),%XMM7,%XMM15 |
0x40b258 VMULSD %XMM1,%XMM0,%XMM0 |
0x40b25c VMOVSD %XMM15,(%RSI) |
0x40b260 MOV 0x28(%R9),%RSI |
0x40b264 ADD %R10,%RSI |
0x40b267 VMULSD %XMM14,%XMM0,%XMM14 |
0x40b26c VMOVDDUP %XMM14,%XMM15 |
0x40b271 VFNMADD213SD 0x10(%RSI),%XMM2,%XMM14 |
0x40b277 VFNMADD213PD (%RSI),%XMM15,%XMM3 |
0x40b27c VMOVSD %XMM14,0x10(%RSI) |
0x40b281 VMOVUPD %XMM3,(%RSI) |
0x40b285 ADD $0x18,%RAX |
0x40b289 CMP %RCX,%RAX |
0x40b28c JE 40b3f1 |
0x40b292 NOPW (%RAX,%RAX,1) |
(84) 0x40b298 VMOVSD (%RDX),%XMM2 |
(84) 0x40b29c VMOVSD 0x10(%RDX),%XMM14 |
(84) 0x40b2a1 VMOVUPD (%RDX),%XMM3 |
(84) 0x40b2a5 VSUBSD (%RAX),%XMM2,%XMM1 |
(84) 0x40b2a9 VSUBSD 0x10(%RAX),%XMM14,%XMM2 |
(84) 0x40b2ae VSUBPD (%RAX),%XMM3,%XMM3 |
(84) 0x40b2b2 VMULSD %XMM2,%XMM2,%XMM15 |
(84) 0x40b2b6 VUNPCKHPD %XMM3,%XMM3,%XMM0 |
(84) 0x40b2ba VFMADD132SD %XMM1,%XMM15,%XMM1 |
(84) 0x40b2bf VFMADD132SD %XMM0,%XMM1,%XMM0 |
(84) 0x40b2c4 VCOMISD %XMM0,%XMM4 |
(84) 0x40b2c8 JB 40b33b |
(84) 0x40b2ca VCOMISD %XMM5,%XMM0 |
(84) 0x40b2ce JBE 40b33b |
(84) 0x40b2d0 VDIVSD %XMM0,%XMM8,%XMM0 |
(84) 0x40b2d4 MOV 0x30(%R9),%RSI |
(84) 0x40b2d8 ADD %R8,%RSI |
(84) 0x40b2db VMULSD %XMM0,%XMM0,%XMM1 |
(84) 0x40b2df VMULSD %XMM0,%XMM11,%XMM15 |
(84) 0x40b2e3 VMULSD %XMM9,%XMM0,%XMM14 |
(84) 0x40b2e8 VMULSD %XMM15,%XMM1,%XMM0 |
(84) 0x40b2ed VSUBSD %XMM8,%XMM0,%XMM1 |
(84) 0x40b2f2 VFMSUB132SD %XMM0,%XMM10,%XMM1 |
(84) 0x40b2f7 VMOVSD %XMM1,%XMM1,%XMM15 |
(84) 0x40b2fb VFMADD231SD %XMM7,%XMM1,%XMM6 |
(84) 0x40b300 VMOVSD %XMM0,%XMM0,%XMM1 |
(84) 0x40b304 VFMADD132SD %XMM12,%XMM13,%XMM1 |
(84) 0x40b309 VFMADD213SD (%RSI),%XMM7,%XMM15 |
(84) 0x40b30e VMULSD %XMM1,%XMM0,%XMM0 |
(84) 0x40b312 VMOVSD %XMM15,(%RSI) |
(84) 0x40b316 MOV 0x28(%R9),%RSI |
(84) 0x40b31a ADD %R10,%RSI |
(84) 0x40b31d VMULSD %XMM14,%XMM0,%XMM14 |
(84) 0x40b322 VMOVDDUP %XMM14,%XMM15 |
(84) 0x40b327 VFNMADD213SD 0x10(%RSI),%XMM2,%XMM14 |
(84) 0x40b32d VFNMADD213PD (%RSI),%XMM15,%XMM3 |
(84) 0x40b332 VMOVSD %XMM14,0x10(%RSI) |
(84) 0x40b337 VMOVUPD %XMM3,(%RSI) |
(84) 0x40b33b VMOVSD (%RDX),%XMM2 |
(84) 0x40b33f VMOVSD 0x10(%RDX),%XMM14 |
(84) 0x40b344 LEA 0x18(%RAX),%RSI |
(84) 0x40b348 VMOVUPD (%RDX),%XMM3 |
(84) 0x40b34c VSUBSD 0x18(%RAX),%XMM2,%XMM1 |
(84) 0x40b351 VSUBSD 0x28(%RAX),%XMM14,%XMM2 |
(84) 0x40b356 VSUBPD 0x18(%RAX),%XMM3,%XMM3 |
(84) 0x40b35b VMULSD %XMM2,%XMM2,%XMM15 |
(84) 0x40b35f VUNPCKHPD %XMM3,%XMM3,%XMM0 |
(84) 0x40b363 VFMADD132SD %XMM1,%XMM15,%XMM1 |
(84) 0x40b368 VFMADD132SD %XMM0,%XMM1,%XMM0 |
(84) 0x40b36d VCOMISD %XMM0,%XMM4 |
(84) 0x40b371 JB 40b3e4 |
(84) 0x40b373 VCOMISD %XMM5,%XMM0 |
(84) 0x40b377 JBE 40b3e4 |
(84) 0x40b379 VDIVSD %XMM0,%XMM8,%XMM0 |
(84) 0x40b37d MOV 0x30(%R9),%RAX |
(84) 0x40b381 ADD %R8,%RAX |
(84) 0x40b384 VMULSD %XMM0,%XMM0,%XMM1 |
(84) 0x40b388 VMULSD %XMM0,%XMM11,%XMM15 |
(84) 0x40b38c VMULSD %XMM9,%XMM0,%XMM14 |
(84) 0x40b391 VMULSD %XMM15,%XMM1,%XMM0 |
(84) 0x40b396 VSUBSD %XMM8,%XMM0,%XMM1 |
(84) 0x40b39b VFMSUB132SD %XMM0,%XMM10,%XMM1 |
(84) 0x40b3a0 VMOVSD %XMM1,%XMM1,%XMM15 |
(84) 0x40b3a4 VFMADD231SD %XMM7,%XMM1,%XMM6 |
(84) 0x40b3a9 VMOVSD %XMM0,%XMM0,%XMM1 |
(84) 0x40b3ad VFMADD132SD %XMM12,%XMM13,%XMM1 |
(84) 0x40b3b2 VFMADD213SD (%RAX),%XMM7,%XMM15 |
(84) 0x40b3b7 VMULSD %XMM1,%XMM0,%XMM0 |
(84) 0x40b3bb VMOVSD %XMM15,(%RAX) |
(84) 0x40b3bf MOV 0x28(%R9),%RAX |
(84) 0x40b3c3 ADD %R10,%RAX |
(84) 0x40b3c6 VMULSD %XMM14,%XMM0,%XMM14 |
(84) 0x40b3cb VMOVDDUP %XMM14,%XMM15 |
(84) 0x40b3d0 VFNMADD213SD 0x10(%RAX),%XMM2,%XMM14 |
(84) 0x40b3d6 VFNMADD213PD (%RAX),%XMM15,%XMM3 |
(84) 0x40b3db VMOVSD %XMM14,0x10(%RAX) |
(84) 0x40b3e0 VMOVUPD %XMM3,(%RAX) |
(84) 0x40b3e4 LEA 0x18(%RSI),%RAX |
(84) 0x40b3e8 CMP %RCX,%RAX |
(84) 0x40b3eb JNE 40b298 |
0x40b3f1 ADD $0x8,%R8 |
0x40b3f5 CMP %RBX,%R8 |
0x40b3f8 JNE 40b1b0 |
/scratch_na/users/xoserete/qaas_runs/171-172-2581/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 187 - 216 |
-------------------------------------------------------------------------------- |
187: for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++) |
188: { |
189: |
190: // loop over atoms in jBox |
191: for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++) |
[...] |
197: dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m]; |
198: r2+=dr[m]*dr[m]; |
199: } |
200: |
201: if ( r2 <= rCut2 && r2 > 0.0) |
202: { |
203: |
204: // Important note: |
205: // from this point on r actually refers to 1.0/r |
206: r2 = 1.0/r2; |
207: real_t r6 = s6 * (r2*r2*r2); |
208: real_t eLocal = r6 * (r6 - 1.0) - eShift; |
209: s->atoms->U[iOff] += 0.5*eLocal; |
210: ePot += 0.5*eLocal; |
211: |
212: // different formulation to avoid sqrt computation |
213: real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0); |
214: for (int m=0; m<3; m++) |
215: { |
216: s->atoms->f[iOff][m] -= dr[m]*fr; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 3.29 |
CQA speedup if fully vectorized | 5.25 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.05 |
Bottlenecks | P0, |
Function | ljForce._omp_fn.1 |
Source | ljForce.c:187-187,ljForce.c:191-191,ljForce.c:197-198,ljForce.c:201-201,ljForce.c:206-210,ljForce.c:213-213,ljForce.c:216-216 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 10.50 |
CQA cycles if no scalar integer | 10.50 |
CQA cycles if FP arith vectorized | 3.19 |
CQA cycles if fully vectorized | 2.00 |
Front-end cycles | 9.33 |
DIV/SQRT cycles | 10.50 |
P0 cycles | 10.00 |
P1 cycles | 4.33 |
P2 cycles | 4.33 |
P3 cycles | 1.50 |
P4 cycles | 6.10 |
P5 cycles | 6.20 |
P6 cycles | 1.50 |
P7 cycles | 1.50 |
P8 cycles | 1.50 |
P9 cycles | 6.20 |
P10 cycles | 4.33 |
P11 cycles | 4.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 10.90 - 11.13 |
Stall cycles (UFS) | 0.76 - 0.99 |
Nb insns | 57.00 |
Nb uops | 56.00 |
Nb loads | 13.00 |
Nb stores | 3.00 |
Nb stack references | 0.00 |
FLOP/cycle | 2.95 |
Nb FLOP add-sub | 5.00 |
Nb FLOP mul | 7.00 |
Nb FLOP fma | 9.00 |
Nb FLOP div | 1.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 15.24 |
Bytes prefetched | 0.00 |
Bytes loaded | 128.00 |
Bytes stored | 32.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 11.76 |
Vectorization ratio load | 33.33 |
Vectorization ratio store | 33.33 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 25.00 |
Vectorization ratio fma | 12.50 |
Vectorization ratio div_sqrt | 0.00 |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 13.79 |
Vector-efficiency ratio load | 16.67 |
Vector-efficiency ratio store | 16.67 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 15.63 |
Vector-efficiency ratio fma | 14.06 |
Vector-efficiency ratio div_sqrt | 12.50 |
Vector-efficiency ratio other | 11.72 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 3.29 |
CQA speedup if fully vectorized | 5.25 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.05 |
Bottlenecks | P0, |
Function | ljForce._omp_fn.1 |
Source | ljForce.c:187-187,ljForce.c:191-191,ljForce.c:197-198,ljForce.c:201-201,ljForce.c:206-210,ljForce.c:213-213,ljForce.c:216-216 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 10.50 |
CQA cycles if no scalar integer | 10.50 |
CQA cycles if FP arith vectorized | 3.19 |
CQA cycles if fully vectorized | 2.00 |
Front-end cycles | 9.33 |
DIV/SQRT cycles | 10.50 |
P0 cycles | 10.00 |
P1 cycles | 4.33 |
P2 cycles | 4.33 |
P3 cycles | 1.50 |
P4 cycles | 6.10 |
P5 cycles | 6.20 |
P6 cycles | 1.50 |
P7 cycles | 1.50 |
P8 cycles | 1.50 |
P9 cycles | 6.20 |
P10 cycles | 4.33 |
P11 cycles | 4.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 10.90 - 11.13 |
Stall cycles (UFS) | 0.76 - 0.99 |
Nb insns | 57.00 |
Nb uops | 56.00 |
Nb loads | 13.00 |
Nb stores | 3.00 |
Nb stack references | 0.00 |
FLOP/cycle | 2.95 |
Nb FLOP add-sub | 5.00 |
Nb FLOP mul | 7.00 |
Nb FLOP fma | 9.00 |
Nb FLOP div | 1.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 15.24 |
Bytes prefetched | 0.00 |
Bytes loaded | 128.00 |
Bytes stored | 32.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 11.76 |
Vectorization ratio load | 33.33 |
Vectorization ratio store | 33.33 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 25.00 |
Vectorization ratio fma | 12.50 |
Vectorization ratio div_sqrt | 0.00 |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 13.79 |
Vector-efficiency ratio load | 16.67 |
Vector-efficiency ratio store | 16.67 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 15.63 |
Vector-efficiency ratio fma | 14.06 |
Vector-efficiency ratio div_sqrt | 12.50 |
Vector-efficiency ratio other | 11.72 |
Path / |
Function | ljForce._omp_fn.1 |
Source file and lines | ljForce.c:187-216 |
Module | exec |
nb instructions | 57 |
nb uops | 56 |
loop length | 245 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 16 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 0.57 |
micro-operation queue | 9.33 cycles |
front end | 9.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 10.50 | 10.00 | 4.33 | 4.33 | 1.50 | 6.10 | 6.20 | 1.50 | 1.50 | 1.50 | 6.20 | 4.33 |
cycles | 10.50 | 10.00 | 4.33 | 4.33 | 1.50 | 6.10 | 6.20 | 1.50 | 1.50 | 1.50 | 6.20 | 4.33 |
Cycles executing div or sqrt instructions | 4.00 |
FE+BE cycles | 10.90-11.13 |
Stall cycles | 0.76-0.99 |
ROB full (events) | 0.96-1.22 |
RS full (events) | 0.06-0.11 |
Front-end | 9.33 |
Dispatch | 10.50 |
DIV/SQRT | 4.00 |
Overall L1 | 10.50 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 33% |
store | 33% |
mul | 0% |
add-sub | 25% |
fma | 12% |
div/sqrt | 0% |
other | 0% |
all | 11% |
load | 33% |
store | 33% |
mul | 0% |
add-sub | 25% |
fma | 12% |
div/sqrt | 0% |
other | 0% |
all | 9% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 14% |
load | 16% |
store | 16% |
mul | 12% |
add-sub | 15% |
fma | 14% |
div/sqrt | 12% |
other | 12% |
all | 13% |
load | 16% |
store | 16% |
mul | 12% |
add-sub | 15% |
fma | 14% |
div/sqrt | 12% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CMP %R13D,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 40b3f1 <ljForce._omp_fn.1+0x3d1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x20(%R15),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R8,%R8,2),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x18(%R9),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RCX,%R12,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%RCX,%R10,1),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %R14,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
AND $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 40b298 <ljForce._omp_fn.1+0x278> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVUPD (%RDX),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVSD 0x10(%RDX),%XMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RDX),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VSUBPD (%RAX),%XMM2,%XMM3 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VSUBSD 0x10(%RAX),%XMM14,%XMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VSUBSD (%RAX),%XMM1,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMULSD %XMM2,%XMM2,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VUNPCKHPD %XMM3,%XMM3,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VFMADD132SD %XMM0,%XMM1,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132SD %XMM15,%XMM0,%XMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCOMISD %XMM15,%XMM4 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JB 40b285 <ljForce._omp_fn.1+0x265> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VCOMISD %XMM5,%XMM15 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JBE 40b285 <ljForce._omp_fn.1+0x265> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VDIVSD %XMM15,%XMM8,%XMM15 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
MOV 0x30(%R9),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R8,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMULSD %XMM15,%XMM15,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD %XMM15,%XMM11,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD %XMM9,%XMM15,%XMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD %XMM0,%XMM1,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VSUBSD %XMM8,%XMM0,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMSUB132SD %XMM0,%XMM10,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM1,%XMM1,%XMM15 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VFMADD231SD %XMM7,%XMM1,%XMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM0,%XMM0,%XMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VFMADD132SD %XMM12,%XMM13,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SD (%RSI),%XMM7,%XMM15 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMULSD %XMM1,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM15,(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%R9),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R10,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMULSD %XMM14,%XMM0,%XMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVDDUP %XMM14,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VFNMADD213SD 0x10(%RSI),%XMM2,%XMM14 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFNMADD213PD (%RSI),%XMM15,%XMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM14,0x10(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVUPD %XMM3,(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
ADD $0x18,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 40b3f1 <ljForce._omp_fn.1+0x3d1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x8,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RBX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 40b1b0 <ljForce._omp_fn.1+0x190> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | ljForce._omp_fn.1 |
Source file and lines | ljForce.c:187-216 |
Module | exec |
nb instructions | 57 |
nb uops | 56 |
loop length | 245 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 16 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 0.57 |
micro-operation queue | 9.33 cycles |
front end | 9.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 10.50 | 10.00 | 4.33 | 4.33 | 1.50 | 6.10 | 6.20 | 1.50 | 1.50 | 1.50 | 6.20 | 4.33 |
cycles | 10.50 | 10.00 | 4.33 | 4.33 | 1.50 | 6.10 | 6.20 | 1.50 | 1.50 | 1.50 | 6.20 | 4.33 |
Cycles executing div or sqrt instructions | 4.00 |
FE+BE cycles | 10.90-11.13 |
Stall cycles | 0.76-0.99 |
ROB full (events) | 0.96-1.22 |
RS full (events) | 0.06-0.11 |
Front-end | 9.33 |
Dispatch | 10.50 |
DIV/SQRT | 4.00 |
Overall L1 | 10.50 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 33% |
store | 33% |
mul | 0% |
add-sub | 25% |
fma | 12% |
div/sqrt | 0% |
other | 0% |
all | 11% |
load | 33% |
store | 33% |
mul | 0% |
add-sub | 25% |
fma | 12% |
div/sqrt | 0% |
other | 0% |
all | 9% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 14% |
load | 16% |
store | 16% |
mul | 12% |
add-sub | 15% |
fma | 14% |
div/sqrt | 12% |
other | 12% |
all | 13% |
load | 16% |
store | 16% |
mul | 12% |
add-sub | 15% |
fma | 14% |
div/sqrt | 12% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CMP %R13D,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 40b3f1 <ljForce._omp_fn.1+0x3d1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x20(%R15),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R8,%R8,2),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x18(%R9),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RCX,%R12,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%RCX,%R10,1),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %R14,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
AND $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 40b298 <ljForce._omp_fn.1+0x278> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVUPD (%RDX),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVSD 0x10(%RDX),%XMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD (%RDX),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VSUBPD (%RAX),%XMM2,%XMM3 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VSUBSD 0x10(%RAX),%XMM14,%XMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VSUBSD (%RAX),%XMM1,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMULSD %XMM2,%XMM2,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VUNPCKHPD %XMM3,%XMM3,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VFMADD132SD %XMM0,%XMM1,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132SD %XMM15,%XMM0,%XMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCOMISD %XMM15,%XMM4 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JB 40b285 <ljForce._omp_fn.1+0x265> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VCOMISD %XMM5,%XMM15 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JBE 40b285 <ljForce._omp_fn.1+0x265> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VDIVSD %XMM15,%XMM8,%XMM15 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
MOV 0x30(%R9),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R8,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMULSD %XMM15,%XMM15,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD %XMM15,%XMM11,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD %XMM9,%XMM15,%XMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD %XMM0,%XMM1,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VSUBSD %XMM8,%XMM0,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMSUB132SD %XMM0,%XMM10,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM1,%XMM1,%XMM15 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VFMADD231SD %XMM7,%XMM1,%XMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM0,%XMM0,%XMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VFMADD132SD %XMM12,%XMM13,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SD (%RSI),%XMM7,%XMM15 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMULSD %XMM1,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM15,(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%R9),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R10,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMULSD %XMM14,%XMM0,%XMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVDDUP %XMM14,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VFNMADD213SD 0x10(%RSI),%XMM2,%XMM14 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFNMADD213PD (%RSI),%XMM15,%XMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM14,0x10(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVUPD %XMM3,(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
ADD $0x18,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 40b3f1 <ljForce._omp_fn.1+0x3d1> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x8,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RBX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 40b1b0 <ljForce._omp_fn.1+0x190> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |