Function: ljForce._omp_fn.1 | Module: exec | Source: ljForce.c:172-216 [...] | Coverage: 65.1% |
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Function: ljForce._omp_fn.1 | Module: exec | Source: ljForce.c:172-216 [...] | Coverage: 65.1% |
---|
/scratch_na/users/xoserete/qaas_runs/171-172-2581/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 172 - 216 |
-------------------------------------------------------------------------------- |
172: #pragma omp parallel for reduction(+:ePot) |
173: for (int iBox=0; iBox<s->boxes->nLocalBoxes; iBox++) |
174: { |
175: int nIBox = s->boxes->nAtoms[iBox]; |
176: |
177: // loop over neighbors of iBox |
178: for (int jTmp=0; jTmp<nNbrBoxes; jTmp++) |
179: { |
180: int jBox = s->boxes->nbrBoxes[iBox][jTmp]; |
181: |
182: assert(jBox>=0); |
183: |
184: int nJBox = s->boxes->nAtoms[jBox]; |
185: |
186: // loop over atoms in iBox |
187: for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++) |
188: { |
189: |
190: // loop over atoms in jBox |
191: for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++) |
[...] |
197: dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m]; |
198: r2+=dr[m]*dr[m]; |
199: } |
200: |
201: if ( r2 <= rCut2 && r2 > 0.0) |
202: { |
203: |
204: // Important note: |
205: // from this point on r actually refers to 1.0/r |
206: r2 = 1.0/r2; |
207: real_t r6 = s6 * (r2*r2*r2); |
208: real_t eLocal = r6 * (r6 - 1.0) - eShift; |
209: s->atoms->U[iOff] += 0.5*eLocal; |
210: ePot += 0.5*eLocal; |
211: |
212: // different formulation to avoid sqrt computation |
213: real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0); |
214: for (int m=0; m<3; m++) |
215: { |
216: s->atoms->f[iOff][m] -= dr[m]*fr; |
0x40b020 PUSH %RBP |
0x40b021 MOV %RSP,%RBP |
0x40b024 PUSH %R15 |
0x40b026 PUSH %R14 |
0x40b028 PUSH %R13 |
0x40b02a PUSH %R12 |
0x40b02c MOV %RDI,%R12 |
0x40b02f PUSH %RBX |
0x40b030 SUB $0x58,%RSP |
0x40b034 VMOVSD 0x20(%RDI),%XMM10 |
0x40b039 VMOVSD 0x18(%RDI),%XMM11 |
0x40b03e VMOVSD 0x10(%RDI),%XMM4 |
0x40b043 MOV 0x30(%RDI),%EAX |
0x40b046 VMOVSD 0x8(%RDI),%XMM9 |
0x40b04b MOV (%RDI),%R15 |
0x40b04e VMOVSD %XMM10,-0x50(%RBP) |
0x40b053 VMOVSD %XMM11,-0x48(%RBP) |
0x40b058 VMOVSD %XMM4,-0x40(%RBP) |
0x40b05d MOV 0x18(%R15),%R13 |
0x40b061 VMOVSD %XMM9,-0x38(%RBP) |
0x40b066 MOV %EAX,-0x60(%RBP) |
0x40b069 CALL 403070 <omp_get_num_threads@plt> |
0x40b06e MOV %EAX,%EBX |
0x40b070 CALL 403160 <omp_get_thread_num@plt> |
0x40b075 VMOVSD -0x38(%RBP),%XMM0 |
0x40b07a VMOVSD -0x40(%RBP),%XMM4 |
0x40b07f MOV %EAX,%ECX |
0x40b081 MOV 0xc(%R13),%EAX |
0x40b085 VMOVSD -0x48(%RBP),%XMM11 |
0x40b08a VMOVSD -0x50(%RBP),%XMM10 |
0x40b08f CLTD |
0x40b090 IDIV %EBX |
0x40b092 CMP %EDX,%ECX |
0x40b094 JL 40b472 |
0x40b09a IMUL %EAX,%ECX |
0x40b09d ADD %ECX,%EDX |
0x40b09f ADD %EDX,%EAX |
0x40b0a1 MOV %EAX,-0x64(%RBP) |
0x40b0a4 CMP %EAX,%EDX |
0x40b0a6 JGE 40b488 |
0x40b0ac VMULSD 0x4fd4(%RIP),%XMM0,%XMM9 |
0x40b0b4 MOVSXD -0x60(%RBP),%RDI |
0x40b0b8 MOVSXD %EDX,%RSI |
0x40b0bb SAL $0x6,%EDX |
0x40b0be MOV 0x78(%R13),%R14 |
0x40b0c2 VMOVSD 0x466e(%RIP),%XMM8 |
0x40b0ca MOV %EDX,%ECX |
0x40b0cc VXORPD %XMM6,%XMM6,%XMM6 |
0x40b0d0 VMOVSD 0x4a10(%RIP),%XMM7 |
0x40b0d8 VMOVSD 0x4fb0(%RIP),%XMM12 |
0x40b0e0 LEA (,%RDI,4),%R11 |
0x40b0e8 MOV %RSI,%RDX |
(80) 0x40b0eb MOV -0x60(%RBP),%R9D |
(80) 0x40b0ef MOV (%R14,%RDX,4),%R8D |
(80) 0x40b0f3 TEST %R9D,%R9D |
(80) 0x40b0f6 JLE 40b429 |
(80) 0x40b0fc MOV 0x80(%R13),%RBX |
(80) 0x40b103 MOV %EDX,%EDI |
(80) 0x40b105 LEA (%R8,%RCX,1),%R10D |
(80) 0x40b109 MOV %R13,-0x70(%RBP) |
(80) 0x40b10d SAL $0x6,%EDI |
(80) 0x40b110 MOV %R10D,-0x48(%RBP) |
(80) 0x40b114 DEC %R10D |
(80) 0x40b117 VMOVSD 0x4f79(%RIP),%XMM13 |
(80) 0x40b11f MOV (%RBX,%RDX,8),%RAX |
(80) 0x40b123 MOVSXD %EDI,%R8 |
(80) 0x40b126 SUB %EDI,%R10D |
(80) 0x40b129 MOV %R14,-0x40(%RBP) |
(80) 0x40b12d LEA (,%R8,8),%R9 |
(80) 0x40b135 MOV %R11,-0x78(%RBP) |
(80) 0x40b139 LEA 0x1(%R8,%R10,1),%RBX |
(80) 0x40b13e LEA (%RAX,%R11,1),%RSI |
(80) 0x40b142 MOV %R9,-0x50(%RBP) |
(80) 0x40b146 SAL $0x3,%RBX |
(80) 0x40b14a MOV %RSI,-0x58(%RBP) |
(80) 0x40b14e MOV %RDX,-0x80(%RBP) |
(80) 0x40b152 MOV %ECX,-0x68(%RBP) |
(80) 0x40b155 MOV %EDI,-0x5c(%RBP) |
(80) 0x40b158 MOV %R12,%RDI |
(82) 0x40b15b MOV (%RAX),%R11D |
(82) 0x40b15e TEST %R11D,%R11D |
(82) 0x40b161 JS 40b48e |
(82) 0x40b167 MOV -0x40(%RBP),%R12 |
(82) 0x40b16b MOV -0x5c(%RBP),%R13D |
(82) 0x40b16f MOVSXD %R11D,%R14 |
(82) 0x40b172 MOV (%R12,%R14,4),%ECX |
(82) 0x40b176 CMP %R13D,-0x48(%RBP) |
(82) 0x40b17a JLE 40b402 |
(82) 0x40b180 SAL $0x6,%R11D |
(82) 0x40b184 LEA (%R14,%R14,2),%RSI |
(82) 0x40b188 MOV %RAX,-0x38(%RBP) |
(82) 0x40b18c LEA (%RCX,%RCX,2),%R10 |
(82) 0x40b190 MOVSXD %R11D,%RDX |
(82) 0x40b193 SAL $0x9,%RSI |
(82) 0x40b197 MOV -0x50(%RBP),%R8 |
(82) 0x40b19b LEA (%RCX,%R11,1),%R13D |
(82) 0x40b19f LEA (%RDX,%RDX,2),%R12 |
(82) 0x40b1a3 LEA (%RSI,%R10,8),%R14 |
(82) 0x40b1a7 VXORPD %XMM5,%XMM5,%XMM5 |
(82) 0x40b1ab SAL $0x3,%R12 |
(82) 0x40b1af NOP |
(83) 0x40b1b0 CMP %R13D,%R11D |
(83) 0x40b1b3 JGE 40b3f1 |
(83) 0x40b1b9 MOV 0x20(%R15),%R9 |
(83) 0x40b1bd LEA (%R8,%R8,2),%R10 |
(83) 0x40b1c1 MOV 0x18(%R9),%RCX |
(83) 0x40b1c5 LEA (%RCX,%R12,1),%RAX |
(83) 0x40b1c9 LEA (%RCX,%R10,1),%RDX |
(83) 0x40b1cd ADD %R14,%RCX |
(83) 0x40b1d0 MOV %RCX,%RSI |
(83) 0x40b1d3 SUB %RAX,%RSI |
(83) 0x40b1d6 AND $0x8,%ESI |
(83) 0x40b1d9 JE 40b298 |
(83) 0x40b1df VMOVUPD (%RDX),%XMM2 |
(83) 0x40b1e3 VMOVSD 0x10(%RDX),%XMM14 |
(83) 0x40b1e8 VMOVSD (%RDX),%XMM1 |
(83) 0x40b1ec VSUBPD (%RAX),%XMM2,%XMM3 |
(83) 0x40b1f0 VSUBSD 0x10(%RAX),%XMM14,%XMM2 |
(83) 0x40b1f5 VSUBSD (%RAX),%XMM1,%XMM0 |
(83) 0x40b1f9 VMULSD %XMM2,%XMM2,%XMM1 |
(83) 0x40b1fd VUNPCKHPD %XMM3,%XMM3,%XMM15 |
(83) 0x40b201 VFMADD132SD %XMM0,%XMM1,%XMM0 |
(83) 0x40b206 VFMADD132SD %XMM15,%XMM0,%XMM15 |
(83) 0x40b20b VCOMISD %XMM15,%XMM4 |
(83) 0x40b210 JB 40b285 |
(83) 0x40b212 VCOMISD %XMM5,%XMM15 |
(83) 0x40b216 JBE 40b285 |
(83) 0x40b218 VDIVSD %XMM15,%XMM8,%XMM15 |
(83) 0x40b21d MOV 0x30(%R9),%RSI |
(83) 0x40b221 ADD %R8,%RSI |
(83) 0x40b224 VMULSD %XMM15,%XMM15,%XMM1 |
(83) 0x40b229 VMULSD %XMM15,%XMM11,%XMM0 |
(83) 0x40b22e VMULSD %XMM9,%XMM15,%XMM14 |
(83) 0x40b233 VMULSD %XMM0,%XMM1,%XMM0 |
(83) 0x40b237 VSUBSD %XMM8,%XMM0,%XMM1 |
(83) 0x40b23c VFMSUB132SD %XMM0,%XMM10,%XMM1 |
(83) 0x40b241 VMOVSD %XMM1,%XMM1,%XMM15 |
(83) 0x40b245 VFMADD231SD %XMM7,%XMM1,%XMM6 |
(83) 0x40b24a VMOVSD %XMM0,%XMM0,%XMM1 |
(83) 0x40b24e VFMADD132SD %XMM12,%XMM13,%XMM1 |
(83) 0x40b253 VFMADD213SD (%RSI),%XMM7,%XMM15 |
(83) 0x40b258 VMULSD %XMM1,%XMM0,%XMM0 |
(83) 0x40b25c VMOVSD %XMM15,(%RSI) |
(83) 0x40b260 MOV 0x28(%R9),%RSI |
(83) 0x40b264 ADD %R10,%RSI |
(83) 0x40b267 VMULSD %XMM14,%XMM0,%XMM14 |
(83) 0x40b26c VMOVDDUP %XMM14,%XMM15 |
(83) 0x40b271 VFNMADD213SD 0x10(%RSI),%XMM2,%XMM14 |
(83) 0x40b277 VFNMADD213PD (%RSI),%XMM15,%XMM3 |
(83) 0x40b27c VMOVSD %XMM14,0x10(%RSI) |
(83) 0x40b281 VMOVUPD %XMM3,(%RSI) |
(83) 0x40b285 ADD $0x18,%RAX |
(83) 0x40b289 CMP %RCX,%RAX |
(83) 0x40b28c JE 40b3f1 |
(83) 0x40b292 NOPW (%RAX,%RAX,1) |
(84) 0x40b298 VMOVSD (%RDX),%XMM2 |
(84) 0x40b29c VMOVSD 0x10(%RDX),%XMM14 |
(84) 0x40b2a1 VMOVUPD (%RDX),%XMM3 |
(84) 0x40b2a5 VSUBSD (%RAX),%XMM2,%XMM1 |
(84) 0x40b2a9 VSUBSD 0x10(%RAX),%XMM14,%XMM2 |
(84) 0x40b2ae VSUBPD (%RAX),%XMM3,%XMM3 |
(84) 0x40b2b2 VMULSD %XMM2,%XMM2,%XMM15 |
(84) 0x40b2b6 VUNPCKHPD %XMM3,%XMM3,%XMM0 |
(84) 0x40b2ba VFMADD132SD %XMM1,%XMM15,%XMM1 |
(84) 0x40b2bf VFMADD132SD %XMM0,%XMM1,%XMM0 |
(84) 0x40b2c4 VCOMISD %XMM0,%XMM4 |
(84) 0x40b2c8 JB 40b33b |
(84) 0x40b2ca VCOMISD %XMM5,%XMM0 |
(84) 0x40b2ce JBE 40b33b |
(84) 0x40b2d0 VDIVSD %XMM0,%XMM8,%XMM0 |
(84) 0x40b2d4 MOV 0x30(%R9),%RSI |
(84) 0x40b2d8 ADD %R8,%RSI |
(84) 0x40b2db VMULSD %XMM0,%XMM0,%XMM1 |
(84) 0x40b2df VMULSD %XMM0,%XMM11,%XMM15 |
(84) 0x40b2e3 VMULSD %XMM9,%XMM0,%XMM14 |
(84) 0x40b2e8 VMULSD %XMM15,%XMM1,%XMM0 |
(84) 0x40b2ed VSUBSD %XMM8,%XMM0,%XMM1 |
(84) 0x40b2f2 VFMSUB132SD %XMM0,%XMM10,%XMM1 |
(84) 0x40b2f7 VMOVSD %XMM1,%XMM1,%XMM15 |
(84) 0x40b2fb VFMADD231SD %XMM7,%XMM1,%XMM6 |
(84) 0x40b300 VMOVSD %XMM0,%XMM0,%XMM1 |
(84) 0x40b304 VFMADD132SD %XMM12,%XMM13,%XMM1 |
(84) 0x40b309 VFMADD213SD (%RSI),%XMM7,%XMM15 |
(84) 0x40b30e VMULSD %XMM1,%XMM0,%XMM0 |
(84) 0x40b312 VMOVSD %XMM15,(%RSI) |
(84) 0x40b316 MOV 0x28(%R9),%RSI |
(84) 0x40b31a ADD %R10,%RSI |
(84) 0x40b31d VMULSD %XMM14,%XMM0,%XMM14 |
(84) 0x40b322 VMOVDDUP %XMM14,%XMM15 |
(84) 0x40b327 VFNMADD213SD 0x10(%RSI),%XMM2,%XMM14 |
(84) 0x40b32d VFNMADD213PD (%RSI),%XMM15,%XMM3 |
(84) 0x40b332 VMOVSD %XMM14,0x10(%RSI) |
(84) 0x40b337 VMOVUPD %XMM3,(%RSI) |
(84) 0x40b33b VMOVSD (%RDX),%XMM2 |
(84) 0x40b33f VMOVSD 0x10(%RDX),%XMM14 |
(84) 0x40b344 LEA 0x18(%RAX),%RSI |
(84) 0x40b348 VMOVUPD (%RDX),%XMM3 |
(84) 0x40b34c VSUBSD 0x18(%RAX),%XMM2,%XMM1 |
(84) 0x40b351 VSUBSD 0x28(%RAX),%XMM14,%XMM2 |
(84) 0x40b356 VSUBPD 0x18(%RAX),%XMM3,%XMM3 |
(84) 0x40b35b VMULSD %XMM2,%XMM2,%XMM15 |
(84) 0x40b35f VUNPCKHPD %XMM3,%XMM3,%XMM0 |
(84) 0x40b363 VFMADD132SD %XMM1,%XMM15,%XMM1 |
(84) 0x40b368 VFMADD132SD %XMM0,%XMM1,%XMM0 |
(84) 0x40b36d VCOMISD %XMM0,%XMM4 |
(84) 0x40b371 JB 40b3e4 |
(84) 0x40b373 VCOMISD %XMM5,%XMM0 |
(84) 0x40b377 JBE 40b3e4 |
(84) 0x40b379 VDIVSD %XMM0,%XMM8,%XMM0 |
(84) 0x40b37d MOV 0x30(%R9),%RAX |
(84) 0x40b381 ADD %R8,%RAX |
(84) 0x40b384 VMULSD %XMM0,%XMM0,%XMM1 |
(84) 0x40b388 VMULSD %XMM0,%XMM11,%XMM15 |
(84) 0x40b38c VMULSD %XMM9,%XMM0,%XMM14 |
(84) 0x40b391 VMULSD %XMM15,%XMM1,%XMM0 |
(84) 0x40b396 VSUBSD %XMM8,%XMM0,%XMM1 |
(84) 0x40b39b VFMSUB132SD %XMM0,%XMM10,%XMM1 |
(84) 0x40b3a0 VMOVSD %XMM1,%XMM1,%XMM15 |
(84) 0x40b3a4 VFMADD231SD %XMM7,%XMM1,%XMM6 |
(84) 0x40b3a9 VMOVSD %XMM0,%XMM0,%XMM1 |
(84) 0x40b3ad VFMADD132SD %XMM12,%XMM13,%XMM1 |
(84) 0x40b3b2 VFMADD213SD (%RAX),%XMM7,%XMM15 |
(84) 0x40b3b7 VMULSD %XMM1,%XMM0,%XMM0 |
(84) 0x40b3bb VMOVSD %XMM15,(%RAX) |
(84) 0x40b3bf MOV 0x28(%R9),%RAX |
(84) 0x40b3c3 ADD %R10,%RAX |
(84) 0x40b3c6 VMULSD %XMM14,%XMM0,%XMM14 |
(84) 0x40b3cb VMOVDDUP %XMM14,%XMM15 |
(84) 0x40b3d0 VFNMADD213SD 0x10(%RAX),%XMM2,%XMM14 |
(84) 0x40b3d6 VFNMADD213PD (%RAX),%XMM15,%XMM3 |
(84) 0x40b3db VMOVSD %XMM14,0x10(%RAX) |
(84) 0x40b3e0 VMOVUPD %XMM3,(%RAX) |
(84) 0x40b3e4 LEA 0x18(%RSI),%RAX |
(84) 0x40b3e8 CMP %RCX,%RAX |
(84) 0x40b3eb JNE 40b298 |
(83) 0x40b3f1 ADD $0x8,%R8 |
(83) 0x40b3f5 CMP %RBX,%R8 |
(83) 0x40b3f8 JNE 40b1b0 |
(82) 0x40b3fe MOV -0x38(%RBP),%RAX |
(82) 0x40b402 MOV -0x58(%RBP),%R11 |
(82) 0x40b406 ADD $0x4,%RAX |
(82) 0x40b40a CMP %R11,%RAX |
(82) 0x40b40d JNE 40b15b |
(80) 0x40b413 MOV -0x70(%RBP),%R13 |
(80) 0x40b417 MOV -0x40(%RBP),%R14 |
(80) 0x40b41b MOV %RDI,%R12 |
(80) 0x40b41e MOV -0x78(%RBP),%R11 |
(80) 0x40b422 MOV -0x80(%RBP),%RDX |
(80) 0x40b426 MOV -0x68(%RBP),%ECX |
(80) 0x40b429 INC %RDX |
(80) 0x40b42c ADD $0x40,%ECX |
(80) 0x40b42f CMP %EDX,-0x64(%RBP) |
(80) 0x40b432 JG 40b0eb |
0x40b438 MOV 0x28(%R12),%R8 |
0x40b43d LEA 0x28(%R12),%R15 |
(81) 0x40b442 VMOVQ %R8,%XMM4 |
(81) 0x40b447 MOV %R8,%RAX |
(81) 0x40b44a VADDSD %XMM4,%XMM6,%XMM11 |
(81) 0x40b44e VMOVQ %XMM11,%RBX |
(81) 0x40b453 LOCK CMPXCHG %RBX,(%R15) |
(81) 0x40b458 MOV %R8,%RDI |
(81) 0x40b45b MOV %RAX,%R8 |
(81) 0x40b45e CMP %RAX,%RDI |
(81) 0x40b461 JNE 40b442 |
0x40b463 ADD $0x58,%RSP |
0x40b467 POP %RBX |
0x40b468 POP %R12 |
0x40b46a POP %R13 |
0x40b46c POP %R14 |
0x40b46e POP %R15 |
0x40b470 POP %RBP |
0x40b471 RET |
0x40b472 INC %EAX |
0x40b474 XOR %EDX,%EDX |
0x40b476 IMUL %EAX,%ECX |
0x40b479 ADD %ECX,%EDX |
0x40b47b ADD %EDX,%EAX |
0x40b47d MOV %EAX,-0x64(%RBP) |
0x40b480 CMP %EAX,%EDX |
0x40b482 JL 40b0ac |
0x40b488 VXORPD %XMM6,%XMM6,%XMM6 |
0x40b48c JMP 40b438 |
0x40b48e MOV $0x410080,%ECX |
0x40b493 MOV $0xb6,%EDX |
0x40b498 MOV $0x40ff90,%ESI |
0x40b49d MOV $0x410078,%EDI |
0x40b4a2 CALL 4030d0 <__assert_fail@plt> |
0x40b4a7 NOPW (%RAX,%RAX,1) |
Path / |
Source file and lines | ljForce.c:172-216 |
Module | exec |
nb instructions | 78 |
nb uops | 84 |
loop length | 290 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 9 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 14.00 cycles |
front end | 14.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.10 | 5.00 | 8.67 | 8.67 | 8.00 | 5.07 | 4.90 | 8.00 | 8.00 | 8.00 | 4.93 | 8.67 |
cycles | 5.10 | 7.73 | 8.67 | 8.67 | 8.00 | 5.07 | 4.90 | 8.00 | 8.00 | 8.00 | 4.93 | 8.67 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 13.57 |
Stall cycles | 0.00 |
Front-end | 14.00 |
Dispatch | 8.67 |
DIV/SQRT | 6.00 |
Overall L1 | 14.00 |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 11% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 5% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 18% |
all | 7% |
load | 12% |
store | 6% |
mul | 6% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 13% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 10% |
load | 12% |
store | 9% |
mul | 8% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x58,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVSD 0x20(%RDI),%XMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x18(%RDI),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x10(%RDI),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x8(%RDI),%XMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM10,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM11,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM4,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%R15),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM9,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 403070 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 403160 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD -0x38(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x40(%RBP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xc(%R13),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x48(%RBP),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x50(%RBP),%XMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %EBX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 40b472 <ljForce._omp_fn.1+0x452> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ECX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,-0x64(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 40b488 <ljForce._omp_fn.1+0x468> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMULSD 0x4fd4(%RIP),%XMM0,%XMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
MOVSXD -0x60(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDX,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
SAL $0x6,%EDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV 0x78(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x466e(%RIP),%XMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VXORPD %XMM6,%XMM6,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0x4a10(%RIP),%XMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x4fb0(%RIP),%XMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%RDI,4),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%R12),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x28(%R12),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x58,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %EAX,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ECX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,-0x64(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 40b0ac <ljForce._omp_fn.1+0x8c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VXORPD %XMM6,%XMM6,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40b438 <ljForce._omp_fn.1+0x418> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV $0x410080,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0xb6,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x40ff90,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x410078,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4030d0 <__assert_fail@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | ljForce.c:172-216 |
Module | exec |
nb instructions | 78 |
nb uops | 84 |
loop length | 290 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 9 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 14.00 cycles |
front end | 14.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.10 | 5.00 | 8.67 | 8.67 | 8.00 | 5.07 | 4.90 | 8.00 | 8.00 | 8.00 | 4.93 | 8.67 |
cycles | 5.10 | 7.73 | 8.67 | 8.67 | 8.00 | 5.07 | 4.90 | 8.00 | 8.00 | 8.00 | 4.93 | 8.67 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 13.57 |
Stall cycles | 0.00 |
Front-end | 14.00 |
Dispatch | 8.67 |
DIV/SQRT | 6.00 |
Overall L1 | 14.00 |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 11% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 5% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 18% |
all | 7% |
load | 12% |
store | 6% |
mul | 6% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 13% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 10% |
load | 12% |
store | 9% |
mul | 8% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x58,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVSD 0x20(%RDI),%XMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x18(%RDI),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x10(%RDI),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x8(%RDI),%XMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM10,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM11,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM4,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x18(%R15),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD %XMM9,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %EAX,-0x60(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 403070 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 403160 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD -0x38(%RBP),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x40(%RBP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xc(%R13),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x48(%RBP),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD -0x50(%RBP),%XMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %EBX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 40b472 <ljForce._omp_fn.1+0x452> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ECX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,-0x64(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 40b488 <ljForce._omp_fn.1+0x468> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMULSD 0x4fd4(%RIP),%XMM0,%XMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
MOVSXD -0x60(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %EDX,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
SAL $0x6,%EDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV 0x78(%R13),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x466e(%RIP),%XMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VXORPD %XMM6,%XMM6,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0x4a10(%RIP),%XMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x4fb0(%RIP),%XMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%RDI,4),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x28(%R12),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x28(%R12),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x58,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
IMUL %EAX,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ECX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %EDX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %EAX,-0x64(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EAX,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 40b0ac <ljForce._omp_fn.1+0x8c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VXORPD %XMM6,%XMM6,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40b438 <ljForce._omp_fn.1+0x418> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV $0x410080,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0xb6,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x40ff90,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x410078,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 4030d0 <__assert_fail@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼ljForce._omp_fn.1– | 65.1 | 11.9 |
▼Loop 80 - ljForce.c:175-216 - exec– | 0.03 | 0 |
▼Loop 82 - ljForce.c:178-216 - exec– | 0.32 | 0.04 |
▼Loop 83 - ljForce.c:187-216 - exec– | 4.96 | 0.66 |
○Loop 84 - ljForce.c:191-216 - exec | 59.79 | 8.01 |
○Loop 81 - ljForce.c:172-172 - exec | 0 | 0 |