Function: updateLinkCells | Module: exec | Source: linkCells.c:209-385 [...] | Coverage: 0.22% |
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Function: updateLinkCells | Module: exec | Source: linkCells.c:209-385 [...] | Coverage: 0.22% |
---|
/scratch_na/users/xoserete/qaas_runs/171-172-2581/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 209 - 385 |
-------------------------------------------------------------------------------- |
209: if (iz == gridSize[2]) |
210: { |
211: iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) + |
212: (gridSize[0]+2)*(gridSize[1]+2) + (gridSize[0]+2)*(iy+1) + (ix+1); |
213: } |
214: // Halo in Z- |
215: else if (iz == -1) |
216: { |
217: iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) + |
218: (gridSize[0]+2)*(iy+1) + (ix+1); |
219: } |
220: // Halo in Y+ |
221: else if (iy == gridSize[1]) |
[...] |
227: else if (iy == -1) |
228: { |
229: iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + iz*(gridSize[0]+2) + (ix+1); |
230: } |
231: // Halo in X+ |
232: else if (ix == gridSize[0]) |
233: { |
234: iBox = boxes->nLocalBoxes + gridSize[1]*gridSize[2] + iz*gridSize[1] + iy; |
235: } |
236: // Halo in X- |
237: else if (ix == -1) |
238: { |
239: iBox = boxes->nLocalBoxes + iz*gridSize[1] + iy; |
240: } |
241: // local link celll. |
242: else |
243: { |
244: iBox = ix + gridSize[0]*iy + gridSize[0]*gridSize[1]*iz; |
245: } |
246: assert(iBox >= 0); |
247: assert(iBox < boxes->nTotalBoxes); |
[...] |
258: int nj = boxes->nAtoms[jBox]; |
259: copyAtom(boxes, atoms, iId, iBox, nj, jBox); |
260: boxes->nAtoms[jBox]++; |
261: |
262: assert(boxes->nAtoms[jBox] < MAXATOMS); |
263: |
264: boxes->nAtoms[iBox]--; |
265: int ni = boxes->nAtoms[iBox]; |
266: if (ni) copyAtom(boxes, atoms, ni, iBox, iId, iBox); |
267: |
268: if (jBox > boxes->nLocalBoxes) |
269: --atoms->nLocal; |
[...] |
288: { |
289: emptyHaloCells(boxes); |
290: |
291: for (int iBox=0; iBox<boxes->nLocalBoxes; ++iBox) |
292: { |
293: int iOff = iBox*MAXATOMS; |
294: int ii=0; |
295: while (ii < boxes->nAtoms[iBox]) |
296: { |
297: int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]); |
298: if (jBox != iBox) |
299: moveAtom(boxes, atoms, ii, iBox, jBox); |
300: else |
301: ++ii; |
302: } |
303: } |
304: } |
[...] |
327: const int iOff = MAXATOMS*iBox+iAtom; |
328: const int jOff = MAXATOMS*jBox+jAtom; |
329: atoms->gid[jOff] = atoms->gid[iOff]; |
330: atoms->iSpecies[jOff] = atoms->iSpecies[iOff]; |
331: memcpy(atoms->r[jOff], atoms->r[iOff], sizeof(real3)); |
332: memcpy(atoms->p[jOff], atoms->p[iOff], sizeof(real3)); |
333: memcpy(atoms->f[jOff], atoms->f[iOff], sizeof(real3)); |
334: memcpy(atoms->U+jOff, atoms->U+iOff, sizeof(real_t)); |
[...] |
352: int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0])); |
353: int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1])); |
[...] |
359: if (rr[0] < localMax[0]) |
360: { |
361: if (ix == gridSize[0]) ix = gridSize[0] - 1; |
362: } |
363: else |
364: ix = gridSize[0]; // assign to halo cell |
365: if (rr[1] < localMax[1]) |
[...] |
371: if (rr[2] < localMax[2]) |
[...] |
384: for (int ii=boxes->nLocalBoxes; ii<boxes->nTotalBoxes; ++ii) |
385: boxes->nAtoms[ii] = 0; |
0x40c040 PUSH %RBP |
0x40c041 MOV %RSP,%RBP |
0x40c044 PUSH %R15 |
0x40c046 PUSH %R14 |
0x40c048 PUSH %R13 |
0x40c04a PUSH %R12 |
0x40c04c PUSH %RBX |
0x40c04d SUB $0x78,%RSP |
0x40c051 MOV %RSI,-0x48(%RBP) |
0x40c055 MOV 0xc(%RDI),%R14D |
0x40c059 MOV %RDI,-0x40(%RBP) |
0x40c05d MOV 0x14(%RDI),%R15D |
0x40c061 CMP %R15D,%R14D |
0x40c064 MOV %R15D,-0x38(%RBP) |
0x40c068 JGE 40c094 |
0x40c06a MOVSXD %R14D,%RDI |
0x40c06d SAL $0x2,%RDI |
0x40c071 MOV -0x40(%RBP),%RAX |
0x40c075 ADD 0x78(%RAX),%RDI |
0x40c079 MOV %R14D,%EAX |
0x40c07c NOT %EAX |
0x40c07e ADD %R15D,%EAX |
0x40c081 LEA 0x4(,%RAX,4),%RDX |
0x40c089 XOR %ESI,%ESI |
0x40c08b CALL 415930 <_intel_fast_memset> |
0x40c090 MOV -0x38(%RBP),%R15D |
0x40c094 TEST %R14D,%R14D |
0x40c097 JLE 40c457 |
0x40c09d MOV -0x40(%RBP),%RAX |
0x40c0a1 MOV 0x78(%RAX),%RAX |
0x40c0a5 LEA 0x1(%R14),%ECX |
0x40c0a9 MOV %ECX,-0x2c(%RBP) |
0x40c0ac XOR %R9D,%R9D |
0x40c0af VPCMPEQD %XMM0,%XMM0,%XMM0 |
0x40c0b3 MOV %RAX,-0x58(%RBP) |
0x40c0b7 MOV %R14,-0xa0(%RBP) |
0x40c0be JMP 40c0cc |
(86) 0x40c0c0 INC %R9 |
(86) 0x40c0c3 CMP %R14,%R9 |
(86) 0x40c0c6 JE 40c457 |
(86) 0x40c0cc CMPL $0,(%RAX,%R9,4) |
(86) 0x40c0d1 JLE 40c0c0 |
(86) 0x40c0d3 MOVSXD %R9D,%RCX |
(86) 0x40c0d6 SAL $0x6,%RCX |
(86) 0x40c0da MOV %RCX,-0x88(%RBP) |
(86) 0x40c0e1 MOV -0x48(%RBP),%RCX |
(86) 0x40c0e5 MOV 0x18(%RCX),%R10 |
(86) 0x40c0e9 MOV -0x40(%RBP),%RAX |
(86) 0x40c0ed VMOVSD 0x30(%RAX),%XMM1 |
(86) 0x40c0f2 MOV (%RAX),%R11D |
(86) 0x40c0f5 LEA -0x1(%R11),%ECX |
(86) 0x40c0f9 MOV %ECX,-0x64(%RBP) |
(86) 0x40c0fc VMOVUPD 0x38(%RAX),%XMM2 |
(86) 0x40c101 VMOVUPD 0x20(%RAX),%XMM3 |
(86) 0x40c106 VMOVUPD 0x68(%RAX),%XMM4 |
(86) 0x40c10b MOV 0x4(%RAX),%R13 |
(86) 0x40c10f MOV -0x58(%RBP),%RAX |
(86) 0x40c113 VMOVQ %R13,%XMM5 |
(86) 0x40c118 MOV %R13,%RCX |
(86) 0x40c11b SHR $0x20,%RCX |
(86) 0x40c11f VPADDD %XMM0,%XMM5,%XMM6 |
(86) 0x40c123 MOV %RCX,-0x98(%RBP) |
(86) 0x40c12a LEA (%RCX,%RCX,1),%EDX |
(86) 0x40c12d MOV %RDX,%RCX |
(86) 0x40c130 MOV %RDX,-0x80(%RBP) |
(86) 0x40c134 IMUL %R13D,%ECX |
(86) 0x40c138 MOV %ECX,-0x34(%RBP) |
(86) 0x40c13b LEA 0x2(%R11),%ECX |
(86) 0x40c13f MOV %ECX,-0x30(%RBP) |
(86) 0x40c142 VPINSRD $0,%R14D,%XMM5,%XMM7 |
(86) 0x40c148 XOR %EBX,%EBX |
(86) 0x40c14a MOV %R11,-0x78(%RBP) |
(86) 0x40c14e MOV %R13,-0x70(%RBP) |
(86) 0x40c152 MOV %R9,-0x50(%RBP) |
(86) 0x40c156 JMP 40c170 |
0x40c158 NOPL (%RAX,%RAX,1) |
(87) 0x40c160 MOV -0x60(%RBP),%RBX |
(87) 0x40c164 INC %EBX |
(87) 0x40c166 CMP (%RAX,%R9,4),%EBX |
(87) 0x40c16a JGE 40c0c0 |
(87) 0x40c170 MOV -0x88(%RBP),%RCX |
(87) 0x40c177 ADD %EBX,%ECX |
(87) 0x40c179 MOVSXD %ECX,%RCX |
(87) 0x40c17c MOV %RCX,-0x90(%RBP) |
(87) 0x40c183 LEA (%RCX,%RCX,2),%R12 |
(87) 0x40c187 VMOVSD (%R10,%R12,8),%XMM8 |
(87) 0x40c18d VUCOMISD %XMM8,%XMM1 |
(87) 0x40c192 MOV %R11D,%ECX |
(87) 0x40c195 JBE 40c1bb |
(87) 0x40c197 MOV -0x40(%RBP),%RAX |
(87) 0x40c19b VSUBSD 0x18(%RAX),%XMM8,%XMM8 |
(87) 0x40c1a0 VMULSD 0x60(%RAX),%XMM8,%XMM8 |
(87) 0x40c1a5 MOV -0x58(%RBP),%RAX |
(87) 0x40c1a9 VROUNDSD $0x9,%XMM8,%XMM8,%XMM8 |
(87) 0x40c1af VCVTTSD2SI %XMM8,%ECX |
(87) 0x40c1b4 CMP %ECX,%R11D |
(87) 0x40c1b7 CMOVE -0x64(%RBP),%ECX |
(87) 0x40c1bb VMOVUPD 0x8(%R10,%R12,8),%XMM8 |
(87) 0x40c1c2 VSUBPD %XMM3,%XMM8,%XMM9 |
(87) 0x40c1c6 VMULPD %XMM4,%XMM9,%XMM9 |
(87) 0x40c1ca VROUNDPD $0x9,%XMM9,%XMM9 |
(87) 0x40c1d0 VCVTTPD2DQ %XMM9,%XMM9 |
(87) 0x40c1d5 VPCMPEQD %XMM5,%XMM9,%XMM10 |
(87) 0x40c1d9 VCMPPD $0x2,%XMM8,%XMM2,%XMM8 |
(87) 0x40c1df VMOVMSKPD %XMM8,%R8D |
(87) 0x40c1e4 VBLENDVPS %XMM10,%XMM6,%XMM9,%XMM8 |
(87) 0x40c1ea VMOVD %XMM8,%ESI |
(87) 0x40c1ee TEST $0x1,%R8B |
(87) 0x40c1f2 MOV %ESI,%EDX |
(87) 0x40c1f4 CMOVNE %R13D,%EDX |
(87) 0x40c1f8 TEST $0x2,%R8B |
(87) 0x40c1fc JE 40c220 |
(87) 0x40c1fe ADD %R13D,%EDX |
(87) 0x40c201 MOV -0x80(%RBP),%RSI |
(87) 0x40c205 ADD %ESI,%EDX |
(87) 0x40c207 ADD $0x3,%EDX |
(87) 0x40c20a IMUL -0x30(%RBP),%EDX |
(87) 0x40c20e ADD -0x2c(%RBP),%ECX |
(87) 0x40c211 ADD -0x34(%RBP),%ECX |
(87) 0x40c214 ADD %EDX,%ECX |
(87) 0x40c216 JMP 40c291 |
0x40c218 NOPL (%RAX,%RAX,1) |
(87) 0x40c220 MOV %R15D,%EDI |
(87) 0x40c223 VPEXTRD $0x1,%XMM8,%R15D |
(87) 0x40c229 CMP $-0x1,%R15D |
(87) 0x40c22d JE 40c23e |
(87) 0x40c22f TEST $0x1,%R8B |
(87) 0x40c233 JE 40c254 |
(87) 0x40c235 ADD -0x98(%RBP),%R15D |
(87) 0x40c23c JMP 40c280 |
(87) 0x40c23e MOV -0x80(%RBP),%RSI |
(87) 0x40c242 ADD %ESI,%EDX |
(87) 0x40c244 INC %EDX |
(87) 0x40c246 IMUL -0x30(%RBP),%EDX |
(87) 0x40c24a ADD -0x2c(%RBP),%ECX |
(87) 0x40c24d ADD -0x34(%RBP),%ECX |
(87) 0x40c250 ADD %EDX,%ECX |
(87) 0x40c252 JMP 40c28e |
(87) 0x40c254 CMP $-0x1,%ESI |
(87) 0x40c257 JE 40c280 |
(87) 0x40c259 CMP %ECX,%R11D |
(87) 0x40c25c JNE 40c435 |
(87) 0x40c262 VPADDD %XMM7,%XMM8,%XMM8 |
(87) 0x40c266 VPEXTRD $0x1,%XMM8,%EDX |
(87) 0x40c26c IMUL %R13D,%EDX |
(87) 0x40c270 VMOVD %XMM8,%ECX |
(87) 0x40c274 ADD %EDX,%ECX |
(87) 0x40c276 JMP 40c28e |
0x40c278 NOPL (%RAX,%RAX,1) |
(87) 0x40c280 IMUL -0x30(%RBP),%R15D |
(87) 0x40c285 ADD -0x2c(%RBP),%ECX |
(87) 0x40c288 ADD -0x34(%RBP),%ECX |
(87) 0x40c28b ADD %R15D,%ECX |
(87) 0x40c28e MOV %EDI,%R15D |
(87) 0x40c291 TEST %ECX,%ECX |
(87) 0x40c293 JS 40c466 |
(87) 0x40c299 CMP %R15D,%ECX |
(87) 0x40c29c JGE 40c47f |
(87) 0x40c2a2 MOV %RBX,-0x60(%RBP) |
(87) 0x40c2a6 MOV %ECX,%EBX |
(87) 0x40c2a8 CMP %RBX,%R9 |
(87) 0x40c2ab JE 40c160 |
(87) 0x40c2b1 LEA (%R10,%R12,8),%R12 |
(87) 0x40c2b5 MOVSXD (%RAX,%RBX,4),%RSI |
(87) 0x40c2b9 MOVSXD %ECX,%RDX |
(87) 0x40c2bc SAL $0x6,%RDX |
(87) 0x40c2c0 ADD %RSI,%RDX |
(87) 0x40c2c3 MOV -0x48(%RBP),%RAX |
(87) 0x40c2c7 MOV 0x8(%RAX),%R14 |
(87) 0x40c2cb MOV -0x90(%RBP),%R13 |
(87) 0x40c2d2 MOV (%R14,%R13,4),%ESI |
(87) 0x40c2d6 MOV %ESI,(%R14,%RDX,4) |
(87) 0x40c2da MOV 0x10(%RAX),%R11 |
(87) 0x40c2de MOV (%R11,%R13,4),%ESI |
(87) 0x40c2e2 MOV %ESI,(%R11,%RDX,4) |
(87) 0x40c2e6 LEA (,%RDX,8),%RSI |
(87) 0x40c2ee MOV %R10,%R8 |
(87) 0x40c2f1 LEA (%RSI,%RSI,2),%R10 |
(87) 0x40c2f5 MOV 0x10(%R12),%RSI |
(87) 0x40c2fa MOV %RSI,0x10(%R8,%R10,1) |
(87) 0x40c2ff VMOVUPS (%R12),%XMM8 |
(87) 0x40c305 MOV %R8,%RDI |
(87) 0x40c308 VMOVUPS %XMM8,(%R8,%R10,1) |
(87) 0x40c30e MOV 0x20(%RAX),%RSI |
(87) 0x40c312 LEA (,%R13,8),%R8 |
(87) 0x40c31a LEA (%R8,%R8,2),%R15 |
(87) 0x40c31e MOV 0x10(%RSI,%R15,1),%R8 |
(87) 0x40c323 MOV %R8,0x10(%RSI,%R10,1) |
(87) 0x40c328 VMOVUPS (%RSI,%R15,1),%XMM8 |
(87) 0x40c32e VMOVUPS %XMM8,(%RSI,%R10,1) |
(87) 0x40c334 MOV 0x28(%RAX),%R8 |
(87) 0x40c338 MOV 0x10(%R8,%R15,1),%R9 |
(87) 0x40c33d MOV %R9,0x10(%R8,%R10,1) |
(87) 0x40c342 VMOVUPS (%R8,%R15,1),%XMM8 |
(87) 0x40c348 VMOVUPS %XMM8,(%R8,%R10,1) |
(87) 0x40c34e MOV 0x30(%RAX),%R10 |
(87) 0x40c352 MOV -0x58(%RBP),%RAX |
(87) 0x40c356 MOV (%R10,%R13,8),%R9 |
(87) 0x40c35a MOV %R9,(%R10,%RDX,8) |
(87) 0x40c35e MOV (%RAX,%RBX,4),%EDX |
(87) 0x40c361 LEA 0x1(%RDX),%R9D |
(87) 0x40c365 MOV %R9D,(%RAX,%RBX,4) |
(87) 0x40c369 CMP $0x3f,%EDX |
(87) 0x40c36c JGE 40c498 |
(87) 0x40c372 MOV -0x50(%RBP),%RDX |
(87) 0x40c376 MOVSXD (%RAX,%RDX,4),%RBX |
(87) 0x40c37a DEC %RBX |
(87) 0x40c37d MOV %EBX,(%RAX,%RDX,4) |
(87) 0x40c380 TEST %EBX,%EBX |
(87) 0x40c382 JE 40c3fd |
(87) 0x40c384 LEA (%RSI,%R15,1),%RDX |
(87) 0x40c388 ADD -0x88(%RBP),%RBX |
(87) 0x40c38f MOV (%R14,%RBX,4),%R9D |
(87) 0x40c393 MOV -0x90(%RBP),%R13 |
(87) 0x40c39a MOV %R9D,(%R14,%R13,4) |
(87) 0x40c39e MOV (%R11,%RBX,4),%R9D |
(87) 0x40c3a2 MOV %R9D,(%R11,%R13,4) |
(87) 0x40c3a6 LEA (,%RBX,8),%R9 |
(87) 0x40c3ae LEA (%R9,%R9,2),%R9 |
(87) 0x40c3b2 MOV %RDI,%R14 |
(87) 0x40c3b5 MOV 0x10(%RDI,%R9,1),%R11 |
(87) 0x40c3ba MOV %R11,0x10(%R12) |
(87) 0x40c3bf VMOVUPS (%RDI,%R9,1),%XMM8 |
(87) 0x40c3c5 VMOVUPS %XMM8,(%R12) |
(87) 0x40c3cb MOV 0x10(%RSI,%R9,1),%R11 |
(87) 0x40c3d0 MOV %R11,0x10(%RDX) |
(87) 0x40c3d4 VMOVUPS (%RSI,%R9,1),%XMM8 |
(87) 0x40c3da VMOVUPS %XMM8,(%RDX) |
(87) 0x40c3de ADD %R8,%R15 |
(87) 0x40c3e1 MOV 0x10(%R8,%R9,1),%RDX |
(87) 0x40c3e6 MOV %RDX,0x10(%R15) |
(87) 0x40c3ea VMOVUPS (%R8,%R9,1),%XMM8 |
(87) 0x40c3f0 VMOVUPS %XMM8,(%R15) |
(87) 0x40c3f5 MOV (%R10,%RBX,8),%RDX |
(87) 0x40c3f9 MOV %RDX,(%R10,%R13,8) |
(87) 0x40c3fd MOV -0xa0(%RBP),%R14 |
(87) 0x40c404 CMP %ECX,%R14D |
(87) 0x40c407 JGE 40c40f |
(87) 0x40c409 MOV -0x48(%RBP),%RCX |
(87) 0x40c40d DECL (%RCX) |
(87) 0x40c40f MOV -0x38(%RBP),%R15D |
(87) 0x40c413 MOV -0x50(%RBP),%R9 |
(87) 0x40c417 MOV %RDI,%R10 |
(87) 0x40c41a MOV -0x78(%RBP),%R11 |
(87) 0x40c41e MOV -0x70(%RBP),%R13 |
(87) 0x40c422 MOV -0x60(%RBP),%RBX |
(87) 0x40c426 CMP (%RAX,%R9,4),%EBX |
(87) 0x40c42a JL 40c170 |
(86) 0x40c430 JMP 40c0c0 |
(87) 0x40c435 IMUL %R13D,%R15D |
(87) 0x40c439 CMP $-0x1,%ECX |
(87) 0x40c43c JE 40c44a |
(87) 0x40c43e ADD %ESI,%R15D |
(87) 0x40c441 IMUL %R11D,%R15D |
(87) 0x40c445 JMP 40c28b |
(87) 0x40c44a ADD %R14D,%ESI |
(87) 0x40c44d ADD %R15D,%ESI |
(87) 0x40c450 MOV %ESI,%ECX |
(87) 0x40c452 JMP 40c28e |
0x40c457 ADD $0x78,%RSP |
0x40c45b POP %RBX |
0x40c45c POP %R12 |
0x40c45e POP %R13 |
0x40c460 POP %R14 |
0x40c462 POP %R15 |
0x40c464 POP %RBP |
0x40c465 RET |
0x40c466 MOV $0x424e1d,%EDI |
0x40c46b MOV $0x424d3e,%ESI |
0x40c470 MOV $0x424e27,%ECX |
0x40c475 MOV $0xf6,%EDX |
0x40c47a CALL 402fa0 <__assert_fail@plt> |
0x40c47f MOV $0x424e56,%EDI |
0x40c484 MOV $0x424d3e,%ESI |
0x40c489 MOV $0x424e27,%ECX |
0x40c48e MOV $0xf7,%EDX |
0x40c493 CALL 402fa0 <__assert_fail@plt> |
0x40c498 MOV $0x424e70,%EDI |
0x40c49d MOV $0x424d3e,%ESI |
0x40c4a2 MOV $0x424e8f,%ECX |
0x40c4a7 MOV $0x106,%EDX |
0x40c4ac CALL 402fa0 <__assert_fail@plt> |
0x40c4b1 NOPW %CS:(%RAX,%RAX,1) |
0x40c4bb NOPL (%RAX,%RAX,1) |
Path / |
Source file and lines | linkCells.c:209-385 |
Module | exec |
nb instructions | 65 |
nb uops | 69 |
loop length | 257 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 11.50 cycles |
front end | 11.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.80 | 4.80 | 4.67 | 4.67 | 8.00 | 4.87 | 4.80 | 8.00 | 8.00 | 8.00 | 4.73 | 4.67 |
cycles | 4.80 | 4.80 | 4.67 | 4.67 | 8.00 | 4.87 | 4.80 | 8.00 | 8.00 | 8.00 | 4.73 | 4.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 10.97 |
Stall cycles | 0.00 |
Front-end | 11.50 |
Dispatch | 8.00 |
Overall L1 | 11.50 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 7% |
all | 8% |
load | 6% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 7% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x78,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc(%RDI),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x14(%RDI),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %R15D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15D,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JGE 40c094 <updateLinkCells+0x54> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD %R14D,%RDI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
SAL $0x2,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV -0x40(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD 0x78(%RAX),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOT %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x4(,%RAX,4),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 415930 <_intel_fast_memset> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x38(%RBP),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R14D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 40c457 <updateLinkCells+0x417> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x40(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%R14),%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ECX,-0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R9D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPCMPEQD %XMM0,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
MOV %RAX,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,-0xa0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 40c0cc <updateLinkCells+0x8c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x78,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
MOV $0x424e1d,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x424d3e,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x424e27,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0xf6,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 402fa0 <__assert_fail@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x424e56,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x424d3e,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x424e27,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0xf7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 402fa0 <__assert_fail@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x424e70,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x424d3e,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x424e8f,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x106,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 402fa0 <__assert_fail@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | linkCells.c:209-385 |
Module | exec |
nb instructions | 65 |
nb uops | 69 |
loop length | 257 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 11.50 cycles |
front end | 11.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.80 | 4.80 | 4.67 | 4.67 | 8.00 | 4.87 | 4.80 | 8.00 | 8.00 | 8.00 | 4.73 | 4.67 |
cycles | 4.80 | 4.80 | 4.67 | 4.67 | 8.00 | 4.87 | 4.80 | 8.00 | 8.00 | 8.00 | 4.73 | 4.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 10.97 |
Stall cycles | 0.00 |
Front-end | 11.50 |
Dispatch | 8.00 |
Overall L1 | 11.50 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 7% |
all | 8% |
load | 6% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 7% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x78,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc(%RDI),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x14(%RDI),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %R15D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15D,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JGE 40c094 <updateLinkCells+0x54> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD %R14D,%RDI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
SAL $0x2,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV -0x40(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD 0x78(%RAX),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOT %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x4(,%RAX,4),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 415930 <_intel_fast_memset> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x38(%RBP),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R14D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 40c457 <updateLinkCells+0x417> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x40(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%R14),%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ECX,-0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R9D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPCMPEQD %XMM0,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
MOV %RAX,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,-0xa0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 40c0cc <updateLinkCells+0x8c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x78,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
MOV $0x424e1d,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x424d3e,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x424e27,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0xf6,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 402fa0 <__assert_fail@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x424e56,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x424d3e,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x424e27,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0xf7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 402fa0 <__assert_fail@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x424e70,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x424d3e,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x424e8f,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x106,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 402fa0 <__assert_fail@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼updateLinkCells– | 0.22 | 0.06 |
▼Loop 86 - linkCells.c:209-371 - exec– | 0 | 0.04 |
○Loop 87 - linkCells.c:209-371 - exec | 0.22 | 3.18 |