Loop Id: 91 | Module: exec | Source: timestep.c:88-94 | Coverage: 0.97% |
---|
Loop Id: 91 | Module: exec | Source: timestep.c:88-94 | Coverage: 0.97% |
---|
0x40ddc0 MOVSXD (%R13,%R10,4),%R8 |
0x40ddc5 TEST %R8D,%R8D |
0x40ddc8 JLE 40e01d |
0x40ddce MOV 0x20(%R12),%R11 |
0x40ddd3 MOVSXD %R9D,%RSI |
0x40ddd6 MOV 0x28(%R12),%RDI |
0x40dddb MOV 0x10(%R11),%R14 |
0x40dddf MOV 0x18(%R11),%RDX |
0x40dde3 MOV 0x20(%R11),%RCX |
0x40dde7 MOV %R10,%R11 |
0x40ddea SAL $0x6,%R11 |
0x40ddee LEA (%R14,%RSI,4),%RSI |
0x40ddf2 ADD %RAX,%RDX |
0x40ddf5 ADD %R8,%R11 |
0x40ddf8 ADD %RAX,%RCX |
0x40ddfb LEA (%R14,%R11,4),%R11 |
0x40ddff MOV %R11,%R8 |
0x40de02 SUB %RSI,%R8 |
0x40de05 SUB $0x4,%R8 |
0x40de09 SHR $0x2,%R8 |
0x40de0d INC %R8 |
0x40de10 AND $0x3,%R8D |
0x40de14 JE 40df0e |
0x40de1a CMP $0x1,%R8 |
0x40de1e JE 40debc |
0x40de24 CMP $0x2,%R8 |
0x40de28 JE 40de73 |
0x40de2a VMULSD (%RCX),%XMM0,%XMM3 |
0x40de2e MOVSXD (%RSI),%R14 |
0x40de31 ADD $0x18,%RDX |
0x40de35 ADD $0x4,%RSI |
0x40de39 ADD $0x18,%RCX |
0x40de3d SAL $0x4,%R14 |
0x40de41 VDIVSD 0x8(%RDI,%R14,1),%XMM2,%XMM1 |
0x40de48 VFMADD213SD -0x18(%RDX),%XMM1,%XMM3 |
0x40de4e VMOVSD %XMM3,-0x18(%RDX) |
0x40de53 VMULSD -0x10(%RCX),%XMM0,%XMM4 |
0x40de58 VFMADD213SD -0x10(%RDX),%XMM1,%XMM4 |
0x40de5e VMOVSD %XMM4,-0x10(%RDX) |
0x40de63 VMULSD -0x8(%RCX),%XMM0,%XMM5 |
0x40de68 VFMADD213SD -0x8(%RDX),%XMM5,%XMM1 |
0x40de6e VMOVSD %XMM1,-0x8(%RDX) |
0x40de73 VMULSD (%RCX),%XMM0,%XMM7 |
0x40de77 MOVSXD (%RSI),%R8 |
0x40de7a ADD $0x18,%RDX |
0x40de7e ADD $0x4,%RSI |
0x40de82 ADD $0x18,%RCX |
0x40de86 SAL $0x4,%R8 |
0x40de8a VDIVSD 0x8(%RDI,%R8,1),%XMM2,%XMM6 |
0x40de91 VFMADD213SD -0x18(%RDX),%XMM6,%XMM7 |
0x40de97 VMOVSD %XMM7,-0x18(%RDX) |
0x40de9c VMULSD -0x10(%RCX),%XMM0,%XMM8 |
0x40dea1 VFMADD213SD -0x10(%RDX),%XMM6,%XMM8 |
0x40dea7 VMOVSD %XMM8,-0x10(%RDX) |
0x40deac VMULSD -0x8(%RCX),%XMM0,%XMM9 |
0x40deb1 VFMADD213SD -0x8(%RDX),%XMM9,%XMM6 |
0x40deb7 VMOVSD %XMM6,-0x8(%RDX) |
0x40debc VMULSD (%RCX),%XMM0,%XMM11 |
0x40dec0 MOVSXD (%RSI),%R14 |
0x40dec3 ADD $0x4,%RSI |
0x40dec7 ADD $0x18,%RDX |
0x40decb ADD $0x18,%RCX |
0x40decf SAL $0x4,%R14 |
0x40ded3 VDIVSD 0x8(%RDI,%R14,1),%XMM2,%XMM10 |
0x40deda VFMADD213SD -0x18(%RDX),%XMM10,%XMM11 |
0x40dee0 VMOVSD %XMM11,-0x18(%RDX) |
0x40dee5 VMULSD -0x10(%RCX),%XMM0,%XMM12 |
0x40deea VFMADD213SD -0x10(%RDX),%XMM10,%XMM12 |
0x40def0 VMOVSD %XMM12,-0x10(%RDX) |
0x40def5 VMULSD -0x8(%RCX),%XMM0,%XMM13 |
0x40defa VFMADD213SD -0x8(%RDX),%XMM13,%XMM10 |
0x40df00 VMOVSD %XMM10,-0x8(%RDX) |
0x40df05 CMP %RSI,%R11 |
0x40df08 JE 40e01d |
(92) 0x40df0e VMULSD (%RCX),%XMM0,%XMM15 |
(92) 0x40df12 MOVSXD (%RSI),%R8 |
(92) 0x40df15 ADD $0x10,%RSI |
(92) 0x40df19 ADD $0x60,%RDX |
(92) 0x40df1d MOVSXD -0xc(%RSI),%R14 |
(92) 0x40df21 ADD $0x60,%RCX |
(92) 0x40df25 SAL $0x4,%R8 |
(92) 0x40df29 VDIVSD 0x8(%RDI,%R8,1),%XMM2,%XMM14 |
(92) 0x40df30 SAL $0x4,%R14 |
(92) 0x40df34 MOVSXD -0x8(%RSI),%R8 |
(92) 0x40df38 VFMADD213SD -0x60(%RDX),%XMM14,%XMM15 |
(92) 0x40df3e SAL $0x4,%R8 |
(92) 0x40df42 VMOVSD %XMM15,-0x60(%RDX) |
(92) 0x40df47 VMULSD -0x58(%RCX),%XMM0,%XMM1 |
(92) 0x40df4c VFMADD213SD -0x58(%RDX),%XMM14,%XMM1 |
(92) 0x40df52 VMOVSD %XMM1,-0x58(%RDX) |
(92) 0x40df57 VMULSD -0x50(%RCX),%XMM0,%XMM3 |
(92) 0x40df5c VFMADD213SD -0x50(%RDX),%XMM3,%XMM14 |
(92) 0x40df62 VMOVSD %XMM14,-0x50(%RDX) |
(92) 0x40df67 VMULSD -0x48(%RCX),%XMM0,%XMM5 |
(92) 0x40df6c VDIVSD 0x8(%RDI,%R14,1),%XMM2,%XMM4 |
(92) 0x40df73 VFMADD213SD -0x48(%RDX),%XMM4,%XMM5 |
(92) 0x40df79 VMOVSD %XMM5,-0x48(%RDX) |
(92) 0x40df7e VMULSD -0x40(%RCX),%XMM0,%XMM6 |
(92) 0x40df83 VFMADD213SD -0x40(%RDX),%XMM4,%XMM6 |
(92) 0x40df89 VMOVSD %XMM6,-0x40(%RDX) |
(92) 0x40df8e VMULSD -0x38(%RCX),%XMM0,%XMM7 |
(92) 0x40df93 VFMADD213SD -0x38(%RDX),%XMM7,%XMM4 |
(92) 0x40df99 VMOVSD %XMM4,-0x38(%RDX) |
(92) 0x40df9e VMULSD -0x30(%RCX),%XMM0,%XMM9 |
(92) 0x40dfa3 VDIVSD 0x8(%RDI,%R8,1),%XMM2,%XMM8 |
(92) 0x40dfaa VFMADD213SD -0x30(%RDX),%XMM8,%XMM9 |
(92) 0x40dfb0 VMOVSD %XMM9,-0x30(%RDX) |
(92) 0x40dfb5 VMULSD -0x28(%RCX),%XMM0,%XMM10 |
(92) 0x40dfba VFMADD213SD -0x28(%RDX),%XMM8,%XMM10 |
(92) 0x40dfc0 VMOVSD %XMM10,-0x28(%RDX) |
(92) 0x40dfc5 VMULSD -0x20(%RCX),%XMM0,%XMM11 |
(92) 0x40dfca VFMADD213SD -0x20(%RDX),%XMM11,%XMM8 |
(92) 0x40dfd0 VMOVSD %XMM8,-0x20(%RDX) |
(92) 0x40dfd5 VMULSD -0x18(%RCX),%XMM0,%XMM13 |
(92) 0x40dfda MOVSXD -0x4(%RSI),%R14 |
(92) 0x40dfde SAL $0x4,%R14 |
(92) 0x40dfe2 VDIVSD 0x8(%RDI,%R14,1),%XMM2,%XMM12 |
(92) 0x40dfe9 VFMADD213SD -0x18(%RDX),%XMM12,%XMM13 |
(92) 0x40dfef VMOVSD %XMM13,-0x18(%RDX) |
(92) 0x40dff4 VMULSD -0x10(%RCX),%XMM0,%XMM14 |
(92) 0x40dff9 VFMADD213SD -0x10(%RDX),%XMM12,%XMM14 |
(92) 0x40dfff VMOVSD %XMM14,-0x10(%RDX) |
(92) 0x40e004 VMULSD -0x8(%RCX),%XMM0,%XMM15 |
(92) 0x40e009 VFMADD213SD -0x8(%RDX),%XMM15,%XMM12 |
(92) 0x40e00f VMOVSD %XMM12,-0x8(%RDX) |
(92) 0x40e014 CMP %RSI,%R11 |
(92) 0x40e017 JNE 40df0e |
0x40e01d INC %R10 |
0x40e020 ADD $0x40,%R9D |
0x40e024 ADD $0x600,%RAX |
0x40e02a CMP %R10D,%EBX |
0x40e02d JG 40ddc0 |
/scratch_na/users/xoserete/qaas_runs/171-172-2581/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 88 - 94 |
-------------------------------------------------------------------------------- |
88: for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++) |
89: { |
90: int iSpecies = s->atoms->iSpecies[iOff]; |
91: real_t invMass = 1.0/s->species[iSpecies].mass; |
92: s->atoms->r[iOff][0] += dt*s->atoms->p[iOff][0]*invMass; |
93: s->atoms->r[iOff][1] += dt*s->atoms->p[iOff][1]*invMass; |
94: s->atoms->r[iOff][2] += dt*s->atoms->p[iOff][2]*invMass; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.13 |
CQA speedup if FP arith vectorized | 1.83 |
CQA speedup if fully vectorized | 2.25 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | NA |
Bottlenecks | micro-operation queue, |
Function | advancePosition._omp_fn.0 |
Source | timestep.c:88-94 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 13.50 |
CQA cycles if no scalar integer | 12.00 |
CQA cycles if FP arith vectorized | 7.38 |
CQA cycles if fully vectorized | 6.00 |
Front-end cycles | 13.50 |
DIV/SQRT cycles | 11.50 |
P0 cycles | 11.50 |
P1 cycles | 10.00 |
P2 cycles | 10.00 |
P3 cycles | 4.50 |
P4 cycles | 6.07 |
P5 cycles | 9.00 |
P6 cycles | 4.50 |
P7 cycles | 4.50 |
P8 cycles | 4.50 |
P9 cycles | 5.93 |
P10 cycles | 10.00 |
P11 cycles | 12.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 15.89 - 15.88 |
Stall cycles (UFS) | 2.04 |
Nb insns | 79.00 |
Nb uops | 78.00 |
Nb loads | 30.00 |
Nb stores | 9.00 |
Nb stack references | 0.00 |
FLOP/cycle | 2.22 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 9.00 |
Nb FLOP fma | 9.00 |
Nb FLOP div | 3.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 21.93 |
Bytes prefetched | 0.00 |
Bytes loaded | 224.00 |
Bytes stored | 72.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | 0.00 |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.15 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 9.38 |
Vector-efficiency ratio fma | 12.50 |
Vector-efficiency ratio div_sqrt | 12.50 |
Vector-efficiency ratio other | 10.94 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.13 |
CQA speedup if FP arith vectorized | 1.83 |
CQA speedup if fully vectorized | 2.25 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | NA |
Bottlenecks | micro-operation queue, |
Function | advancePosition._omp_fn.0 |
Source | timestep.c:88-94 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 13.50 |
CQA cycles if no scalar integer | 12.00 |
CQA cycles if FP arith vectorized | 7.38 |
CQA cycles if fully vectorized | 6.00 |
Front-end cycles | 13.50 |
DIV/SQRT cycles | 11.50 |
P0 cycles | 11.50 |
P1 cycles | 10.00 |
P2 cycles | 10.00 |
P3 cycles | 4.50 |
P4 cycles | 6.07 |
P5 cycles | 9.00 |
P6 cycles | 4.50 |
P7 cycles | 4.50 |
P8 cycles | 4.50 |
P9 cycles | 5.93 |
P10 cycles | 10.00 |
P11 cycles | 12.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 15.89 - 15.88 |
Stall cycles (UFS) | 2.04 |
Nb insns | 79.00 |
Nb uops | 78.00 |
Nb loads | 30.00 |
Nb stores | 9.00 |
Nb stack references | 0.00 |
FLOP/cycle | 2.22 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 9.00 |
Nb FLOP fma | 9.00 |
Nb FLOP div | 3.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 21.93 |
Bytes prefetched | 0.00 |
Bytes loaded | 224.00 |
Bytes stored | 72.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | 0.00 |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.15 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 9.38 |
Vector-efficiency ratio fma | 12.50 |
Vector-efficiency ratio div_sqrt | 12.50 |
Vector-efficiency ratio other | 10.94 |
Path / |
Function | advancePosition._omp_fn.0 |
Source file and lines | timestep.c:88-94 |
Module | exec |
nb instructions | 79 |
nb uops | 78 |
loop length | 356 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 14 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 13.50 cycles |
front end | 13.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 11.50 | 11.50 | 10.00 | 10.00 | 4.50 | 6.07 | 9.00 | 4.50 | 4.50 | 4.50 | 5.93 | 10.00 |
cycles | 11.50 | 11.50 | 10.00 | 10.00 | 4.50 | 6.07 | 9.00 | 4.50 | 4.50 | 4.50 | 5.93 | 10.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 15.89-15.88 |
Stall cycles | 2.04 |
LM full (events) | 4.08 |
Front-end | 13.50 |
Dispatch | 11.50 |
DIV/SQRT | 12.00 |
Overall L1 | 13.50 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 0% |
div/sqrt | 0% |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
all | 10% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 9% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 12% |
div/sqrt | 12% |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 9% |
fma | 12% |
div/sqrt | 12% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOVSXD (%R13,%R10,4),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R8D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 40e01d <advancePosition._omp_fn.0+0x2cd> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x20(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %R9D,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV 0x28(%R12),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R11),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R11),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R11),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x6,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R14,%RSI,4),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %RAX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R8,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%R14,%R11,4),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R11,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RSI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB $0x4,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x2,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
INC %R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $0x3,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 40df0e <advancePosition._omp_fn.0+0x1be> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x1,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 40debc <advancePosition._omp_fn.0+0x16c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x2,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 40de73 <advancePosition._omp_fn.0+0x123> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMULSD (%RCX),%XMM0,%XMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
MOVSXD (%RSI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x18,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x4,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x18,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x4,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
VDIVSD 0x8(%RDI,%R14,1),%XMM2,%XMM1 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 4 |
VFMADD213SD -0x18(%RDX),%XMM1,%XMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM3,-0x18(%RDX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD -0x10(%RCX),%XMM0,%XMM4 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFMADD213SD -0x10(%RDX),%XMM1,%XMM4 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM4,-0x10(%RDX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD -0x8(%RCX),%XMM0,%XMM5 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFMADD213SD -0x8(%RDX),%XMM5,%XMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM1,-0x8(%RDX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD (%RCX),%XMM0,%XMM7 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
MOVSXD (%RSI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x18,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x4,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x18,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x4,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
VDIVSD 0x8(%RDI,%R8,1),%XMM2,%XMM6 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 4 |
VFMADD213SD -0x18(%RDX),%XMM6,%XMM7 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM7,-0x18(%RDX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD -0x10(%RCX),%XMM0,%XMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFMADD213SD -0x10(%RDX),%XMM6,%XMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM8,-0x10(%RDX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD -0x8(%RCX),%XMM0,%XMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFMADD213SD -0x8(%RDX),%XMM9,%XMM6 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM6,-0x8(%RDX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD (%RCX),%XMM0,%XMM11 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
MOVSXD (%RSI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x18,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x18,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x4,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
VDIVSD 0x8(%RDI,%R14,1),%XMM2,%XMM10 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 4 |
VFMADD213SD -0x18(%RDX),%XMM10,%XMM11 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM11,-0x18(%RDX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD -0x10(%RCX),%XMM0,%XMM12 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFMADD213SD -0x10(%RDX),%XMM10,%XMM12 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM12,-0x10(%RDX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD -0x8(%RCX),%XMM0,%XMM13 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFMADD213SD -0x8(%RDX),%XMM13,%XMM10 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM10,-0x8(%RDX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %RSI,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 40e01d <advancePosition._omp_fn.0+0x2cd> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
INC %R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x40,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD $0x600,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R10D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JG 40ddc0 <advancePosition._omp_fn.0+0x70> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | advancePosition._omp_fn.0 |
Source file and lines | timestep.c:88-94 |
Module | exec |
nb instructions | 79 |
nb uops | 78 |
loop length | 356 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 14 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 13.50 cycles |
front end | 13.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 11.50 | 11.50 | 10.00 | 10.00 | 4.50 | 6.07 | 9.00 | 4.50 | 4.50 | 4.50 | 5.93 | 10.00 |
cycles | 11.50 | 11.50 | 10.00 | 10.00 | 4.50 | 6.07 | 9.00 | 4.50 | 4.50 | 4.50 | 5.93 | 10.00 |
Cycles executing div or sqrt instructions | 12.00 |
FE+BE cycles | 15.89-15.88 |
Stall cycles | 2.04 |
LM full (events) | 4.08 |
Front-end | 13.50 |
Dispatch | 11.50 |
DIV/SQRT | 12.00 |
Overall L1 | 13.50 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 0% |
div/sqrt | 0% |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
all | 10% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 9% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 12% |
div/sqrt | 12% |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 9% |
fma | 12% |
div/sqrt | 12% |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOVSXD (%R13,%R10,4),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R8D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 40e01d <advancePosition._omp_fn.0+0x2cd> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x20(%R12),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %R9D,%RSI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV 0x28(%R12),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%R11),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R11),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R11),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x6,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R14,%RSI,4),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %RAX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R8,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%R14,%R11,4),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R11,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RSI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB $0x4,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x2,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
INC %R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $0x3,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 40df0e <advancePosition._omp_fn.0+0x1be> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x1,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 40debc <advancePosition._omp_fn.0+0x16c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x2,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 40de73 <advancePosition._omp_fn.0+0x123> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMULSD (%RCX),%XMM0,%XMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
MOVSXD (%RSI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x18,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x4,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x18,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x4,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
VDIVSD 0x8(%RDI,%R14,1),%XMM2,%XMM1 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 4 |
VFMADD213SD -0x18(%RDX),%XMM1,%XMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM3,-0x18(%RDX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD -0x10(%RCX),%XMM0,%XMM4 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFMADD213SD -0x10(%RDX),%XMM1,%XMM4 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM4,-0x10(%RDX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD -0x8(%RCX),%XMM0,%XMM5 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFMADD213SD -0x8(%RDX),%XMM5,%XMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM1,-0x8(%RDX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD (%RCX),%XMM0,%XMM7 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
MOVSXD (%RSI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x18,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x4,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x18,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x4,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
VDIVSD 0x8(%RDI,%R8,1),%XMM2,%XMM6 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 4 |
VFMADD213SD -0x18(%RDX),%XMM6,%XMM7 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM7,-0x18(%RDX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD -0x10(%RCX),%XMM0,%XMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFMADD213SD -0x10(%RDX),%XMM6,%XMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM8,-0x10(%RDX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD -0x8(%RCX),%XMM0,%XMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFMADD213SD -0x8(%RDX),%XMM9,%XMM6 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM6,-0x8(%RDX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD (%RCX),%XMM0,%XMM11 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
MOVSXD (%RSI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x4,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x18,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x18,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x4,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
VDIVSD 0x8(%RDI,%R14,1),%XMM2,%XMM10 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 4 |
VFMADD213SD -0x18(%RDX),%XMM10,%XMM11 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM11,-0x18(%RDX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD -0x10(%RCX),%XMM0,%XMM12 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFMADD213SD -0x10(%RDX),%XMM10,%XMM12 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM12,-0x10(%RDX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMULSD -0x8(%RCX),%XMM0,%XMM13 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFMADD213SD -0x8(%RDX),%XMM13,%XMM10 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM10,-0x8(%RDX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %RSI,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 40e01d <advancePosition._omp_fn.0+0x2cd> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
INC %R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x40,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD $0x600,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R10D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JG 40ddc0 <advancePosition._omp_fn.0+0x70> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |