Function: advanceVelocity._omp_fn.0 | Module: exec | Source: timestep.c:71-78 | Coverage: 4.08% |
---|
Function: advanceVelocity._omp_fn.0 | Module: exec | Source: timestep.c:71-78 | Coverage: 4.08% |
---|
/scratch_na/users/xoserete/qaas_runs/171-172-2581/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 78 |
-------------------------------------------------------------------------------- |
71: #pragma omp parallel for |
72: for (int iBox=0; iBox<nBoxes; iBox++) |
73: { |
74: for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++) |
75: { |
76: s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0]; |
77: s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1]; |
78: s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2]; |
0x40e050 PUSH %RBP |
0x40e051 MOV %RSP,%RBP |
0x40e054 PUSH %R12 |
0x40e056 PUSH %RBX |
0x40e057 MOV %RDI,%RBX |
0x40e05a CALL 403070 <omp_get_num_threads@plt> |
0x40e05f MOV %EAX,%R12D |
0x40e062 CALL 403160 <omp_get_thread_num@plt> |
0x40e067 MOV %EAX,%ESI |
0x40e069 MOV 0x10(%RBX),%EAX |
0x40e06c CLTD |
0x40e06d IDIV %R12D |
0x40e070 CMP %EDX,%ESI |
0x40e072 JL 40e4a5 |
0x40e078 IMUL %EAX,%ESI |
0x40e07b ADD %EDX,%ESI |
0x40e07d ADD %ESI,%EAX |
0x40e07f CMP %EAX,%ESI |
0x40e081 JGE 40e4a0 |
0x40e087 MOV (%RBX),%R10 |
0x40e08a MOVSXD %ESI,%R12 |
0x40e08d VMOVSD 0x8(%RBX),%XMM0 |
0x40e092 LEA (%R12,%R12,2),%R8 |
0x40e096 MOV 0x18(%R10),%RCX |
0x40e09a SAL $0x9,%R8 |
0x40e09e MOV 0x78(%RCX),%R9 |
0x40e0a2 NOPW (%RAX,%RAX,1) |
(93) 0x40e0a8 MOVSXD (%R9,%R12,4),%RDI |
(93) 0x40e0ac TEST %EDI,%EDI |
(93) 0x40e0ae JLE 40e48d |
(93) 0x40e0b4 MOV 0x20(%R10),%R11 |
(93) 0x40e0b8 LEA (%RDI,%RDI,2),%RBX |
(93) 0x40e0bc LEA -0x18(,%RBX,8),%RDI |
(93) 0x40e0c4 MOV 0x20(%R11),%RSI |
(93) 0x40e0c8 MOV 0x28(%R11),%RCX |
(93) 0x40e0cc SHR $0x3,%RDI |
(93) 0x40e0d0 MOV $0xaaaaaaaaaaaaaab,%R11 |
(93) 0x40e0da IMUL %R11,%RDI |
(93) 0x40e0de ADD %R8,%RSI |
(93) 0x40e0e1 ADD %R8,%RCX |
(93) 0x40e0e4 LEA (%RSI,%RBX,8),%RDX |
(93) 0x40e0e8 INC %RDI |
(93) 0x40e0eb AND $0x7,%EDI |
(93) 0x40e0ee JE 40e2b2 |
(93) 0x40e0f4 CMP $0x1,%RDI |
(93) 0x40e0f8 JE 40e272 |
(93) 0x40e0fe CMP $0x2,%RDI |
(93) 0x40e102 JE 40e23b |
(93) 0x40e108 CMP $0x3,%RDI |
(93) 0x40e10c JE 40e204 |
(93) 0x40e112 CMP $0x4,%RDI |
(93) 0x40e116 JE 40e1cd |
(93) 0x40e11c CMP $0x5,%RDI |
(93) 0x40e120 JE 40e196 |
(93) 0x40e122 CMP $0x6,%RDI |
(93) 0x40e126 JE 40e15f |
(93) 0x40e128 VMOVSD (%RCX),%XMM1 |
(93) 0x40e12c ADD $0x18,%RSI |
(93) 0x40e130 ADD $0x18,%RCX |
(93) 0x40e134 VFMADD213SD -0x18(%RSI),%XMM0,%XMM1 |
(93) 0x40e13a VMOVSD %XMM1,-0x18(%RSI) |
(93) 0x40e13f VMOVSD -0x10(%RCX),%XMM2 |
(93) 0x40e144 VFMADD213SD -0x10(%RSI),%XMM0,%XMM2 |
(93) 0x40e14a VMOVSD %XMM2,-0x10(%RSI) |
(93) 0x40e14f VMOVSD -0x8(%RCX),%XMM3 |
(93) 0x40e154 VFMADD213SD -0x8(%RSI),%XMM0,%XMM3 |
(93) 0x40e15a VMOVSD %XMM3,-0x8(%RSI) |
(93) 0x40e15f VMOVSD (%RCX),%XMM4 |
(93) 0x40e163 ADD $0x18,%RSI |
(93) 0x40e167 ADD $0x18,%RCX |
(93) 0x40e16b VFMADD213SD -0x18(%RSI),%XMM0,%XMM4 |
(93) 0x40e171 VMOVSD %XMM4,-0x18(%RSI) |
(93) 0x40e176 VMOVSD -0x10(%RCX),%XMM5 |
(93) 0x40e17b VFMADD213SD -0x10(%RSI),%XMM0,%XMM5 |
(93) 0x40e181 VMOVSD %XMM5,-0x10(%RSI) |
(93) 0x40e186 VMOVSD -0x8(%RCX),%XMM6 |
(93) 0x40e18b VFMADD213SD -0x8(%RSI),%XMM0,%XMM6 |
(93) 0x40e191 VMOVSD %XMM6,-0x8(%RSI) |
(93) 0x40e196 VMOVSD (%RCX),%XMM7 |
(93) 0x40e19a ADD $0x18,%RSI |
(93) 0x40e19e ADD $0x18,%RCX |
(93) 0x40e1a2 VFMADD213SD -0x18(%RSI),%XMM0,%XMM7 |
(93) 0x40e1a8 VMOVSD %XMM7,-0x18(%RSI) |
(93) 0x40e1ad VMOVSD -0x10(%RCX),%XMM8 |
(93) 0x40e1b2 VFMADD213SD -0x10(%RSI),%XMM0,%XMM8 |
(93) 0x40e1b8 VMOVSD %XMM8,-0x10(%RSI) |
(93) 0x40e1bd VMOVSD -0x8(%RCX),%XMM9 |
(93) 0x40e1c2 VFMADD213SD -0x8(%RSI),%XMM0,%XMM9 |
(93) 0x40e1c8 VMOVSD %XMM9,-0x8(%RSI) |
(93) 0x40e1cd VMOVSD (%RCX),%XMM10 |
(93) 0x40e1d1 ADD $0x18,%RSI |
(93) 0x40e1d5 ADD $0x18,%RCX |
(93) 0x40e1d9 VFMADD213SD -0x18(%RSI),%XMM0,%XMM10 |
(93) 0x40e1df VMOVSD %XMM10,-0x18(%RSI) |
(93) 0x40e1e4 VMOVSD -0x10(%RCX),%XMM11 |
(93) 0x40e1e9 VFMADD213SD -0x10(%RSI),%XMM0,%XMM11 |
(93) 0x40e1ef VMOVSD %XMM11,-0x10(%RSI) |
(93) 0x40e1f4 VMOVSD -0x8(%RCX),%XMM12 |
(93) 0x40e1f9 VFMADD213SD -0x8(%RSI),%XMM0,%XMM12 |
(93) 0x40e1ff VMOVSD %XMM12,-0x8(%RSI) |
(93) 0x40e204 VMOVSD (%RCX),%XMM13 |
(93) 0x40e208 ADD $0x18,%RSI |
(93) 0x40e20c ADD $0x18,%RCX |
(93) 0x40e210 VFMADD213SD -0x18(%RSI),%XMM0,%XMM13 |
(93) 0x40e216 VMOVSD %XMM13,-0x18(%RSI) |
(93) 0x40e21b VMOVSD -0x10(%RCX),%XMM14 |
(93) 0x40e220 VFMADD213SD -0x10(%RSI),%XMM0,%XMM14 |
(93) 0x40e226 VMOVSD %XMM14,-0x10(%RSI) |
(93) 0x40e22b VMOVSD -0x8(%RCX),%XMM15 |
(93) 0x40e230 VFMADD213SD -0x8(%RSI),%XMM0,%XMM15 |
(93) 0x40e236 VMOVSD %XMM15,-0x8(%RSI) |
(93) 0x40e23b VMOVSD (%RCX),%XMM1 |
(93) 0x40e23f ADD $0x18,%RSI |
(93) 0x40e243 ADD $0x18,%RCX |
(93) 0x40e247 VFMADD213SD -0x18(%RSI),%XMM0,%XMM1 |
(93) 0x40e24d VMOVSD %XMM1,-0x18(%RSI) |
(93) 0x40e252 VMOVSD -0x10(%RCX),%XMM2 |
(93) 0x40e257 VFMADD213SD -0x10(%RSI),%XMM0,%XMM2 |
(93) 0x40e25d VMOVSD %XMM2,-0x10(%RSI) |
(93) 0x40e262 VMOVSD -0x8(%RCX),%XMM3 |
(93) 0x40e267 VFMADD213SD -0x8(%RSI),%XMM0,%XMM3 |
(93) 0x40e26d VMOVSD %XMM3,-0x8(%RSI) |
(93) 0x40e272 VMOVSD (%RCX),%XMM4 |
(93) 0x40e276 ADD $0x18,%RSI |
(93) 0x40e27a ADD $0x18,%RCX |
(93) 0x40e27e VFMADD213SD -0x18(%RSI),%XMM0,%XMM4 |
(93) 0x40e284 VMOVSD %XMM4,-0x18(%RSI) |
(93) 0x40e289 VMOVSD -0x10(%RCX),%XMM5 |
(93) 0x40e28e VFMADD213SD -0x10(%RSI),%XMM0,%XMM5 |
(93) 0x40e294 VMOVSD %XMM5,-0x10(%RSI) |
(93) 0x40e299 VMOVSD -0x8(%RCX),%XMM6 |
(93) 0x40e29e VFMADD213SD -0x8(%RSI),%XMM0,%XMM6 |
(93) 0x40e2a4 VMOVSD %XMM6,-0x8(%RSI) |
(93) 0x40e2a9 CMP %RDX,%RSI |
(93) 0x40e2ac JE 40e48d |
(94) 0x40e2b2 VMOVSD (%RCX),%XMM7 |
(94) 0x40e2b6 ADD $0xc0,%RSI |
(94) 0x40e2bd ADD $0xc0,%RCX |
(94) 0x40e2c4 VFMADD213SD -0xc0(%RSI),%XMM0,%XMM7 |
(94) 0x40e2cd VMOVSD %XMM7,-0xc0(%RSI) |
(94) 0x40e2d5 VMOVSD -0xb8(%RCX),%XMM8 |
(94) 0x40e2dd VFMADD213SD -0xb8(%RSI),%XMM0,%XMM8 |
(94) 0x40e2e6 VMOVSD %XMM8,-0xb8(%RSI) |
(94) 0x40e2ee VMOVSD -0xb0(%RCX),%XMM9 |
(94) 0x40e2f6 VFMADD213SD -0xb0(%RSI),%XMM0,%XMM9 |
(94) 0x40e2ff VMOVSD %XMM9,-0xb0(%RSI) |
(94) 0x40e307 VMOVSD -0xa8(%RCX),%XMM10 |
(94) 0x40e30f VFMADD213SD -0xa8(%RSI),%XMM0,%XMM10 |
(94) 0x40e318 VMOVSD %XMM10,-0xa8(%RSI) |
(94) 0x40e320 VMOVSD -0xa0(%RCX),%XMM11 |
(94) 0x40e328 VFMADD213SD -0xa0(%RSI),%XMM0,%XMM11 |
(94) 0x40e331 VMOVSD %XMM11,-0xa0(%RSI) |
(94) 0x40e339 VMOVSD -0x98(%RCX),%XMM12 |
(94) 0x40e341 VFMADD213SD -0x98(%RSI),%XMM0,%XMM12 |
(94) 0x40e34a VMOVSD %XMM12,-0x98(%RSI) |
(94) 0x40e352 VMOVSD -0x90(%RCX),%XMM13 |
(94) 0x40e35a VFMADD213SD -0x90(%RSI),%XMM0,%XMM13 |
(94) 0x40e363 VMOVSD %XMM13,-0x90(%RSI) |
(94) 0x40e36b VMOVSD -0x88(%RCX),%XMM14 |
(94) 0x40e373 VFMADD213SD -0x88(%RSI),%XMM0,%XMM14 |
(94) 0x40e37c VMOVSD %XMM14,-0x88(%RSI) |
(94) 0x40e384 VMOVSD -0x80(%RCX),%XMM15 |
(94) 0x40e389 VFMADD213SD -0x80(%RSI),%XMM0,%XMM15 |
(94) 0x40e38f VMOVSD %XMM15,-0x80(%RSI) |
(94) 0x40e394 VMOVSD -0x78(%RCX),%XMM1 |
(94) 0x40e399 VFMADD213SD -0x78(%RSI),%XMM0,%XMM1 |
(94) 0x40e39f VMOVSD %XMM1,-0x78(%RSI) |
(94) 0x40e3a4 VMOVSD -0x70(%RCX),%XMM2 |
(94) 0x40e3a9 VFMADD213SD -0x70(%RSI),%XMM0,%XMM2 |
(94) 0x40e3af VMOVSD %XMM2,-0x70(%RSI) |
(94) 0x40e3b4 VMOVSD -0x68(%RCX),%XMM3 |
(94) 0x40e3b9 VFMADD213SD -0x68(%RSI),%XMM0,%XMM3 |
(94) 0x40e3bf VMOVSD %XMM3,-0x68(%RSI) |
(94) 0x40e3c4 VMOVSD -0x60(%RCX),%XMM4 |
(94) 0x40e3c9 VFMADD213SD -0x60(%RSI),%XMM0,%XMM4 |
(94) 0x40e3cf VMOVSD %XMM4,-0x60(%RSI) |
(94) 0x40e3d4 VMOVSD -0x58(%RCX),%XMM5 |
(94) 0x40e3d9 VFMADD213SD -0x58(%RSI),%XMM0,%XMM5 |
(94) 0x40e3df VMOVSD %XMM5,-0x58(%RSI) |
(94) 0x40e3e4 VMOVSD -0x50(%RCX),%XMM6 |
(94) 0x40e3e9 VFMADD213SD -0x50(%RSI),%XMM0,%XMM6 |
(94) 0x40e3ef VMOVSD %XMM6,-0x50(%RSI) |
(94) 0x40e3f4 VMOVSD -0x48(%RCX),%XMM7 |
(94) 0x40e3f9 VFMADD213SD -0x48(%RSI),%XMM0,%XMM7 |
(94) 0x40e3ff VMOVSD %XMM7,-0x48(%RSI) |
(94) 0x40e404 VMOVSD -0x40(%RCX),%XMM8 |
(94) 0x40e409 VFMADD213SD -0x40(%RSI),%XMM0,%XMM8 |
(94) 0x40e40f VMOVSD %XMM8,-0x40(%RSI) |
(94) 0x40e414 VMOVSD -0x38(%RCX),%XMM9 |
(94) 0x40e419 VFMADD213SD -0x38(%RSI),%XMM0,%XMM9 |
(94) 0x40e41f VMOVSD %XMM9,-0x38(%RSI) |
(94) 0x40e424 VMOVSD -0x30(%RCX),%XMM10 |
(94) 0x40e429 VFMADD213SD -0x30(%RSI),%XMM0,%XMM10 |
(94) 0x40e42f VMOVSD %XMM10,-0x30(%RSI) |
(94) 0x40e434 VMOVSD -0x28(%RCX),%XMM11 |
(94) 0x40e439 VFMADD213SD -0x28(%RSI),%XMM0,%XMM11 |
(94) 0x40e43f VMOVSD %XMM11,-0x28(%RSI) |
(94) 0x40e444 VMOVSD -0x20(%RCX),%XMM12 |
(94) 0x40e449 VFMADD213SD -0x20(%RSI),%XMM0,%XMM12 |
(94) 0x40e44f VMOVSD %XMM12,-0x20(%RSI) |
(94) 0x40e454 VMOVSD -0x18(%RCX),%XMM13 |
(94) 0x40e459 VFMADD213SD -0x18(%RSI),%XMM0,%XMM13 |
(94) 0x40e45f VMOVSD %XMM13,-0x18(%RSI) |
(94) 0x40e464 VMOVSD -0x10(%RCX),%XMM14 |
(94) 0x40e469 VFMADD213SD -0x10(%RSI),%XMM0,%XMM14 |
(94) 0x40e46f VMOVSD %XMM14,-0x10(%RSI) |
(94) 0x40e474 VMOVSD -0x8(%RCX),%XMM15 |
(94) 0x40e479 VFMADD213SD -0x8(%RSI),%XMM0,%XMM15 |
(94) 0x40e47f VMOVSD %XMM15,-0x8(%RSI) |
(94) 0x40e484 CMP %RDX,%RSI |
(94) 0x40e487 JNE 40e2b2 |
(93) 0x40e48d INC %R12 |
(93) 0x40e490 ADD $0x600,%R8 |
(93) 0x40e497 CMP %R12D,%EAX |
(93) 0x40e49a JG 40e0a8 |
0x40e4a0 POP %RBX |
0x40e4a1 POP %R12 |
0x40e4a3 POP %RBP |
0x40e4a4 RET |
0x40e4a5 INC %EAX |
0x40e4a7 XOR %EDX,%EDX |
0x40e4a9 JMP 40e078 |
0x40e4ae XCHG %AX,%AX |
Path / |
Source file and lines | timestep.c:71-78 |
Module | exec |
nb instructions | 35 |
nb uops | 40 |
loop length | 104 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 6.67 cycles |
front end | 6.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.70 | 4.00 | 3.00 | 3.00 | 2.50 | 2.87 | 2.70 | 2.50 | 2.50 | 2.50 | 2.73 | 3.00 |
cycles | 2.70 | 5.33 | 3.00 | 3.00 | 2.50 | 2.87 | 2.70 | 2.50 | 2.50 | 2.50 | 2.73 | 3.00 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 6.54-6.55 |
Stall cycles | 0.00 |
Front-end | 6.67 |
Dispatch | 5.33 |
DIV/SQRT | 6.00 |
Overall L1 | 6.67 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 0% |
all | 7% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 6% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 7% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 8% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 6% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 403070 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 403160 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x10(%RBX),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 40e4a5 <advanceVelocity._omp_fn.0+0x455> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %ESI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 40e4a0 <advanceVelocity._omp_fn.0+0x450> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%RBX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %ESI,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
VMOVSD 0x8(%RBX),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R12,%R12,2),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x18(%R10),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x9,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV 0x78(%RCX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40e078 <advanceVelocity._omp_fn.0+0x28> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | timestep.c:71-78 |
Module | exec |
nb instructions | 35 |
nb uops | 40 |
loop length | 104 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 6.67 cycles |
front end | 6.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.70 | 4.00 | 3.00 | 3.00 | 2.50 | 2.87 | 2.70 | 2.50 | 2.50 | 2.50 | 2.73 | 3.00 |
cycles | 2.70 | 5.33 | 3.00 | 3.00 | 2.50 | 2.87 | 2.70 | 2.50 | 2.50 | 2.50 | 2.73 | 3.00 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 6.54-6.55 |
Stall cycles | 0.00 |
Front-end | 6.67 |
Dispatch | 5.33 |
DIV/SQRT | 6.00 |
Overall L1 | 6.67 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 0% |
all | 7% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 6% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 7% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 8% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 6% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 403070 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 403160 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x10(%RBX),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 40e4a5 <advanceVelocity._omp_fn.0+0x455> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %ESI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 40e4a0 <advanceVelocity._omp_fn.0+0x450> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%RBX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %ESI,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
VMOVSD 0x8(%RBX),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R12,%R12,2),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x18(%R10),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x9,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV 0x78(%RCX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40e078 <advanceVelocity._omp_fn.0+0x28> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advanceVelocity._omp_fn.0– | 4.08 | 0.74 |
▼Loop 93 - timestep.c:74-78 - exec– | 1.86 | 0.25 |
○Loop 94 - timestep.c:74-78 - exec | 2.21 | 0.3 |