Loop Id: 108 | Module: exec | Source: timestep.c:88-94 | Coverage: 1.35% |
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Loop Id: 108 | Module: exec | Source: timestep.c:88-94 | Coverage: 1.35% |
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0x4114d0 MOVSXD (%R12,%RBX,4),%RCX [3] |
0x4114d4 MOVSXD 0x4(%R12,%RBX,4),%RAX [3] |
0x4114d9 MOVSXD 0x8(%R12,%RBX,4),%R14 [3] |
0x4114de MOVSXD 0xc(%R12,%RBX,4),%RSI [3] |
0x4114e3 SAL $0x4,%RCX |
0x4114e7 SAL $0x4,%R14 |
0x4114eb SAL $0x4,%RSI |
0x4114ef VMOVSD 0x8(%R9,%R14,1),%XMM2 [6] |
0x4114f6 VMOVHPD 0x8(%R9,%RSI,1),%XMM2,%XMM2 [1] |
0x4114fd SAL $0x4,%RAX |
0x411501 VMOVSD 0x8(%R9,%RCX,1),%XMM3 [7] |
0x411508 VMOVHPD 0x8(%R9,%RAX,1),%XMM3,%XMM3 [5] |
0x41150f VINSERTF128 $0x1,%XMM2,%YMM3,%YMM2 |
0x411515 VDIVPD %YMM2,%YMM1,%YMM2 |
0x411519 VMOVUPD 0x20(%R11,%R13,1),%YMM3 [2] |
0x411520 VBLENDPD $0x3,(%R11,%R13,1),%YMM3,%YMM4 [2] |
0x411527 VMOVUPD 0x10(%R11,%R13,1),%XMM5 [2] |
0x41152e VMOVUPD 0x20(%R11,%R13,1),%XMM6 [2] |
0x411535 VINSERTF128 $0x1,0x40(%R11,%R13,1),%YMM5,%YMM5 [2] |
0x41153d VBLENDPD $0xa,%YMM5,%YMM4,%YMM7 |
0x411543 VSHUFPD $0x5,%YMM3,%YMM4,%YMM3 |
0x411548 VBROADCASTSD 0x50(%R11,%R13,1),%YMM4 [2] |
0x41154f VBLENDPD $0xc,0x40(%R11,%R13,1),%YMM6,%YMM6 [2] |
0x411557 VBLENDPD $0x8,%YMM4,%YMM3,%YMM3 |
0x41155d VMOVUPD 0x20(%R10,%R13,1),%YMM4 [4] |
0x411564 VBLENDPD $0x3,(%R10,%R13,1),%YMM4,%YMM8 [4] |
0x41156b VBLENDPD $0xa,%YMM6,%YMM5,%YMM5 |
0x411571 VMOVUPD 0x10(%R10,%R13,1),%XMM6 [4] |
0x411578 VINSERTF128 $0x1,0x40(%R10,%R13,1),%YMM6,%YMM6 [4] |
0x411580 VMOVUPD 0x20(%R10,%R13,1),%XMM9 [4] |
0x411587 VBLENDPD $0xa,%YMM6,%YMM8,%YMM10 |
0x41158d VSHUFPD $0x5,%YMM4,%YMM8,%YMM4 |
0x411592 VBROADCASTSD 0x50(%R10,%R13,1),%YMM8 [4] |
0x411599 VBLENDPD $0x8,%YMM8,%YMM4,%YMM4 |
0x41159f VBLENDPD $0xc,0x40(%R10,%R13,1),%YMM9,%YMM8 [4] |
0x4115a7 VBLENDPD $0xa,%YMM8,%YMM6,%YMM6 |
0x4115ad VFMADD231PD %YMM7,%YMM2,%YMM10 |
0x4115b2 VFMADD231PD %YMM3,%YMM2,%YMM4 |
0x4115b7 VFMADD231PD %YMM5,%YMM2,%YMM6 |
0x4115bc VSHUFPD $0x1,%YMM4,%YMM4,%YMM2 |
0x4115c1 VBLENDPD $0x4,%YMM10,%YMM2,%YMM2 |
0x4115c7 VMOVDDUP %XMM4,%XMM3 |
0x4115cb VPERM2F128 $0x20,%YMM10,%YMM3,%YMM3 |
0x4115d1 VSHUFPD $0x4,%YMM4,%YMM4,%YMM4 |
0x4115d6 VINSERTF128 $0x1,%XMM6,%YMM10,%YMM5 |
0x4115dc VBLENDPD $0xa,%YMM3,%YMM5,%YMM3 |
0x4115e2 VPERM2F128 $0x31,%YMM6,%YMM10,%YMM5 |
0x4115e8 VPERM2F128 $0x31,%YMM4,%YMM6,%YMM4 |
0x4115ee VBLENDPD $0xa,%YMM5,%YMM4,%YMM4 |
0x4115f4 VBLENDPD $0x2,%YMM6,%YMM2,%YMM2 |
0x4115fa VMOVUPD %YMM2,0x20(%R10,%R13,1) [4] |
0x411601 VMOVUPD %YMM4,0x40(%R10,%R13,1) [4] |
0x411608 VMOVUPD %YMM3,(%R10,%R13,1) [4] |
0x41160e ADD $0x4,%RBX |
0x411612 ADD $0x60,%R13 |
0x411616 CMP %EDX,%EBX |
0x411618 JLE 4114d0 |
/scratch_na/users/xoserete/qaas_runs/171-172-2581/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 88 - 94 |
-------------------------------------------------------------------------------- |
88: for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++) |
89: { |
90: int iSpecies = s->atoms->iSpecies[iOff]; |
91: real_t invMass = 1.0/s->species[iSpecies].mass; |
92: s->atoms->r[iOff][0] += dt*s->atoms->p[iOff][0]*invMass; |
93: s->atoms->r[iOff][1] += dt*s->atoms->p[iOff][1]*invMass; |
94: s->atoms->r[iOff][2] += dt*s->atoms->p[iOff][2]*invMass; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.06 |
CQA speedup if FP arith vectorized | 1.11 |
CQA speedup if fully vectorized | 1.42 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.01 |
Bottlenecks | P0, |
Function | advancePosition.extracted |
Source | timestep.c:88-94 |
Source loop unroll info | unrolled by 4 |
Source loop unroll confidence level | high |
Unroll/vectorization loop type | main |
Unroll factor | 4 |
CQA cycles | 11.33 |
CQA cycles if no scalar integer | 10.67 |
CQA cycles if FP arith vectorized | 10.17 |
CQA cycles if fully vectorized | 8.00 |
Front-end cycles | 10.67 |
DIV/SQRT cycles | 11.33 |
P0 cycles | 11.17 |
P1 cycles | 7.33 |
P2 cycles | 7.33 |
P3 cycles | 1.50 |
P4 cycles | 11.00 |
P5 cycles | 3.50 |
P6 cycles | 1.50 |
P7 cycles | 1.50 |
P8 cycles | 1.50 |
P9 cycles | 0.00 |
P10 cycles | 7.33 |
P11 cycles | 8.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 11.42 - 11.46 |
Stall cycles (UFS) | 0.00 - 0.01 |
Nb insns | 57.00 |
Nb uops | 62.00 |
Nb loads | 22.00 |
Nb stores | 3.00 |
Nb stack references | 0.00 |
FLOP/cycle | 2.47 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 12.00 |
Nb FLOP div | 4.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 39.53 |
Bytes prefetched | 0.00 |
Bytes loaded | 352.00 |
Bytes stored | 96.00 |
Stride 0 | 0.00 |
Stride 1 | 1.00 |
Stride n | 1.00 |
Stride unknown | 1.00 |
Stride indirect | 4.00 |
Vectorization ratio all | 84.44 |
Vectorization ratio load | 66.67 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | 89.29 |
Vector-efficiency ratio all | 38.06 |
Vector-efficiency ratio load | 29.17 |
Vector-efficiency ratio store | 50.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | 50.00 |
Vector-efficiency ratio div_sqrt | 50.00 |
Vector-efficiency ratio other | 39.73 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.06 |
CQA speedup if FP arith vectorized | 1.11 |
CQA speedup if fully vectorized | 1.42 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.01 |
Bottlenecks | P0, |
Function | advancePosition.extracted |
Source | timestep.c:88-94 |
Source loop unroll info | unrolled by 4 |
Source loop unroll confidence level | high |
Unroll/vectorization loop type | main |
Unroll factor | 4 |
CQA cycles | 11.33 |
CQA cycles if no scalar integer | 10.67 |
CQA cycles if FP arith vectorized | 10.17 |
CQA cycles if fully vectorized | 8.00 |
Front-end cycles | 10.67 |
DIV/SQRT cycles | 11.33 |
P0 cycles | 11.17 |
P1 cycles | 7.33 |
P2 cycles | 7.33 |
P3 cycles | 1.50 |
P4 cycles | 11.00 |
P5 cycles | 3.50 |
P6 cycles | 1.50 |
P7 cycles | 1.50 |
P8 cycles | 1.50 |
P9 cycles | 0.00 |
P10 cycles | 7.33 |
P11 cycles | 8.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | 11.42 - 11.46 |
Stall cycles (UFS) | 0.00 - 0.01 |
Nb insns | 57.00 |
Nb uops | 62.00 |
Nb loads | 22.00 |
Nb stores | 3.00 |
Nb stack references | 0.00 |
FLOP/cycle | 2.47 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 12.00 |
Nb FLOP div | 4.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 39.53 |
Bytes prefetched | 0.00 |
Bytes loaded | 352.00 |
Bytes stored | 96.00 |
Stride 0 | 0.00 |
Stride 1 | 1.00 |
Stride n | 1.00 |
Stride unknown | 1.00 |
Stride indirect | 4.00 |
Vectorization ratio all | 84.44 |
Vectorization ratio load | 66.67 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | 89.29 |
Vector-efficiency ratio all | 38.06 |
Vector-efficiency ratio load | 29.17 |
Vector-efficiency ratio store | 50.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | 50.00 |
Vector-efficiency ratio div_sqrt | 50.00 |
Vector-efficiency ratio other | 39.73 |
Path / |
Function | advancePosition.extracted |
Source file and lines | timestep.c:88-94 |
Module | exec |
nb instructions | 57 |
nb uops | 62 |
loop length | 334 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 6 |
used ymm registers | 10 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 10.67 cycles |
front end | 10.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 11.33 | 11.17 | 7.33 | 7.33 | 1.50 | 11.00 | 3.50 | 1.50 | 1.50 | 1.50 | 0.00 | 7.33 |
cycles | 11.33 | 11.17 | 7.33 | 7.33 | 1.50 | 11.00 | 3.50 | 1.50 | 1.50 | 1.50 | 0.00 | 7.33 |
Cycles executing div or sqrt instructions | 8.00 |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 11.42-11.46 |
Stall cycles | 0.00-0.01 |
Front-end | 10.67 |
Dispatch | 11.33 |
DIV/SQRT | 8.00 |
Data deps. | 1.00 |
Overall L1 | 11.33 |
all | 84% |
load | 66% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 100% |
div/sqrt | 100% |
other | 89% |
all | 38% |
load | 29% |
store | 50% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 50% |
div/sqrt | 50% |
other | 39% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOVSXD (%R12,%RBX,4),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD 0x4(%R12,%RBX,4),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD 0x8(%R12,%RBX,4),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD 0xc(%R12,%RBX,4),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x4,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
SAL $0x4,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
SAL $0x4,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
VMOVSD 0x8(%R9,%R14,1),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVHPD 0x8(%R9,%RSI,1),%XMM2,%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4-12 | 1 |
SAL $0x4,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
VMOVSD 0x8(%R9,%RCX,1),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVHPD 0x8(%R9,%RAX,1),%XMM3,%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4-12 | 1 |
VINSERTF128 $0x1,%XMM2,%YMM3,%YMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VDIVPD %YMM2,%YMM1,%YMM2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 8 |
VMOVUPD 0x20(%R11,%R13,1),%YMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VBLENDPD $0x3,(%R11,%R13,1),%YMM3,%YMM4 | 2 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVUPD 0x10(%R11,%R13,1),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x20(%R11,%R13,1),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VINSERTF128 $0x1,0x40(%R11,%R13,1),%YMM5,%YMM5 | 2 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBLENDPD $0xa,%YMM5,%YMM4,%YMM7 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VSHUFPD $0x5,%YMM3,%YMM4,%YMM3 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD 0x50(%R11,%R13,1),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBLENDPD $0xc,0x40(%R11,%R13,1),%YMM6,%YMM6 | 2 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VBLENDPD $0x8,%YMM4,%YMM3,%YMM3 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMOVUPD 0x20(%R10,%R13,1),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VBLENDPD $0x3,(%R10,%R13,1),%YMM4,%YMM8 | 2 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VBLENDPD $0xa,%YMM6,%YMM5,%YMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMOVUPD 0x10(%R10,%R13,1),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VINSERTF128 $0x1,0x40(%R10,%R13,1),%YMM6,%YMM6 | 2 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VMOVUPD 0x20(%R10,%R13,1),%XMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VBLENDPD $0xa,%YMM6,%YMM8,%YMM10 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VSHUFPD $0x5,%YMM4,%YMM8,%YMM4 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD 0x50(%R10,%R13,1),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBLENDPD $0x8,%YMM8,%YMM4,%YMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VBLENDPD $0xc,0x40(%R10,%R13,1),%YMM9,%YMM8 | 2 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VBLENDPD $0xa,%YMM8,%YMM6,%YMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VFMADD231PD %YMM7,%YMM2,%YMM10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PD %YMM3,%YMM2,%YMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PD %YMM5,%YMM2,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VSHUFPD $0x1,%YMM4,%YMM4,%YMM2 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VBLENDPD $0x4,%YMM10,%YMM2,%YMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMOVDDUP %XMM4,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VPERM2F128 $0x20,%YMM10,%YMM3,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VSHUFPD $0x4,%YMM4,%YMM4,%YMM4 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VINSERTF128 $0x1,%XMM6,%YMM10,%YMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBLENDPD $0xa,%YMM3,%YMM5,%YMM3 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPERM2F128 $0x31,%YMM6,%YMM10,%YMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPERM2F128 $0x31,%YMM4,%YMM6,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBLENDPD $0xa,%YMM5,%YMM4,%YMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VBLENDPD $0x2,%YMM6,%YMM2,%YMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMOVUPD %YMM2,0x20(%R10,%R13,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVUPD %YMM4,0x40(%R10,%R13,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVUPD %YMM3,(%R10,%R13,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
ADD $0x4,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x60,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 4114d0 <advancePosition.extracted+0x1f0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | advancePosition.extracted |
Source file and lines | timestep.c:88-94 |
Module | exec |
nb instructions | 57 |
nb uops | 62 |
loop length | 334 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 6 |
used ymm registers | 10 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 10.67 cycles |
front end | 10.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 11.33 | 11.17 | 7.33 | 7.33 | 1.50 | 11.00 | 3.50 | 1.50 | 1.50 | 1.50 | 0.00 | 7.33 |
cycles | 11.33 | 11.17 | 7.33 | 7.33 | 1.50 | 11.00 | 3.50 | 1.50 | 1.50 | 1.50 | 0.00 | 7.33 |
Cycles executing div or sqrt instructions | 8.00 |
Longest recurrence chain latency (RecMII) | 1.00 |
FE+BE cycles | 11.42-11.46 |
Stall cycles | 0.00-0.01 |
Front-end | 10.67 |
Dispatch | 11.33 |
DIV/SQRT | 8.00 |
Data deps. | 1.00 |
Overall L1 | 11.33 |
all | 84% |
load | 66% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 100% |
div/sqrt | 100% |
other | 89% |
all | 38% |
load | 29% |
store | 50% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 50% |
div/sqrt | 50% |
other | 39% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOVSXD (%R12,%RBX,4),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD 0x4(%R12,%RBX,4),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD 0x8(%R12,%RBX,4),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD 0xc(%R12,%RBX,4),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x4,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
SAL $0x4,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
SAL $0x4,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
VMOVSD 0x8(%R9,%R14,1),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVHPD 0x8(%R9,%RSI,1),%XMM2,%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4-12 | 1 |
SAL $0x4,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
VMOVSD 0x8(%R9,%RCX,1),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVHPD 0x8(%R9,%RAX,1),%XMM3,%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4-12 | 1 |
VINSERTF128 $0x1,%XMM2,%YMM3,%YMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VDIVPD %YMM2,%YMM1,%YMM2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 8 |
VMOVUPD 0x20(%R11,%R13,1),%YMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VBLENDPD $0x3,(%R11,%R13,1),%YMM3,%YMM4 | 2 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VMOVUPD 0x10(%R11,%R13,1),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x20(%R11,%R13,1),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VINSERTF128 $0x1,0x40(%R11,%R13,1),%YMM5,%YMM5 | 2 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBLENDPD $0xa,%YMM5,%YMM4,%YMM7 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VSHUFPD $0x5,%YMM3,%YMM4,%YMM3 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD 0x50(%R11,%R13,1),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBLENDPD $0xc,0x40(%R11,%R13,1),%YMM6,%YMM6 | 2 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VBLENDPD $0x8,%YMM4,%YMM3,%YMM3 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMOVUPD 0x20(%R10,%R13,1),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VBLENDPD $0x3,(%R10,%R13,1),%YMM4,%YMM8 | 2 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VBLENDPD $0xa,%YMM6,%YMM5,%YMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMOVUPD 0x10(%R10,%R13,1),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VINSERTF128 $0x1,0x40(%R10,%R13,1),%YMM6,%YMM6 | 2 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VMOVUPD 0x20(%R10,%R13,1),%XMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VBLENDPD $0xa,%YMM6,%YMM8,%YMM10 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VSHUFPD $0x5,%YMM4,%YMM8,%YMM4 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VBROADCASTSD 0x50(%R10,%R13,1),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
VBLENDPD $0x8,%YMM8,%YMM4,%YMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VBLENDPD $0xc,0x40(%R10,%R13,1),%YMM9,%YMM8 | 2 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.40 |
VBLENDPD $0xa,%YMM8,%YMM6,%YMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VFMADD231PD %YMM7,%YMM2,%YMM10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PD %YMM3,%YMM2,%YMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PD %YMM5,%YMM2,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VSHUFPD $0x1,%YMM4,%YMM4,%YMM2 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VBLENDPD $0x4,%YMM10,%YMM2,%YMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMOVDDUP %XMM4,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VPERM2F128 $0x20,%YMM10,%YMM3,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VSHUFPD $0x4,%YMM4,%YMM4,%YMM4 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VINSERTF128 $0x1,%XMM6,%YMM10,%YMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBLENDPD $0xa,%YMM3,%YMM5,%YMM3 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPERM2F128 $0x31,%YMM6,%YMM10,%YMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPERM2F128 $0x31,%YMM4,%YMM6,%YMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VBLENDPD $0xa,%YMM5,%YMM4,%YMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VBLENDPD $0x2,%YMM6,%YMM2,%YMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMOVUPD %YMM2,0x20(%R10,%R13,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVUPD %YMM4,0x40(%R10,%R13,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMOVUPD %YMM3,(%R10,%R13,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
ADD $0x4,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
ADD $0x60,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %EDX,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 4114d0 <advancePosition.extracted+0x1f0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |