Function: randomDisplacements.extracted | Module: exec | Source: initAtoms.c:194-202 [...] | Coverage: 0.02% |
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Function: randomDisplacements.extracted | Module: exec | Source: initAtoms.c:194-202 [...] | Coverage: 0.02% |
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/scratch_na/users/xoserete/qaas_runs/171-172-2581/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 194 - 202 |
-------------------------------------------------------------------------------- |
194: #pragma omp parallel for |
195: for (int iBox=0; iBox<s->boxes->nLocalBoxes; ++iBox) |
196: { |
197: for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff) |
198: { |
199: uint64_t seed = mkSeed(s->atoms->gid[iOff], 457); |
200: s->atoms->r[iOff][0] += (2.0*lcg61(&seed)-1.0) * delta; |
201: s->atoms->r[iOff][1] += (2.0*lcg61(&seed)-1.0) * delta; |
202: s->atoms->r[iOff][2] += (2.0*lcg61(&seed)-1.0) * delta; |
/scratch_na/users/xoserete/qaas_runs/171-172-2581/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c: 45 - 70 |
-------------------------------------------------------------------------------- |
45: *seed *= UINT64_C(437799614237992725); |
46: *seed %= UINT64_C(2305843009213693951); |
47: |
48: return *seed*convertToDouble; |
[...] |
68: uint32_t s2 = (id+callSite) * UINT32_C(2654435761); |
69: |
70: uint64_t iSeed = (UINT64_C(0x100000000) * s1) + s2; |
0x40adf0 PUSH %RBP |
0x40adf1 MOV %RSP,%RBP |
0x40adf4 PUSH %R15 |
0x40adf6 PUSH %R14 |
0x40adf8 PUSH %R13 |
0x40adfa PUSH %R12 |
0x40adfc PUSH %RBX |
0x40adfd SUB $0x28,%RSP |
0x40ae01 MOV %RCX,%R15 |
0x40ae04 MOV %RDX,-0x48(%RBP) |
0x40ae08 MOVL $0,-0x3c(%RBP) |
0x40ae0f MOV (%RDI),%ESI |
0x40ae11 MOVL $0,-0x30(%RBP) |
0x40ae18 MOV %R9D,-0x2c(%RBP) |
0x40ae1c MOVL $0x1,-0x38(%RBP) |
0x40ae23 SUB $0x8,%RSP |
0x40ae27 LEA -0x38(%RBP),%RAX |
0x40ae2b LEA -0x3c(%RBP),%RCX |
0x40ae2f LEA -0x30(%RBP),%R8 |
0x40ae33 LEA -0x2c(%RBP),%R9 |
0x40ae37 MOV $0x62f6f0,%EDI |
0x40ae3c MOV %ESI,-0x34(%RBP) |
0x40ae3f MOV $0x22,%EDX |
0x40ae44 PUSH $0x1 |
0x40ae46 PUSH $0x1 |
0x40ae48 PUSH %RAX |
0x40ae49 CALL 403120 <__kmpc_for_static_init_4@plt> |
0x40ae4e ADD $0x20,%RSP |
0x40ae52 MOV -0x30(%RBP),%ESI |
0x40ae55 MOV -0x2c(%RBP),%EDI |
0x40ae58 CMP %EDI,%ESI |
0x40ae5a JBE 40ae77 |
0x40ae5c MOV $0x62f710,%EDI |
0x40ae61 MOV -0x34(%RBP),%ESI |
0x40ae64 ADD $0x28,%RSP |
0x40ae68 POP %RBX |
0x40ae69 POP %R12 |
0x40ae6b POP %R13 |
0x40ae6d POP %R14 |
0x40ae6f POP %R15 |
0x40ae71 POP %RBP |
0x40ae72 JMP 402fe0 |
0x40ae77 VMOVQ %R15,%XMM0 |
0x40ae7c MOV -0x48(%RBP),%RAX |
0x40ae80 MOV 0x18(%RAX),%RAX |
0x40ae84 MOV 0x78(%RAX),%R8 |
0x40ae88 SUB %RSI,%RDI |
0x40ae8b MOV %ESI,%R9D |
0x40ae8e SAL $0x6,%R9D |
0x40ae92 XOR %R10D,%R10D |
0x40ae95 VPBROADCASTQ %XMM0,%XMM1 |
0x40ae9a MOV $0x613606df9756715,%R11 |
0x40aea4 MOV $0x9,%R15D |
0x40aeaa VMOVDDUP 0x18f46(%RIP),%XMM2 |
0x40aeb2 VMOVDDUP 0x1dbc6(%RIP),%XMM3 |
0x40aeba VMOVSD 0x18f36(%RIP),%XMM4 |
0x40aec2 VMOVSD 0x1dbb6(%RIP),%XMM5 |
0x40aeca JMP 40aee1 |
0x40aecc NOPL (%RAX) |
(78) 0x40aed0 ADD $0x40,%R9D |
(78) 0x40aed4 CMP %RDI,%R10 |
(78) 0x40aed7 LEA 0x1(%R10),%R10 |
(78) 0x40aedb JE 40ae5c |
(78) 0x40aee1 LEA (%R10,%RSI,1),%RAX |
(78) 0x40aee5 MOV (%R8,%RAX,4),%R12D |
(78) 0x40aee9 TEST %R12D,%R12D |
(78) 0x40aeec JLE 40aed0 |
(78) 0x40aeee MOV %R9D,%R13D |
(78) 0x40aef1 LEA (,%R13,8),%RAX |
(78) 0x40aef9 LEA (%RAX,%RAX,2),%RAX |
(78) 0x40aefd SAL $0x2,%R13 |
(78) 0x40af01 MOV -0x48(%RBP),%RCX |
(78) 0x40af05 MOV 0x20(%RCX),%RCX |
(78) 0x40af09 MOV 0x18(%RCX),%RDX |
(78) 0x40af0d LEA (%RDX,%RAX,1),%R14 |
(78) 0x40af11 ADD $0x10,%R14 |
(78) 0x40af15 ADD 0x8(%RCX),%R13 |
(78) 0x40af19 XOR %EBX,%EBX |
(78) 0x40af1b NOPL (%RAX,%RAX,1) |
(79) 0x40af20 IMUL $-0x61c8864f,(%R13,%RBX,4),%EAX |
(79) 0x40af29 LEA 0x71083cf9(%RAX),%ECX |
(79) 0x40af2f SAL $0x20,%RAX |
(79) 0x40af33 OR %RCX,%RAX |
(79) 0x40af36 IMUL %R11,%RAX |
(79) 0x40af3a MOV %RAX,%RDX |
(79) 0x40af3d MULX %R15,%RCX,%RCX |
(79) 0x40af42 SUB %RCX,%RDX |
(79) 0x40af45 SHR $0x1,%RDX |
(79) 0x40af48 ADD %RCX,%RDX |
(79) 0x40af4b SHR $0x3c,%RDX |
(79) 0x40af4f MOV %RDX,%RCX |
(79) 0x40af52 SAL $0x3d,%RCX |
(79) 0x40af56 SUB %RCX,%RDX |
(79) 0x40af59 ADD %RAX,%RDX |
(79) 0x40af5c IMUL %R11,%RDX |
(79) 0x40af60 MULX %R15,%RCX,%RCX |
(79) 0x40af65 MOV %RDX,%RAX |
(79) 0x40af68 SUB %RCX,%RAX |
(79) 0x40af6b SHR $0x1,%RAX |
(79) 0x40af6e ADD %RCX,%RAX |
(79) 0x40af71 SHR $0x3c,%RAX |
(79) 0x40af75 MOV %RAX,%RCX |
(79) 0x40af78 SAL $0x3d,%RCX |
(79) 0x40af7c SUB %RCX,%RAX |
(79) 0x40af7f ADD %RDX,%RAX |
(79) 0x40af82 IMUL %R11,%RAX |
(79) 0x40af86 MOV %RAX,%RDX |
(79) 0x40af89 MULX %R15,%RCX,%RCX |
(79) 0x40af8e SUB %RCX,%RDX |
(79) 0x40af91 SHR $0x1,%RDX |
(79) 0x40af94 ADD %RCX,%RDX |
(79) 0x40af97 SHR $0x3c,%RDX |
(79) 0x40af9b MOV %RDX,%RCX |
(79) 0x40af9e SAL $0x3d,%RCX |
(79) 0x40afa2 SUB %RCX,%RDX |
(79) 0x40afa5 ADD %RAX,%RDX |
(79) 0x40afa8 IMUL %R11,%RDX |
(79) 0x40afac MULX %R15,%RCX,%RCX |
(79) 0x40afb1 MOV %RDX,%RAX |
(79) 0x40afb4 SUB %RCX,%RAX |
(79) 0x40afb7 SHR $0x1,%RAX |
(79) 0x40afba ADD %RCX,%RAX |
(79) 0x40afbd SHR $0x3c,%RAX |
(79) 0x40afc1 MOV %RAX,%RCX |
(79) 0x40afc4 SAL $0x3d,%RCX |
(79) 0x40afc8 SUB %RCX,%RAX |
(79) 0x40afcb ADD %RDX,%RAX |
(79) 0x40afce IMUL %R11,%RAX |
(79) 0x40afd2 MOV %RAX,%RDX |
(79) 0x40afd5 MULX %R15,%RCX,%RCX |
(79) 0x40afda SUB %RCX,%RDX |
(79) 0x40afdd SHR $0x1,%RDX |
(79) 0x40afe0 ADD %RCX,%RDX |
(79) 0x40afe3 SHR $0x3c,%RDX |
(79) 0x40afe7 MOV %RDX,%RCX |
(79) 0x40afea SAL $0x3d,%RCX |
(79) 0x40afee SUB %RCX,%RDX |
(79) 0x40aff1 ADD %RAX,%RDX |
(79) 0x40aff4 IMUL %R11,%RDX |
(79) 0x40aff8 MULX %R15,%RCX,%RCX |
(79) 0x40affd MOV %RDX,%RAX |
(79) 0x40b000 SUB %RCX,%RAX |
(79) 0x40b003 SHR $0x1,%RAX |
(79) 0x40b006 ADD %RCX,%RAX |
(79) 0x40b009 SHR $0x3c,%RAX |
(79) 0x40b00d MOV %RAX,%RCX |
(79) 0x40b010 SAL $0x3d,%RCX |
(79) 0x40b014 SUB %RCX,%RAX |
(79) 0x40b017 ADD %RDX,%RAX |
(79) 0x40b01a IMUL %R11,%RAX |
(79) 0x40b01e MOV %RAX,%RDX |
(79) 0x40b021 MULX %R15,%RCX,%RCX |
(79) 0x40b026 SUB %RCX,%RDX |
(79) 0x40b029 SHR $0x1,%RDX |
(79) 0x40b02c ADD %RCX,%RDX |
(79) 0x40b02f SHR $0x3c,%RDX |
(79) 0x40b033 MOV %RDX,%RCX |
(79) 0x40b036 SAL $0x3d,%RCX |
(79) 0x40b03a SUB %RCX,%RDX |
(79) 0x40b03d ADD %RAX,%RDX |
(79) 0x40b040 IMUL %R11,%RDX |
(79) 0x40b044 MULX %R15,%RCX,%RCX |
(79) 0x40b049 MOV %RDX,%RAX |
(79) 0x40b04c SUB %RCX,%RAX |
(79) 0x40b04f SHR $0x1,%RAX |
(79) 0x40b052 ADD %RCX,%RAX |
(79) 0x40b055 SHR $0x3c,%RAX |
(79) 0x40b059 MOV %RAX,%RCX |
(79) 0x40b05c SAL $0x3d,%RCX |
(79) 0x40b060 SUB %RCX,%RAX |
(79) 0x40b063 ADD %RDX,%RAX |
(79) 0x40b066 IMUL %R11,%RAX |
(79) 0x40b06a MOV %RAX,%RDX |
(79) 0x40b06d MULX %R15,%RCX,%RCX |
(79) 0x40b072 SUB %RCX,%RDX |
(79) 0x40b075 SHR $0x1,%RDX |
(79) 0x40b078 ADD %RCX,%RDX |
(79) 0x40b07b SHR $0x3c,%RDX |
(79) 0x40b07f MOV %RDX,%RCX |
(79) 0x40b082 SAL $0x3d,%RCX |
(79) 0x40b086 SUB %RCX,%RDX |
(79) 0x40b089 ADD %RAX,%RDX |
(79) 0x40b08c IMUL %R11,%RDX |
(79) 0x40b090 MULX %R15,%RAX,%RAX |
(79) 0x40b095 MOV %RDX,%RCX |
(79) 0x40b098 SUB %RAX,%RCX |
(79) 0x40b09b SHR $0x1,%RCX |
(79) 0x40b09e ADD %RAX,%RCX |
(79) 0x40b0a1 SHR $0x3c,%RCX |
(79) 0x40b0a5 MOV %RCX,%RAX |
(79) 0x40b0a8 SAL $0x3d,%RAX |
(79) 0x40b0ac SUB %RAX,%RCX |
(79) 0x40b0af ADD %RDX,%RCX |
(79) 0x40b0b2 IMUL %R11,%RCX |
(79) 0x40b0b6 MOV %RCX,%RDX |
(79) 0x40b0b9 MULX %R15,%RDX,%RDX |
(79) 0x40b0be MOV %RCX,%RAX |
(79) 0x40b0c1 SUB %RDX,%RAX |
(79) 0x40b0c4 SHR $0x1,%RAX |
(79) 0x40b0c7 ADD %RDX,%RAX |
(79) 0x40b0ca SHR $0x3c,%RAX |
(79) 0x40b0ce MOV %RAX,%RDX |
(79) 0x40b0d1 SAL $0x3d,%RDX |
(79) 0x40b0d5 SUB %RDX,%RAX |
(79) 0x40b0d8 ADD %RCX,%RAX |
(79) 0x40b0db VCVTSI2SD %RAX,%XMM0,%XMM6 |
(79) 0x40b0e0 IMUL %R11,%RAX |
(79) 0x40b0e4 MOV %RAX,%RDX |
(79) 0x40b0e7 MULX %R15,%RCX,%RCX |
(79) 0x40b0ec MOV %RAX,%RDX |
(79) 0x40b0ef SUB %RCX,%RDX |
(79) 0x40b0f2 SHR $0x1,%RDX |
(79) 0x40b0f5 ADD %RCX,%RDX |
(79) 0x40b0f8 SHR $0x3c,%RDX |
(79) 0x40b0fc MOV %RDX,%RCX |
(79) 0x40b0ff SAL $0x3d,%RCX |
(79) 0x40b103 SUB %RCX,%RDX |
(79) 0x40b106 ADD %RAX,%RDX |
(79) 0x40b109 VCVTSI2SD %RDX,%XMM0,%XMM7 |
(79) 0x40b10e VUNPCKLPD %XMM7,%XMM6,%XMM6 |
(79) 0x40b112 IMUL %R11,%RDX |
(79) 0x40b116 VFMADD213PD %XMM3,%XMM2,%XMM6 |
(79) 0x40b11b MULX %R15,%RAX,%RAX |
(79) 0x40b120 VFMADD213PD -0x10(%R14),%XMM1,%XMM6 |
(79) 0x40b126 MOV %RDX,%RCX |
(79) 0x40b129 SUB %RAX,%RCX |
(79) 0x40b12c SHR $0x1,%RCX |
(79) 0x40b12f ADD %RAX,%RCX |
(79) 0x40b132 SHR $0x3c,%RCX |
(79) 0x40b136 MOV %RCX,%RAX |
(79) 0x40b139 SAL $0x3d,%RAX |
(79) 0x40b13d SUB %RAX,%RCX |
(79) 0x40b140 VMOVUPD %XMM6,-0x10(%R14) |
(79) 0x40b146 ADD %RDX,%RCX |
(79) 0x40b149 VCVTSI2SD %RCX,%XMM0,%XMM6 |
(79) 0x40b14e VFMADD213SD %XMM5,%XMM4,%XMM6 |
(79) 0x40b153 VFMADD213SD (%R14),%XMM0,%XMM6 |
(79) 0x40b158 VMOVSD %XMM6,(%R14) |
(79) 0x40b15d ADD $0x18,%R14 |
(79) 0x40b161 INC %RBX |
(79) 0x40b164 CMP %EBX,%R12D |
(79) 0x40b167 JNE 40af20 |
(78) 0x40b16d JMP 40aed0 |
0x40b172 NOPW %CS:(%RAX,%RAX,1) |
0x40b17c NOPL (%RAX) |
Path / |
Source file and lines | initAtoms.c:194-202 |
Module | exec |
nb instructions | 61 |
nb uops | 62 |
loop length | 238 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 6 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 10.33 cycles |
front end | 10.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.20 | 2.20 | 5.67 | 5.67 | 8.00 | 2.20 | 2.20 | 8.00 | 8.00 | 8.00 | 2.20 | 5.67 |
cycles | 2.20 | 2.20 | 5.67 | 5.67 | 8.00 | 2.20 | 2.20 | 8.00 | 8.00 | 8.00 | 2.20 | 5.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 10.35-10.41 |
Stall cycles | 0.00 |
Front-end | 10.33 |
Dispatch | 8.00 |
Overall L1 | 10.33 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 9% |
load | 12% |
store | 7% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 9% |
load | 12% |
store | 7% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 8% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x28,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0,-0x3c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9D,-0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x38(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x3c(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x30(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x2c(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x62f6f0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,-0x34(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 403120 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x30(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x2c(%RBP),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %EDI,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 40ae77 <randomDisplacements.extracted+0x87> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x62f710,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x34(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x28,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 402fe0 <__kmpc_for_static_fini@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VMOVQ %R15,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV -0x48(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RAX),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RSI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x6,%R9D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
XOR %R10D,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPBROADCASTQ %XMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV $0x613606df9756715,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
MOV $0x9,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVDDUP 0x18f46(%RIP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVDDUP 0x1dbc6(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x18f36(%RIP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x1dbb6(%RIP),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 40aee1 <randomDisplacements.extracted+0xf1> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | initAtoms.c:194-202 |
Module | exec |
nb instructions | 61 |
nb uops | 62 |
loop length | 238 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 6 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 10.33 cycles |
front end | 10.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.20 | 2.20 | 5.67 | 5.67 | 8.00 | 2.20 | 2.20 | 8.00 | 8.00 | 8.00 | 2.20 | 5.67 |
cycles | 2.20 | 2.20 | 5.67 | 5.67 | 8.00 | 2.20 | 2.20 | 8.00 | 8.00 | 8.00 | 2.20 | 5.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 10.35-10.41 |
Stall cycles | 0.00 |
Front-end | 10.33 |
Dispatch | 8.00 |
Overall L1 | 10.33 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 9% |
load | 12% |
store | 7% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 9% |
load | 12% |
store | 7% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 8% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x28,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0,-0x3c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9D,-0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x38(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x3c(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x30(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x2c(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x62f6f0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,-0x34(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 403120 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x30(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x2c(%RBP),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %EDI,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 40ae77 <randomDisplacements.extracted+0x87> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x62f710,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x34(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x28,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 402fe0 <__kmpc_for_static_fini@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VMOVQ %R15,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV -0x48(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RAX),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RSI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x6,%R9D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
XOR %R10D,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPBROADCASTQ %XMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV $0x613606df9756715,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
MOV $0x9,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVDDUP 0x18f46(%RIP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVDDUP 0x1dbc6(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x18f36(%RIP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x1dbb6(%RIP),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 40aee1 <randomDisplacements.extracted+0xf1> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼randomDisplacements.extracted– | 0.02 | 0 |
▼Loop 78 - initAtoms.c:194-202 - exec– | 0 | 0 |
○Loop 79 - initAtoms.c:197-202 - exec | 0.02 | 0 |