Loop Id: 83 | Module: exec | Source: ljForce.c:187-216 [...] | Coverage: 4.54% |
---|
Loop Id: 83 | Module: exec | Source: ljForce.c:187-216 [...] | Coverage: 4.54% |
---|
0x40b388 CMP %R13D,%R11D |
0x40b38b JGE 40b5d8 |
0x40b391 MOV 0x20(%R15),%RDI |
0x40b395 LEA (%R8,%R8,2),%R10 |
0x40b399 MOV 0x18(%RDI),%RCX |
0x40b39d LEA (%RCX,%R12,1),%RAX |
0x40b3a1 LEA (%RCX,%R10,1),%RDX |
0x40b3a5 ADD %R14,%RCX |
0x40b3a8 MOV %RCX,%RSI |
0x40b3ab SUB %RAX,%RSI |
0x40b3ae AND $0x8,%ESI |
0x40b3b1 JE 40b470 |
0x40b3b7 VMOVSD 0x8(%RDX),%XMM2 |
0x40b3bc VSUBSD 0x8(%RAX),%XMM2,%XMM0 |
0x40b3c1 VMOVSD (%RDX),%XMM1 |
0x40b3c5 VSUBSD (%RAX),%XMM1,%XMM1 |
0x40b3c9 VMOVSD 0x10(%RDX),%XMM13 |
0x40b3ce VSUBSD 0x10(%RAX),%XMM13,%XMM2 |
0x40b3d3 VMULSD %XMM0,%XMM0,%XMM3 |
0x40b3d7 VFMADD231SD %XMM1,%XMM1,%XMM3 |
0x40b3dc VFMADD231SD %XMM2,%XMM2,%XMM3 |
0x40b3e1 VCOMISD %XMM3,%XMM9 |
0x40b3e5 JB 40b461 |
0x40b3e7 VCOMISD %XMM4,%XMM3 |
0x40b3eb JBE 40b461 |
0x40b3ed VDIVSD %XMM3,%XMM7,%XMM15 |
0x40b3f1 MOV 0x30(%RDI),%RSI |
0x40b3f5 ADD %R8,%RSI |
0x40b3f8 VMULSD %XMM15,%XMM15,%XMM13 |
0x40b3fd VMULSD %XMM15,%XMM10,%XMM3 |
0x40b402 VMULSD %XMM8,%XMM15,%XMM14 |
0x40b407 VMULSD %XMM3,%XMM13,%XMM3 |
0x40b40b VSUBSD %XMM7,%XMM3,%XMM13 |
0x40b40f VFMSUB213SD -0x38(%RBP),%XMM3,%XMM13 |
0x40b415 VMOVSD %XMM13,%XMM13,%XMM15 |
0x40b41a VFMADD231SD %XMM6,%XMM13,%XMM5 |
0x40b41f VMOVSD %XMM3,%XMM3,%XMM13 |
0x40b423 VFMADD132SD %XMM11,%XMM12,%XMM13 |
0x40b428 VFMADD213SD (%RSI),%XMM6,%XMM15 |
0x40b42d VMULSD %XMM13,%XMM3,%XMM3 |
0x40b432 VMOVSD %XMM15,(%RSI) |
0x40b436 MOV 0x28(%RDI),%RSI |
0x40b43a ADD %R10,%RSI |
0x40b43d VMULSD %XMM14,%XMM3,%XMM14 |
0x40b442 VFNMADD213SD (%RSI),%XMM14,%XMM1 |
0x40b447 VFNMADD213SD 0x8(%RSI),%XMM14,%XMM0 |
0x40b44d VFNMADD213SD 0x10(%RSI),%XMM2,%XMM14 |
0x40b453 VMOVSD %XMM1,(%RSI) |
0x40b457 VMOVSD %XMM0,0x8(%RSI) |
0x40b45c VMOVSD %XMM14,0x10(%RSI) |
0x40b461 ADD $0x18,%RAX |
0x40b465 CMP %RAX,%RCX |
0x40b468 JE 40b5d8 |
0x40b46e XCHG %AX,%AX |
(84) 0x40b470 VMOVSD 0x8(%RDX),%XMM0 |
(84) 0x40b475 VSUBSD 0x8(%RAX),%XMM0,%XMM0 |
(84) 0x40b47a VMOVSD (%RDX),%XMM1 |
(84) 0x40b47e VSUBSD (%RAX),%XMM1,%XMM1 |
(84) 0x40b482 VMOVSD 0x10(%RDX),%XMM2 |
(84) 0x40b487 VSUBSD 0x10(%RAX),%XMM2,%XMM2 |
(84) 0x40b48c VMULSD %XMM0,%XMM0,%XMM15 |
(84) 0x40b490 VFMADD231SD %XMM1,%XMM1,%XMM15 |
(84) 0x40b495 VFMADD231SD %XMM2,%XMM2,%XMM15 |
(84) 0x40b49a VCOMISD %XMM15,%XMM9 |
(84) 0x40b49f JB 40b51b |
(84) 0x40b4a1 VCOMISD %XMM4,%XMM15 |
(84) 0x40b4a5 JBE 40b51b |
(84) 0x40b4a7 VDIVSD %XMM15,%XMM7,%XMM3 |
(84) 0x40b4ac MOV 0x30(%RDI),%RSI |
(84) 0x40b4b0 ADD %R8,%RSI |
(84) 0x40b4b3 VMULSD %XMM3,%XMM3,%XMM13 |
(84) 0x40b4b7 VMULSD %XMM3,%XMM10,%XMM15 |
(84) 0x40b4bb VMULSD %XMM8,%XMM3,%XMM14 |
(84) 0x40b4c0 VMULSD %XMM15,%XMM13,%XMM3 |
(84) 0x40b4c5 VSUBSD %XMM7,%XMM3,%XMM13 |
(84) 0x40b4c9 VFMSUB213SD -0x38(%RBP),%XMM3,%XMM13 |
(84) 0x40b4cf VMOVSD %XMM13,%XMM13,%XMM15 |
(84) 0x40b4d4 VFMADD231SD %XMM6,%XMM13,%XMM5 |
(84) 0x40b4d9 VMOVSD %XMM3,%XMM3,%XMM13 |
(84) 0x40b4dd VFMADD132SD %XMM11,%XMM12,%XMM13 |
(84) 0x40b4e2 VFMADD213SD (%RSI),%XMM6,%XMM15 |
(84) 0x40b4e7 VMULSD %XMM13,%XMM3,%XMM3 |
(84) 0x40b4ec VMOVSD %XMM15,(%RSI) |
(84) 0x40b4f0 MOV 0x28(%RDI),%RSI |
(84) 0x40b4f4 ADD %R10,%RSI |
(84) 0x40b4f7 VMULSD %XMM14,%XMM3,%XMM14 |
(84) 0x40b4fc VFNMADD213SD (%RSI),%XMM14,%XMM1 |
(84) 0x40b501 VFNMADD213SD 0x8(%RSI),%XMM14,%XMM0 |
(84) 0x40b507 VFNMADD213SD 0x10(%RSI),%XMM2,%XMM14 |
(84) 0x40b50d VMOVSD %XMM1,(%RSI) |
(84) 0x40b511 VMOVSD %XMM0,0x8(%RSI) |
(84) 0x40b516 VMOVSD %XMM14,0x10(%RSI) |
(84) 0x40b51b VMOVSD 0x8(%RDX),%XMM0 |
(84) 0x40b520 VSUBSD 0x20(%RAX),%XMM0,%XMM0 |
(84) 0x40b525 LEA 0x18(%RAX),%RSI |
(84) 0x40b529 VMOVSD (%RDX),%XMM1 |
(84) 0x40b52d VSUBSD 0x18(%RAX),%XMM1,%XMM1 |
(84) 0x40b532 VMOVSD 0x10(%RDX),%XMM2 |
(84) 0x40b537 VSUBSD 0x28(%RAX),%XMM2,%XMM2 |
(84) 0x40b53c VMULSD %XMM0,%XMM0,%XMM15 |
(84) 0x40b540 VFMADD231SD %XMM1,%XMM1,%XMM15 |
(84) 0x40b545 VFMADD231SD %XMM2,%XMM2,%XMM15 |
(84) 0x40b54a VCOMISD %XMM15,%XMM9 |
(84) 0x40b54f JB 40b5cb |
(84) 0x40b551 VCOMISD %XMM4,%XMM15 |
(84) 0x40b555 JBE 40b5cb |
(84) 0x40b557 VDIVSD %XMM15,%XMM7,%XMM3 |
(84) 0x40b55c MOV 0x30(%RDI),%RAX |
(84) 0x40b560 ADD %R8,%RAX |
(84) 0x40b563 VMULSD %XMM3,%XMM3,%XMM13 |
(84) 0x40b567 VMULSD %XMM3,%XMM10,%XMM15 |
(84) 0x40b56b VMULSD %XMM8,%XMM3,%XMM14 |
(84) 0x40b570 VMULSD %XMM15,%XMM13,%XMM3 |
(84) 0x40b575 VSUBSD %XMM7,%XMM3,%XMM13 |
(84) 0x40b579 VFMSUB213SD -0x38(%RBP),%XMM3,%XMM13 |
(84) 0x40b57f VMOVSD %XMM13,%XMM13,%XMM15 |
(84) 0x40b584 VFMADD231SD %XMM6,%XMM13,%XMM5 |
(84) 0x40b589 VMOVSD %XMM3,%XMM3,%XMM13 |
(84) 0x40b58d VFMADD132SD %XMM11,%XMM12,%XMM13 |
(84) 0x40b592 VFMADD213SD (%RAX),%XMM6,%XMM15 |
(84) 0x40b597 VMULSD %XMM13,%XMM3,%XMM3 |
(84) 0x40b59c VMOVSD %XMM15,(%RAX) |
(84) 0x40b5a0 MOV 0x28(%RDI),%RAX |
(84) 0x40b5a4 ADD %R10,%RAX |
(84) 0x40b5a7 VMULSD %XMM14,%XMM3,%XMM14 |
(84) 0x40b5ac VFNMADD213SD (%RAX),%XMM14,%XMM1 |
(84) 0x40b5b1 VFNMADD213SD 0x8(%RAX),%XMM14,%XMM0 |
(84) 0x40b5b7 VFNMADD213SD 0x10(%RAX),%XMM2,%XMM14 |
(84) 0x40b5bd VMOVSD %XMM1,(%RAX) |
(84) 0x40b5c1 VMOVSD %XMM0,0x8(%RAX) |
(84) 0x40b5c6 VMOVSD %XMM14,0x10(%RAX) |
(84) 0x40b5cb LEA 0x18(%RSI),%RAX |
(84) 0x40b5cf CMP %RAX,%RCX |
(84) 0x40b5d2 JNE 40b470 |
0x40b5d8 ADD $0x8,%R8 |
0x40b5dc CMP %R8,%RBX |
0x40b5df JNE 40b388 |
/scratch_na/users/xoserete/qaas_runs/171-416-1926/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 187 - 216 |
-------------------------------------------------------------------------------- |
187: for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++) |
188: { |
189: |
190: // loop over atoms in jBox |
191: for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++) |
[...] |
197: dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m]; |
198: r2+=dr[m]*dr[m]; |
199: } |
200: |
201: if ( r2 <= rCut2 && r2 > 0.0) |
202: { |
203: |
204: // Important note: |
205: // from this point on r actually refers to 1.0/r |
206: r2 = 1.0/r2; |
207: real_t r6 = s6 * (r2*r2*r2); |
208: real_t eLocal = r6 * (r6 - 1.0) - eShift; |
209: s->atoms->U[iOff] += 0.5*eLocal; |
210: ePot += 0.5*eLocal; |
211: |
212: // different formulation to avoid sqrt computation |
213: real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0); |
214: for (int m=0; m<3; m++) |
215: { |
216: s->atoms->f[iOff][m] -= dr[m]*fr; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○98.29 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
○1.71 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 2.74 |
CQA speedup if fully vectorized | 5.25 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.05 |
Bottlenecks | P0, |
Function | ljForce._omp_fn.1 |
Source | ljForce.c:187-187,ljForce.c:191-191,ljForce.c:197-198,ljForce.c:201-201,ljForce.c:206-210,ljForce.c:213-213,ljForce.c:216-216 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 10.50 |
CQA cycles if no scalar integer | 10.50 |
CQA cycles if FP arith vectorized | 3.83 |
CQA cycles if fully vectorized | 2.00 |
Front-end cycles | 9.33 |
DIV/SQRT cycles | 10.50 |
P0 cycles | 10.00 |
P1 cycles | 5.00 |
P2 cycles | 5.00 |
P3 cycles | 2.00 |
P4 cycles | 5.70 |
P5 cycles | 6.00 |
P6 cycles | 2.00 |
P7 cycles | 2.00 |
P8 cycles | 2.00 |
P9 cycles | 5.80 |
P10 cycles | 5.00 |
P11 cycles | 4.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 11.28 - 11.54 |
Stall cycles (UFS) | 1.12 - 1.36 |
Nb insns | 57.00 |
Nb uops | 56.00 |
Nb loads | 15.00 |
Nb stores | 4.00 |
Nb stack references | 1.00 |
FLOP/cycle | 2.86 |
Nb FLOP add-sub | 4.00 |
Nb FLOP mul | 7.00 |
Nb FLOP fma | 9.00 |
Nb FLOP div | 1.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 14.48 |
Bytes prefetched | 0.00 |
Bytes loaded | 120.00 |
Bytes stored | 32.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | 0.00 |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.32 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | 12.50 |
Vector-efficiency ratio div_sqrt | 12.50 |
Vector-efficiency ratio other | 11.46 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 2.74 |
CQA speedup if fully vectorized | 5.25 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.05 |
Bottlenecks | P0, |
Function | ljForce._omp_fn.1 |
Source | ljForce.c:187-187,ljForce.c:191-191,ljForce.c:197-198,ljForce.c:201-201,ljForce.c:206-210,ljForce.c:213-213,ljForce.c:216-216 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 10.50 |
CQA cycles if no scalar integer | 10.50 |
CQA cycles if FP arith vectorized | 3.83 |
CQA cycles if fully vectorized | 2.00 |
Front-end cycles | 9.33 |
DIV/SQRT cycles | 10.50 |
P0 cycles | 10.00 |
P1 cycles | 5.00 |
P2 cycles | 5.00 |
P3 cycles | 2.00 |
P4 cycles | 5.70 |
P5 cycles | 6.00 |
P6 cycles | 2.00 |
P7 cycles | 2.00 |
P8 cycles | 2.00 |
P9 cycles | 5.80 |
P10 cycles | 5.00 |
P11 cycles | 4.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 11.28 - 11.54 |
Stall cycles (UFS) | 1.12 - 1.36 |
Nb insns | 57.00 |
Nb uops | 56.00 |
Nb loads | 15.00 |
Nb stores | 4.00 |
Nb stack references | 1.00 |
FLOP/cycle | 2.86 |
Nb FLOP add-sub | 4.00 |
Nb FLOP mul | 7.00 |
Nb FLOP fma | 9.00 |
Nb FLOP div | 1.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 14.48 |
Bytes prefetched | 0.00 |
Bytes loaded | 120.00 |
Bytes stored | 32.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | 0.00 |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.32 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | 12.50 |
Vector-efficiency ratio div_sqrt | 12.50 |
Vector-efficiency ratio other | 11.46 |
Path / |
Function | ljForce._omp_fn.1 |
Source file and lines | ljForce.c:187-216 |
Module | exec |
nb instructions | 57 |
nb uops | 56 |
loop length | 245 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 16 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 1 |
ADD-SUB / MUL ratio | 0.57 |
micro-operation queue | 9.33 cycles |
front end | 9.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 10.50 | 10.00 | 5.00 | 5.00 | 2.00 | 5.70 | 6.00 | 2.00 | 2.00 | 2.00 | 5.80 | 5.00 |
cycles | 10.50 | 10.00 | 5.00 | 5.00 | 2.00 | 5.70 | 6.00 | 2.00 | 2.00 | 2.00 | 5.80 | 5.00 |
Cycles executing div or sqrt instructions | 4.00 |
FE+BE cycles | 11.28-11.54 |
Stall cycles | 1.12-1.36 |
ROB full (events) | 0.94-0.95 |
RS full (events) | 1.52-2.07 |
Front-end | 9.33 |
Dispatch | 10.50 |
DIV/SQRT | 4.00 |
Overall L1 | 10.50 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
all | 9% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | 12% |
other | 12% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | 12% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CMP %R13D,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 40b5d8 <ljForce._omp_fn.1+0x3d8> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x20(%R15),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R8,%R8,2),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x18(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RCX,%R12,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%RCX,%R10,1),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %R14,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
AND $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 40b470 <ljForce._omp_fn.1+0x270> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD 0x8(%RDX),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VSUBSD 0x8(%RAX),%XMM2,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVSD (%RDX),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VSUBSD (%RAX),%XMM1,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVSD 0x10(%RDX),%XMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VSUBSD 0x10(%RAX),%XMM13,%XMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMULSD %XMM0,%XMM0,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD %XMM1,%XMM1,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD %XMM2,%XMM2,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCOMISD %XMM3,%XMM9 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JB 40b461 <ljForce._omp_fn.1+0x261> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VCOMISD %XMM4,%XMM3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JBE 40b461 <ljForce._omp_fn.1+0x261> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VDIVSD %XMM3,%XMM7,%XMM15 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
MOV 0x30(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R8,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMULSD %XMM15,%XMM15,%XMM13 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD %XMM15,%XMM10,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD %XMM8,%XMM15,%XMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD %XMM3,%XMM13,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VSUBSD %XMM7,%XMM3,%XMM13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMSUB213SD -0x38(%RBP),%XMM3,%XMM13 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM13,%XMM13,%XMM15 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VFMADD231SD %XMM6,%XMM13,%XMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM3,%XMM3,%XMM13 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VFMADD132SD %XMM11,%XMM12,%XMM13 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SD (%RSI),%XMM6,%XMM15 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMULSD %XMM13,%XMM3,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM15,(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R10,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMULSD %XMM14,%XMM3,%XMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFNMADD213SD (%RSI),%XMM14,%XMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFNMADD213SD 0x8(%RSI),%XMM14,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFNMADD213SD 0x10(%RSI),%XMM2,%XMM14 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM1,(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM0,0x8(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM14,0x10(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD $0x18,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 40b5d8 <ljForce._omp_fn.1+0x3d8> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x8,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R8,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 40b388 <ljForce._omp_fn.1+0x188> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | ljForce._omp_fn.1 |
Source file and lines | ljForce.c:187-216 |
Module | exec |
nb instructions | 57 |
nb uops | 56 |
loop length | 245 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 16 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 1 |
ADD-SUB / MUL ratio | 0.57 |
micro-operation queue | 9.33 cycles |
front end | 9.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 10.50 | 10.00 | 5.00 | 5.00 | 2.00 | 5.70 | 6.00 | 2.00 | 2.00 | 2.00 | 5.80 | 5.00 |
cycles | 10.50 | 10.00 | 5.00 | 5.00 | 2.00 | 5.70 | 6.00 | 2.00 | 2.00 | 2.00 | 5.80 | 5.00 |
Cycles executing div or sqrt instructions | 4.00 |
FE+BE cycles | 11.28-11.54 |
Stall cycles | 1.12-1.36 |
ROB full (events) | 0.94-0.95 |
RS full (events) | 1.52-2.07 |
Front-end | 9.33 |
Dispatch | 10.50 |
DIV/SQRT | 4.00 |
Overall L1 | 10.50 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
all | 9% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | 12% |
other | 12% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | 12% |
div/sqrt | 12% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CMP %R13D,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 40b5d8 <ljForce._omp_fn.1+0x3d8> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x20(%R15),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R8,%R8,2),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x18(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RCX,%R12,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%RCX,%R10,1),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %R14,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RAX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
AND $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 40b470 <ljForce._omp_fn.1+0x270> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD 0x8(%RDX),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VSUBSD 0x8(%RAX),%XMM2,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVSD (%RDX),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VSUBSD (%RAX),%XMM1,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMOVSD 0x10(%RDX),%XMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VSUBSD 0x10(%RAX),%XMM13,%XMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VMULSD %XMM0,%XMM0,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD %XMM1,%XMM1,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SD %XMM2,%XMM2,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCOMISD %XMM3,%XMM9 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JB 40b461 <ljForce._omp_fn.1+0x261> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VCOMISD %XMM4,%XMM3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JBE 40b461 <ljForce._omp_fn.1+0x261> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VDIVSD %XMM3,%XMM7,%XMM15 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
MOV 0x30(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R8,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMULSD %XMM15,%XMM15,%XMM13 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD %XMM15,%XMM10,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD %XMM8,%XMM15,%XMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULSD %XMM3,%XMM13,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VSUBSD %XMM7,%XMM3,%XMM13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMSUB213SD -0x38(%RBP),%XMM3,%XMM13 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM13,%XMM13,%XMM15 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VFMADD231SD %XMM6,%XMM13,%XMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM3,%XMM3,%XMM13 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VFMADD132SD %XMM11,%XMM12,%XMM13 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SD (%RSI),%XMM6,%XMM15 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMULSD %XMM13,%XMM3,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM15,(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R10,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMULSD %XMM14,%XMM3,%XMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFNMADD213SD (%RSI),%XMM14,%XMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFNMADD213SD 0x8(%RSI),%XMM14,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFNMADD213SD 0x10(%RSI),%XMM2,%XMM14 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM1,(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM0,0x8(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM14,0x10(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD $0x18,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 40b5d8 <ljForce._omp_fn.1+0x3d8> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x8,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R8,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 40b388 <ljForce._omp_fn.1+0x188> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |