Loop Id: 66 | Module: exec | Source: initAtoms.c:221-228 | Coverage: 0.01% |
---|
Loop Id: 66 | Module: exec | Source: initAtoms.c:221-228 | Coverage: 0.01% |
---|
0x40b340 VMOVQ %RBX,%XMM10 |
0x40b345 VPADDQ %XMM10,%XMM8,%XMM10 |
0x40b34a VPSLLQ $0x3,%XMM10,%XMM11 |
0x40b350 VPSLLQ $0x4,%XMM10,%XMM10 |
0x40b356 VPADDQ %XMM11,%XMM10,%XMM10 |
0x40b35b VPBROADCASTQ %XMM10,%YMM10 |
0x40b360 VPADDQ %YMM4,%YMM10,%YMM10 |
0x40b364 KXNORW %K0,%K0,%K1 |
0x40b368 VPXOR %XMM11,%XMM11,%XMM11 |
0x40b36d VGATHERQPD (%R10,%YMM10,1),%YMM11{%K1} [3] |
0x40b374 KXNORW %K0,%K0,%K1 |
0x40b378 VXORPD %XMM12,%XMM12,%XMM12 |
0x40b37d VGATHERQPD 0x8(%R10,%YMM10,1),%YMM12{%K1} [3] |
0x40b385 KXNORW %K0,%K0,%K1 |
0x40b389 VXORPD %XMM13,%XMM13,%XMM13 |
0x40b38e VGATHERQPD 0x10(%R10,%YMM10,1),%YMM13{%K1} [3] |
0x40b396 VPMOVSXDQ (%R13,%RBX,4),%YMM10 [1] |
0x40b39d VPSLLQ $0x4,%YMM10,%YMM10 |
0x40b3a3 KXNORW %K0,%K0,%K1 |
0x40b3a7 VXORPD %XMM14,%XMM14,%XMM14 |
0x40b3ac VGATHERQPD 0x8(%R9,%YMM10,1),%YMM14{%K1} [2] |
0x40b3b4 VADDPD %YMM9,%YMM11,%YMM9 |
0x40b3b9 VADDPD %YMM7,%YMM12,%YMM7 |
0x40b3bd VADDPD %YMM6,%YMM13,%YMM6 |
0x40b3c1 VADDPD %YMM5,%YMM14,%YMM5 |
0x40b3c5 ADD $0x4,%RBX |
0x40b3c9 CMP %R15D,%EBX |
0x40b3cc JLE 40b340 |
/home/eoseret/qaas_runs_CPU_9468/171-110-4860/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 221 - 228 |
-------------------------------------------------------------------------------- |
221: for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff) |
222: { |
223: v0 += s->atoms->p[iOff][0]; |
224: v1 += s->atoms->p[iOff][1]; |
225: v2 += s->atoms->p[iOff][2]; |
226: |
227: int iSpecies = s->atoms->iSpecies[iOff]; |
228: v3 += s->species[iSpecies].mass; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.14 |
CQA speedup if FP arith vectorized | 1.18 |
CQA speedup if fully vectorized | 2.58 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.32 |
Bottlenecks | P0, P1, P5, |
Function | computeVcm.extracted |
Source | initAtoms.c:221-228 |
Source loop unroll info | unrolled by 4 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 4 |
CQA cycles | 9.67 |
CQA cycles if no scalar integer | 8.50 |
CQA cycles if FP arith vectorized | 8.17 |
CQA cycles if fully vectorized | 3.75 |
Front-end cycles | 7.33 |
DIV/SQRT cycles | 9.67 |
P0 cycles | 9.67 |
P1 cycles | 5.67 |
P2 cycles | 5.67 |
P3 cycles | 0.00 |
P4 cycles | 9.67 |
P5 cycles | 1.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 5.67 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 3 |
FE+BE cycles (UFS) | 10.03 - 87.28 |
Stall cycles (UFS) | 3.57 - 80.49 |
Nb insns | 28.00 |
Nb uops | 44.00 |
Nb loads | 5.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 1.66 |
Nb FLOP add-sub | 16.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 14.90 |
Bytes prefetched | 0.00 |
Bytes loaded | 144.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 1.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 2.00 |
Vectorization ratio all | 90.48 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 84.62 |
Vector-efficiency ratio all | 35.71 |
Vector-efficiency ratio load | 45.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 42.86 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 32.69 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.14 |
CQA speedup if FP arith vectorized | 1.18 |
CQA speedup if fully vectorized | 2.58 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.32 |
Bottlenecks | P0, P1, P5, |
Function | computeVcm.extracted |
Source | initAtoms.c:221-228 |
Source loop unroll info | unrolled by 4 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 4 |
CQA cycles | 9.67 |
CQA cycles if no scalar integer | 8.50 |
CQA cycles if FP arith vectorized | 8.17 |
CQA cycles if fully vectorized | 3.75 |
Front-end cycles | 7.33 |
DIV/SQRT cycles | 9.67 |
P0 cycles | 9.67 |
P1 cycles | 5.67 |
P2 cycles | 5.67 |
P3 cycles | 0.00 |
P4 cycles | 9.67 |
P5 cycles | 1.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 5.67 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 3 |
FE+BE cycles (UFS) | 10.03 - 87.28 |
Stall cycles (UFS) | 3.57 - 80.49 |
Nb insns | 28.00 |
Nb uops | 44.00 |
Nb loads | 5.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 1.66 |
Nb FLOP add-sub | 16.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 14.90 |
Bytes prefetched | 0.00 |
Bytes loaded | 144.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 1.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 2.00 |
Vectorization ratio all | 90.48 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 84.62 |
Vector-efficiency ratio all | 35.71 |
Vector-efficiency ratio load | 45.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 42.86 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 32.69 |
Path / |
Function | computeVcm.extracted |
Source file and lines | initAtoms.c:221-228 |
Module | exec |
nb instructions | 28 |
nb uops | 44 |
loop length | 146 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 6 |
used ymm registers | 10 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 7.33 cycles |
front end | 7.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 9.67 | 9.67 | 5.67 | 5.67 | 0.00 | 9.67 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 5.67 |
cycles | 9.67 | 9.67 | 5.67 | 5.67 | 0.00 | 9.67 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 5.67 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 3.00 |
FE+BE cycles | 10.03-87.28 |
Stall cycles | 3.57-80.49 |
RS full (events) | 8.71-0.81 |
Front-end | 7.33 |
Dispatch | 9.67 |
Data deps. | 3.00 |
Overall L1 | 9.67 |
all | 80% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 66% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 90% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 84% |
all | 27% |
load | 25% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 33% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 25% |
all | 43% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 39% |
all | 35% |
load | 45% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 42% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 32% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVQ %RBX,%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VPADDQ %XMM10,%XMM8,%XMM10 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPSLLQ $0x3,%XMM10,%XMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 |
VPSLLQ $0x4,%XMM10,%XMM10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 |
VPADDQ %XMM11,%XMM10,%XMM10 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPBROADCASTQ %XMM10,%YMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPADDQ %YMM4,%YMM10,%YMM10 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VPXOR %XMM11,%XMM11,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VGATHERQPD (%R10,%YMM10,1),%YMM11{%K1} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VXORPD %XMM12,%XMM12,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VGATHERQPD 0x8(%R10,%YMM10,1),%YMM12{%K1} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VXORPD %XMM13,%XMM13,%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VGATHERQPD 0x10(%R10,%YMM10,1),%YMM13{%K1} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VPMOVSXDQ (%R13,%RBX,4),%YMM10 | 2 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
VPSLLQ $0x4,%YMM10,%YMM10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 |
KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VXORPD %XMM14,%XMM14,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VGATHERQPD 0x8(%R9,%YMM10,1),%YMM14{%K1} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VADDPD %YMM9,%YMM11,%YMM9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPD %YMM7,%YMM12,%YMM7 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPD %YMM6,%YMM13,%YMM6 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPD %YMM5,%YMM14,%YMM5 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
ADD $0x4,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 40b340 <computeVcm.extracted+0x240> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | computeVcm.extracted |
Source file and lines | initAtoms.c:221-228 |
Module | exec |
nb instructions | 28 |
nb uops | 44 |
loop length | 146 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 6 |
used ymm registers | 10 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 7.33 cycles |
front end | 7.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 9.67 | 9.67 | 5.67 | 5.67 | 0.00 | 9.67 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 5.67 |
cycles | 9.67 | 9.67 | 5.67 | 5.67 | 0.00 | 9.67 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 5.67 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 3.00 |
FE+BE cycles | 10.03-87.28 |
Stall cycles | 3.57-80.49 |
RS full (events) | 8.71-0.81 |
Front-end | 7.33 |
Dispatch | 9.67 |
Data deps. | 3.00 |
Overall L1 | 9.67 |
all | 80% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 66% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 90% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 84% |
all | 27% |
load | 25% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 33% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 25% |
all | 43% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 39% |
all | 35% |
load | 45% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 42% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 32% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVQ %RBX,%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VPADDQ %XMM10,%XMM8,%XMM10 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPSLLQ $0x3,%XMM10,%XMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 |
VPSLLQ $0x4,%XMM10,%XMM10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 |
VPADDQ %XMM11,%XMM10,%XMM10 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VPBROADCASTQ %XMM10,%YMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPADDQ %YMM4,%YMM10,%YMM10 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VPXOR %XMM11,%XMM11,%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VGATHERQPD (%R10,%YMM10,1),%YMM11{%K1} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VXORPD %XMM12,%XMM12,%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VGATHERQPD 0x8(%R10,%YMM10,1),%YMM12{%K1} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VXORPD %XMM13,%XMM13,%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VGATHERQPD 0x10(%R10,%YMM10,1),%YMM13{%K1} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VPMOVSXDQ (%R13,%RBX,4),%YMM10 | 2 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
VPSLLQ $0x4,%YMM10,%YMM10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 |
KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VXORPD %XMM14,%XMM14,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VGATHERQPD 0x8(%R9,%YMM10,1),%YMM14{%K1} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VADDPD %YMM9,%YMM11,%YMM9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPD %YMM7,%YMM12,%YMM7 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPD %YMM6,%YMM13,%YMM6 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPD %YMM5,%YMM14,%YMM5 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
ADD $0x4,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R15D,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 40b340 <computeVcm.extracted+0x240> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |