Function: setVcm._omp_fn.0 | Module: exec | Source: initAtoms.c:123-133 | Coverage: 0.01% |
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Function: setVcm._omp_fn.0 | Module: exec | Source: initAtoms.c:123-133 | Coverage: 0.01% |
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/home/eoseret/qaas_runs_CPU_9468/171-110-4860/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 123 - 133 |
-------------------------------------------------------------------------------- |
123: #pragma omp parallel for |
124: for (int iBox=0; iBox<s->boxes->nLocalBoxes; ++iBox) |
125: { |
126: for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff) |
127: { |
128: int iSpecies = s->atoms->iSpecies[iOff]; |
129: real_t mass = s->species[iSpecies].mass; |
130: |
131: s->atoms->p[iOff][0] += mass * vShift[0]; |
132: s->atoms->p[iOff][1] += mass * vShift[1]; |
133: s->atoms->p[iOff][2] += mass * vShift[2]; |
0x404f50 PUSH %RBP |
0x404f51 MOV %RSP,%RBP |
0x404f54 PUSH %R14 |
0x404f56 PUSH %R13 |
0x404f58 MOV %RDI,%R13 |
0x404f5b PUSH %R12 |
0x404f5d PUSH %RBX |
0x404f5e MOV (%RDI),%RBX |
0x404f61 MOV 0x18(%RBX),%R14 |
0x404f65 CALL 403060 <omp_get_num_threads@plt> |
0x404f6a MOV %EAX,%R12D |
0x404f6d CALL 403150 <omp_get_thread_num@plt> |
0x404f72 MOV %EAX,%R8D |
0x404f75 MOV 0xc(%R14),%EAX |
0x404f79 CLTD |
0x404f7a IDIV %R12D |
0x404f7d CMP %EDX,%R8D |
0x404f80 JL 405212 |
0x404f86 IMUL %EAX,%R8D |
0x404f8a ADD %EDX,%R8D |
0x404f8d ADD %R8D,%EAX |
0x404f90 CMP %EAX,%R8D |
0x404f93 JGE 405209 |
0x404f99 MOVSXD %R8D,%R9 |
0x404f9c MOV 0x78(%R14),%R12 |
0x404fa0 MOV 0x8(%R13),%RCX |
0x404fa4 SAL $0x6,%R8D |
0x404fa8 LEA (%R9,%R9,2),%R11 |
0x404fac SAL $0x9,%R11 |
(10) 0x404fb0 MOVSXD (%R12,%R9,4),%R10 |
(10) 0x404fb4 TEST %R10D,%R10D |
(10) 0x404fb7 JLE 4051f2 |
(10) 0x404fbd MOV 0x20(%RBX),%R14 |
(10) 0x404fc1 MOVSXD %R8D,%RSI |
(10) 0x404fc4 MOV 0x28(%RBX),%RDI |
(10) 0x404fc8 MOV 0x10(%R14),%R13 |
(10) 0x404fcc MOV 0x20(%R14),%RDX |
(10) 0x404fd0 MOV %R9,%R14 |
(10) 0x404fd3 SAL $0x6,%R14 |
(10) 0x404fd7 ADD %R14,%R10 |
(10) 0x404fda LEA (%R13,%RSI,4),%RSI |
(10) 0x404fdf ADD %R11,%RDX |
(10) 0x404fe2 LEA (%R13,%R10,4),%R10 |
(10) 0x404fe7 MOV %R10,%R13 |
(10) 0x404fea SUB %RSI,%R13 |
(10) 0x404fed SUB $0x4,%R13 |
(10) 0x404ff1 SHR $0x2,%R13 |
(10) 0x404ff5 INC %R13 |
(10) 0x404ff8 AND $0x3,%R13D |
(10) 0x404ffc JE 4050ea |
(10) 0x405002 CMP $0x1,%R13 |
(10) 0x405006 JE 40509c |
(10) 0x40500c CMP $0x2,%R13 |
(10) 0x405010 JE 405057 |
(10) 0x405012 MOVSXD (%RSI),%R14 |
(10) 0x405015 VMOVSD (%RCX),%XMM1 |
(10) 0x405019 ADD $0x4,%RSI |
(10) 0x40501d ADD $0x18,%RDX |
(10) 0x405021 VMOVSD -0x8(%RDX),%XMM7 |
(10) 0x405026 SAL $0x4,%R14 |
(10) 0x40502a VMOVSD 0x8(%RDI,%R14,1),%XMM0 |
(10) 0x405031 VFMADD213SD -0x18(%RDX),%XMM0,%XMM1 |
(10) 0x405037 VMOVSD %XMM1,-0x18(%RDX) |
(10) 0x40503c VMOVSD 0x8(%RCX),%XMM2 |
(10) 0x405041 VFMADD213SD -0x10(%RDX),%XMM0,%XMM2 |
(10) 0x405047 VMOVSD %XMM2,-0x10(%RDX) |
(10) 0x40504c VFMADD132SD 0x10(%RCX),%XMM7,%XMM0 |
(10) 0x405052 VMOVSD %XMM0,-0x8(%RDX) |
(10) 0x405057 MOVSXD (%RSI),%R13 |
(10) 0x40505a VMOVSD (%RCX),%XMM4 |
(10) 0x40505e ADD $0x4,%RSI |
(10) 0x405062 ADD $0x18,%RDX |
(10) 0x405066 VMOVSD -0x8(%RDX),%XMM6 |
(10) 0x40506b SAL $0x4,%R13 |
(10) 0x40506f VMOVSD 0x8(%RDI,%R13,1),%XMM3 |
(10) 0x405076 VFMADD213SD -0x18(%RDX),%XMM3,%XMM4 |
(10) 0x40507c VMOVSD %XMM4,-0x18(%RDX) |
(10) 0x405081 VMOVSD 0x8(%RCX),%XMM5 |
(10) 0x405086 VFMADD213SD -0x10(%RDX),%XMM3,%XMM5 |
(10) 0x40508c VMOVSD %XMM5,-0x10(%RDX) |
(10) 0x405091 VFMADD132SD 0x10(%RCX),%XMM6,%XMM3 |
(10) 0x405097 VMOVSD %XMM3,-0x8(%RDX) |
(10) 0x40509c MOVSXD (%RSI),%R14 |
(10) 0x40509f VMOVSD (%RCX),%XMM9 |
(10) 0x4050a3 ADD $0x4,%RSI |
(10) 0x4050a7 ADD $0x18,%RDX |
(10) 0x4050ab VMOVSD -0x8(%RDX),%XMM11 |
(10) 0x4050b0 SAL $0x4,%R14 |
(10) 0x4050b4 VMOVSD 0x8(%RDI,%R14,1),%XMM8 |
(10) 0x4050bb VFMADD213SD -0x18(%RDX),%XMM8,%XMM9 |
(10) 0x4050c1 VMOVSD %XMM9,-0x18(%RDX) |
(10) 0x4050c6 VMOVSD 0x8(%RCX),%XMM10 |
(10) 0x4050cb VFMADD213SD -0x10(%RDX),%XMM8,%XMM10 |
(10) 0x4050d1 VMOVSD %XMM10,-0x10(%RDX) |
(10) 0x4050d6 VFMADD132SD 0x10(%RCX),%XMM11,%XMM8 |
(10) 0x4050dc VMOVSD %XMM8,-0x8(%RDX) |
(10) 0x4050e1 CMP %RSI,%R10 |
(10) 0x4050e4 JE 4051f2 |
(11) 0x4050ea MOVSXD (%RSI),%R13 |
(11) 0x4050ed VMOVSD (%RCX),%XMM13 |
(11) 0x4050f1 ADD $0x10,%RSI |
(11) 0x4050f5 ADD $0x60,%RDX |
(11) 0x4050f9 VMOVSD -0x50(%RDX),%XMM15 |
(11) 0x4050fe MOVSXD -0xc(%RSI),%R14 |
(11) 0x405102 SAL $0x4,%R13 |
(11) 0x405106 VMOVSD -0x38(%RDX),%XMM7 |
(11) 0x40510b VMOVSD -0x20(%RDX),%XMM6 |
(11) 0x405110 VMOVSD 0x8(%RDI,%R13,1),%XMM12 |
(11) 0x405117 SAL $0x4,%R14 |
(11) 0x40511b MOVSXD -0x8(%RSI),%R13 |
(11) 0x40511f VFMADD213SD -0x60(%RDX),%XMM12,%XMM13 |
(11) 0x405125 SAL $0x4,%R13 |
(11) 0x405129 VMOVSD %XMM13,-0x60(%RDX) |
(11) 0x40512e VMOVSD 0x8(%RCX),%XMM14 |
(11) 0x405133 VFMADD213SD -0x58(%RDX),%XMM12,%XMM14 |
(11) 0x405139 VMOVSD %XMM14,-0x58(%RDX) |
(11) 0x40513e VFMADD132SD 0x10(%RCX),%XMM15,%XMM12 |
(11) 0x405144 VMOVSD %XMM12,-0x50(%RDX) |
(11) 0x405149 VMOVSD 0x8(%RDI,%R14,1),%XMM0 |
(11) 0x405150 VMOVSD (%RCX),%XMM1 |
(11) 0x405154 VFMADD213SD -0x48(%RDX),%XMM0,%XMM1 |
(11) 0x40515a VMOVSD %XMM1,-0x48(%RDX) |
(11) 0x40515f VMOVSD 0x8(%RCX),%XMM2 |
(11) 0x405164 VFMADD213SD -0x40(%RDX),%XMM0,%XMM2 |
(11) 0x40516a VMOVSD %XMM2,-0x40(%RDX) |
(11) 0x40516f VFMADD132SD 0x10(%RCX),%XMM7,%XMM0 |
(11) 0x405175 VMOVSD %XMM0,-0x38(%RDX) |
(11) 0x40517a VMOVSD 0x8(%RDI,%R13,1),%XMM3 |
(11) 0x405181 VMOVSD (%RCX),%XMM4 |
(11) 0x405185 VFMADD213SD -0x30(%RDX),%XMM3,%XMM4 |
(11) 0x40518b VMOVSD %XMM4,-0x30(%RDX) |
(11) 0x405190 VMOVSD 0x8(%RCX),%XMM5 |
(11) 0x405195 VFMADD213SD -0x28(%RDX),%XMM3,%XMM5 |
(11) 0x40519b VMOVSD %XMM5,-0x28(%RDX) |
(11) 0x4051a0 VFMADD132SD 0x10(%RCX),%XMM6,%XMM3 |
(11) 0x4051a6 VMOVSD %XMM3,-0x20(%RDX) |
(11) 0x4051ab MOVSXD -0x4(%RSI),%R14 |
(11) 0x4051af VMOVSD (%RCX),%XMM9 |
(11) 0x4051b3 VMOVSD -0x8(%RDX),%XMM11 |
(11) 0x4051b8 SAL $0x4,%R14 |
(11) 0x4051bc VMOVSD 0x8(%RDI,%R14,1),%XMM8 |
(11) 0x4051c3 VFMADD213SD -0x18(%RDX),%XMM8,%XMM9 |
(11) 0x4051c9 VMOVSD %XMM9,-0x18(%RDX) |
(11) 0x4051ce VMOVSD 0x8(%RCX),%XMM10 |
(11) 0x4051d3 VFMADD213SD -0x10(%RDX),%XMM8,%XMM10 |
(11) 0x4051d9 VMOVSD %XMM10,-0x10(%RDX) |
(11) 0x4051de VFMADD132SD 0x10(%RCX),%XMM11,%XMM8 |
(11) 0x4051e4 VMOVSD %XMM8,-0x8(%RDX) |
(11) 0x4051e9 CMP %RSI,%R10 |
(11) 0x4051ec JNE 4050ea |
(10) 0x4051f2 INC %R9 |
(10) 0x4051f5 ADD $0x40,%R8D |
(10) 0x4051f9 ADD $0x600,%R11 |
(10) 0x405200 CMP %R9D,%EAX |
(10) 0x405203 JG 404fb0 |
0x405209 POP %RBX |
0x40520a POP %R12 |
0x40520c POP %R13 |
0x40520e POP %R14 |
0x405210 POP %RBP |
0x405211 RET |
0x405212 INC %EAX |
0x405214 XOR %EDX,%EDX |
0x405216 JMP 404f86 |
0x40521b NOPL (%RAX,%RAX,1) |
Path / |
Source file and lines | initAtoms.c:123-133 |
Module | exec |
nb instructions | 39 |
nb uops | 44 |
loop length | 119 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 7.33 cycles |
front end | 7.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.00 | 4.00 | 3.67 | 3.67 | 3.50 | 3.07 | 3.00 | 3.50 | 3.50 | 3.50 | 2.93 | 3.67 |
cycles | 3.00 | 5.33 | 3.67 | 3.67 | 3.50 | 3.07 | 3.00 | 3.50 | 3.50 | 3.50 | 2.93 | 3.67 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 7.09-7.14 |
Stall cycles | 0.00 |
Front-end | 7.33 |
Dispatch | 5.33 |
DIV/SQRT | 6.00 |
Overall L1 | 7.33 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 0% |
all | 8% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 6% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 7% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV (%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 403060 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 403150 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xc(%R14),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 405212 <setVcm._omp_fn.0+0x2c2> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 405209 <setVcm._omp_fn.0+0x2b9> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD %R8D,%R9 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV 0x78(%R14),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x6,%R8D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R9,%R9,2),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SAL $0x9,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 404f86 <setVcm._omp_fn.0+0x36> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | initAtoms.c:123-133 |
Module | exec |
nb instructions | 39 |
nb uops | 44 |
loop length | 119 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 7.33 cycles |
front end | 7.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.00 | 4.00 | 3.67 | 3.67 | 3.50 | 3.07 | 3.00 | 3.50 | 3.50 | 3.50 | 2.93 | 3.67 |
cycles | 3.00 | 5.33 | 3.67 | 3.67 | 3.50 | 3.07 | 3.00 | 3.50 | 3.50 | 3.50 | 2.93 | 3.67 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 7.09-7.14 |
Stall cycles | 0.00 |
Front-end | 7.33 |
Dispatch | 5.33 |
DIV/SQRT | 6.00 |
Overall L1 | 7.33 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 0% |
all | 8% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 6% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 7% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV (%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 403060 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 403150 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xc(%R14),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 405212 <setVcm._omp_fn.0+0x2c2> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%R8D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R8D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 405209 <setVcm._omp_fn.0+0x2b9> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD %R8D,%R9 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
MOV 0x78(%R14),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%R13),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x6,%R8D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R9,%R9,2),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SAL $0x9,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 404f86 <setVcm._omp_fn.0+0x36> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼setVcm._omp_fn.0– | 0.01 | 0 |
▼Loop 10 - initAtoms.c:126-133 - exec– | 0 | 0 |
○Loop 11 - initAtoms.c:126-133 - exec | 0.01 | 0 |