Function: advanceVelocity._omp_fn.0 | Module: exec | Source: timestep.c:71-78 | Coverage: 5.27% |
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Function: advanceVelocity._omp_fn.0 | Module: exec | Source: timestep.c:71-78 | Coverage: 5.27% |
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/home/eoseret/qaas_runs_CPU_9468/171-110-4860/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 78 |
-------------------------------------------------------------------------------- |
71: #pragma omp parallel for |
72: for (int iBox=0; iBox<nBoxes; iBox++) |
73: { |
74: for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++) |
75: { |
76: s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0]; |
77: s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1]; |
78: s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2]; |
0x405a60 PUSH %RBP |
0x405a61 MOV %RSP,%RBP |
0x405a64 PUSH %R12 |
0x405a66 PUSH %RBX |
0x405a67 MOV %RDI,%RBX |
0x405a6a CALL 403060 <omp_get_num_threads@plt> |
0x405a6f MOV %EAX,%R12D |
0x405a72 CALL 403150 <omp_get_thread_num@plt> |
0x405a77 MOV %EAX,%ESI |
0x405a79 MOV 0x10(%RBX),%EAX |
0x405a7c CLTD |
0x405a7d IDIV %R12D |
0x405a80 CMP %EDX,%ESI |
0x405a82 JL 405eaa |
0x405a88 IMUL %EAX,%ESI |
0x405a8b ADD %EDX,%ESI |
0x405a8d ADD %ESI,%EAX |
0x405a8f CMP %EAX,%ESI |
0x405a91 JGE 405ea5 |
0x405a97 MOV (%RBX),%R10 |
0x405a9a MOVSXD %ESI,%R12 |
0x405a9d VMOVSD 0x8(%RBX),%XMM0 |
0x405aa2 LEA (%R12,%R12,2),%R8 |
0x405aa6 MOV 0x18(%R10),%RCX |
0x405aaa SAL $0x9,%R8 |
0x405aae MOV 0x78(%RCX),%R9 |
0x405ab2 NOPW (%RAX,%RAX,1) |
(17) 0x405ab8 MOVSXD (%R9,%R12,4),%RDI |
(17) 0x405abc TEST %EDI,%EDI |
(17) 0x405abe JLE 405e92 |
(17) 0x405ac4 MOV 0x20(%R10),%R11 |
(17) 0x405ac8 LEA (%RDI,%RDI,2),%RBX |
(17) 0x405acc LEA -0x18(,%RBX,8),%RDI |
(17) 0x405ad4 MOV 0x20(%R11),%RSI |
(17) 0x405ad8 MOV 0x28(%R11),%RCX |
(17) 0x405adc SHR $0x3,%RDI |
(17) 0x405ae0 MOV $0xaaaaaaaaaaaaaab,%R11 |
(17) 0x405aea IMUL %R11,%RDI |
(17) 0x405aee ADD %R8,%RSI |
(17) 0x405af1 ADD %R8,%RCX |
(17) 0x405af4 LEA (%RSI,%RBX,8),%RDX |
(17) 0x405af8 INC %RDI |
(17) 0x405afb AND $0x7,%EDI |
(17) 0x405afe JE 405cbb |
(17) 0x405b04 CMP $0x1,%RDI |
(17) 0x405b08 JE 405c7c |
(17) 0x405b0e CMP $0x2,%RDI |
(17) 0x405b12 JE 405c46 |
(17) 0x405b18 CMP $0x3,%RDI |
(17) 0x405b1c JE 405c10 |
(17) 0x405b22 CMP $0x4,%RDI |
(17) 0x405b26 JE 405bda |
(17) 0x405b2c CMP $0x5,%RDI |
(17) 0x405b30 JE 405ba4 |
(17) 0x405b32 CMP $0x6,%RDI |
(17) 0x405b36 JE 405b6e |
(17) 0x405b38 VMOVSD (%RCX),%XMM1 |
(17) 0x405b3c VFMADD213SD (%RSI),%XMM0,%XMM1 |
(17) 0x405b41 ADD $0x18,%RCX |
(17) 0x405b45 ADD $0x18,%RSI |
(17) 0x405b49 VMOVSD %XMM1,-0x18(%RSI) |
(17) 0x405b4e VMOVSD -0x10(%RCX),%XMM2 |
(17) 0x405b53 VFMADD213SD -0x10(%RSI),%XMM0,%XMM2 |
(17) 0x405b59 VMOVSD %XMM2,-0x10(%RSI) |
(17) 0x405b5e VMOVSD -0x8(%RCX),%XMM3 |
(17) 0x405b63 VFMADD213SD -0x8(%RSI),%XMM0,%XMM3 |
(17) 0x405b69 VMOVSD %XMM3,-0x8(%RSI) |
(17) 0x405b6e VMOVSD (%RCX),%XMM4 |
(17) 0x405b72 VFMADD213SD (%RSI),%XMM0,%XMM4 |
(17) 0x405b77 ADD $0x18,%RCX |
(17) 0x405b7b ADD $0x18,%RSI |
(17) 0x405b7f VMOVSD %XMM4,-0x18(%RSI) |
(17) 0x405b84 VMOVSD -0x10(%RCX),%XMM5 |
(17) 0x405b89 VFMADD213SD -0x10(%RSI),%XMM0,%XMM5 |
(17) 0x405b8f VMOVSD %XMM5,-0x10(%RSI) |
(17) 0x405b94 VMOVSD -0x8(%RCX),%XMM6 |
(17) 0x405b99 VFMADD213SD -0x8(%RSI),%XMM0,%XMM6 |
(17) 0x405b9f VMOVSD %XMM6,-0x8(%RSI) |
(17) 0x405ba4 VMOVSD (%RCX),%XMM7 |
(17) 0x405ba8 VFMADD213SD (%RSI),%XMM0,%XMM7 |
(17) 0x405bad ADD $0x18,%RCX |
(17) 0x405bb1 ADD $0x18,%RSI |
(17) 0x405bb5 VMOVSD %XMM7,-0x18(%RSI) |
(17) 0x405bba VMOVSD -0x10(%RCX),%XMM8 |
(17) 0x405bbf VFMADD213SD -0x10(%RSI),%XMM0,%XMM8 |
(17) 0x405bc5 VMOVSD %XMM8,-0x10(%RSI) |
(17) 0x405bca VMOVSD -0x8(%RCX),%XMM9 |
(17) 0x405bcf VFMADD213SD -0x8(%RSI),%XMM0,%XMM9 |
(17) 0x405bd5 VMOVSD %XMM9,-0x8(%RSI) |
(17) 0x405bda VMOVSD (%RCX),%XMM10 |
(17) 0x405bde VFMADD213SD (%RSI),%XMM0,%XMM10 |
(17) 0x405be3 ADD $0x18,%RCX |
(17) 0x405be7 ADD $0x18,%RSI |
(17) 0x405beb VMOVSD %XMM10,-0x18(%RSI) |
(17) 0x405bf0 VMOVSD -0x10(%RCX),%XMM11 |
(17) 0x405bf5 VFMADD213SD -0x10(%RSI),%XMM0,%XMM11 |
(17) 0x405bfb VMOVSD %XMM11,-0x10(%RSI) |
(17) 0x405c00 VMOVSD -0x8(%RCX),%XMM12 |
(17) 0x405c05 VFMADD213SD -0x8(%RSI),%XMM0,%XMM12 |
(17) 0x405c0b VMOVSD %XMM12,-0x8(%RSI) |
(17) 0x405c10 VMOVSD (%RCX),%XMM13 |
(17) 0x405c14 VFMADD213SD (%RSI),%XMM0,%XMM13 |
(17) 0x405c19 ADD $0x18,%RCX |
(17) 0x405c1d ADD $0x18,%RSI |
(17) 0x405c21 VMOVSD %XMM13,-0x18(%RSI) |
(17) 0x405c26 VMOVSD -0x10(%RCX),%XMM14 |
(17) 0x405c2b VFMADD213SD -0x10(%RSI),%XMM0,%XMM14 |
(17) 0x405c31 VMOVSD %XMM14,-0x10(%RSI) |
(17) 0x405c36 VMOVSD -0x8(%RCX),%XMM15 |
(17) 0x405c3b VFMADD213SD -0x8(%RSI),%XMM0,%XMM15 |
(17) 0x405c41 VMOVSD %XMM15,-0x8(%RSI) |
(17) 0x405c46 VMOVSD (%RCX),%XMM1 |
(17) 0x405c4a VFMADD213SD (%RSI),%XMM0,%XMM1 |
(17) 0x405c4f ADD $0x18,%RCX |
(17) 0x405c53 ADD $0x18,%RSI |
(17) 0x405c57 VMOVSD %XMM1,-0x18(%RSI) |
(17) 0x405c5c VMOVSD -0x10(%RCX),%XMM2 |
(17) 0x405c61 VFMADD213SD -0x10(%RSI),%XMM0,%XMM2 |
(17) 0x405c67 VMOVSD %XMM2,-0x10(%RSI) |
(17) 0x405c6c VMOVSD -0x8(%RCX),%XMM3 |
(17) 0x405c71 VFMADD213SD -0x8(%RSI),%XMM0,%XMM3 |
(17) 0x405c77 VMOVSD %XMM3,-0x8(%RSI) |
(17) 0x405c7c VMOVSD (%RCX),%XMM4 |
(17) 0x405c80 VFMADD213SD (%RSI),%XMM0,%XMM4 |
(17) 0x405c85 ADD $0x18,%RSI |
(17) 0x405c89 ADD $0x18,%RCX |
(17) 0x405c8d VMOVSD %XMM4,-0x18(%RSI) |
(17) 0x405c92 VMOVSD -0x10(%RCX),%XMM5 |
(17) 0x405c97 VFMADD213SD -0x10(%RSI),%XMM0,%XMM5 |
(17) 0x405c9d VMOVSD %XMM5,-0x10(%RSI) |
(17) 0x405ca2 VMOVSD -0x8(%RCX),%XMM6 |
(17) 0x405ca7 VFMADD213SD -0x8(%RSI),%XMM0,%XMM6 |
(17) 0x405cad VMOVSD %XMM6,-0x8(%RSI) |
(17) 0x405cb2 CMP %RDX,%RSI |
(17) 0x405cb5 JE 405e92 |
(18) 0x405cbb VMOVSD (%RCX),%XMM7 |
(18) 0x405cbf VFMADD213SD (%RSI),%XMM0,%XMM7 |
(18) 0x405cc4 ADD $0xc0,%RSI |
(18) 0x405ccb ADD $0xc0,%RCX |
(18) 0x405cd2 VMOVSD %XMM7,-0xc0(%RSI) |
(18) 0x405cda VMOVSD -0xb8(%RCX),%XMM8 |
(18) 0x405ce2 VFMADD213SD -0xb8(%RSI),%XMM0,%XMM8 |
(18) 0x405ceb VMOVSD %XMM8,-0xb8(%RSI) |
(18) 0x405cf3 VMOVSD -0xb0(%RCX),%XMM9 |
(18) 0x405cfb VFMADD213SD -0xb0(%RSI),%XMM0,%XMM9 |
(18) 0x405d04 VMOVSD %XMM9,-0xb0(%RSI) |
(18) 0x405d0c VMOVSD -0xa8(%RCX),%XMM10 |
(18) 0x405d14 VFMADD213SD -0xa8(%RSI),%XMM0,%XMM10 |
(18) 0x405d1d VMOVSD %XMM10,-0xa8(%RSI) |
(18) 0x405d25 VMOVSD -0xa0(%RCX),%XMM11 |
(18) 0x405d2d VFMADD213SD -0xa0(%RSI),%XMM0,%XMM11 |
(18) 0x405d36 VMOVSD %XMM11,-0xa0(%RSI) |
(18) 0x405d3e VMOVSD -0x98(%RCX),%XMM12 |
(18) 0x405d46 VFMADD213SD -0x98(%RSI),%XMM0,%XMM12 |
(18) 0x405d4f VMOVSD %XMM12,-0x98(%RSI) |
(18) 0x405d57 VMOVSD -0x90(%RCX),%XMM13 |
(18) 0x405d5f VFMADD213SD -0x90(%RSI),%XMM0,%XMM13 |
(18) 0x405d68 VMOVSD %XMM13,-0x90(%RSI) |
(18) 0x405d70 VMOVSD -0x88(%RCX),%XMM14 |
(18) 0x405d78 VFMADD213SD -0x88(%RSI),%XMM0,%XMM14 |
(18) 0x405d81 VMOVSD %XMM14,-0x88(%RSI) |
(18) 0x405d89 VMOVSD -0x80(%RCX),%XMM15 |
(18) 0x405d8e VFMADD213SD -0x80(%RSI),%XMM0,%XMM15 |
(18) 0x405d94 VMOVSD %XMM15,-0x80(%RSI) |
(18) 0x405d99 VMOVSD -0x78(%RCX),%XMM1 |
(18) 0x405d9e VFMADD213SD -0x78(%RSI),%XMM0,%XMM1 |
(18) 0x405da4 VMOVSD %XMM1,-0x78(%RSI) |
(18) 0x405da9 VMOVSD -0x70(%RCX),%XMM2 |
(18) 0x405dae VFMADD213SD -0x70(%RSI),%XMM0,%XMM2 |
(18) 0x405db4 VMOVSD %XMM2,-0x70(%RSI) |
(18) 0x405db9 VMOVSD -0x68(%RCX),%XMM3 |
(18) 0x405dbe VFMADD213SD -0x68(%RSI),%XMM0,%XMM3 |
(18) 0x405dc4 VMOVSD %XMM3,-0x68(%RSI) |
(18) 0x405dc9 VMOVSD -0x60(%RCX),%XMM4 |
(18) 0x405dce VFMADD213SD -0x60(%RSI),%XMM0,%XMM4 |
(18) 0x405dd4 VMOVSD %XMM4,-0x60(%RSI) |
(18) 0x405dd9 VMOVSD -0x58(%RCX),%XMM5 |
(18) 0x405dde VFMADD213SD -0x58(%RSI),%XMM0,%XMM5 |
(18) 0x405de4 VMOVSD %XMM5,-0x58(%RSI) |
(18) 0x405de9 VMOVSD -0x50(%RCX),%XMM6 |
(18) 0x405dee VFMADD213SD -0x50(%RSI),%XMM0,%XMM6 |
(18) 0x405df4 VMOVSD %XMM6,-0x50(%RSI) |
(18) 0x405df9 VMOVSD -0x48(%RCX),%XMM7 |
(18) 0x405dfe VFMADD213SD -0x48(%RSI),%XMM0,%XMM7 |
(18) 0x405e04 VMOVSD %XMM7,-0x48(%RSI) |
(18) 0x405e09 VMOVSD -0x40(%RCX),%XMM8 |
(18) 0x405e0e VFMADD213SD -0x40(%RSI),%XMM0,%XMM8 |
(18) 0x405e14 VMOVSD %XMM8,-0x40(%RSI) |
(18) 0x405e19 VMOVSD -0x38(%RCX),%XMM9 |
(18) 0x405e1e VFMADD213SD -0x38(%RSI),%XMM0,%XMM9 |
(18) 0x405e24 VMOVSD %XMM9,-0x38(%RSI) |
(18) 0x405e29 VMOVSD -0x30(%RCX),%XMM10 |
(18) 0x405e2e VFMADD213SD -0x30(%RSI),%XMM0,%XMM10 |
(18) 0x405e34 VMOVSD %XMM10,-0x30(%RSI) |
(18) 0x405e39 VMOVSD -0x28(%RCX),%XMM11 |
(18) 0x405e3e VFMADD213SD -0x28(%RSI),%XMM0,%XMM11 |
(18) 0x405e44 VMOVSD %XMM11,-0x28(%RSI) |
(18) 0x405e49 VMOVSD -0x20(%RCX),%XMM12 |
(18) 0x405e4e VFMADD213SD -0x20(%RSI),%XMM0,%XMM12 |
(18) 0x405e54 VMOVSD %XMM12,-0x20(%RSI) |
(18) 0x405e59 VMOVSD -0x18(%RCX),%XMM13 |
(18) 0x405e5e VFMADD213SD -0x18(%RSI),%XMM0,%XMM13 |
(18) 0x405e64 VMOVSD %XMM13,-0x18(%RSI) |
(18) 0x405e69 VMOVSD -0x10(%RCX),%XMM14 |
(18) 0x405e6e VFMADD213SD -0x10(%RSI),%XMM0,%XMM14 |
(18) 0x405e74 VMOVSD %XMM14,-0x10(%RSI) |
(18) 0x405e79 VMOVSD -0x8(%RCX),%XMM15 |
(18) 0x405e7e VFMADD213SD -0x8(%RSI),%XMM0,%XMM15 |
(18) 0x405e84 VMOVSD %XMM15,-0x8(%RSI) |
(18) 0x405e89 CMP %RDX,%RSI |
(18) 0x405e8c JNE 405cbb |
(17) 0x405e92 INC %R12 |
(17) 0x405e95 ADD $0x600,%R8 |
(17) 0x405e9c CMP %R12D,%EAX |
(17) 0x405e9f JG 405ab8 |
0x405ea5 POP %RBX |
0x405ea6 POP %R12 |
0x405ea8 POP %RBP |
0x405ea9 RET |
0x405eaa INC %EAX |
0x405eac XOR %EDX,%EDX |
0x405eae JMP 405a88 |
0x405eb3 NOPW %CS:(%RAX,%RAX,1) |
0x405ebe XCHG %AX,%AX |
Path / |
Source file and lines | timestep.c:71-78 |
Module | exec |
nb instructions | 36 |
nb uops | 41 |
loop length | 115 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 6.83 cycles |
front end | 6.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.70 | 4.00 | 3.00 | 3.00 | 2.50 | 2.87 | 2.70 | 2.50 | 2.50 | 2.50 | 2.73 | 3.00 |
cycles | 2.70 | 5.33 | 3.00 | 3.00 | 2.50 | 2.87 | 2.70 | 2.50 | 2.50 | 2.50 | 2.73 | 3.00 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 6.52-6.58 |
Stall cycles | 0.00 |
Front-end | 6.83 |
Dispatch | 5.33 |
DIV/SQRT | 6.00 |
Overall L1 | 6.83 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 0% |
all | 7% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 6% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 7% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 8% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 6% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 403060 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 403150 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x10(%RBX),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 405eaa <advanceVelocity._omp_fn.0+0x44a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %ESI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 405ea5 <advanceVelocity._omp_fn.0+0x445> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%RBX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %ESI,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
VMOVSD 0x8(%RBX),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R12,%R12,2),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x18(%R10),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x9,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV 0x78(%RCX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 405a88 <advanceVelocity._omp_fn.0+0x28> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | timestep.c:71-78 |
Module | exec |
nb instructions | 36 |
nb uops | 41 |
loop length | 115 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 6.83 cycles |
front end | 6.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.70 | 4.00 | 3.00 | 3.00 | 2.50 | 2.87 | 2.70 | 2.50 | 2.50 | 2.50 | 2.73 | 3.00 |
cycles | 2.70 | 5.33 | 3.00 | 3.00 | 2.50 | 2.87 | 2.70 | 2.50 | 2.50 | 2.50 | 2.73 | 3.00 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 6.52-6.58 |
Stall cycles | 0.00 |
Front-end | 6.83 |
Dispatch | 5.33 |
DIV/SQRT | 6.00 |
Overall L1 | 6.83 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 0% |
all | 7% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 6% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 7% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 8% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 6% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 8% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 403060 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 403150 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x10(%RBX),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 405eaa <advanceVelocity._omp_fn.0+0x44a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%ESI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %ESI,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %EAX,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 405ea5 <advanceVelocity._omp_fn.0+0x445> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%RBX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %ESI,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
VMOVSD 0x8(%RBX),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R12,%R12,2),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x18(%R10),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x9,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV 0x78(%RCX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 405a88 <advanceVelocity._omp_fn.0+0x28> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advanceVelocity._omp_fn.0– | 5.27 | 0.82 |
▼Loop 17 - timestep.c:74-78 - exec– | 2.49 | 0.29 |
○Loop 18 - timestep.c:74-78 - exec | 2.77 | 0.32 |