Function: advancePosition._omp_fn.0 | Module: exec | Source: timestep.c:85-94 | Coverage: 3.54% |
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Function: advancePosition._omp_fn.0 | Module: exec | Source: timestep.c:85-94 | Coverage: 3.54% |
---|
/home/eoseret/qaas_runs_CPU_9468/171-110-4860/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 85 - 94 |
-------------------------------------------------------------------------------- |
85: #pragma omp parallel for |
86: for (int iBox=0; iBox<nBoxes; iBox++) |
87: { |
88: for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++) |
89: { |
90: int iSpecies = s->atoms->iSpecies[iOff]; |
91: real_t invMass = 1.0/s->species[iSpecies].mass; |
92: s->atoms->r[iOff][0] += dt*s->atoms->p[iOff][0]*invMass; |
93: s->atoms->r[iOff][1] += dt*s->atoms->p[iOff][1]*invMass; |
94: s->atoms->r[iOff][2] += dt*s->atoms->p[iOff][2]*invMass; |
0x405ec0 PUSH %RBP |
0x405ec1 MOV %RSP,%RBP |
0x405ec4 PUSH %R14 |
0x405ec6 PUSH %R13 |
0x405ec8 PUSH %R12 |
0x405eca MOV %RDI,%R12 |
0x405ecd PUSH %RBX |
0x405ece CALL 403060 <omp_get_num_threads@plt> |
0x405ed3 MOV %EAX,%EBX |
0x405ed5 CALL 403150 <omp_get_thread_num@plt> |
0x405eda MOV %EAX,%R9D |
0x405edd MOV 0x10(%R12),%EAX |
0x405ee2 CLTD |
0x405ee3 IDIV %EBX |
0x405ee5 CMP %EDX,%R9D |
0x405ee8 JL 4061ac |
0x405eee IMUL %EAX,%R9D |
0x405ef2 ADD %EDX,%R9D |
0x405ef5 LEA (%RAX,%R9,1),%EBX |
0x405ef9 CMP %EBX,%R9D |
0x405efc JGE 4061a3 |
0x405f02 VMOVSD 0x8(%R12),%XMM0 |
0x405f09 MOV (%R12),%R12 |
0x405f0d MOVSXD %R9D,%R10 |
0x405f10 SAL $0x6,%R9D |
0x405f14 LEA (%R10,%R10,2),%RAX |
0x405f18 VMOVSD 0xccd0(%RIP),%XMM2 |
0x405f20 MOV 0x18(%R12),%RCX |
0x405f25 SAL $0x9,%RAX |
0x405f29 MOV 0x78(%RCX),%R13 |
0x405f2d NOPL (%RAX) |
(19) 0x405f30 MOVSXD (%R13,%R10,4),%R8 |
(19) 0x405f35 TEST %R8D,%R8D |
(19) 0x405f38 JLE 40618d |
(19) 0x405f3e MOV 0x20(%R12),%R11 |
(19) 0x405f43 MOVSXD %R9D,%RSI |
(19) 0x405f46 MOV 0x28(%R12),%RDI |
(19) 0x405f4b MOV 0x10(%R11),%R14 |
(19) 0x405f4f MOV 0x18(%R11),%RDX |
(19) 0x405f53 MOV 0x20(%R11),%RCX |
(19) 0x405f57 MOV %R10,%R11 |
(19) 0x405f5a SAL $0x6,%R11 |
(19) 0x405f5e LEA (%R14,%RSI,4),%RSI |
(19) 0x405f62 ADD %RAX,%RDX |
(19) 0x405f65 ADD %R8,%R11 |
(19) 0x405f68 ADD %RAX,%RCX |
(19) 0x405f6b LEA (%R14,%R11,4),%R11 |
(19) 0x405f6f MOV %R11,%R8 |
(19) 0x405f72 SUB %RSI,%R8 |
(19) 0x405f75 SUB $0x4,%R8 |
(19) 0x405f79 SHR $0x2,%R8 |
(19) 0x405f7d INC %R8 |
(19) 0x405f80 AND $0x3,%R8D |
(19) 0x405f84 JE 40607e |
(19) 0x405f8a CMP $0x1,%R8 |
(19) 0x405f8e JE 40602c |
(19) 0x405f94 CMP $0x2,%R8 |
(19) 0x405f98 JE 405fe3 |
(19) 0x405f9a MOVSXD (%RSI),%R14 |
(19) 0x405f9d VMULSD (%RCX),%XMM0,%XMM3 |
(19) 0x405fa1 ADD $0x4,%RSI |
(19) 0x405fa5 ADD $0x18,%RDX |
(19) 0x405fa9 ADD $0x18,%RCX |
(19) 0x405fad SAL $0x4,%R14 |
(19) 0x405fb1 VDIVSD 0x8(%RDI,%R14,1),%XMM2,%XMM1 |
(19) 0x405fb8 VFMADD213SD -0x18(%RDX),%XMM1,%XMM3 |
(19) 0x405fbe VMOVSD %XMM3,-0x18(%RDX) |
(19) 0x405fc3 VMULSD -0x10(%RCX),%XMM0,%XMM4 |
(19) 0x405fc8 VFMADD213SD -0x10(%RDX),%XMM1,%XMM4 |
(19) 0x405fce VMOVSD %XMM4,-0x10(%RDX) |
(19) 0x405fd3 VMULSD -0x8(%RCX),%XMM0,%XMM5 |
(19) 0x405fd8 VFMADD213SD -0x8(%RDX),%XMM5,%XMM1 |
(19) 0x405fde VMOVSD %XMM1,-0x8(%RDX) |
(19) 0x405fe3 MOVSXD (%RSI),%R8 |
(19) 0x405fe6 VMULSD (%RCX),%XMM0,%XMM7 |
(19) 0x405fea ADD $0x4,%RSI |
(19) 0x405fee ADD $0x18,%RDX |
(19) 0x405ff2 ADD $0x18,%RCX |
(19) 0x405ff6 SAL $0x4,%R8 |
(19) 0x405ffa VDIVSD 0x8(%RDI,%R8,1),%XMM2,%XMM6 |
(19) 0x406001 VFMADD213SD -0x18(%RDX),%XMM6,%XMM7 |
(19) 0x406007 VMOVSD %XMM7,-0x18(%RDX) |
(19) 0x40600c VMULSD -0x10(%RCX),%XMM0,%XMM8 |
(19) 0x406011 VFMADD213SD -0x10(%RDX),%XMM6,%XMM8 |
(19) 0x406017 VMOVSD %XMM8,-0x10(%RDX) |
(19) 0x40601c VMULSD -0x8(%RCX),%XMM0,%XMM9 |
(19) 0x406021 VFMADD213SD -0x8(%RDX),%XMM9,%XMM6 |
(19) 0x406027 VMOVSD %XMM6,-0x8(%RDX) |
(19) 0x40602c MOVSXD (%RSI),%R14 |
(19) 0x40602f VMULSD (%RCX),%XMM0,%XMM11 |
(19) 0x406033 ADD $0x4,%RSI |
(19) 0x406037 ADD $0x18,%RDX |
(19) 0x40603b ADD $0x18,%RCX |
(19) 0x40603f SAL $0x4,%R14 |
(19) 0x406043 VDIVSD 0x8(%RDI,%R14,1),%XMM2,%XMM10 |
(19) 0x40604a VFMADD213SD -0x18(%RDX),%XMM10,%XMM11 |
(19) 0x406050 VMOVSD %XMM11,-0x18(%RDX) |
(19) 0x406055 VMULSD -0x10(%RCX),%XMM0,%XMM12 |
(19) 0x40605a VFMADD213SD -0x10(%RDX),%XMM10,%XMM12 |
(19) 0x406060 VMOVSD %XMM12,-0x10(%RDX) |
(19) 0x406065 VMULSD -0x8(%RCX),%XMM0,%XMM13 |
(19) 0x40606a VFMADD213SD -0x8(%RDX),%XMM13,%XMM10 |
(19) 0x406070 VMOVSD %XMM10,-0x8(%RDX) |
(19) 0x406075 CMP %RSI,%R11 |
(19) 0x406078 JE 40618d |
(20) 0x40607e MOVSXD (%RSI),%R8 |
(20) 0x406081 VMULSD (%RCX),%XMM0,%XMM15 |
(20) 0x406085 ADD $0x10,%RSI |
(20) 0x406089 ADD $0x60,%RDX |
(20) 0x40608d MOVSXD -0xc(%RSI),%R14 |
(20) 0x406091 ADD $0x60,%RCX |
(20) 0x406095 SAL $0x4,%R8 |
(20) 0x406099 VDIVSD 0x8(%RDI,%R8,1),%XMM2,%XMM14 |
(20) 0x4060a0 SAL $0x4,%R14 |
(20) 0x4060a4 MOVSXD -0x8(%RSI),%R8 |
(20) 0x4060a8 VFMADD213SD -0x60(%RDX),%XMM14,%XMM15 |
(20) 0x4060ae SAL $0x4,%R8 |
(20) 0x4060b2 VMOVSD %XMM15,-0x60(%RDX) |
(20) 0x4060b7 VMULSD -0x58(%RCX),%XMM0,%XMM1 |
(20) 0x4060bc VFMADD213SD -0x58(%RDX),%XMM14,%XMM1 |
(20) 0x4060c2 VMOVSD %XMM1,-0x58(%RDX) |
(20) 0x4060c7 VMULSD -0x50(%RCX),%XMM0,%XMM3 |
(20) 0x4060cc VFMADD213SD -0x50(%RDX),%XMM3,%XMM14 |
(20) 0x4060d2 VMOVSD %XMM14,-0x50(%RDX) |
(20) 0x4060d7 VMULSD -0x48(%RCX),%XMM0,%XMM5 |
(20) 0x4060dc VDIVSD 0x8(%RDI,%R14,1),%XMM2,%XMM4 |
(20) 0x4060e3 VFMADD213SD -0x48(%RDX),%XMM4,%XMM5 |
(20) 0x4060e9 VMOVSD %XMM5,-0x48(%RDX) |
(20) 0x4060ee VMULSD -0x40(%RCX),%XMM0,%XMM6 |
(20) 0x4060f3 VFMADD213SD -0x40(%RDX),%XMM4,%XMM6 |
(20) 0x4060f9 VMOVSD %XMM6,-0x40(%RDX) |
(20) 0x4060fe VMULSD -0x38(%RCX),%XMM0,%XMM7 |
(20) 0x406103 VFMADD213SD -0x38(%RDX),%XMM7,%XMM4 |
(20) 0x406109 VMOVSD %XMM4,-0x38(%RDX) |
(20) 0x40610e VMULSD -0x30(%RCX),%XMM0,%XMM9 |
(20) 0x406113 VDIVSD 0x8(%RDI,%R8,1),%XMM2,%XMM8 |
(20) 0x40611a VFMADD213SD -0x30(%RDX),%XMM8,%XMM9 |
(20) 0x406120 VMOVSD %XMM9,-0x30(%RDX) |
(20) 0x406125 VMULSD -0x28(%RCX),%XMM0,%XMM10 |
(20) 0x40612a VFMADD213SD -0x28(%RDX),%XMM8,%XMM10 |
(20) 0x406130 VMOVSD %XMM10,-0x28(%RDX) |
(20) 0x406135 VMULSD -0x20(%RCX),%XMM0,%XMM11 |
(20) 0x40613a VFMADD213SD -0x20(%RDX),%XMM11,%XMM8 |
(20) 0x406140 VMOVSD %XMM8,-0x20(%RDX) |
(20) 0x406145 MOVSXD -0x4(%RSI),%R14 |
(20) 0x406149 VMULSD -0x18(%RCX),%XMM0,%XMM13 |
(20) 0x40614e SAL $0x4,%R14 |
(20) 0x406152 VDIVSD 0x8(%RDI,%R14,1),%XMM2,%XMM12 |
(20) 0x406159 VFMADD213SD -0x18(%RDX),%XMM12,%XMM13 |
(20) 0x40615f VMOVSD %XMM13,-0x18(%RDX) |
(20) 0x406164 VMULSD -0x10(%RCX),%XMM0,%XMM14 |
(20) 0x406169 VFMADD213SD -0x10(%RDX),%XMM12,%XMM14 |
(20) 0x40616f VMOVSD %XMM14,-0x10(%RDX) |
(20) 0x406174 VMULSD -0x8(%RCX),%XMM0,%XMM15 |
(20) 0x406179 VFMADD213SD -0x8(%RDX),%XMM15,%XMM12 |
(20) 0x40617f VMOVSD %XMM12,-0x8(%RDX) |
(20) 0x406184 CMP %RSI,%R11 |
(20) 0x406187 JNE 40607e |
(19) 0x40618d INC %R10 |
(19) 0x406190 ADD $0x40,%R9D |
(19) 0x406194 ADD $0x600,%RAX |
(19) 0x40619a CMP %R10D,%EBX |
(19) 0x40619d JG 405f30 |
0x4061a3 POP %RBX |
0x4061a4 POP %R12 |
0x4061a6 POP %R13 |
0x4061a8 POP %R14 |
0x4061aa POP %RBP |
0x4061ab RET |
0x4061ac INC %EAX |
0x4061ae XOR %EDX,%EDX |
0x4061b0 JMP 405eee |
0x4061b5 NOPW %CS:(%RAX,%RAX,1) |
Path / |
Source file and lines | timestep.c:85-94 |
Module | exec |
nb instructions | 41 |
nb uops | 46 |
loop length | 141 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 7.67 cycles |
front end | 7.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.00 | 4.00 | 4.00 | 4.00 | 3.50 | 3.07 | 3.00 | 3.50 | 3.50 | 3.50 | 2.93 | 4.00 |
cycles | 3.00 | 5.33 | 4.00 | 4.00 | 3.50 | 3.07 | 3.00 | 3.50 | 3.50 | 3.50 | 2.93 | 4.00 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 7.33-7.36 |
Stall cycles | 0.00 |
Front-end | 7.67 |
Dispatch | 5.33 |
DIV/SQRT | 6.00 |
Overall L1 | 7.67 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 0% |
all | 7% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 7% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 8% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 7% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 403060 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 403150 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x10(%R12),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %EBX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 4061ac <advancePosition._omp_fn.0+0x2ec> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R9,1),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %EBX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4061a3 <advancePosition._omp_fn.0+0x2e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD 0x8(%R12),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %R9D,%R10 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
SAL $0x6,%R9D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R10,%R10,2),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0xccd0(%RIP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x9,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV 0x78(%RCX),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 405eee <advancePosition._omp_fn.0+0x2e> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | timestep.c:85-94 |
Module | exec |
nb instructions | 41 |
nb uops | 46 |
loop length | 141 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 7.67 cycles |
front end | 7.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.00 | 4.00 | 4.00 | 4.00 | 3.50 | 3.07 | 3.00 | 3.50 | 3.50 | 3.50 | 2.93 | 4.00 |
cycles | 3.00 | 5.33 | 4.00 | 4.00 | 3.50 | 3.07 | 3.00 | 3.50 | 3.50 | 3.50 | 2.93 | 4.00 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 7.33-7.36 |
Stall cycles | 0.00 |
Front-end | 7.67 |
Dispatch | 5.33 |
DIV/SQRT | 6.00 |
Overall L1 | 7.67 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 0% |
all | 7% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 7% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 8% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 7% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 403060 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 403150 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %EAX,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x10(%R12),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %EBX | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
CMP %EDX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 4061ac <advancePosition._omp_fn.0+0x2ec> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
IMUL %EAX,%R9D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EDX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%R9,1),%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %EBX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4061a3 <advancePosition._omp_fn.0+0x2e3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD 0x8(%R12),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R12),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVSXD %R9D,%R10 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
SAL $0x6,%R9D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R10,%R10,2),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0xccd0(%RIP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%R12),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x9,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV 0x78(%RCX),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 405eee <advancePosition._omp_fn.0+0x2e> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advancePosition._omp_fn.0– | 3.54 | 0.55 |
▼Loop 19 - timestep.c:88-94 - exec– | 1.26 | 0.15 |
○Loop 20 - timestep.c:88-94 - exec | 2.28 | 0.27 |