Function: updateLinkCells | Module: exec | Source: linkCells.c:209-385 [...] | Coverage: 0.21% |
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Function: updateLinkCells | Module: exec | Source: linkCells.c:209-385 [...] | Coverage: 0.21% |
---|
/scratch_na/users/xoserete/qaas_runs/171-322-9862/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 209 - 385 |
-------------------------------------------------------------------------------- |
209: if (iz == gridSize[2]) |
210: { |
211: iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) + |
212: (gridSize[0]+2)*(gridSize[1]+2) + (gridSize[0]+2)*(iy+1) + (ix+1); |
213: } |
214: // Halo in Z- |
215: else if (iz == -1) |
216: { |
217: iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) + |
218: (gridSize[0]+2)*(iy+1) + (ix+1); |
219: } |
220: // Halo in Y+ |
221: else if (iy == gridSize[1]) |
[...] |
227: else if (iy == -1) |
228: { |
229: iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + iz*(gridSize[0]+2) + (ix+1); |
230: } |
231: // Halo in X+ |
232: else if (ix == gridSize[0]) |
233: { |
234: iBox = boxes->nLocalBoxes + gridSize[1]*gridSize[2] + iz*gridSize[1] + iy; |
235: } |
236: // Halo in X- |
237: else if (ix == -1) |
238: { |
239: iBox = boxes->nLocalBoxes + iz*gridSize[1] + iy; |
240: } |
241: // local link celll. |
242: else |
243: { |
244: iBox = ix + gridSize[0]*iy + gridSize[0]*gridSize[1]*iz; |
245: } |
246: assert(iBox >= 0); |
247: assert(iBox < boxes->nTotalBoxes); |
[...] |
258: int nj = boxes->nAtoms[jBox]; |
259: copyAtom(boxes, atoms, iId, iBox, nj, jBox); |
260: boxes->nAtoms[jBox]++; |
261: |
262: assert(boxes->nAtoms[jBox] < MAXATOMS); |
263: |
264: boxes->nAtoms[iBox]--; |
265: int ni = boxes->nAtoms[iBox]; |
266: if (ni) copyAtom(boxes, atoms, ni, iBox, iId, iBox); |
267: |
268: if (jBox > boxes->nLocalBoxes) |
269: --atoms->nLocal; |
[...] |
288: { |
289: emptyHaloCells(boxes); |
290: |
291: for (int iBox=0; iBox<boxes->nLocalBoxes; ++iBox) |
292: { |
293: int iOff = iBox*MAXATOMS; |
294: int ii=0; |
295: while (ii < boxes->nAtoms[iBox]) |
296: { |
297: int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]); |
298: if (jBox != iBox) |
299: moveAtom(boxes, atoms, ii, iBox, jBox); |
300: else |
301: ++ii; |
302: } |
303: } |
304: } |
[...] |
327: const int iOff = MAXATOMS*iBox+iAtom; |
328: const int jOff = MAXATOMS*jBox+jAtom; |
329: atoms->gid[jOff] = atoms->gid[iOff]; |
330: atoms->iSpecies[jOff] = atoms->iSpecies[iOff]; |
331: memcpy(atoms->r[jOff], atoms->r[iOff], sizeof(real3)); |
332: memcpy(atoms->p[jOff], atoms->p[iOff], sizeof(real3)); |
333: memcpy(atoms->f[jOff], atoms->f[iOff], sizeof(real3)); |
334: memcpy(atoms->U+jOff, atoms->U+iOff, sizeof(real_t)); |
[...] |
352: int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0])); |
353: int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1])); |
[...] |
359: if (rr[0] < localMax[0]) |
360: { |
361: if (ix == gridSize[0]) ix = gridSize[0] - 1; |
362: } |
363: else |
364: ix = gridSize[0]; // assign to halo cell |
365: if (rr[1] < localMax[1]) |
[...] |
371: if (rr[2] < localMax[2]) |
[...] |
384: for (int ii=boxes->nLocalBoxes; ii<boxes->nTotalBoxes; ++ii) |
385: boxes->nAtoms[ii] = 0; |
0x40a690 PUSH %RBP |
0x40a691 MOV %RSP,%RBP |
0x40a694 PUSH %R15 |
0x40a696 PUSH %R14 |
0x40a698 PUSH %R13 |
0x40a69a PUSH %R12 |
0x40a69c PUSH %RBX |
0x40a69d SUB $0x78,%RSP |
0x40a6a1 MOV %RSI,-0x48(%RBP) |
0x40a6a5 MOV 0xc(%RDI),%R14D |
0x40a6a9 MOV %RDI,-0x40(%RBP) |
0x40a6ad MOV 0x14(%RDI),%R15D |
0x40a6b1 CMP %R15D,%R14D |
0x40a6b4 MOV %R15D,-0x38(%RBP) |
0x40a6b8 JGE 40a6e4 |
0x40a6ba MOVSXD %R14D,%RDI |
0x40a6bd SAL $0x2,%RDI |
0x40a6c1 MOV -0x40(%RBP),%RAX |
0x40a6c5 ADD 0x78(%RAX),%RDI |
0x40a6c9 MOV %R14D,%EAX |
0x40a6cc NOT %EAX |
0x40a6ce ADD %R15D,%EAX |
0x40a6d1 LEA 0x4(,%RAX,4),%RDX |
0x40a6d9 XOR %ESI,%ESI |
0x40a6db CALL 412a60 <_intel_fast_memset> |
0x40a6e0 MOV -0x38(%RBP),%R15D |
0x40a6e4 TEST %R14D,%R14D |
0x40a6e7 JLE 40aaa7 |
0x40a6ed MOV -0x40(%RBP),%RAX |
0x40a6f1 MOV 0x78(%RAX),%RAX |
0x40a6f5 LEA 0x1(%R14),%ECX |
0x40a6f9 MOV %ECX,-0x2c(%RBP) |
0x40a6fc XOR %R9D,%R9D |
0x40a6ff VPCMPEQD %XMM0,%XMM0,%XMM0 |
0x40a703 MOV %RAX,-0x58(%RBP) |
0x40a707 MOV %R14,-0xa0(%RBP) |
0x40a70e JMP 40a71c |
(82) 0x40a710 INC %R9 |
(82) 0x40a713 CMP %R14,%R9 |
(82) 0x40a716 JE 40aaa7 |
(82) 0x40a71c CMPL $0,(%RAX,%R9,4) |
(82) 0x40a721 JLE 40a710 |
(82) 0x40a723 MOVSXD %R9D,%RCX |
(82) 0x40a726 SAL $0x6,%RCX |
(82) 0x40a72a MOV %RCX,-0x88(%RBP) |
(82) 0x40a731 MOV -0x48(%RBP),%RCX |
(82) 0x40a735 MOV 0x18(%RCX),%R10 |
(82) 0x40a739 MOV -0x40(%RBP),%RAX |
(82) 0x40a73d VMOVSD 0x30(%RAX),%XMM1 |
(82) 0x40a742 MOV (%RAX),%R11D |
(82) 0x40a745 LEA -0x1(%R11),%ECX |
(82) 0x40a749 MOV %ECX,-0x64(%RBP) |
(82) 0x40a74c VMOVUPD 0x38(%RAX),%XMM2 |
(82) 0x40a751 VMOVUPD 0x20(%RAX),%XMM3 |
(82) 0x40a756 VMOVUPD 0x68(%RAX),%XMM4 |
(82) 0x40a75b MOV 0x4(%RAX),%R13 |
(82) 0x40a75f MOV -0x58(%RBP),%RAX |
(82) 0x40a763 VMOVQ %R13,%XMM5 |
(82) 0x40a768 MOV %R13,%RCX |
(82) 0x40a76b SHR $0x20,%RCX |
(82) 0x40a76f VPADDD %XMM0,%XMM5,%XMM6 |
(82) 0x40a773 MOV %RCX,-0x98(%RBP) |
(82) 0x40a77a LEA (%RCX,%RCX,1),%EDX |
(82) 0x40a77d MOV %RDX,%RCX |
(82) 0x40a780 MOV %RDX,-0x80(%RBP) |
(82) 0x40a784 IMUL %R13D,%ECX |
(82) 0x40a788 MOV %ECX,-0x34(%RBP) |
(82) 0x40a78b LEA 0x2(%R11),%ECX |
(82) 0x40a78f MOV %ECX,-0x30(%RBP) |
(82) 0x40a792 VPINSRD $0,%R14D,%XMM5,%XMM7 |
(82) 0x40a798 XOR %EBX,%EBX |
(82) 0x40a79a MOV %R11,-0x78(%RBP) |
(82) 0x40a79e MOV %R13,-0x70(%RBP) |
(82) 0x40a7a2 MOV %R9,-0x50(%RBP) |
(82) 0x40a7a6 JMP 40a7c0 |
0x40a7a8 NOPL (%RAX,%RAX,1) |
(83) 0x40a7b0 MOV -0x60(%RBP),%RBX |
(83) 0x40a7b4 INC %EBX |
(83) 0x40a7b6 CMP (%RAX,%R9,4),%EBX |
(83) 0x40a7ba JGE 40a710 |
(83) 0x40a7c0 MOV -0x88(%RBP),%RCX |
(83) 0x40a7c7 ADD %EBX,%ECX |
(83) 0x40a7c9 MOVSXD %ECX,%RCX |
(83) 0x40a7cc MOV %RCX,-0x90(%RBP) |
(83) 0x40a7d3 LEA (%RCX,%RCX,2),%R12 |
(83) 0x40a7d7 VMOVSD (%R10,%R12,8),%XMM8 |
(83) 0x40a7dd VUCOMISD %XMM8,%XMM1 |
(83) 0x40a7e2 MOV %R11D,%ECX |
(83) 0x40a7e5 JBE 40a80b |
(83) 0x40a7e7 MOV -0x40(%RBP),%RAX |
(83) 0x40a7eb VSUBSD 0x18(%RAX),%XMM8,%XMM8 |
(83) 0x40a7f0 VMULSD 0x60(%RAX),%XMM8,%XMM8 |
(83) 0x40a7f5 MOV -0x58(%RBP),%RAX |
(83) 0x40a7f9 VROUNDSD $0x9,%XMM8,%XMM8,%XMM8 |
(83) 0x40a7ff VCVTTSD2SI %XMM8,%ECX |
(83) 0x40a804 CMP %ECX,%R11D |
(83) 0x40a807 CMOVE -0x64(%RBP),%ECX |
(83) 0x40a80b VMOVUPD 0x8(%R10,%R12,8),%XMM9 |
(83) 0x40a812 VSUBPD %XMM3,%XMM9,%XMM8 |
(83) 0x40a816 VMULPD %XMM4,%XMM8,%XMM8 |
(83) 0x40a81a VROUNDPD $0x9,%XMM8,%XMM8 |
(83) 0x40a820 VCVTTPD2DQ %XMM8,%XMM8 |
(83) 0x40a825 VPCMPEQD %XMM8,%XMM5,%K1 |
(83) 0x40a82b VCMPPD $0x2,%XMM9,%XMM2,%K0 |
(83) 0x40a832 KMOVD %K0,%EDX |
(83) 0x40a836 VMOVDQA32 %XMM6,%XMM8{%K1} |
(83) 0x40a83c VMOVD %XMM8,%ESI |
(83) 0x40a840 TEST $0x1,%DL |
(83) 0x40a843 MOV %ESI,%R8D |
(83) 0x40a846 CMOVNE %R13D,%R8D |
(83) 0x40a84a TEST $0x2,%DL |
(83) 0x40a84d JE 40a870 |
(83) 0x40a84f ADD %R13D,%R8D |
(83) 0x40a852 MOV -0x80(%RBP),%RDX |
(83) 0x40a856 LEA 0x3(%RDX,%R8,1),%EDX |
(83) 0x40a85b IMUL -0x30(%RBP),%EDX |
(83) 0x40a85f ADD -0x2c(%RBP),%ECX |
(83) 0x40a862 ADD -0x34(%RBP),%ECX |
(83) 0x40a865 ADD %EDX,%ECX |
(83) 0x40a867 JMP 40a8e1 |
0x40a869 NOPL (%RAX) |
(83) 0x40a870 MOV %R15D,%EDI |
(83) 0x40a873 VPEXTRD $0x1,%XMM8,%R15D |
(83) 0x40a879 CMP $-0x1,%R15D |
(83) 0x40a87d JE 40a88d |
(83) 0x40a87f TEST $0x1,%DL |
(83) 0x40a882 JE 40a8a4 |
(83) 0x40a884 ADD -0x98(%RBP),%R15D |
(83) 0x40a88b JMP 40a8d0 |
(83) 0x40a88d MOV -0x80(%RBP),%RDX |
(83) 0x40a891 LEA 0x1(%R8,%RDX,1),%EDX |
(83) 0x40a896 IMUL -0x30(%RBP),%EDX |
(83) 0x40a89a ADD -0x2c(%RBP),%ECX |
(83) 0x40a89d ADD -0x34(%RBP),%ECX |
(83) 0x40a8a0 ADD %EDX,%ECX |
(83) 0x40a8a2 JMP 40a8de |
(83) 0x40a8a4 CMP $-0x1,%ESI |
(83) 0x40a8a7 JE 40a8d0 |
(83) 0x40a8a9 CMP %ECX,%R11D |
(83) 0x40a8ac JNE 40aa85 |
(83) 0x40a8b2 VPADDD %XMM7,%XMM8,%XMM8 |
(83) 0x40a8b6 VPEXTRD $0x1,%XMM8,%EDX |
(83) 0x40a8bc IMUL %R13D,%EDX |
(83) 0x40a8c0 VMOVD %XMM8,%ECX |
(83) 0x40a8c4 ADD %EDX,%ECX |
(83) 0x40a8c6 JMP 40a8de |
0x40a8c8 NOPL (%RAX,%RAX,1) |
(83) 0x40a8d0 IMUL -0x30(%RBP),%R15D |
(83) 0x40a8d5 ADD -0x2c(%RBP),%ECX |
(83) 0x40a8d8 ADD -0x34(%RBP),%ECX |
(83) 0x40a8db ADD %R15D,%ECX |
(83) 0x40a8de MOV %EDI,%R15D |
(83) 0x40a8e1 TEST %ECX,%ECX |
(83) 0x40a8e3 JS 40aab6 |
(83) 0x40a8e9 CMP %R15D,%ECX |
(83) 0x40a8ec JGE 40aacf |
(83) 0x40a8f2 MOV %RBX,-0x60(%RBP) |
(83) 0x40a8f6 MOV %ECX,%EBX |
(83) 0x40a8f8 CMP %RBX,%R9 |
(83) 0x40a8fb JE 40a7b0 |
(83) 0x40a901 MOVSXD (%RAX,%RBX,4),%RSI |
(83) 0x40a905 MOVSXD %ECX,%RDX |
(83) 0x40a908 SAL $0x6,%RDX |
(83) 0x40a90c ADD %RSI,%RDX |
(83) 0x40a90f MOV -0x48(%RBP),%RAX |
(83) 0x40a913 MOV 0x8(%RAX),%R14 |
(83) 0x40a917 MOV -0x90(%RBP),%R13 |
(83) 0x40a91e MOV (%R14,%R13,4),%ESI |
(83) 0x40a922 MOV %ESI,(%R14,%RDX,4) |
(83) 0x40a926 MOV 0x10(%RAX),%R11 |
(83) 0x40a92a MOV (%R11,%R13,4),%ESI |
(83) 0x40a92e MOV %ESI,(%R11,%RDX,4) |
(83) 0x40a932 LEA (%R10,%R12,8),%R12 |
(83) 0x40a936 LEA (,%RDX,8),%RSI |
(83) 0x40a93e MOV %R10,%R8 |
(83) 0x40a941 LEA (%RSI,%RSI,2),%R10 |
(83) 0x40a945 MOV 0x10(%R12),%RSI |
(83) 0x40a94a MOV %RSI,0x10(%R8,%R10,1) |
(83) 0x40a94f VMOVUPS (%R12),%XMM8 |
(83) 0x40a955 MOV %R8,%RDI |
(83) 0x40a958 VMOVUPS %XMM8,(%R8,%R10,1) |
(83) 0x40a95e MOV 0x20(%RAX),%RSI |
(83) 0x40a962 LEA (,%R13,8),%R8 |
(83) 0x40a96a LEA (%R8,%R8,2),%R15 |
(83) 0x40a96e MOV 0x10(%RSI,%R15,1),%R8 |
(83) 0x40a973 MOV %R8,0x10(%RSI,%R10,1) |
(83) 0x40a978 VMOVUPS (%RSI,%R15,1),%XMM8 |
(83) 0x40a97e VMOVUPS %XMM8,(%RSI,%R10,1) |
(83) 0x40a984 MOV 0x28(%RAX),%R8 |
(83) 0x40a988 MOV 0x10(%R8,%R15,1),%R9 |
(83) 0x40a98d MOV %R9,0x10(%R8,%R10,1) |
(83) 0x40a992 VMOVDQU (%R8,%R15,1),%XMM8 |
(83) 0x40a998 VMOVDQU %XMM8,(%R8,%R10,1) |
(83) 0x40a99e MOV 0x30(%RAX),%R10 |
(83) 0x40a9a2 MOV -0x58(%RBP),%RAX |
(83) 0x40a9a6 MOV (%R10,%R13,8),%R9 |
(83) 0x40a9aa MOV %R9,(%R10,%RDX,8) |
(83) 0x40a9ae MOV (%RAX,%RBX,4),%EDX |
(83) 0x40a9b1 LEA 0x1(%RDX),%R9D |
(83) 0x40a9b5 MOV %R9D,(%RAX,%RBX,4) |
(83) 0x40a9b9 CMP $0x3f,%EDX |
(83) 0x40a9bc JGE 40aae8 |
(83) 0x40a9c2 MOV -0x50(%RBP),%RDX |
(83) 0x40a9c6 MOVSXD (%RAX,%RDX,4),%RBX |
(83) 0x40a9ca DEC %RBX |
(83) 0x40a9cd MOV %EBX,(%RAX,%RDX,4) |
(83) 0x40a9d0 TEST %EBX,%EBX |
(83) 0x40a9d2 JE 40aa4d |
(83) 0x40a9d4 LEA (%RSI,%R15,1),%RDX |
(83) 0x40a9d8 ADD -0x88(%RBP),%RBX |
(83) 0x40a9df MOV (%R14,%RBX,4),%R9D |
(83) 0x40a9e3 MOV -0x90(%RBP),%R13 |
(83) 0x40a9ea MOV %R9D,(%R14,%R13,4) |
(83) 0x40a9ee MOV (%R11,%RBX,4),%R9D |
(83) 0x40a9f2 MOV %R9D,(%R11,%R13,4) |
(83) 0x40a9f6 ADD %R8,%R15 |
(83) 0x40a9f9 LEA (,%RBX,8),%R9 |
(83) 0x40aa01 LEA (%R9,%R9,2),%R9 |
(83) 0x40aa05 MOV %RDI,%R14 |
(83) 0x40aa08 MOV 0x10(%RDI,%R9,1),%R11 |
(83) 0x40aa0d MOV %R11,0x10(%R12) |
(83) 0x40aa12 VMOVUPS (%RDI,%R9,1),%XMM8 |
(83) 0x40aa18 VMOVUPS %XMM8,(%R12) |
(83) 0x40aa1e MOV 0x10(%RSI,%R9,1),%R11 |
(83) 0x40aa23 MOV %R11,0x10(%RDX) |
(83) 0x40aa27 VMOVUPS (%RSI,%R9,1),%XMM8 |
(83) 0x40aa2d VMOVUPS %XMM8,(%RDX) |
(83) 0x40aa31 MOV 0x10(%R8,%R9,1),%RDX |
(83) 0x40aa36 MOV %RDX,0x10(%R15) |
(83) 0x40aa3a VMOVDQU (%R8,%R9,1),%XMM8 |
(83) 0x40aa40 VMOVDQU %XMM8,(%R15) |
(83) 0x40aa45 MOV (%R10,%RBX,8),%RDX |
(83) 0x40aa49 MOV %RDX,(%R10,%R13,8) |
(83) 0x40aa4d MOV -0xa0(%RBP),%R14 |
(83) 0x40aa54 CMP %ECX,%R14D |
(83) 0x40aa57 JGE 40aa5f |
(83) 0x40aa59 MOV -0x48(%RBP),%RCX |
(83) 0x40aa5d DECL (%RCX) |
(83) 0x40aa5f MOV -0x38(%RBP),%R15D |
(83) 0x40aa63 MOV -0x50(%RBP),%R9 |
(83) 0x40aa67 MOV %RDI,%R10 |
(83) 0x40aa6a MOV -0x78(%RBP),%R11 |
(83) 0x40aa6e MOV -0x70(%RBP),%R13 |
(83) 0x40aa72 MOV -0x60(%RBP),%RBX |
(83) 0x40aa76 CMP (%RAX,%R9,4),%EBX |
(83) 0x40aa7a JL 40a7c0 |
(82) 0x40aa80 JMP 40a710 |
(83) 0x40aa85 IMUL %R13D,%R15D |
(83) 0x40aa89 CMP $-0x1,%ECX |
(83) 0x40aa8c JE 40aa9a |
(83) 0x40aa8e ADD %ESI,%R15D |
(83) 0x40aa91 IMUL %R11D,%R15D |
(83) 0x40aa95 JMP 40a8db |
(83) 0x40aa9a ADD %R14D,%ESI |
(83) 0x40aa9d ADD %R15D,%ESI |
(83) 0x40aaa0 MOV %ESI,%ECX |
(83) 0x40aaa2 JMP 40a8de |
0x40aaa7 ADD $0x78,%RSP |
0x40aaab POP %RBX |
0x40aaac POP %R12 |
0x40aaae POP %R13 |
0x40aab0 POP %R14 |
0x40aab2 POP %R15 |
0x40aab4 POP %RBP |
0x40aab5 RET |
0x40aab6 MOV $0x422e02,%EDI |
0x40aabb MOV $0x422d23,%ESI |
0x40aac0 MOV $0x422e0c,%ECX |
0x40aac5 MOV $0xf6,%EDX |
0x40aaca CALL 402bd0 <__assert_fail@plt> |
0x40aacf MOV $0x422e3b,%EDI |
0x40aad4 MOV $0x422d23,%ESI |
0x40aad9 MOV $0x422e0c,%ECX |
0x40aade MOV $0xf7,%EDX |
0x40aae3 CALL 402bd0 <__assert_fail@plt> |
0x40aae8 MOV $0x422e55,%EDI |
0x40aaed MOV $0x422d23,%ESI |
0x40aaf2 MOV $0x422e74,%ECX |
0x40aaf7 MOV $0x106,%EDX |
0x40aafc CALL 402bd0 <__assert_fail@plt> |
0x40ab01 NOPW %CS:(%RAX,%RAX,1) |
Path / |
Source file and lines | linkCells.c:209-385 |
Module | exec |
nb instructions | 64 |
nb uops | 68 |
loop length | 256 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 11.33 cycles |
front end | 11.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.80 | 4.80 | 4.67 | 4.67 | 8.00 | 4.87 | 4.80 | 8.00 | 8.00 | 8.00 | 4.73 | 4.67 |
cycles | 4.80 | 4.80 | 4.67 | 4.67 | 8.00 | 4.87 | 4.80 | 8.00 | 8.00 | 8.00 | 4.73 | 4.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 10.80 |
Stall cycles | 0.00 |
Front-end | 11.33 |
Dispatch | 8.00 |
Overall L1 | 11.33 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 7% |
all | 8% |
load | 6% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 7% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x78,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc(%RDI),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x14(%RDI),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %R15D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15D,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JGE 40a6e4 <updateLinkCells+0x54> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD %R14D,%RDI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
SAL $0x2,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV -0x40(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD 0x78(%RAX),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOT %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x4(,%RAX,4),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 412a60 <_intel_fast_memset> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x38(%RBP),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R14D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 40aaa7 <updateLinkCells+0x417> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x40(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%R14),%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ECX,-0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R9D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPCMPEQD %XMM0,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
MOV %RAX,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,-0xa0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 40a71c <updateLinkCells+0x8c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x78,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
MOV $0x422e02,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x422d23,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x422e0c,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0xf6,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 402bd0 <__assert_fail@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x422e3b,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x422d23,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x422e0c,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0xf7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 402bd0 <__assert_fail@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x422e55,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x422d23,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x422e74,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x106,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 402bd0 <__assert_fail@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | linkCells.c:209-385 |
Module | exec |
nb instructions | 64 |
nb uops | 68 |
loop length | 256 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 11.33 cycles |
front end | 11.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.80 | 4.80 | 4.67 | 4.67 | 8.00 | 4.87 | 4.80 | 8.00 | 8.00 | 8.00 | 4.73 | 4.67 |
cycles | 4.80 | 4.80 | 4.67 | 4.67 | 8.00 | 4.87 | 4.80 | 8.00 | 8.00 | 8.00 | 4.73 | 4.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 10.80 |
Stall cycles | 0.00 |
Front-end | 11.33 |
Dispatch | 8.00 |
Overall L1 | 11.33 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 7% |
all | 8% |
load | 6% |
store | 10% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 7% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x78,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc(%RDI),%R14D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x14(%RDI),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %R15D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R15D,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JGE 40a6e4 <updateLinkCells+0x54> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVSXD %R14D,%RDI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
SAL $0x2,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV -0x40(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD 0x78(%RAX),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %R14D,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOT %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R15D,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x4(,%RAX,4),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 412a60 <_intel_fast_memset> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV -0x38(%RBP),%R15D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R14D,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 40aaa7 <updateLinkCells+0x417> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x40(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%R14),%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOV %ECX,-0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R9D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPCMPEQD %XMM0,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
MOV %RAX,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,-0xa0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 40a71c <updateLinkCells+0x8c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x78,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
MOV $0x422e02,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x422d23,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x422e0c,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0xf6,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 402bd0 <__assert_fail@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x422e3b,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x422d23,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x422e0c,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0xf7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 402bd0 <__assert_fail@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x422e55,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x422d23,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x422e74,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x106,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 402bd0 <__assert_fail@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼updateLinkCells– | 0.21 | 0.06 |
▼Loop 82 - linkCells.c:209-371 - exec– | 0 | 0.05 |
○Loop 83 - linkCells.c:209-371 - exec | 0.21 | 3.05 |