Function: setTemperature.extracted.30 | Module: exec | Source: initAtoms.c:151-164 [...] | Coverage: 0.02% |
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Function: setTemperature.extracted.30 | Module: exec | Source: initAtoms.c:151-164 [...] | Coverage: 0.02% |
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/scratch_na/users/xoserete/qaas_runs/171-322-9862/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c: 27 - 70 |
-------------------------------------------------------------------------------- |
27: v2 = 2.0*lcg61(seed)-1.0; |
28: rsq = v1*v1+v2*v2; |
29: } while (rsq >= 1.0 || rsq == 0.0); |
30: |
31: return v2 * sqrt(-2.0*log(rsq)/rsq); |
[...] |
45: *seed *= UINT64_C(437799614237992725); |
46: *seed %= UINT64_C(2305843009213693951); |
47: |
48: return *seed*convertToDouble; |
[...] |
70: uint64_t iSeed = (UINT64_C(0x100000000) * s1) + s2; |
/scratch_na/users/xoserete/qaas_runs/171-322-9862/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 151 - 164 |
-------------------------------------------------------------------------------- |
151: #pragma omp parallel for |
152: for (int iBox=0; iBox<s->boxes->nLocalBoxes; ++iBox) |
153: { |
154: for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff) |
155: { |
156: int iType = s->atoms->iSpecies[iOff]; |
157: real_t mass = s->species[iType].mass; |
158: real_t sigma = sqrt(kB_eV * temperature/mass); |
159: uint64_t seed = mkSeed(s->atoms->gid[iOff], 123); |
160: s->atoms->p[iOff][0] = mass * sigma * gasdev(&seed); |
161: s->atoms->p[iOff][1] = mass * sigma * gasdev(&seed); |
162: s->atoms->p[iOff][2] = mass * sigma * gasdev(&seed); |
163: } |
164: } |
0x409bb0 PUSH %RBP |
0x409bb1 MOV %RSP,%RBP |
0x409bb4 PUSH %R15 |
0x409bb6 PUSH %R14 |
0x409bb8 PUSH %R13 |
0x409bba PUSH %R12 |
0x409bbc PUSH %RBX |
0x409bbd SUB $0x98,%RSP |
0x409bc4 MOV %RCX,%R15 |
0x409bc7 MOV %RDX,-0x88(%RBP) |
0x409bce MOVL $0,-0x5c(%RBP) |
0x409bd5 MOV (%RDI),%ESI |
0x409bd7 MOVL $0,-0x34(%RBP) |
0x409bde MOV %R9D,-0x30(%RBP) |
0x409be2 MOVL $0x1,-0x58(%RBP) |
0x409be9 SUB $0x8,%RSP |
0x409bed LEA -0x58(%RBP),%RAX |
0x409bf1 LEA -0x5c(%RBP),%RCX |
0x409bf5 LEA -0x34(%RBP),%R8 |
0x409bf9 LEA -0x30(%RBP),%R9 |
0x409bfd MOV $0x62e690,%EDI |
0x409c02 MOV %ESI,-0x4c(%RBP) |
0x409c05 MOV $0x22,%EDX |
0x409c0a PUSH $0x1 |
0x409c0c PUSH $0x1 |
0x409c0e PUSH %RAX |
0x409c0f CALL 403130 <__kmpc_for_static_init_4@plt> |
0x409c14 ADD $0x20,%RSP |
0x409c18 MOV -0x34(%RBP),%ECX |
0x409c1b MOV -0x30(%RBP),%EAX |
0x409c1e MOV %RAX,-0x90(%RBP) |
0x409c25 CMP %EAX,%ECX |
0x409c27 JBE 409c47 |
0x409c29 MOV $0x62e6b0,%EDI |
0x409c2e MOV -0x4c(%RBP),%ESI |
0x409c31 ADD $0x98,%RSP |
0x409c38 POP %RBX |
0x409c39 POP %R12 |
0x409c3b POP %R13 |
0x409c3d POP %R14 |
0x409c3f POP %R15 |
0x409c41 POP %RBP |
0x409c42 JMP 402fe0 |
0x409c47 MOV $0x613606df9756715,%R14 |
0x409c51 VMOVQ %R15,%XMM0 |
0x409c56 VMULSD 0x1922a(%RIP),%XMM0,%XMM0 |
0x409c5e VMOVSD %XMM0,-0xa8(%RBP) |
0x409c66 MOV %ECX,%EAX |
0x409c68 SAL $0x6,%EAX |
0x409c6b MOV %EAX,-0x2c(%RBP) |
0x409c6e INCQ -0x90(%RBP) |
0x409c75 MOV -0x88(%RBP),%RAX |
0x409c7c MOV 0x18(%RAX),%RAX |
0x409c80 MOV 0x78(%RAX),%RAX |
0x409c84 MOV %RAX,-0x98(%RBP) |
0x409c8b MOV $0x9,%EBX |
0x409c90 VMOVDDUP 0x19200(%RIP),%XMM4 |
0x409c98 VMOVDDUP 0x1dee0(%RIP),%XMM5 |
0x409ca0 VMOVSD 0x1dee0(%RIP),%XMM6 |
0x409ca8 VXORPD %XMM7,%XMM7,%XMM7 |
0x409cac JMP 409ccb |
0x409cae XCHG %AX,%AX |
(70) 0x409cb0 MOV -0xa0(%RBP),%RCX |
(70) 0x409cb7 INC %RCX |
(70) 0x409cba ADDL $0x40,-0x2c(%RBP) |
(70) 0x409cbe CMP -0x90(%RBP),%RCX |
(70) 0x409cc5 JE 409c29 |
(70) 0x409ccb MOV %RCX,-0xa0(%RBP) |
(70) 0x409cd2 MOV -0x98(%RBP),%RAX |
(70) 0x409cd9 MOV (%RAX,%RCX,4),%EAX |
(70) 0x409cdc MOV %EAX,-0x50(%RBP) |
(70) 0x409cdf TEST %EAX,%EAX |
(70) 0x409ce1 JLE 409cb0 |
(70) 0x409ce3 MOV -0x2c(%RBP),%R12D |
(70) 0x409ce7 MOV -0x88(%RBP),%RCX |
(70) 0x409cee MOV 0x20(%RCX),%RAX |
(70) 0x409cf2 MOV 0x28(%RCX),%RCX |
(70) 0x409cf6 MOV %RCX,-0xc0(%RBP) |
(70) 0x409cfd MOV 0x20(%RAX),%RCX |
(70) 0x409d01 MOV %RCX,-0x40(%RBP) |
(70) 0x409d05 MOV 0x8(%RAX),%RCX |
(70) 0x409d09 MOV %RCX,-0xb8(%RBP) |
(70) 0x409d10 MOV 0x10(%RAX),%RAX |
(70) 0x409d14 MOV %RAX,-0xb0(%RBP) |
(70) 0x409d1b XOR %EAX,%EAX |
(70) 0x409d1d NOPL (%RAX) |
(74) 0x409d20 MOV %EAX,-0x54(%RBP) |
(74) 0x409d23 MOV -0xb0(%RBP),%RAX |
(74) 0x409d2a MOVSXD (%RAX,%R12,4),%RAX |
(74) 0x409d2e SAL $0x4,%RAX |
(74) 0x409d32 MOV -0xc0(%RBP),%RCX |
(74) 0x409d39 VMOVSD 0x8(%RCX,%RAX,1),%XMM9 |
(74) 0x409d3f VMOVSD -0xa8(%RBP),%XMM1 |
(74) 0x409d47 VDIVSD %XMM9,%XMM1,%XMM1 |
(74) 0x409d4c MOV -0xb8(%RBP),%RAX |
(74) 0x409d53 IMUL $-0x61c8864f,(%RAX,%R12,4),%EAX |
(74) 0x409d5b LEA 0x4a7780b(%RAX),%ECX |
(74) 0x409d61 SAL $0x20,%RAX |
(74) 0x409d65 OR %RCX,%RAX |
(74) 0x409d68 IMUL %R14,%RAX |
(74) 0x409d6c MOV %RAX,%RDX |
(74) 0x409d6f MULX %RBX,%RCX,%RCX |
(74) 0x409d74 SUB %RCX,%RDX |
(74) 0x409d77 SHR $0x1,%RDX |
(74) 0x409d7a ADD %RCX,%RDX |
(74) 0x409d7d SHR $0x3c,%RDX |
(74) 0x409d81 MOV %RDX,%RCX |
(74) 0x409d84 SAL $0x3d,%RCX |
(74) 0x409d88 SUB %RCX,%RDX |
(74) 0x409d8b ADD %RAX,%RDX |
(74) 0x409d8e IMUL %R14,%RDX |
(74) 0x409d92 MULX %RBX,%RCX,%RCX |
(74) 0x409d97 MOV %RDX,%RAX |
(74) 0x409d9a SUB %RCX,%RAX |
(74) 0x409d9d SHR $0x1,%RAX |
(74) 0x409da0 ADD %RCX,%RAX |
(74) 0x409da3 SHR $0x3c,%RAX |
(74) 0x409da7 MOV %RAX,%RCX |
(74) 0x409daa SAL $0x3d,%RCX |
(74) 0x409dae SUB %RCX,%RAX |
(74) 0x409db1 ADD %RDX,%RAX |
(74) 0x409db4 IMUL %R14,%RAX |
(74) 0x409db8 MOV %RAX,%RDX |
(74) 0x409dbb MULX %RBX,%RCX,%RCX |
(74) 0x409dc0 SUB %RCX,%RDX |
(74) 0x409dc3 SHR $0x1,%RDX |
(74) 0x409dc6 ADD %RCX,%RDX |
(74) 0x409dc9 SHR $0x3c,%RDX |
(74) 0x409dcd MOV %RDX,%RCX |
(74) 0x409dd0 SAL $0x3d,%RCX |
(74) 0x409dd4 SUB %RCX,%RDX |
(74) 0x409dd7 ADD %RAX,%RDX |
(74) 0x409dda IMUL %R14,%RDX |
(74) 0x409dde MULX %RBX,%RCX,%RCX |
(74) 0x409de3 MOV %RDX,%RAX |
(74) 0x409de6 SUB %RCX,%RAX |
(74) 0x409de9 SHR $0x1,%RAX |
(74) 0x409dec ADD %RCX,%RAX |
(74) 0x409def SHR $0x3c,%RAX |
(74) 0x409df3 MOV %RAX,%RCX |
(74) 0x409df6 SAL $0x3d,%RCX |
(74) 0x409dfa SUB %RCX,%RAX |
(74) 0x409dfd ADD %RDX,%RAX |
(74) 0x409e00 IMUL %R14,%RAX |
(74) 0x409e04 MOV %RAX,%RDX |
(74) 0x409e07 MULX %RBX,%RCX,%RCX |
(74) 0x409e0c SUB %RCX,%RDX |
(74) 0x409e0f SHR $0x1,%RDX |
(74) 0x409e12 ADD %RCX,%RDX |
(74) 0x409e15 SHR $0x3c,%RDX |
(74) 0x409e19 MOV %RDX,%RCX |
(74) 0x409e1c SAL $0x3d,%RCX |
(74) 0x409e20 SUB %RCX,%RDX |
(74) 0x409e23 ADD %RAX,%RDX |
(74) 0x409e26 IMUL %R14,%RDX |
(74) 0x409e2a MULX %RBX,%RCX,%RCX |
(74) 0x409e2f MOV %RDX,%RAX |
(74) 0x409e32 SUB %RCX,%RAX |
(74) 0x409e35 SHR $0x1,%RAX |
(74) 0x409e38 ADD %RCX,%RAX |
(74) 0x409e3b SHR $0x3c,%RAX |
(74) 0x409e3f MOV %RAX,%RCX |
(74) 0x409e42 SAL $0x3d,%RCX |
(74) 0x409e46 SUB %RCX,%RAX |
(74) 0x409e49 ADD %RDX,%RAX |
(74) 0x409e4c IMUL %R14,%RAX |
(74) 0x409e50 MOV %RAX,%RDX |
(74) 0x409e53 MULX %RBX,%RCX,%RCX |
(74) 0x409e58 SUB %RCX,%RDX |
(74) 0x409e5b SHR $0x1,%RDX |
(74) 0x409e5e ADD %RCX,%RDX |
(74) 0x409e61 SHR $0x3c,%RDX |
(74) 0x409e65 MOV %RDX,%RCX |
(74) 0x409e68 SAL $0x3d,%RCX |
(74) 0x409e6c SUB %RCX,%RDX |
(74) 0x409e6f ADD %RAX,%RDX |
(74) 0x409e72 IMUL %R14,%RDX |
(74) 0x409e76 MULX %RBX,%RCX,%RCX |
(74) 0x409e7b MOV %RDX,%RAX |
(74) 0x409e7e SUB %RCX,%RAX |
(74) 0x409e81 SHR $0x1,%RAX |
(74) 0x409e84 ADD %RCX,%RAX |
(74) 0x409e87 SHR $0x3c,%RAX |
(74) 0x409e8b MOV %RAX,%RCX |
(74) 0x409e8e SAL $0x3d,%RCX |
(74) 0x409e92 SUB %RCX,%RAX |
(74) 0x409e95 ADD %RDX,%RAX |
(74) 0x409e98 IMUL %R14,%RAX |
(74) 0x409e9c MOV %RAX,%RDX |
(74) 0x409e9f MULX %RBX,%RCX,%RCX |
(74) 0x409ea4 SUB %RCX,%RDX |
(74) 0x409ea7 SHR $0x1,%RDX |
(74) 0x409eaa ADD %RCX,%RDX |
(74) 0x409ead SHR $0x3c,%RDX |
(74) 0x409eb1 MOV %RDX,%RCX |
(74) 0x409eb4 SAL $0x3d,%RCX |
(74) 0x409eb8 SUB %RCX,%RDX |
(74) 0x409ebb ADD %RAX,%RDX |
(74) 0x409ebe IMUL %R14,%RDX |
(74) 0x409ec2 MULX %RBX,%RAX,%RAX |
(74) 0x409ec7 VSQRTSD %XMM1,%XMM1,%XMM1 |
(74) 0x409ecb MOV %RDX,%R15 |
(74) 0x409ece SUB %RAX,%R15 |
(74) 0x409ed1 SHR $0x1,%R15 |
(74) 0x409ed4 ADD %RAX,%R15 |
(74) 0x409ed7 SHR $0x3c,%R15 |
(74) 0x409edb MOV %R15,%RAX |
(74) 0x409ede SAL $0x3d,%RAX |
(74) 0x409ee2 SUB %RAX,%R15 |
(74) 0x409ee5 ADD %RDX,%R15 |
(74) 0x409ee8 NOPL (%RAX,%RAX,1) |
(71) 0x409ef0 IMUL %R14,%R15 |
(71) 0x409ef4 MOV %R15,%RDX |
(71) 0x409ef7 MULX %RBX,%RAX,%RAX |
(71) 0x409efc SUB %RAX,%RDX |
(71) 0x409eff SHR $0x1,%RDX |
(71) 0x409f02 ADD %RAX,%RDX |
(71) 0x409f05 SHR $0x3c,%RDX |
(71) 0x409f09 MOV %RDX,%RAX |
(71) 0x409f0c SAL $0x3d,%RAX |
(71) 0x409f10 SUB %RAX,%RDX |
(71) 0x409f13 ADD %R15,%RDX |
(71) 0x409f16 VCVTSI2SD %RDX,%XMM4,%XMM2 |
(71) 0x409f1b IMUL %R14,%RDX |
(71) 0x409f1f MULX %RBX,%RAX,%RAX |
(71) 0x409f24 MOV %RDX,%R15 |
(71) 0x409f27 SUB %RAX,%R15 |
(71) 0x409f2a SHR $0x1,%R15 |
(71) 0x409f2d ADD %RAX,%R15 |
(71) 0x409f30 SHR $0x3c,%R15 |
(71) 0x409f34 MOV %R15,%RAX |
(71) 0x409f37 SAL $0x3d,%RAX |
(71) 0x409f3b SUB %RAX,%R15 |
(71) 0x409f3e ADD %RDX,%R15 |
(71) 0x409f41 VCVTSI2SD %R15,%XMM4,%XMM3 |
(71) 0x409f46 VUNPCKLPD %XMM2,%XMM3,%XMM8 |
(71) 0x409f4a VFMADD213PD %XMM5,%XMM4,%XMM8 |
(71) 0x409f4f VMULPD %XMM8,%XMM8,%XMM2 |
(71) 0x409f54 VSHUFPD $0x1,%XMM2,%XMM2,%XMM3 |
(71) 0x409f59 VADDSD %XMM3,%XMM2,%XMM0 |
(71) 0x409f5d VUCOMISD %XMM6,%XMM0 |
(71) 0x409f61 JAE 409ef0 |
(71) 0x409f63 VUCOMISD %XMM7,%XMM0 |
(71) 0x409f67 JE 409ef0 |
(74) 0x409f69 VMULSD %XMM1,%XMM9,%XMM1 |
(74) 0x409f6d VMOVSD %XMM1,-0x48(%RBP) |
(74) 0x409f72 VMOVUPD %XMM8,-0x80(%RBP) |
(74) 0x409f77 VMOVSD %XMM0,-0x70(%RBP) |
(74) 0x409f7c CALL 410ab0 <log> |
(74) 0x409f81 VXORPD %XMM5,%XMM5,%XMM5 |
(74) 0x409f85 VMOVSD 0x1dbfb(%RIP),%XMM4 |
(74) 0x409f8d VMOVDDUP 0x1dbeb(%RIP),%XMM3 |
(74) 0x409f95 VMOVDDUP 0x18efb(%RIP),%XMM2 |
(74) 0x409f9d VMULSD 0x18eeb(%RIP),%XMM0,%XMM0 |
(74) 0x409fa5 VDIVSD -0x70(%RBP),%XMM0,%XMM0 |
(74) 0x409faa VSQRTSD %XMM0,%XMM0,%XMM0 |
(74) 0x409fae VMOVUPD -0x80(%RBP),%XMM1 |
(74) 0x409fb3 VMULSD -0x48(%RBP),%XMM1,%XMM1 |
(74) 0x409fb8 VMULSD %XMM1,%XMM0,%XMM0 |
(74) 0x409fbc LEA (%R12,%R12,2),%R13 |
(74) 0x409fc0 MOV -0x40(%RBP),%RAX |
(74) 0x409fc4 VMOVSD %XMM0,(%RAX,%R13,8) |
(74) 0x409fca NOPW (%RAX,%RAX,1) |
(72) 0x409fd0 IMUL %R14,%R15 |
(72) 0x409fd4 MOV %R15,%RDX |
(72) 0x409fd7 MULX %RBX,%RAX,%RAX |
(72) 0x409fdc SUB %RAX,%RDX |
(72) 0x409fdf SHR $0x1,%RDX |
(72) 0x409fe2 ADD %RAX,%RDX |
(72) 0x409fe5 SHR $0x3c,%RDX |
(72) 0x409fe9 MOV %RDX,%RAX |
(72) 0x409fec SAL $0x3d,%RAX |
(72) 0x409ff0 SUB %RAX,%RDX |
(72) 0x409ff3 ADD %R15,%RDX |
(72) 0x409ff6 VCVTSI2SD %RDX,%XMM7,%XMM0 |
(72) 0x409ffb IMUL %R14,%RDX |
(72) 0x409fff MULX %RBX,%RAX,%RAX |
(72) 0x40a004 MOV %RDX,%R15 |
(72) 0x40a007 SUB %RAX,%R15 |
(72) 0x40a00a SHR $0x1,%R15 |
(72) 0x40a00d ADD %RAX,%R15 |
(72) 0x40a010 SHR $0x3c,%R15 |
(72) 0x40a014 MOV %R15,%RAX |
(72) 0x40a017 SAL $0x3d,%RAX |
(72) 0x40a01b SUB %RAX,%R15 |
(72) 0x40a01e ADD %RDX,%R15 |
(72) 0x40a021 VCVTSI2SD %R15,%XMM7,%XMM1 |
(72) 0x40a026 VUNPCKLPD %XMM0,%XMM1,%XMM6 |
(72) 0x40a02a VFMADD213PD %XMM3,%XMM2,%XMM6 |
(72) 0x40a02f VMULPD %XMM6,%XMM6,%XMM0 |
(72) 0x40a033 VSHUFPD $0x1,%XMM0,%XMM0,%XMM1 |
(72) 0x40a038 VADDSD %XMM1,%XMM0,%XMM0 |
(72) 0x40a03c VUCOMISD %XMM4,%XMM0 |
(72) 0x40a040 JAE 409fd0 |
(72) 0x40a042 VUCOMISD %XMM5,%XMM0 |
(72) 0x40a046 JE 409fd0 |
(74) 0x40a048 VMOVSD %XMM0,-0x80(%RBP) |
(74) 0x40a04d VMOVUPD %XMM6,-0x70(%RBP) |
(74) 0x40a052 CALL 410ab0 <log> |
(74) 0x40a057 VXORPD %XMM5,%XMM5,%XMM5 |
(74) 0x40a05b VMOVSD 0x1db25(%RIP),%XMM4 |
(74) 0x40a063 VMOVDDUP 0x1db15(%RIP),%XMM3 |
(74) 0x40a06b VMOVDDUP 0x18e25(%RIP),%XMM2 |
(74) 0x40a073 VMULSD 0x18e15(%RIP),%XMM0,%XMM0 |
(74) 0x40a07b VDIVSD -0x80(%RBP),%XMM0,%XMM0 |
(74) 0x40a080 VSQRTSD %XMM0,%XMM0,%XMM0 |
(74) 0x40a084 VMOVUPD -0x70(%RBP),%XMM1 |
(74) 0x40a089 VMULSD -0x48(%RBP),%XMM1,%XMM1 |
(74) 0x40a08e VMULSD %XMM1,%XMM0,%XMM0 |
(74) 0x40a092 MOV -0x40(%RBP),%RAX |
(74) 0x40a096 VMOVSD %XMM0,0x8(%RAX,%R13,8) |
(74) 0x40a09d NOPL (%RAX) |
(73) 0x40a0a0 IMUL %R14,%R15 |
(73) 0x40a0a4 MOV %R15,%RDX |
(73) 0x40a0a7 MULX %RBX,%RAX,%RAX |
(73) 0x40a0ac SUB %RAX,%RDX |
(73) 0x40a0af SHR $0x1,%RDX |
(73) 0x40a0b2 ADD %RAX,%RDX |
(73) 0x40a0b5 SHR $0x3c,%RDX |
(73) 0x40a0b9 MOV %RDX,%RAX |
(73) 0x40a0bc SAL $0x3d,%RAX |
(73) 0x40a0c0 SUB %RAX,%RDX |
(73) 0x40a0c3 ADD %R15,%RDX |
(73) 0x40a0c6 VCVTSI2SD %RDX,%XMM7,%XMM0 |
(73) 0x40a0cb IMUL %R14,%RDX |
(73) 0x40a0cf MULX %RBX,%RAX,%RAX |
(73) 0x40a0d4 MOV %RDX,%R15 |
(73) 0x40a0d7 SUB %RAX,%R15 |
(73) 0x40a0da SHR $0x1,%R15 |
(73) 0x40a0dd ADD %RAX,%R15 |
(73) 0x40a0e0 SHR $0x3c,%R15 |
(73) 0x40a0e4 MOV %R15,%RAX |
(73) 0x40a0e7 SAL $0x3d,%RAX |
(73) 0x40a0eb SUB %RAX,%R15 |
(73) 0x40a0ee ADD %RDX,%R15 |
(73) 0x40a0f1 VCVTSI2SD %R15,%XMM7,%XMM1 |
(73) 0x40a0f6 VUNPCKLPD %XMM0,%XMM1,%XMM6 |
(73) 0x40a0fa VFMADD213PD %XMM3,%XMM2,%XMM6 |
(73) 0x40a0ff VMULPD %XMM6,%XMM6,%XMM0 |
(73) 0x40a103 VSHUFPD $0x1,%XMM0,%XMM0,%XMM1 |
(73) 0x40a108 VADDSD %XMM1,%XMM0,%XMM0 |
(73) 0x40a10c VUCOMISD %XMM4,%XMM0 |
(73) 0x40a110 JAE 40a0a0 |
(73) 0x40a112 VUCOMISD %XMM5,%XMM0 |
(73) 0x40a116 JE 40a0a0 |
(74) 0x40a118 VMOVSD %XMM0,-0x80(%RBP) |
(74) 0x40a11d VMOVUPD %XMM6,-0x70(%RBP) |
(74) 0x40a122 CALL 410ab0 <log> |
(74) 0x40a127 VXORPD %XMM7,%XMM7,%XMM7 |
(74) 0x40a12b VMOVSD 0x1da55(%RIP),%XMM6 |
(74) 0x40a133 VMOVDDUP 0x1da45(%RIP),%XMM5 |
(74) 0x40a13b VMOVDDUP 0x18d55(%RIP),%XMM4 |
(74) 0x40a143 VMULSD 0x18d45(%RIP),%XMM0,%XMM0 |
(74) 0x40a14b VDIVSD -0x80(%RBP),%XMM0,%XMM0 |
(74) 0x40a150 VSQRTSD %XMM0,%XMM0,%XMM0 |
(74) 0x40a154 VMOVUPD -0x70(%RBP),%XMM1 |
(74) 0x40a159 VMULSD -0x48(%RBP),%XMM1,%XMM1 |
(74) 0x40a15e VMULSD %XMM1,%XMM0,%XMM0 |
(74) 0x40a162 MOV -0x40(%RBP),%RAX |
(74) 0x40a166 VMOVSD %XMM0,0x10(%RAX,%R13,8) |
(74) 0x40a16d MOV -0x54(%RBP),%EAX |
(74) 0x40a170 INC %EAX |
(74) 0x40a172 INC %R12 |
(74) 0x40a175 CMP -0x50(%RBP),%EAX |
(74) 0x40a178 JNE 409d20 |
(70) 0x40a17e JMP 409cb0 |
0x40a183 NOPW %CS:(%RAX,%RAX,1) |
0x40a18d NOPL (%RAX) |
Path / |
Source file and lines | initAtoms.c:151-164 |
Module | exec |
nb instructions | 64 |
nb uops | 67 |
loop length | 269 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 5 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 11.17 cycles |
front end | 11.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 2.70 | 6.00 | 6.00 | 10.50 | 2.60 | 2.60 | 10.50 | 10.50 | 10.50 | 2.60 | 6.00 |
cycles | 2.50 | 2.70 | 6.00 | 6.00 | 10.50 | 2.60 | 2.60 | 10.50 | 10.50 | 10.50 | 2.60 | 6.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 11.21-11.25 |
Stall cycles | 0.00 |
Front-end | 11.17 |
Dispatch | 10.50 |
Overall L1 | 11.17 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 16% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 3% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 14% |
all | 9% |
load | 6% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 14% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 10% |
load | 9% |
store | 8% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x98,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,-0x88(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0,-0x5c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,-0x34(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9D,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x58(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x5c(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x34(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x30(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x62e690,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,-0x4c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 403130 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x34(%RBP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x30(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x90(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EAX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 409c47 <setTemperature.extracted.30+0x97> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x62e6b0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x4c(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x98,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 402fe0 <__kmpc_for_static_fini@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV $0x613606df9756715,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
VMOVQ %R15,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VMULSD 0x1922a(%RIP),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM0,-0xa8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x6,%EAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %EAX,-0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INCQ -0x90(%RBP) | 3 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV -0x88(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x98(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x9,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVDDUP 0x19200(%RIP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVDDUP 0x1dee0(%RIP),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x1dee0(%RIP),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM7,%XMM7,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 409ccb <setTemperature.extracted.30+0x11b> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | initAtoms.c:151-164 |
Module | exec |
nb instructions | 64 |
nb uops | 67 |
loop length | 269 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 5 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 10 |
micro-operation queue | 11.17 cycles |
front end | 11.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 2.70 | 6.00 | 6.00 | 10.50 | 2.60 | 2.60 | 10.50 | 10.50 | 10.50 | 2.60 | 6.00 |
cycles | 2.50 | 2.70 | 6.00 | 6.00 | 10.50 | 2.60 | 2.60 | 10.50 | 10.50 | 10.50 | 2.60 | 6.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 11.21-11.25 |
Stall cycles | 0.00 |
Front-end | 11.17 |
Dispatch | 10.50 |
Overall L1 | 11.17 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 16% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 3% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 14% |
all | 9% |
load | 6% |
store | 8% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 14% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 10% |
load | 9% |
store | 8% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x98,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,-0x88(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0,-0x5c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,-0x34(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9D,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x58(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x5c(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x34(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x30(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x62e690,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,-0x4c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 403130 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x34(%RBP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x30(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x90(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %EAX,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 409c47 <setTemperature.extracted.30+0x97> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x62e6b0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x4c(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x98,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 402fe0 <__kmpc_for_static_fini@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV $0x613606df9756715,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
VMOVQ %R15,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
VMULSD 0x1922a(%RIP),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM0,-0xa8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ECX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x6,%EAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %EAX,-0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INCQ -0x90(%RBP) | 3 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV -0x88(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,-0x98(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x9,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVDDUP 0x19200(%RIP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVDDUP 0x1dee0(%RIP),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x1dee0(%RIP),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM7,%XMM7,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 409ccb <setTemperature.extracted.30+0x11b> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼setTemperature.extracted.30– | 0.02 | 0 |
▼Loop 70 - initAtoms.c:152-164 - exec– | 0 | 0 |
▼Loop 74 - initAtoms.c:154-162 - exec– | 0.01 | 0 |
○Loop 71 - random.c:27-48 - exec | 0 | 0 |
○Loop 73 - random.c:27-48 - exec | 0 | 0 |
○Loop 72 - random.c:27-48 - exec | 0 | 0 |