Loop Id: 96 | Module: exec | Source: timestep.c:71-80 | Coverage: 0.03% |
---|
Loop Id: 96 | Module: exec | Source: timestep.c:71-80 | Coverage: 0.03% |
---|
0x40fac0 LEA 0x1(%RDI),%R8 |
0x40fac4 ADD $0x40,%ESI |
0x40fac7 CMP %RCX,%RDI |
0x40faca MOV %R8,%RDI |
0x40facd JE 40fa7b |
0x40facf MOV %ESI,%ESI |
0x40fad1 LEA (%RDI,%RAX,1),%R8 |
0x40fad5 MOV (%RDX,%R8,4),%R8D |
0x40fad9 TEST %R8D,%R8D |
0x40fadc JLE 40fac0 |
0x40fade LEA (,%RSI,8),%R15 |
0x40fae6 LEA (%RDI,%RAX,1),%R12D |
0x40faea SAL $0x6,%R12D |
0x40faee MOV 0x20(%RBX),%R10 |
0x40faf2 MOV 0x20(%R10),%R9 |
0x40faf6 MOV 0x28(%R10),%R10 |
0x40fafa LEA -0x1(%R8),%R11D |
0x40fafe MOVSXD %R11D,%R11 |
0x40fb01 ADD %R12,%R11 |
0x40fb04 SAL $0x3,%R11 |
0x40fb08 LEA (%R11,%R11,2),%R11 |
0x40fb0c LEA (%R10,%R11,1),%R13 |
0x40fb10 ADD $0x10,%R13 |
0x40fb14 SAL $0x3,%R12 |
0x40fb18 LEA (%R12,%R12,2),%R12 |
0x40fb1c LEA (%R9,%R12,1),%R14 |
0x40fb20 CMP %R14,%R13 |
0x40fb23 JB 40fb90 |
0x40fb25 ADD %R10,%R12 |
0x40fb28 ADD %R9,%R11 |
0x40fb2b ADD $0x10,%R11 |
0x40fb2f CMP %R12,%R11 |
0x40fb32 JB 40fb90 |
0x40fb34 LEA (%R15,%R15,2),%R11 |
0x40fb38 ADD $0x10,%R11 |
0x40fb3c NOPL (%RAX) |
(99) 0x40fb40 VMOVSD -0x10(%R10,%R11,1),%XMM2 |
(99) 0x40fb47 VFMADD213SD -0x10(%R9,%R11,1),%XMM0,%XMM2 |
(99) 0x40fb4e VMOVSD %XMM2,-0x10(%R9,%R11,1) |
(99) 0x40fb55 VMOVSD -0x8(%R10,%R11,1),%XMM2 |
(99) 0x40fb5c VFMADD213SD -0x8(%R9,%R11,1),%XMM0,%XMM2 |
(99) 0x40fb63 VMOVSD %XMM2,-0x8(%R9,%R11,1) |
(99) 0x40fb6a VMOVSD (%R10,%R11,1),%XMM2 |
(99) 0x40fb70 VFMADD213SD (%R9,%R11,1),%XMM0,%XMM2 |
(99) 0x40fb76 VMOVSD %XMM2,(%R9,%R11,1) |
(99) 0x40fb7c ADD $0x18,%R11 |
(99) 0x40fb80 DEC %R8D |
(99) 0x40fb83 JNE 40fb40 |
0x40fb85 JMP 40fac0 |
0x40fb90 MOV %R8D,%R11D |
0x40fb93 AND $-0x8,%R11D |
0x40fb97 JE 40fde0 |
0x40fb9d LEA (%R15,%R15,2),%R15 |
0x40fba1 LEA -0x1(%R11),%R12D |
0x40fba5 XOR %R13D,%R13D |
0x40fba8 NOPL (%RAX,%RAX,1) |
(98) 0x40fbb0 VMOVUPD 0x20(%R10,%R15,1),%YMM2 |
(98) 0x40fbb7 VMOVUPD 0x80(%R10,%R15,1),%YMM3 |
(98) 0x40fbc1 VMOVUPD 0x10(%R10,%R15,1),%XMM4 |
(98) 0x40fbc8 VMOVUPD 0x70(%R10,%R15,1),%XMM5 |
(98) 0x40fbcf VBLENDPD $0x3,0x60(%R10,%R15,1),%YMM3,%YMM6 |
(98) 0x40fbd7 VINSERTF128 $0x1,0xa0(%R10,%R15,1),%YMM5,%YMM8 |
(98) 0x40fbe2 VMOVUPD 0x20(%R10,%R15,1),%XMM9 |
(98) 0x40fbe9 VBLENDPD $0xa,%YMM8,%YMM6,%YMM5 |
(98) 0x40fbef VBLENDPD $0x3,(%R10,%R15,1),%YMM2,%YMM11 |
(98) 0x40fbf6 VINSERTF128 $0x1,0x40(%R10,%R15,1),%YMM4,%YMM4 |
(98) 0x40fbfe VBLENDPD $0xa,%YMM4,%YMM11,%YMM10 |
(98) 0x40fc04 VSHUFPD $0x5,%YMM3,%YMM6,%YMM3 |
(98) 0x40fc09 VBROADCASTSD 0xb0(%R10,%R15,1),%YMM6 |
(98) 0x40fc13 VBLENDPD $0x8,%YMM6,%YMM3,%YMM7 |
(98) 0x40fc19 VSHUFPD $0x5,%YMM2,%YMM11,%YMM2 |
(98) 0x40fc1e VBROADCASTSD 0x50(%R10,%R15,1),%YMM3 |
(98) 0x40fc25 VBLENDPD $0x8,%YMM3,%YMM2,%YMM12 |
(98) 0x40fc2b VMOVUPD 0x80(%R10,%R15,1),%XMM2 |
(98) 0x40fc35 VBLENDPD $0xc,0xa0(%R10,%R15,1),%YMM2,%YMM2 |
(98) 0x40fc40 VBLENDPD $0xa,%YMM2,%YMM8,%YMM11 |
(98) 0x40fc46 VBLENDPD $0xc,0x40(%R10,%R15,1),%YMM9,%YMM2 |
(98) 0x40fc4e VBLENDPD $0xa,%YMM2,%YMM4,%YMM13 |
(98) 0x40fc54 VMOVUPD 0x20(%R9,%R15,1),%YMM3 |
(98) 0x40fc5b VMOVUPD 0x80(%R9,%R15,1),%YMM4 |
(98) 0x40fc65 VMOVUPD 0x10(%R9,%R15,1),%XMM8 |
(98) 0x40fc6c VMOVUPD 0x70(%R9,%R15,1),%XMM2 |
(98) 0x40fc73 VBLENDPD $0x3,0x60(%R9,%R15,1),%YMM4,%YMM6 |
(98) 0x40fc7b VINSERTF128 $0x1,0xa0(%R9,%R15,1),%YMM2,%YMM9 |
(98) 0x40fc86 VBLENDPD $0xa,%YMM9,%YMM6,%YMM2 |
(98) 0x40fc8c VBLENDPD $0x3,(%R9,%R15,1),%YMM3,%YMM14 |
(98) 0x40fc93 VSHUFPD $0x5,%YMM4,%YMM6,%YMM4 |
(98) 0x40fc98 VBROADCASTSD 0xb0(%R9,%R15,1),%YMM6 |
(98) 0x40fca2 VBLENDPD $0x8,%YMM6,%YMM4,%YMM6 |
(98) 0x40fca8 VSHUFPD $0x5,%YMM3,%YMM14,%YMM3 |
(98) 0x40fcad VBROADCASTSD 0x50(%R9,%R15,1),%YMM4 |
(98) 0x40fcb4 VBLENDPD $0x8,%YMM4,%YMM3,%YMM4 |
(98) 0x40fcba VMOVUPD 0x80(%R9,%R15,1),%XMM3 |
(98) 0x40fcc4 VBLENDPD $0xc,0xa0(%R9,%R15,1),%YMM3,%YMM3 |
(98) 0x40fccf VBLENDPD $0xa,%YMM3,%YMM9,%YMM3 |
(98) 0x40fcd5 VMOVUPD 0x20(%R9,%R15,1),%XMM9 |
(98) 0x40fcdc VINSERTF128 $0x1,0x40(%R9,%R15,1),%YMM8,%YMM15 |
(98) 0x40fce4 VBLENDPD $0xa,%YMM15,%YMM14,%YMM8 |
(98) 0x40fcea VBLENDPD $0xc,0x40(%R9,%R15,1),%YMM9,%YMM9 |
(98) 0x40fcf2 VBLENDPD $0xa,%YMM9,%YMM15,%YMM9 |
(98) 0x40fcf8 VFMADD231PD %YMM10,%YMM1,%YMM8 |
(98) 0x40fcfd VFMADD231PD %YMM5,%YMM1,%YMM2 |
(98) 0x40fd02 VFMADD231PD %YMM12,%YMM1,%YMM4 |
(98) 0x40fd07 VFMADD231PD %YMM7,%YMM1,%YMM6 |
(98) 0x40fd0c VFMADD231PD %YMM13,%YMM1,%YMM9 |
(98) 0x40fd11 VFMADD231PD %YMM11,%YMM1,%YMM3 |
(98) 0x40fd16 VMOVDDUP %XMM4,%XMM5 |
(98) 0x40fd1a VPERM2F128 $0x20,%YMM8,%YMM5,%YMM5 |
(98) 0x40fd20 VMOVDDUP %XMM6,%XMM7 |
(98) 0x40fd24 VPERM2F128 $0x20,%YMM2,%YMM7,%YMM7 |
(98) 0x40fd2a VINSERTF128 $0x1,%XMM3,%YMM2,%YMM10 |
(98) 0x40fd30 VBLENDPD $0xa,%YMM7,%YMM10,%YMM7 |
(98) 0x40fd36 VINSERTF128 $0x1,%XMM9,%YMM8,%YMM10 |
(98) 0x40fd3c VBLENDPD $0xa,%YMM5,%YMM10,%YMM5 |
(98) 0x40fd42 VSHUFPD $0x1,%YMM6,%YMM6,%YMM10 |
(98) 0x40fd47 VBLENDPD $0x4,%YMM2,%YMM10,%YMM10 |
(98) 0x40fd4d VSHUFPD $0x4,%YMM6,%YMM6,%YMM6 |
(98) 0x40fd52 VPERM2F128 $0x31,%YMM3,%YMM2,%YMM2 |
(98) 0x40fd58 VPERM2F128 $0x31,%YMM6,%YMM3,%YMM6 |
(98) 0x40fd5e VBLENDPD $0xa,%YMM2,%YMM6,%YMM2 |
(98) 0x40fd64 VSHUFPD $0x1,%YMM4,%YMM4,%YMM6 |
(98) 0x40fd69 VBLENDPD $0x4,%YMM8,%YMM6,%YMM6 |
(98) 0x40fd6f VSHUFPD $0x4,%YMM4,%YMM4,%YMM4 |
(98) 0x40fd74 VPERM2F128 $0x31,%YMM9,%YMM8,%YMM8 |
(98) 0x40fd7a VPERM2F128 $0x31,%YMM4,%YMM9,%YMM4 |
(98) 0x40fd80 VBLENDPD $0xa,%YMM8,%YMM4,%YMM4 |
(98) 0x40fd86 VBLENDPD $0x2,%YMM9,%YMM6,%YMM6 |
(98) 0x40fd8c VBLENDPD $0x2,%YMM3,%YMM10,%YMM3 |
(98) 0x40fd92 VMOVUPD %YMM4,0x40(%R9,%R15,1) |
(98) 0x40fd99 VMOVUPD %YMM2,0xa0(%R9,%R15,1) |
(98) 0x40fda3 VMOVUPD %YMM3,0x80(%R9,%R15,1) |
(98) 0x40fdad VMOVUPD %YMM6,0x20(%R9,%R15,1) |
(98) 0x40fdb4 VMOVUPD %YMM5,(%R9,%R15,1) |
(98) 0x40fdba VMOVUPD %YMM7,0x60(%R9,%R15,1) |
(98) 0x40fdc1 ADD $0x8,%R13D |
(98) 0x40fdc5 ADD $0xc0,%R15 |
(98) 0x40fdcc CMP %R12D,%R13D |
(98) 0x40fdcf JLE 40fbb0 |
0x40fdd5 CMP %R11D,%R8D |
0x40fdd8 JE 40fac0 |
0x40fdde JMP 40fde3 |
0x40fde0 XOR %R11D,%R11D |
0x40fde3 VMOVDDUP %XMM0,%XMM2 |
0x40fde7 SUB %R11D,%R8D |
0x40fdea MOVSXD %R11D,%R11 |
0x40fded ADD %RSI,%R11 |
0x40fdf0 LEA (%R11,%R11,2),%R11 |
0x40fdf4 LEA 0x10(,%R11,8),%R11 |
0x40fdfc NOPL (%RAX) |
(97) 0x40fe00 VMOVUPD -0x10(%R10,%R11,1),%XMM3 |
(97) 0x40fe07 VFMADD213PD -0x10(%R9,%R11,1),%XMM2,%XMM3 |
(97) 0x40fe0e VMOVUPD %XMM3,-0x10(%R9,%R11,1) |
(97) 0x40fe15 VMOVSD (%R10,%R11,1),%XMM3 |
(97) 0x40fe1b VFMADD213SD (%R9,%R11,1),%XMM0,%XMM3 |
(97) 0x40fe21 VMOVSD %XMM3,(%R9,%R11,1) |
(97) 0x40fe27 ADD $0x18,%R11 |
(97) 0x40fe2b DEC %R8D |
(97) 0x40fe2e JNE 40fe00 |
0x40fe30 JMP 40fac0 |
/scratch_na/users/xoserete/qaas_runs/171-322-9862/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 80 |
-------------------------------------------------------------------------------- |
71: #pragma omp parallel for |
72: for (int iBox=0; iBox<nBoxes; iBox++) |
73: { |
74: for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++) |
75: { |
76: s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0]; |
77: s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1]; |
78: s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2]; |
79: } |
80: } |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.67 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 14.93 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.70 |
Bottlenecks | micro-operation queue, |
Function | advanceVelocity.extracted |
Source | timestep.c:71-80 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 9.33 |
CQA cycles if no scalar integer | 3.50 |
CQA cycles if FP arith vectorized | 9.33 |
CQA cycles if fully vectorized | 0.63 |
Front-end cycles | 9.33 |
DIV/SQRT cycles | 5.50 |
P0 cycles | 5.40 |
P1 cycles | 1.33 |
P2 cycles | 1.33 |
P3 cycles | 0.00 |
P4 cycles | 5.40 |
P5 cycles | 5.30 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 5.40 |
P10 cycles | 1.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 9.45 |
Stall cycles (UFS) | 0.00 |
Nb insns | 56.00 |
Nb uops | 56.00 |
Nb loads | 4.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 3.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 28.00 |
Bytes stored | 0.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 10.16 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 9.82 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.67 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 14.93 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.70 |
Bottlenecks | micro-operation queue, |
Function | advanceVelocity.extracted |
Source | timestep.c:71-80 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 9.33 |
CQA cycles if no scalar integer | 3.50 |
CQA cycles if FP arith vectorized | 9.33 |
CQA cycles if fully vectorized | 0.63 |
Front-end cycles | 9.33 |
DIV/SQRT cycles | 5.50 |
P0 cycles | 5.40 |
P1 cycles | 1.33 |
P2 cycles | 1.33 |
P3 cycles | 0.00 |
P4 cycles | 5.40 |
P5 cycles | 5.30 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 5.40 |
P10 cycles | 1.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 9.45 |
Stall cycles (UFS) | 0.00 |
Nb insns | 56.00 |
Nb uops | 56.00 |
Nb loads | 4.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 3.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 28.00 |
Bytes stored | 0.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 10.16 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 9.82 |
Path / |
Function | advanceVelocity.extracted |
Source file and lines | timestep.c:71-80 |
Module | exec |
nb instructions | 56 |
nb uops | 56 |
loop length | 213 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 9.33 cycles |
front end | 9.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.50 | 5.40 | 1.33 | 1.33 | 0.00 | 5.40 | 5.30 | 0.00 | 0.00 | 0.00 | 5.40 | 1.33 |
cycles | 5.50 | 5.40 | 1.33 | 1.33 | 0.00 | 5.40 | 5.30 | 0.00 | 0.00 | 0.00 | 5.40 | 1.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 9.45 |
Stall cycles | 0.00 |
Front-end | 9.33 |
Dispatch | 5.50 |
Overall L1 | 9.33 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 9% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 10% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LEA 0x1(%RDI),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x40,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RCX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JE 40fa7b <advanceVelocity.extracted+0x6b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%RDI,%RAX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%RDX,%R8,4),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R8D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 40fac0 <advanceVelocity.extracted+0xb0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (,%RSI,8),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%RDI,%RAX,1),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SAL $0x6,%R12D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV 0x20(%RBX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R10),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%R10),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x1(%R8),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOVSXD %R11D,%R11 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
ADD %R12,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SAL $0x3,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R11,%R11,2),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R10,%R11,1),%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x10,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x3,%R12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R12,%R12,2),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R9,%R12,1),%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R14,%R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 40fb90 <advanceVelocity.extracted+0x180> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %R10,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R9,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD $0x10,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R12,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 40fb90 <advanceVelocity.extracted+0x180> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%R15,%R15,2),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x10,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40fac0 <advanceVelocity.extracted+0xb0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %R8D,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 40fde0 <advanceVelocity.extracted+0x3d0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%R15,%R15,2),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x1(%R11),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R11D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 40fac0 <advanceVelocity.extracted+0xb0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 40fde3 <advanceVelocity.extracted+0x3d3> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %R11D,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVDDUP %XMM0,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
SUB %R11D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R11D,%R11 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
ADD %RSI,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%R11,%R11,2),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x10(,%R11,8),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40fac0 <advanceVelocity.extracted+0xb0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Function | advanceVelocity.extracted |
Source file and lines | timestep.c:71-80 |
Module | exec |
nb instructions | 56 |
nb uops | 56 |
loop length | 213 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 9.33 cycles |
front end | 9.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.50 | 5.40 | 1.33 | 1.33 | 0.00 | 5.40 | 5.30 | 0.00 | 0.00 | 0.00 | 5.40 | 1.33 |
cycles | 5.50 | 5.40 | 1.33 | 1.33 | 0.00 | 5.40 | 5.30 | 0.00 | 0.00 | 0.00 | 5.40 | 1.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 9.45 |
Stall cycles | 0.00 |
Front-end | 9.33 |
Dispatch | 5.50 |
Overall L1 | 9.33 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 9% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 9% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 10% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LEA 0x1(%RDI),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x40,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RCX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JE 40fa7b <advanceVelocity.extracted+0x6b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%RDI,%RAX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%RDX,%R8,4),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R8D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 40fac0 <advanceVelocity.extracted+0xb0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (,%RSI,8),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%RDI,%RAX,1),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SAL $0x6,%R12D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV 0x20(%RBX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R10),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%R10),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x1(%R8),%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOVSXD %R11D,%R11 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
ADD %R12,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SAL $0x3,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R11,%R11,2),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R10,%R11,1),%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x10,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x3,%R12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R12,%R12,2),%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R9,%R12,1),%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R14,%R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 40fb90 <advanceVelocity.extracted+0x180> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %R10,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R9,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD $0x10,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %R12,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 40fb90 <advanceVelocity.extracted+0x180> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%R15,%R15,2),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x10,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40fac0 <advanceVelocity.extracted+0xb0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %R8D,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 40fde0 <advanceVelocity.extracted+0x3d0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%R15,%R15,2),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x1(%R11),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R11D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 40fac0 <advanceVelocity.extracted+0xb0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 40fde3 <advanceVelocity.extracted+0x3d3> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %R11D,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVDDUP %XMM0,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
SUB %R11D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R11D,%R11 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
ADD %RSI,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%R11,%R11,2),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x10(,%R11,8),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40fac0 <advanceVelocity.extracted+0xb0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |