Loop Id: 94 | Module: exec | Source: timestep.c:72-80 | Coverage: 0.03% |
---|
Loop Id: 94 | Module: exec | Source: timestep.c:72-80 | Coverage: 0.03% |
---|
0x40e9c0 LEA 0x1(%RDI),%R8 |
0x40e9c4 ADD $0x40,%ESI |
0x40e9c7 CMP %RCX,%RDI |
0x40e9ca MOV %R8,%RDI |
0x40e9cd JE 40e94b |
0x40e9d3 LEA (%RDI,%RAX,1),%R8 |
0x40e9d7 MOV (%RDX,%R8,4),%R8D |
0x40e9db TEST %R8D,%R8D |
0x40e9de JLE 40e9c0 |
0x40e9e0 MOV %ESI,%R11D |
0x40e9e3 SAL $0x3,%R11 |
0x40e9e7 LEA (%RDI,%RAX,1),%R15D |
0x40e9eb SAL $0x6,%R15D |
0x40e9ef MOV 0x20(%RBX),%R10 |
0x40e9f3 MOV 0x20(%R10),%R9 |
0x40e9f7 MOV 0x28(%R10),%R10 |
0x40e9fb LEA -0x1(%R8),%R14D |
0x40e9ff MOVSXD %R14D,%R14 |
0x40ea02 ADD %R15,%R14 |
0x40ea05 SAL $0x3,%R14 |
0x40ea09 LEA (%R14,%R14,2),%R14 |
0x40ea0d LEA 0x10(%R10,%R14,1),%R12 |
0x40ea12 SAL $0x3,%R15 |
0x40ea16 LEA (%R15,%R15,2),%R15 |
0x40ea1a LEA (%R9,%R15,1),%R13 |
0x40ea1e CMP %R13,%R12 |
0x40ea21 JB 40ea90 |
0x40ea23 ADD %R10,%R15 |
0x40ea26 LEA 0x10(%R9,%R14,1),%R14 |
0x40ea2b CMP %R15,%R14 |
0x40ea2e JB 40ea90 |
0x40ea30 LEA 0x10(%R11,%R11,2),%R11 |
0x40ea35 NOPW %CS:(%RAX,%RAX,1) |
(97) 0x40ea40 VMOVSD -0x10(%R10,%R11,1),%XMM2 |
(97) 0x40ea47 VFMADD213SD -0x10(%R9,%R11,1),%XMM0,%XMM2 |
(97) 0x40ea4e VMOVSD %XMM2,-0x10(%R9,%R11,1) |
(97) 0x40ea55 VMOVSD -0x8(%R10,%R11,1),%XMM2 |
(97) 0x40ea5c VFMADD213SD -0x8(%R9,%R11,1),%XMM0,%XMM2 |
(97) 0x40ea63 VMOVSD %XMM2,-0x8(%R9,%R11,1) |
(97) 0x40ea6a VMOVSD (%R10,%R11,1),%XMM2 |
(97) 0x40ea70 VFMADD213SD (%R9,%R11,1),%XMM0,%XMM2 |
(97) 0x40ea76 VMOVSD %XMM2,(%R9,%R11,1) |
(97) 0x40ea7c ADD $0x18,%R11 |
(97) 0x40ea80 DEC %R8D |
(97) 0x40ea83 JNE 40ea40 |
0x40ea85 JMP 40e9c0 |
0x40ea90 LEA (%R11,%R11,2),%R14 |
0x40ea94 MOV %R8D,%R15D |
0x40ea97 AND $-0x8,%R15D |
0x40ea9b JE 40ecc0 |
0x40eaa1 LEA -0x1(%R15),%R12D |
0x40eaa5 XOR %R13D,%R13D |
0x40eaa8 MOV %R14,%R11 |
0x40eaab NOPL (%RAX,%RAX,1) |
(96) 0x40eab0 VMOVUPD 0x80(%R10,%R11,1),%YMM7 |
(96) 0x40eaba VMOVUPD 0x20(%R10,%R11,1),%YMM10 |
(96) 0x40eac1 VMOVUPD 0x80(%R9,%R11,1),%YMM8 |
(96) 0x40eacb VMOVUPD 0x20(%R9,%R11,1),%YMM12 |
(96) 0x40ead2 VMOVUPD 0x10(%R10,%R11,1),%XMM9 |
(96) 0x40ead9 VMOVUPD 0x70(%R10,%R11,1),%XMM11 |
(96) 0x40eae0 VBLENDPD $0x3,(%R10,%R11,1),%YMM10,%YMM15 |
(96) 0x40eae7 VBLENDPD $0x3,0x60(%R10,%R11,1),%YMM7,%YMM3 |
(96) 0x40eaef VBLENDPD $0x3,(%R9,%R11,1),%YMM12,%YMM2 |
(96) 0x40eaf6 VMOVUPD 0x10(%R9,%R11,1),%XMM18 |
(96) 0x40eafe VBLENDPD $0x3,0x60(%R9,%R11,1),%YMM8,%YMM14 |
(96) 0x40eb06 VMOVUPD 0x20(%R10,%R11,1),%XMM13 |
(96) 0x40eb0d VMOVUPD 0x80(%R10,%R11,1),%XMM4 |
(96) 0x40eb17 VMOVUPD 0x20(%R9,%R11,1),%XMM5 |
(96) 0x40eb1e VINSERTF128 $0x1,0x40(%R10,%R11,1),%YMM9,%YMM6 |
(96) 0x40eb26 VBLENDPD $0xc,0x40(%R10,%R11,1),%YMM13,%YMM9 |
(96) 0x40eb2e VBLENDPD $0xa,%YMM9,%YMM6,%YMM9 |
(96) 0x40eb34 VBLENDPD $0xa,%YMM6,%YMM15,%YMM13 |
(96) 0x40eb3a VSHUFPD $0x5,%YMM10,%YMM15,%YMM6 |
(96) 0x40eb40 VINSERTF128 $0x1,0xa0(%R10,%R11,1),%YMM11,%YMM11 |
(96) 0x40eb4b VBLENDPD $0xc,0xa0(%R10,%R11,1),%YMM4,%YMM4 |
(96) 0x40eb56 VBLENDPD $0xa,%YMM4,%YMM11,%YMM10 |
(96) 0x40eb5c VBLENDPD $0xa,%YMM11,%YMM3,%YMM15 |
(96) 0x40eb62 VSHUFPD $0x5,%YMM7,%YMM3,%YMM3 |
(96) 0x40eb67 VINSERTF32X4 $0x1,0x40(%R9,%R11,1),%YMM18,%YMM4 |
(96) 0x40eb70 VBLENDPD $0xc,0x40(%R9,%R11,1),%YMM5,%YMM5 |
(96) 0x40eb78 VMOVUPD 0x70(%R9,%R11,1),%XMM18 |
(96) 0x40eb80 VBLENDPD $0xa,%YMM5,%YMM4,%YMM7 |
(96) 0x40eb86 VBLENDPD $0xa,%YMM4,%YMM2,%YMM11 |
(96) 0x40eb8c VSHUFPD $0x5,%YMM12,%YMM2,%YMM2 |
(96) 0x40eb92 VBROADCASTSD 0x50(%R10,%R11,1),%YMM4 |
(96) 0x40eb99 VBLENDPD $0x8,%YMM4,%YMM6,%YMM4 |
(96) 0x40eb9f VBROADCASTSD 0xb0(%R10,%R11,1),%YMM5 |
(96) 0x40eba9 VBLENDPD $0x8,%YMM5,%YMM3,%YMM3 |
(96) 0x40ebaf VBROADCASTSD 0x50(%R9,%R11,1),%YMM5 |
(96) 0x40ebb6 VBLENDPD $0x8,%YMM5,%YMM2,%YMM12 |
(96) 0x40ebbc VBROADCASTSD 0xb0(%R9,%R11,1),%YMM2 |
(96) 0x40ebc6 VSHUFPD $0x5,%YMM8,%YMM14,%YMM5 |
(96) 0x40ebcc VBLENDPD $0x8,%YMM2,%YMM5,%YMM2 |
(96) 0x40ebd2 VINSERTF32X4 $0x1,0xa0(%R9,%R11,1),%YMM18,%YMM5 |
(96) 0x40ebdb VBLENDPD $0xa,%YMM5,%YMM14,%YMM8 |
(96) 0x40ebe1 VFMADD231PD %YMM15,%YMM1,%YMM8 |
(96) 0x40ebe6 VFMADD231PD %YMM13,%YMM1,%YMM11 |
(96) 0x40ebeb VFMADD231PD %YMM3,%YMM1,%YMM2 |
(96) 0x40ebf0 VFMADD231PD %YMM4,%YMM1,%YMM12 |
(96) 0x40ebf5 VMOVUPD 0x80(%R9,%R11,1),%XMM3 |
(96) 0x40ebff VBLENDPD $0xc,0xa0(%R9,%R11,1),%YMM3,%YMM3 |
(96) 0x40ec0a VBLENDPD $0xa,%YMM3,%YMM5,%YMM13 |
(96) 0x40ec10 VFMADD231PD %YMM10,%YMM1,%YMM13 |
(96) 0x40ec15 VFMADD231PD %YMM9,%YMM1,%YMM7 |
(96) 0x40ec1a VMOVAPD %YMM11,%YMM3 |
(96) 0x40ec1e VPERMT2PD %YMM12,%YMM16,%YMM3 |
(96) 0x40ec24 VMOVAPD %YMM2,%YMM4 |
(96) 0x40ec28 VPERMT2PD %YMM8,%YMM17,%YMM4 |
(96) 0x40ec2e VMOVAPD %YMM2,%YMM5 |
(96) 0x40ec32 VPERMT2PD %YMM8,%YMM19,%YMM5 |
(96) 0x40ec38 VPERMT2PD %YMM2,%YMM16,%YMM8 |
(96) 0x40ec3e VMOVAPD %YMM12,%YMM2 |
(96) 0x40ec42 VPERMT2PD %YMM11,%YMM17,%YMM2 |
(96) 0x40ec48 VPERMT2PD %YMM11,%YMM19,%YMM12 |
(96) 0x40ec4e VPERMT2PD %YMM13,%YMM20,%YMM8 |
(96) 0x40ec54 VBLENDPD $0x2,%YMM13,%YMM5,%YMM5 |
(96) 0x40ec5a VPERMT2PD %YMM4,%YMM21,%YMM13 |
(96) 0x40ec60 VBLENDPD $0x2,%YMM7,%YMM12,%YMM4 |
(96) 0x40ec66 VPERMT2PD %YMM7,%YMM20,%YMM3 |
(96) 0x40ec6c VPERMT2PD %YMM2,%YMM21,%YMM7 |
(96) 0x40ec72 VMOVUPD %YMM5,0x80(%R9,%R11,1) |
(96) 0x40ec7c VMOVUPD %YMM4,0x20(%R9,%R11,1) |
(96) 0x40ec83 VMOVUPD %YMM7,0x40(%R9,%R11,1) |
(96) 0x40ec8a VMOVUPD %YMM13,0xa0(%R9,%R11,1) |
(96) 0x40ec94 VMOVUPD %YMM8,0x60(%R9,%R11,1) |
(96) 0x40ec9b VMOVUPD %YMM3,(%R9,%R11,1) |
(96) 0x40eca1 ADD $0x8,%R13D |
(96) 0x40eca5 ADD $0xc0,%R11 |
(96) 0x40ecac CMP %R12D,%R13D |
(96) 0x40ecaf JLE 40eab0 |
0x40ecb5 CMP %R15D,%R8D |
0x40ecb8 JE 40e9c0 |
0x40ecbe JMP 40ecc3 |
0x40ecc0 XOR %R15D,%R15D |
0x40ecc3 SUB %R15D,%R8D |
0x40ecc6 MOVSXD %R15D,%R11 |
0x40ecc9 SAL $0x3,%R11 |
0x40eccd LEA (%R11,%R11,2),%R11 |
0x40ecd1 ADD %R11,%R9 |
0x40ecd4 ADD %R11,%R10 |
0x40ecd7 NOPW (%RAX,%RAX,1) |
(95) 0x40ece0 VMOVUPD (%R10,%R14,1),%XMM2 |
(95) 0x40ece6 VFMADD213PD (%R9,%R14,1),%XMM1,%XMM2 |
(95) 0x40ecec VMOVUPD %XMM2,(%R9,%R14,1) |
(95) 0x40ecf2 VMOVSD 0x10(%R10,%R14,1),%XMM2 |
(95) 0x40ecf9 VFMADD213SD 0x10(%R9,%R14,1),%XMM0,%XMM2 |
(95) 0x40ed00 VMOVSD %XMM2,0x10(%R9,%R14,1) |
(95) 0x40ed07 ADD $0x18,%R14 |
(95) 0x40ed0b DEC %R8D |
(95) 0x40ed0e JNE 40ece0 |
0x40ed10 JMP 40e9c0 |
/scratch_na/users/xoserete/qaas_runs/171-322-9862/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 72 - 80 |
-------------------------------------------------------------------------------- |
72: for (int iBox=0; iBox<nBoxes; iBox++) |
73: { |
74: for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++) |
75: { |
76: s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0]; |
77: s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1]; |
78: s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2]; |
79: } |
80: } |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 15.16 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.35 |
Bottlenecks | micro-operation queue, |
Function | advanceVelocity.extracted |
Source | timestep.c:72-80 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 9.00 |
CQA cycles if no scalar integer | 9.00 |
CQA cycles if FP arith vectorized | 9.00 |
CQA cycles if fully vectorized | 0.59 |
Front-end cycles | 9.00 |
DIV/SQRT cycles | 6.30 |
P0 cycles | 6.67 |
P1 cycles | 1.33 |
P2 cycles | 1.33 |
P3 cycles | 0.00 |
P4 cycles | 6.20 |
P5 cycles | 6.10 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 6.20 |
P10 cycles | 1.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 9.15 |
Stall cycles (UFS) | 0.00 |
Nb insns | 54.00 |
Nb uops | 54.00 |
Nb loads | 4.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 3.11 |
Bytes prefetched | 0.00 |
Bytes loaded | 28.00 |
Bytes stored | 0.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 8.93 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 6.25 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 9.38 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 15.16 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.35 |
Bottlenecks | micro-operation queue, |
Function | advanceVelocity.extracted |
Source | timestep.c:72-80 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 9.00 |
CQA cycles if no scalar integer | 9.00 |
CQA cycles if FP arith vectorized | 9.00 |
CQA cycles if fully vectorized | 0.59 |
Front-end cycles | 9.00 |
DIV/SQRT cycles | 6.30 |
P0 cycles | 6.67 |
P1 cycles | 1.33 |
P2 cycles | 1.33 |
P3 cycles | 0.00 |
P4 cycles | 6.20 |
P5 cycles | 6.10 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 6.20 |
P10 cycles | 1.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 9.15 |
Stall cycles (UFS) | 0.00 |
Nb insns | 54.00 |
Nb uops | 54.00 |
Nb loads | 4.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 3.11 |
Bytes prefetched | 0.00 |
Bytes loaded | 28.00 |
Bytes stored | 0.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 8.93 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 6.25 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 9.38 |
Path / |
Function | advanceVelocity.extracted |
Source file and lines | timestep.c:72-80 |
Module | exec |
nb instructions | 54 |
nb uops | 54 |
loop length | 213 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 9.00 cycles |
front end | 9.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 6.20 | 1.33 | 1.33 | 0.00 | 6.20 | 6.10 | 0.00 | 0.00 | 0.00 | 6.20 | 1.33 |
cycles | 6.30 | 6.67 | 1.33 | 1.33 | 0.00 | 6.20 | 6.10 | 0.00 | 0.00 | 0.00 | 6.20 | 1.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 9.15 |
Stall cycles | 0.00 |
Front-end | 9.00 |
Dispatch | 6.67 |
Overall L1 | 9.00 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 8% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LEA 0x1(%RDI),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x40,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RCX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JE 40e94b <advanceVelocity.extracted+0x6b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%RDI,%RAX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%RDX,%R8,4),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R8D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 40e9c0 <advanceVelocity.extracted+0xe0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ESI,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x3,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%RDI,%RAX,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SAL $0x6,%R15D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV 0x20(%RBX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R10),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%R10),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x1(%R8),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOVSXD %R14D,%R14 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
ADD %R15,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SAL $0x3,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R14,%R14,2),%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x10(%R10,%R14,1),%R12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SAL $0x3,%R15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R15,%R15,2),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R9,%R15,1),%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R13,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 40ea90 <advanceVelocity.extracted+0x1b0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %R10,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x10(%R9,%R14,1),%R14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMP %R15,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 40ea90 <advanceVelocity.extracted+0x1b0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA 0x10(%R11,%R11,2),%R11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40e9c0 <advanceVelocity.extracted+0xe0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
LEA (%R11,%R11,2),%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 40ecc0 <advanceVelocity.extracted+0x3e0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x1(%R15),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R14,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R15D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 40e9c0 <advanceVelocity.extracted+0xe0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 40ecc3 <advanceVelocity.extracted+0x3e3> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %R15D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%R11 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
SAL $0x3,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R11,%R11,2),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %R11,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R11,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40e9c0 <advanceVelocity.extracted+0xe0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Function | advanceVelocity.extracted |
Source file and lines | timestep.c:72-80 |
Module | exec |
nb instructions | 54 |
nb uops | 54 |
loop length | 213 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 9.00 cycles |
front end | 9.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.30 | 6.20 | 1.33 | 1.33 | 0.00 | 6.20 | 6.10 | 0.00 | 0.00 | 0.00 | 6.20 | 1.33 |
cycles | 6.30 | 6.67 | 1.33 | 1.33 | 0.00 | 6.20 | 6.10 | 0.00 | 0.00 | 0.00 | 6.20 | 1.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 9.15 |
Stall cycles | 0.00 |
Front-end | 9.00 |
Dispatch | 6.67 |
Overall L1 | 9.00 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 8% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 9% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LEA 0x1(%RDI),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x40,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RCX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JE 40e94b <advanceVelocity.extracted+0x6b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (%RDI,%RAX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%RDX,%R8,4),%R8D | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R8D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 40e9c0 <advanceVelocity.extracted+0xe0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %ESI,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x3,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%RDI,%RAX,1),%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SAL $0x6,%R15D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV 0x20(%RBX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%R10),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%R10),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA -0x1(%R8),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
MOVSXD %R14D,%R14 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
ADD %R15,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SAL $0x3,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R14,%R14,2),%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA 0x10(%R10,%R14,1),%R12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SAL $0x3,%R15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R15,%R15,2),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R9,%R15,1),%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R13,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 40ea90 <advanceVelocity.extracted+0x1b0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %R10,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA 0x10(%R9,%R14,1),%R14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
CMP %R15,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 40ea90 <advanceVelocity.extracted+0x1b0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA 0x10(%R11,%R11,2),%R11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40e9c0 <advanceVelocity.extracted+0xe0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
LEA (%R11,%R11,2),%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x8,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 40ecc0 <advanceVelocity.extracted+0x3e0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA -0x1(%R15),%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R14,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R15D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 40e9c0 <advanceVelocity.extracted+0xe0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 40ecc3 <advanceVelocity.extracted+0x3e3> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %R15D,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOVSXD %R15D,%R11 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
SAL $0x3,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%R11,%R11,2),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %R11,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
ADD %R11,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40e9c0 <advanceVelocity.extracted+0xe0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |