Function: advancePosition.extracted | Module: exec | Source: timestep.c:85-96 | Coverage: 1.98% |
---|
Function: advancePosition.extracted | Module: exec | Source: timestep.c:85-96 | Coverage: 1.98% |
---|
/scratch_na/users/xoserete/qaas_runs/171-419-7821/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 85 - 96 |
-------------------------------------------------------------------------------- |
85: #pragma omp parallel for |
86: for (int iBox=0; iBox<nBoxes; iBox++) |
87: { |
88: for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++) |
89: { |
90: int iSpecies = s->atoms->iSpecies[iOff]; |
91: real_t invMass = 1.0/s->species[iSpecies].mass; |
92: s->atoms->r[iOff][0] += dt*s->atoms->p[iOff][0]*invMass; |
93: s->atoms->r[iOff][1] += dt*s->atoms->p[iOff][1]*invMass; |
94: s->atoms->r[iOff][2] += dt*s->atoms->p[iOff][2]*invMass; |
95: } |
96: } |
0x40ed20 PUSH %RBP |
0x40ed21 MOV %RSP,%RBP |
0x40ed24 PUSH %R15 |
0x40ed26 PUSH %R14 |
0x40ed28 PUSH %R13 |
0x40ed2a PUSH %R12 |
0x40ed2c PUSH %RBX |
0x40ed2d SUB $0x38,%RSP |
0x40ed31 MOV %RCX,%R15 |
0x40ed34 MOV %RDX,-0x50(%RBP) |
0x40ed38 MOVL $0,-0x44(%RBP) |
0x40ed3f MOV (%RDI),%ESI |
0x40ed41 MOVL $0,-0x30(%RBP) |
0x40ed48 MOV %R9D,-0x2c(%RBP) |
0x40ed4c MOVL $0x1,-0x40(%RBP) |
0x40ed53 SUB $0x8,%RSP |
0x40ed57 LEA -0x40(%RBP),%RAX |
0x40ed5b LEA -0x44(%RBP),%RCX |
0x40ed5f LEA -0x30(%RBP),%R8 |
0x40ed63 LEA -0x2c(%RBP),%R9 |
0x40ed67 MOV $0x62c950,%EDI |
0x40ed6c MOV %ESI,-0x3c(%RBP) |
0x40ed6f MOV $0x22,%EDX |
0x40ed74 PUSH $0x1 |
0x40ed76 PUSH $0x1 |
0x40ed78 PUSH %RAX |
0x40ed79 CALL 402d60 <__kmpc_for_static_init_4@plt> |
0x40ed7e ADD $0x20,%RSP |
0x40ed82 MOV -0x30(%RBP),%EAX |
0x40ed85 MOV -0x2c(%RBP),%ECX |
0x40ed88 MOV %RCX,-0x38(%RBP) |
0x40ed8c CMP %ECX,%EAX |
0x40ed8e JBE 40edae |
0x40ed90 MOV $0x62c970,%EDI |
0x40ed95 MOV -0x3c(%RBP),%ESI |
0x40ed98 ADD $0x38,%RSP |
0x40ed9c POP %RBX |
0x40ed9d POP %R12 |
0x40ed9f POP %R13 |
0x40eda1 POP %R14 |
0x40eda3 POP %R15 |
0x40eda5 POP %RBP |
0x40eda6 VZEROUPPER |
0x40eda9 JMP 402c10 |
0x40edae VMOVQ %R15,%XMM23 |
0x40edb4 MOV -0x50(%RBP),%RCX |
0x40edb8 MOV 0x18(%RCX),%RCX |
0x40edbc MOV 0x78(%RCX),%RCX |
0x40edc0 MOV %RCX,-0x58(%RBP) |
0x40edc4 MOV -0x38(%RBP),%RCX |
0x40edc8 SUB %RAX,%RCX |
0x40edcb MOV %RCX,-0x38(%RBP) |
0x40edcf VPBROADCASTQ %XMM23,%YMM22 |
0x40edd5 MOV %EAX,%ESI |
0x40edd7 SAL $0x6,%ESI |
0x40edda XOR %EDI,%EDI |
0x40eddc VMOVUPD 0x138fa(%RIP),%YMM16 |
0x40ede6 VMOVUPD 0x13850(%RIP),%YMM17 |
0x40edf0 VMOVUPD 0x13866(%RIP),%YMM19 |
0x40edfa VMOVUPD 0x1389c(%RIP),%YMM20 |
0x40ee04 VMOVUPD 0x138b2(%RIP),%YMM21 |
0x40ee0e JMP 40ee24 |
(98) 0x40ee10 LEA 0x1(%RDI),%RCX |
(98) 0x40ee14 ADD $0x40,%ESI |
(98) 0x40ee17 CMP -0x38(%RBP),%RDI |
(98) 0x40ee1b MOV %RCX,%RDI |
(98) 0x40ee1e JE 40ed90 |
(98) 0x40ee24 MOV %ESI,%ESI |
(98) 0x40ee26 LEA (%RDI,%RAX,1),%RCX |
(98) 0x40ee2a MOV -0x58(%RBP),%RDX |
(98) 0x40ee2e MOV (%RDX,%RCX,4),%R8D |
(98) 0x40ee32 TEST %R8D,%R8D |
(98) 0x40ee35 JLE 40ee10 |
(98) 0x40ee37 LEA (,%RSI,8),%RCX |
(98) 0x40ee3f LEA (,%RSI,4),%R12 |
(98) 0x40ee47 LEA (%RDI,%RAX,1),%EBX |
(98) 0x40ee4a SAL $0x6,%EBX |
(98) 0x40ee4d MOV -0x50(%RBP),%R9 |
(98) 0x40ee51 MOV 0x20(%R9),%RDX |
(98) 0x40ee55 MOV 0x28(%R9),%R9 |
(98) 0x40ee59 MOV 0x10(%RDX),%R15 |
(98) 0x40ee5d MOV 0x18(%RDX),%R10 |
(98) 0x40ee61 MOV 0x20(%RDX),%R11 |
(98) 0x40ee65 LEA -0x1(%R8),%EDX |
(98) 0x40ee69 MOVSXD %EDX,%RDX |
(98) 0x40ee6c ADD %RBX,%RDX |
(98) 0x40ee6f SAL $0x3,%RDX |
(98) 0x40ee73 LEA (%RDX,%RDX,2),%RDX |
(98) 0x40ee77 LEA 0x10(%R11,%RDX,1),%R14 |
(98) 0x40ee7c SAL $0x3,%RBX |
(98) 0x40ee80 LEA (%RBX,%RBX,2),%RBX |
(98) 0x40ee84 LEA (%R10,%RBX,1),%R13 |
(98) 0x40ee88 CMP %R13,%R14 |
(98) 0x40ee8b JB 40ef10 |
(98) 0x40ee91 ADD %R11,%RBX |
(98) 0x40ee94 LEA 0x10(%R10,%RDX,1),%RDX |
(98) 0x40ee99 CMP %RBX,%RDX |
(98) 0x40ee9c JB 40ef10 |
(98) 0x40ee9e LEA 0x10(%RCX,%RCX,2),%RCX |
(98) 0x40eea3 ADD %R12,%R15 |
(98) 0x40eea6 XOR %EDX,%EDX |
(98) 0x40eea8 NOPL (%RAX,%RAX,1) |
(101) 0x40eeb0 MOVSXD (%R15,%RDX,4),%RBX |
(101) 0x40eeb4 SAL $0x4,%RBX |
(101) 0x40eeb8 VDIVSD 0x8(%R9,%RBX,1),%XMM23,%XMM0 |
(101) 0x40eec0 VMOVSD -0x10(%R11,%RCX,1),%XMM1 |
(101) 0x40eec7 VFMADD213SD -0x10(%R10,%RCX,1),%XMM0,%XMM1 |
(101) 0x40eece VMOVSD %XMM1,-0x10(%R10,%RCX,1) |
(101) 0x40eed5 VMOVSD -0x8(%R11,%RCX,1),%XMM1 |
(101) 0x40eedc VFMADD213SD -0x8(%R10,%RCX,1),%XMM0,%XMM1 |
(101) 0x40eee3 VMOVSD %XMM1,-0x8(%R10,%RCX,1) |
(101) 0x40eeea VMOVSD (%R11,%RCX,1),%XMM1 |
(101) 0x40eef0 VFMADD213SD (%R10,%RCX,1),%XMM0,%XMM1 |
(101) 0x40eef6 VMOVSD %XMM1,(%R10,%RCX,1) |
(101) 0x40eefc ADD $0x18,%RCX |
(101) 0x40ef00 INC %RDX |
(101) 0x40ef03 CMP %EDX,%R8D |
(101) 0x40ef06 JNE 40eeb0 |
(98) 0x40ef08 JMP 40ee10 |
0x40ef0d NOPL (%RAX) |
(98) 0x40ef10 LEA (%RCX,%RCX,2),%RCX |
(98) 0x40ef14 MOV %R8D,%R14D |
(98) 0x40ef17 AND $-0x8,%R14D |
(98) 0x40ef1b JE 40f181 |
(98) 0x40ef21 LEA -0x1(%R14),%EDX |
(98) 0x40ef25 ADD %R15,%R12 |
(98) 0x40ef28 MOV %RCX,%R13 |
(98) 0x40ef2b XOR %EBX,%EBX |
(98) 0x40ef2d NOPL (%RAX) |
(100) 0x40ef30 VPMOVSXDQ 0x10(%R12,%RBX,4),%YMM2 |
(100) 0x40ef37 KXNORW %K0,%K0,%K1 |
(100) 0x40ef3b VXORPD %XMM7,%XMM7,%XMM7 |
(100) 0x40ef3f VPADDQ %YMM2,%YMM2,%YMM2 |
(100) 0x40ef43 VGATHERQPD 0x8(%R9,%YMM2,8),%YMM7{%K1} |
(100) 0x40ef4b VPMOVSXDQ (%R12,%RBX,4),%YMM2 |
(100) 0x40ef51 KXNORW %K0,%K0,%K1 |
(100) 0x40ef55 VXORPD %XMM8,%XMM8,%XMM8 |
(100) 0x40ef5a VPADDQ %YMM2,%YMM2,%YMM2 |
(100) 0x40ef5e VGATHERQPD 0x8(%R9,%YMM2,8),%YMM8{%K1} |
(100) 0x40ef66 VDIVPD %YMM7,%YMM22,%YMM7 |
(100) 0x40ef6c VMOVUPD 0x80(%R11,%R13,1),%YMM9 |
(100) 0x40ef76 VMOVUPD 0x20(%R11,%R13,1),%YMM10 |
(100) 0x40ef7d VMOVUPD 0x10(%R11,%R13,1),%XMM13 |
(100) 0x40ef84 VMOVUPD 0x20(%R11,%R13,1),%XMM14 |
(100) 0x40ef8b VMOVUPD 0x70(%R11,%R13,1),%XMM15 |
(100) 0x40ef92 VBROADCASTSD 0x50(%R11,%R13,1),%YMM11 |
(100) 0x40ef99 VBROADCASTSD 0xb0(%R11,%R13,1),%YMM12 |
(100) 0x40efa3 VMOVUPD 0x80(%R11,%R13,1),%XMM3 |
(100) 0x40efad VMOVUPD 0x20(%R10,%R13,1),%YMM2 |
(100) 0x40efb4 VMOVUPD 0x10(%R10,%R13,1),%XMM18 |
(100) 0x40efbc VMOVUPD 0x20(%R10,%R13,1),%XMM4 |
(100) 0x40efc3 VINSERTF128 $0x1,0x40(%R11,%R13,1),%YMM13,%YMM13 |
(100) 0x40efcb VINSERTF128 $0x1,0xa0(%R11,%R13,1),%YMM15,%YMM5 |
(100) 0x40efd6 VBLENDPD $0xc,0x40(%R11,%R13,1),%YMM14,%YMM14 |
(100) 0x40efde VBLENDPD $0xc,0xa0(%R11,%R13,1),%YMM3,%YMM3 |
(100) 0x40efe9 VINSERTF32X4 $0x1,0x40(%R10,%R13,1),%YMM18,%YMM6 |
(100) 0x40eff2 VBLENDPD $0xc,0x40(%R10,%R13,1),%YMM4,%YMM4 |
(100) 0x40effa VBLENDPD $0x3,(%R11,%R13,1),%YMM10,%YMM15 |
(100) 0x40f001 VBLENDPD $0xa,%YMM14,%YMM13,%YMM14 |
(100) 0x40f007 VBLENDPD $0xa,%YMM13,%YMM15,%YMM1 |
(100) 0x40f00d VSHUFPD $0x5,%YMM10,%YMM15,%YMM10 |
(100) 0x40f013 VBLENDPD $0x3,0x60(%R11,%R13,1),%YMM9,%YMM13 |
(100) 0x40f01b VBLENDPD $0xa,%YMM3,%YMM5,%YMM15 |
(100) 0x40f021 VBLENDPD $0xa,%YMM5,%YMM13,%YMM3 |
(100) 0x40f027 VSHUFPD $0x5,%YMM9,%YMM13,%YMM5 |
(100) 0x40f02d VBLENDPD $0x3,(%R10,%R13,1),%YMM2,%YMM0 |
(100) 0x40f034 VBLENDPD $0xa,%YMM4,%YMM6,%YMM9 |
(100) 0x40f03a VBLENDPD $0xa,%YMM6,%YMM0,%YMM13 |
(100) 0x40f040 VSHUFPD $0x5,%YMM2,%YMM0,%YMM0 |
(100) 0x40f045 VMOVUPD 0x80(%R10,%R13,1),%YMM2 |
(100) 0x40f04f VMOVUPD 0x70(%R10,%R13,1),%XMM4 |
(100) 0x40f056 VBLENDPD $0x8,%YMM11,%YMM10,%YMM6 |
(100) 0x40f05c VBROADCASTSD 0x50(%R10,%R13,1),%YMM10 |
(100) 0x40f063 VBLENDPD $0x8,%YMM12,%YMM5,%YMM5 |
(100) 0x40f069 VBROADCASTSD 0xb0(%R10,%R13,1),%YMM12 |
(100) 0x40f073 VBLENDPD $0x8,%YMM10,%YMM0,%YMM11 |
(100) 0x40f079 VBLENDPD $0x3,0x60(%R10,%R13,1),%YMM2,%YMM0 |
(100) 0x40f081 VSHUFPD $0x5,%YMM2,%YMM0,%YMM2 |
(100) 0x40f086 VBLENDPD $0x8,%YMM12,%YMM2,%YMM2 |
(100) 0x40f08c VINSERTF128 $0x1,0xa0(%R10,%R13,1),%YMM4,%YMM4 |
(100) 0x40f097 VBLENDPD $0xa,%YMM4,%YMM0,%YMM10 |
(100) 0x40f09d VFMADD231PD %YMM3,%YMM7,%YMM10 |
(100) 0x40f0a2 VDIVPD %YMM8,%YMM22,%YMM0 |
(100) 0x40f0a8 VFMADD231PD %YMM1,%YMM0,%YMM13 |
(100) 0x40f0ad VFMADD231PD %YMM5,%YMM7,%YMM2 |
(100) 0x40f0b2 VFMADD231PD %YMM6,%YMM0,%YMM11 |
(100) 0x40f0b7 VMOVUPD 0x80(%R10,%R13,1),%XMM1 |
(100) 0x40f0c1 VBLENDPD $0xc,0xa0(%R10,%R13,1),%YMM1,%YMM1 |
(100) 0x40f0cc VBLENDPD $0xa,%YMM1,%YMM4,%YMM8 |
(100) 0x40f0d2 VFMADD231PD %YMM15,%YMM7,%YMM8 |
(100) 0x40f0d7 VFMADD231PD %YMM14,%YMM0,%YMM9 |
(100) 0x40f0dc VMOVAPD %YMM13,%YMM0 |
(100) 0x40f0e0 VPERMT2PD %YMM11,%YMM16,%YMM0 |
(100) 0x40f0e6 VMOVAPD %YMM2,%YMM1 |
(100) 0x40f0ea VPERMT2PD %YMM10,%YMM17,%YMM1 |
(100) 0x40f0f0 VMOVAPD %YMM2,%YMM3 |
(100) 0x40f0f4 VPERMT2PD %YMM10,%YMM19,%YMM3 |
(100) 0x40f0fa VPERMT2PD %YMM2,%YMM16,%YMM10 |
(100) 0x40f100 VMOVAPD %YMM11,%YMM2 |
(100) 0x40f104 VPERMT2PD %YMM13,%YMM17,%YMM2 |
(100) 0x40f10a VPERMT2PD %YMM13,%YMM19,%YMM11 |
(100) 0x40f110 VPERMT2PD %YMM8,%YMM20,%YMM10 |
(100) 0x40f116 VBLENDPD $0x2,%YMM8,%YMM3,%YMM3 |
(100) 0x40f11c VPERMT2PD %YMM1,%YMM21,%YMM8 |
(100) 0x40f122 VBLENDPD $0x2,%YMM9,%YMM11,%YMM1 |
(100) 0x40f128 VPERMT2PD %YMM9,%YMM20,%YMM0 |
(100) 0x40f12e VPERMT2PD %YMM2,%YMM21,%YMM9 |
(100) 0x40f134 VMOVUPD %YMM3,0x80(%R10,%R13,1) |
(100) 0x40f13e VMOVUPD %YMM1,0x20(%R10,%R13,1) |
(100) 0x40f145 VMOVUPD %YMM9,0x40(%R10,%R13,1) |
(100) 0x40f14c VMOVUPD %YMM8,0xa0(%R10,%R13,1) |
(100) 0x40f156 VMOVUPD %YMM10,0x60(%R10,%R13,1) |
(100) 0x40f15d VMOVUPD %YMM0,(%R10,%R13,1) |
(100) 0x40f163 ADD $0x8,%RBX |
(100) 0x40f167 ADD $0xc0,%R13 |
(100) 0x40f16e CMP %EDX,%EBX |
(100) 0x40f170 JLE 40ef30 |
(98) 0x40f176 CMP %R14D,%R8D |
(98) 0x40f179 JE 40ee10 |
(98) 0x40f17f JMP 40f184 |
(98) 0x40f181 XOR %R14D,%R14D |
(98) 0x40f184 SUB %R14D,%R8D |
(98) 0x40f187 MOVSXD %R14D,%RDX |
(98) 0x40f18a LEA (%RDX,%RDX,2),%RBX |
(98) 0x40f18e LEA (%RCX,%RBX,8),%RCX |
(98) 0x40f192 ADD %RCX,%R10 |
(98) 0x40f195 ADD %RCX,%R11 |
(98) 0x40f198 ADD %RSI,%RDX |
(98) 0x40f19b LEA (%R15,%RDX,4),%RCX |
(98) 0x40f19f XOR %EDX,%EDX |
(98) 0x40f1a1 XOR %EBX,%EBX |
(98) 0x40f1a3 NOPW %CS:(%RAX,%RAX,1) |
(99) 0x40f1b0 MOVSXD (%RCX,%RBX,4),%R14 |
(99) 0x40f1b4 SAL $0x4,%R14 |
(99) 0x40f1b8 VDIVSD 0x8(%R9,%R14,1),%XMM23,%XMM0 |
(99) 0x40f1c0 VMOVUPD (%R11,%RDX,1),%XMM1 |
(99) 0x40f1c6 VMOVDDUP %XMM0,%XMM2 |
(99) 0x40f1ca VFMADD213PD (%R10,%RDX,1),%XMM1,%XMM2 |
(99) 0x40f1d0 VMOVUPD %XMM2,(%R10,%RDX,1) |
(99) 0x40f1d6 VMOVSD 0x10(%R11,%RDX,1),%XMM1 |
(99) 0x40f1dd VFMADD213SD 0x10(%R10,%RDX,1),%XMM0,%XMM1 |
(99) 0x40f1e4 VMOVSD %XMM1,0x10(%R10,%RDX,1) |
(99) 0x40f1eb INC %RBX |
(99) 0x40f1ee ADD $0x18,%RDX |
(99) 0x40f1f2 CMP %EBX,%R8D |
(99) 0x40f1f5 JNE 40f1b0 |
(98) 0x40f1f7 JMP 40ee10 |
0x40f1fc NOPL (%RAX) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_invoke_task_func | libiomp5.so |
Path / |
Source file and lines | timestep.c:85-96 |
Module | exec |
nb instructions | 64 |
nb uops | 66 |
loop length | 247 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 6 |
used zmm registers | 0 |
nb stack references | 8 |
micro-operation queue | 11.00 cycles |
front end | 11.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.80 | 1.80 | 6.33 | 6.33 | 9.50 | 2.00 | 1.80 | 9.50 | 9.50 | 9.50 | 1.60 | 6.33 |
cycles | 1.80 | 1.80 | 6.33 | 6.33 | 9.50 | 2.00 | 1.80 | 9.50 | 9.50 | 9.50 | 1.60 | 6.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 10.87-10.92 |
Stall cycles | 0.00 |
Front-end | 11.00 |
Dispatch | 9.50 |
Overall L1 | 11.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 21% |
load | 71% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 10% |
load | 6% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 17% |
load | 37% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x38,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0,-0x44(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9D,-0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x40(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x44(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x30(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x2c(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x62c950,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,-0x3c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 402d60 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x30(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x2c(%RBP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 40edae <advancePosition.extracted+0x8e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x62c970,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x3c(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x38,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 402c10 <__kmpc_for_static_fini@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VMOVQ %R15,%XMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV -0x50(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RCX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RCX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x38(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VPBROADCASTQ %XMM23,%YMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x6,%ESI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVUPD 0x138fa(%RIP),%YMM16 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x13850(%RIP),%YMM17 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x13866(%RIP),%YMM19 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x1389c(%RIP),%YMM20 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x138b2(%RIP),%YMM21 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
JMP 40ee24 <advancePosition.extracted+0x104> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | timestep.c:85-96 |
Module | exec |
nb instructions | 64 |
nb uops | 66 |
loop length | 247 |
used x86 registers | 14 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 6 |
used zmm registers | 0 |
nb stack references | 8 |
micro-operation queue | 11.00 cycles |
front end | 11.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.80 | 1.80 | 6.33 | 6.33 | 9.50 | 2.00 | 1.80 | 9.50 | 9.50 | 9.50 | 1.60 | 6.33 |
cycles | 1.80 | 1.80 | 6.33 | 6.33 | 9.50 | 2.00 | 1.80 | 9.50 | 9.50 | 9.50 | 1.60 | 6.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 10.87-10.92 |
Stall cycles | 0.00 |
Front-end | 11.00 |
Dispatch | 9.50 |
Overall L1 | 11.00 |
all | 4% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 21% |
load | 71% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
all | 10% |
load | 6% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 17% |
load | 37% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 10% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x38,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0,-0x44(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9D,-0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x40(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x44(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x30(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x2c(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x62c950,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,-0x3c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 402d60 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x30(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x2c(%RBP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 40edae <advancePosition.extracted+0x8e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x62c970,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x3c(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x38,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 402c10 <__kmpc_for_static_fini@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VMOVQ %R15,%XMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV -0x50(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RCX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RCX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x38(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VPBROADCASTQ %XMM23,%YMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x6,%ESI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVUPD 0x138fa(%RIP),%YMM16 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x13850(%RIP),%YMM17 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x13866(%RIP),%YMM19 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x1389c(%RIP),%YMM20 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVUPD 0x138b2(%RIP),%YMM21 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
JMP 40ee24 <advancePosition.extracted+0x104> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼advancePosition.extracted– | 1.98 | 0.42 |
▼Loop 98 - timestep.c:86-96 - exec– | 0.03 | 0.01 |
○Loop 100 - timestep.c:88-94 - exec | 1.71 | 0.36 |
○Loop 99 - timestep.c:88-94 - exec | 0.24 | 0.05 |
○Loop 101 - timestep.c:88-94 - exec | 0 | 0 |