Function: randomDisplacements.extracted | Module: exec | Source: initAtoms.c:194-204 [...] | Coverage: 0.02% |
---|
Function: randomDisplacements.extracted | Module: exec | Source: initAtoms.c:194-204 [...] | Coverage: 0.02% |
---|
/scratch_na/users/xoserete/qaas_runs/171-419-7821/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c: 45 - 70 |
-------------------------------------------------------------------------------- |
45: *seed *= UINT64_C(437799614237992725); |
46: *seed %= UINT64_C(2305843009213693951); |
47: |
48: return *seed*convertToDouble; |
[...] |
68: uint32_t s2 = (id+callSite) * UINT32_C(2654435761); |
69: |
70: uint64_t iSeed = (UINT64_C(0x100000000) * s1) + s2; |
/scratch_na/users/xoserete/qaas_runs/171-419-7821/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 194 - 204 |
-------------------------------------------------------------------------------- |
194: #pragma omp parallel for |
195: for (int iBox=0; iBox<s->boxes->nLocalBoxes; ++iBox) |
196: { |
197: for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff) |
198: { |
199: uint64_t seed = mkSeed(s->atoms->gid[iOff], 457); |
200: s->atoms->r[iOff][0] += (2.0*lcg61(&seed)-1.0) * delta; |
201: s->atoms->r[iOff][1] += (2.0*lcg61(&seed)-1.0) * delta; |
202: s->atoms->r[iOff][2] += (2.0*lcg61(&seed)-1.0) * delta; |
203: } |
204: } |
0x40a490 PUSH %RBP |
0x40a491 MOV %RSP,%RBP |
0x40a494 PUSH %R15 |
0x40a496 PUSH %R14 |
0x40a498 PUSH %R13 |
0x40a49a PUSH %R12 |
0x40a49c PUSH %RBX |
0x40a49d SUB $0x28,%RSP |
0x40a4a1 MOV %RCX,%R15 |
0x40a4a4 MOV %RDX,-0x48(%RBP) |
0x40a4a8 MOVL $0,-0x3c(%RBP) |
0x40a4af MOV (%RDI),%ESI |
0x40a4b1 MOVL $0,-0x30(%RBP) |
0x40a4b8 MOV %R9D,-0x2c(%RBP) |
0x40a4bc MOVL $0x1,-0x38(%RBP) |
0x40a4c3 SUB $0x8,%RSP |
0x40a4c7 LEA -0x38(%RBP),%RAX |
0x40a4cb LEA -0x3c(%RBP),%RCX |
0x40a4cf LEA -0x30(%RBP),%R8 |
0x40a4d3 LEA -0x2c(%RBP),%R9 |
0x40a4d7 MOV $0x62e6f0,%EDI |
0x40a4dc MOV %ESI,-0x34(%RBP) |
0x40a4df MOV $0x22,%EDX |
0x40a4e4 PUSH $0x1 |
0x40a4e6 PUSH $0x1 |
0x40a4e8 PUSH %RAX |
0x40a4e9 CALL 403130 <__kmpc_for_static_init_4@plt> |
0x40a4ee ADD $0x20,%RSP |
0x40a4f2 MOV -0x30(%RBP),%ESI |
0x40a4f5 MOV -0x2c(%RBP),%EDI |
0x40a4f8 CMP %EDI,%ESI |
0x40a4fa JBE 40a517 |
0x40a4fc MOV $0x62e710,%EDI |
0x40a501 MOV -0x34(%RBP),%ESI |
0x40a504 ADD $0x28,%RSP |
0x40a508 POP %RBX |
0x40a509 POP %R12 |
0x40a50b POP %R13 |
0x40a50d POP %R14 |
0x40a50f POP %R15 |
0x40a511 POP %RBP |
0x40a512 JMP 402fe0 |
0x40a517 VMOVQ %R15,%XMM0 |
0x40a51c MOV $0x613606df9756715,%R8 |
0x40a526 MOV -0x48(%RBP),%RAX |
0x40a52a MOV 0x18(%RAX),%RAX |
0x40a52e SUB %RSI,%RDI |
0x40a531 MOV 0x78(%RAX),%R9 |
0x40a535 MOV %ESI,%R10D |
0x40a538 SAL $0x6,%R10D |
0x40a53c XOR %R15D,%R15D |
0x40a53f MOV $0x9,%R11D |
0x40a545 VMOVDDUP 0x1894b(%RIP),%XMM1 |
0x40a54d VMOVDDUP 0x1d62b(%RIP),%XMM2 |
0x40a555 VMOVSD 0x1893b(%RIP),%XMM3 |
0x40a55d VMOVSD 0x1d61b(%RIP),%XMM4 |
0x40a565 JMP 40a584 |
0x40a567 NOPW (%RAX,%RAX,1) |
(78) 0x40a570 LEA 0x1(%R15),%RAX |
(78) 0x40a574 ADD $0x40,%R10D |
(78) 0x40a578 CMP %RDI,%R15 |
(78) 0x40a57b MOV %RAX,%R15 |
(78) 0x40a57e JE 40a4fc |
(78) 0x40a584 LEA (%R15,%RSI,1),%RAX |
(78) 0x40a588 MOV (%R9,%RAX,4),%R12D |
(78) 0x40a58c TEST %R12D,%R12D |
(78) 0x40a58f JLE 40a570 |
(78) 0x40a591 MOV %R10D,%R13D |
(78) 0x40a594 LEA (,%R13,8),%RAX |
(78) 0x40a59c LEA (%RAX,%RAX,2),%RAX |
(78) 0x40a5a0 SAL $0x2,%R13 |
(78) 0x40a5a4 MOV -0x48(%RBP),%RCX |
(78) 0x40a5a8 MOV 0x20(%RCX),%RCX |
(78) 0x40a5ac MOV 0x18(%RCX),%RDX |
(78) 0x40a5b0 VPBROADCASTQ %XMM0,%XMM5 |
(78) 0x40a5b5 LEA (%RDX,%RAX,1),%R14 |
(78) 0x40a5b9 ADD $0x10,%R14 |
(78) 0x40a5bd ADD 0x8(%RCX),%R13 |
(78) 0x40a5c1 XOR %EBX,%EBX |
(78) 0x40a5c3 NOPW %CS:(%RAX,%RAX,1) |
(79) 0x40a5d0 IMUL $-0x61c8864f,(%R13,%RBX,4),%EAX |
(79) 0x40a5d9 LEA 0x71083cf9(%RAX),%ECX |
(79) 0x40a5df SAL $0x20,%RAX |
(79) 0x40a5e3 OR %RCX,%RAX |
(79) 0x40a5e6 IMUL %R8,%RAX |
(79) 0x40a5ea MOV %RAX,%RDX |
(79) 0x40a5ed MULX %R11,%RCX,%RCX |
(79) 0x40a5f2 SUB %RCX,%RDX |
(79) 0x40a5f5 SHR $0x1,%RDX |
(79) 0x40a5f8 ADD %RCX,%RDX |
(79) 0x40a5fb SHR $0x3c,%RDX |
(79) 0x40a5ff MOV %RDX,%RCX |
(79) 0x40a602 SAL $0x3d,%RCX |
(79) 0x40a606 SUB %RCX,%RDX |
(79) 0x40a609 ADD %RAX,%RDX |
(79) 0x40a60c IMUL %R8,%RDX |
(79) 0x40a610 MULX %R11,%RCX,%RCX |
(79) 0x40a615 MOV %RDX,%RAX |
(79) 0x40a618 SUB %RCX,%RAX |
(79) 0x40a61b SHR $0x1,%RAX |
(79) 0x40a61e ADD %RCX,%RAX |
(79) 0x40a621 SHR $0x3c,%RAX |
(79) 0x40a625 MOV %RAX,%RCX |
(79) 0x40a628 SAL $0x3d,%RCX |
(79) 0x40a62c SUB %RCX,%RAX |
(79) 0x40a62f ADD %RDX,%RAX |
(79) 0x40a632 IMUL %R8,%RAX |
(79) 0x40a636 MOV %RAX,%RDX |
(79) 0x40a639 MULX %R11,%RCX,%RCX |
(79) 0x40a63e SUB %RCX,%RDX |
(79) 0x40a641 SHR $0x1,%RDX |
(79) 0x40a644 ADD %RCX,%RDX |
(79) 0x40a647 SHR $0x3c,%RDX |
(79) 0x40a64b MOV %RDX,%RCX |
(79) 0x40a64e SAL $0x3d,%RCX |
(79) 0x40a652 SUB %RCX,%RDX |
(79) 0x40a655 ADD %RAX,%RDX |
(79) 0x40a658 IMUL %R8,%RDX |
(79) 0x40a65c MULX %R11,%RCX,%RCX |
(79) 0x40a661 MOV %RDX,%RAX |
(79) 0x40a664 SUB %RCX,%RAX |
(79) 0x40a667 SHR $0x1,%RAX |
(79) 0x40a66a ADD %RCX,%RAX |
(79) 0x40a66d SHR $0x3c,%RAX |
(79) 0x40a671 MOV %RAX,%RCX |
(79) 0x40a674 SAL $0x3d,%RCX |
(79) 0x40a678 SUB %RCX,%RAX |
(79) 0x40a67b ADD %RDX,%RAX |
(79) 0x40a67e IMUL %R8,%RAX |
(79) 0x40a682 MOV %RAX,%RDX |
(79) 0x40a685 MULX %R11,%RCX,%RCX |
(79) 0x40a68a SUB %RCX,%RDX |
(79) 0x40a68d SHR $0x1,%RDX |
(79) 0x40a690 ADD %RCX,%RDX |
(79) 0x40a693 SHR $0x3c,%RDX |
(79) 0x40a697 MOV %RDX,%RCX |
(79) 0x40a69a SAL $0x3d,%RCX |
(79) 0x40a69e SUB %RCX,%RDX |
(79) 0x40a6a1 ADD %RAX,%RDX |
(79) 0x40a6a4 IMUL %R8,%RDX |
(79) 0x40a6a8 MULX %R11,%RCX,%RCX |
(79) 0x40a6ad MOV %RDX,%RAX |
(79) 0x40a6b0 SUB %RCX,%RAX |
(79) 0x40a6b3 SHR $0x1,%RAX |
(79) 0x40a6b6 ADD %RCX,%RAX |
(79) 0x40a6b9 SHR $0x3c,%RAX |
(79) 0x40a6bd MOV %RAX,%RCX |
(79) 0x40a6c0 SAL $0x3d,%RCX |
(79) 0x40a6c4 SUB %RCX,%RAX |
(79) 0x40a6c7 ADD %RDX,%RAX |
(79) 0x40a6ca IMUL %R8,%RAX |
(79) 0x40a6ce MOV %RAX,%RDX |
(79) 0x40a6d1 MULX %R11,%RCX,%RCX |
(79) 0x40a6d6 SUB %RCX,%RDX |
(79) 0x40a6d9 SHR $0x1,%RDX |
(79) 0x40a6dc ADD %RCX,%RDX |
(79) 0x40a6df SHR $0x3c,%RDX |
(79) 0x40a6e3 MOV %RDX,%RCX |
(79) 0x40a6e6 SAL $0x3d,%RCX |
(79) 0x40a6ea SUB %RCX,%RDX |
(79) 0x40a6ed ADD %RAX,%RDX |
(79) 0x40a6f0 IMUL %R8,%RDX |
(79) 0x40a6f4 MULX %R11,%RCX,%RCX |
(79) 0x40a6f9 MOV %RDX,%RAX |
(79) 0x40a6fc SUB %RCX,%RAX |
(79) 0x40a6ff SHR $0x1,%RAX |
(79) 0x40a702 ADD %RCX,%RAX |
(79) 0x40a705 SHR $0x3c,%RAX |
(79) 0x40a709 MOV %RAX,%RCX |
(79) 0x40a70c SAL $0x3d,%RCX |
(79) 0x40a710 SUB %RCX,%RAX |
(79) 0x40a713 ADD %RDX,%RAX |
(79) 0x40a716 IMUL %R8,%RAX |
(79) 0x40a71a MOV %RAX,%RDX |
(79) 0x40a71d MULX %R11,%RCX,%RCX |
(79) 0x40a722 SUB %RCX,%RDX |
(79) 0x40a725 SHR $0x1,%RDX |
(79) 0x40a728 ADD %RCX,%RDX |
(79) 0x40a72b SHR $0x3c,%RDX |
(79) 0x40a72f MOV %RDX,%RCX |
(79) 0x40a732 SAL $0x3d,%RCX |
(79) 0x40a736 SUB %RCX,%RDX |
(79) 0x40a739 ADD %RAX,%RDX |
(79) 0x40a73c IMUL %R8,%RDX |
(79) 0x40a740 MULX %R11,%RAX,%RAX |
(79) 0x40a745 MOV %RDX,%RCX |
(79) 0x40a748 SUB %RAX,%RCX |
(79) 0x40a74b SHR $0x1,%RCX |
(79) 0x40a74e ADD %RAX,%RCX |
(79) 0x40a751 SHR $0x3c,%RCX |
(79) 0x40a755 MOV %RCX,%RAX |
(79) 0x40a758 SAL $0x3d,%RAX |
(79) 0x40a75c SUB %RAX,%RCX |
(79) 0x40a75f ADD %RDX,%RCX |
(79) 0x40a762 IMUL %R8,%RCX |
(79) 0x40a766 MOV %RCX,%RDX |
(79) 0x40a769 MULX %R11,%RDX,%RDX |
(79) 0x40a76e MOV %RCX,%RAX |
(79) 0x40a771 SUB %RDX,%RAX |
(79) 0x40a774 SHR $0x1,%RAX |
(79) 0x40a777 ADD %RDX,%RAX |
(79) 0x40a77a SHR $0x3c,%RAX |
(79) 0x40a77e MOV %RAX,%RDX |
(79) 0x40a781 SAL $0x3d,%RDX |
(79) 0x40a785 SUB %RDX,%RAX |
(79) 0x40a788 ADD %RCX,%RAX |
(79) 0x40a78b VCVTSI2SD %RAX,%XMM0,%XMM6 |
(79) 0x40a790 IMUL %R8,%RAX |
(79) 0x40a794 MOV %RAX,%RDX |
(79) 0x40a797 MULX %R11,%RCX,%RCX |
(79) 0x40a79c MOV %RAX,%RDX |
(79) 0x40a79f SUB %RCX,%RDX |
(79) 0x40a7a2 SHR $0x1,%RDX |
(79) 0x40a7a5 ADD %RCX,%RDX |
(79) 0x40a7a8 SHR $0x3c,%RDX |
(79) 0x40a7ac MOV %RDX,%RCX |
(79) 0x40a7af SAL $0x3d,%RCX |
(79) 0x40a7b3 SUB %RCX,%RDX |
(79) 0x40a7b6 ADD %RAX,%RDX |
(79) 0x40a7b9 VCVTSI2SD %RDX,%XMM0,%XMM7 |
(79) 0x40a7be VUNPCKLPD %XMM7,%XMM6,%XMM6 |
(79) 0x40a7c2 IMUL %R8,%RDX |
(79) 0x40a7c6 VFMADD213PD %XMM2,%XMM1,%XMM6 |
(79) 0x40a7cb MULX %R11,%RAX,%RAX |
(79) 0x40a7d0 VFMADD213PD -0x10(%R14),%XMM5,%XMM6 |
(79) 0x40a7d6 MOV %RDX,%RCX |
(79) 0x40a7d9 SUB %RAX,%RCX |
(79) 0x40a7dc SHR $0x1,%RCX |
(79) 0x40a7df ADD %RAX,%RCX |
(79) 0x40a7e2 SHR $0x3c,%RCX |
(79) 0x40a7e6 MOV %RCX,%RAX |
(79) 0x40a7e9 SAL $0x3d,%RAX |
(79) 0x40a7ed SUB %RAX,%RCX |
(79) 0x40a7f0 VMOVUPD %XMM6,-0x10(%R14) |
(79) 0x40a7f6 ADD %RDX,%RCX |
(79) 0x40a7f9 VCVTSI2SD %RCX,%XMM0,%XMM6 |
(79) 0x40a7fe VFMADD213SD %XMM4,%XMM3,%XMM6 |
(79) 0x40a803 VFMADD213SD (%R14),%XMM0,%XMM6 |
(79) 0x40a808 VMOVSD %XMM6,(%R14) |
(79) 0x40a80d ADD $0x18,%R14 |
(79) 0x40a811 INC %RBX |
(79) 0x40a814 CMP %EBX,%R12D |
(79) 0x40a817 JNE 40a5d0 |
(78) 0x40a81d JMP 40a570 |
0x40a822 NOPW %CS:(%RAX,%RAX,1) |
0x40a82c NOPL (%RAX) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_invoke_task_func | libiomp5.so |
Path / |
Source file and lines | initAtoms.c:194-204 |
Module | exec |
nb instructions | 60 |
nb uops | 61 |
loop length | 238 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 5 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 10.17 cycles |
front end | 10.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.00 | 2.00 | 5.67 | 5.67 | 8.00 | 2.00 | 2.00 | 8.00 | 8.00 | 8.00 | 2.00 | 5.67 |
cycles | 2.00 | 2.00 | 5.67 | 5.67 | 8.00 | 2.00 | 2.00 | 8.00 | 8.00 | 8.00 | 2.00 | 5.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 10.18-10.24 |
Stall cycles | 0.00 |
Front-end | 10.17 |
Dispatch | 8.00 |
Overall L1 | 10.17 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 9% |
load | 12% |
store | 7% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 9% |
load | 12% |
store | 7% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 8% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x28,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0,-0x3c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9D,-0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x38(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x3c(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x30(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x2c(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x62e6f0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,-0x34(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 403130 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x30(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x2c(%RBP),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %EDI,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 40a517 <randomDisplacements.extracted+0x87> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x62e710,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x34(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x28,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 402fe0 <__kmpc_for_static_fini@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VMOVQ %R15,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV $0x613606df9756715,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
MOV -0x48(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RSI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x78(%RAX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %ESI,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x6,%R10D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x9,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVDDUP 0x1894b(%RIP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVDDUP 0x1d62b(%RIP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x1893b(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x1d61b(%RIP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 40a584 <randomDisplacements.extracted+0xf4> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | initAtoms.c:194-204 |
Module | exec |
nb instructions | 60 |
nb uops | 61 |
loop length | 238 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 5 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 10.17 cycles |
front end | 10.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.00 | 2.00 | 5.67 | 5.67 | 8.00 | 2.00 | 2.00 | 8.00 | 8.00 | 8.00 | 2.00 | 5.67 |
cycles | 2.00 | 2.00 | 5.67 | 5.67 | 8.00 | 2.00 | 2.00 | 8.00 | 8.00 | 8.00 | 2.00 | 5.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 10.18-10.24 |
Stall cycles | 0.00 |
Front-end | 10.17 |
Dispatch | 8.00 |
Overall L1 | 10.17 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 9% |
load | 12% |
store | 7% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 8% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 9% |
load | 12% |
store | 7% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 8% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x28,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0,-0x3c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOVL $0,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9D,-0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVL $0x1,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x38(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x3c(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x30(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA -0x2c(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x62e6f0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %ESI,-0x34(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
CALL 403130 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x30(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x2c(%RBP),%EDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %EDI,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 40a517 <randomDisplacements.extracted+0x87> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV $0x62e710,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV -0x34(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD $0x28,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 402fe0 <__kmpc_for_static_fini@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
VMOVQ %R15,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
MOV $0x613606df9756715,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
MOV -0x48(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SUB %RSI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x78(%RAX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %ESI,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SAL $0x6,%R10D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x9,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVDDUP 0x1894b(%RIP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVDDUP 0x1d62b(%RIP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x1893b(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0x1d61b(%RIP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 40a584 <randomDisplacements.extracted+0xf4> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼randomDisplacements.extracted– | 0.02 | 0 |
▼Loop 78 - initAtoms.c:195-204 - exec– | 0 | 0 |
○Loop 79 - initAtoms.c:197-202 - exec | 0.02 | 0 |