Function: main | Module: exec | Source: main.c:50-191 [...] | Coverage: 0.03% |
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Function: main | Module: exec | Source: main.c:50-191 [...] | Coverage: 0.03% |
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/home/hbollore/qaas-runs/170-256-3563/intel/HACCmk/build/HACCmk/src/main.c: 50 - 191 |
-------------------------------------------------------------------------------- |
50: { |
[...] |
65: rank = 0; |
[...] |
73: printf( "count is set %d\n", count ); |
74: printf( "Total MPI ranks %d\n", nprocs ); |
75: } |
76: |
77: if (argc == 2 && strncmp(argv[1], "-s", 2) == 0) |
78: NN = 15000; |
79: |
80: printf( "N is set %ld\n", NN ); |
81: |
82: #pragma omp parallel |
[...] |
97: for ( n = 400; n < NN; n = n + 20 ) |
98: { |
99: /* Initial data preparation */ |
100: fcoeff = 0.23f; |
101: fsrrmax2 = 0.5f; |
102: mp_rsm2 = 0.03f; |
103: dx1 = 1.0f/(float)n; |
104: dy1 = 2.0f/(float)n; |
105: dz1 = 3.0f/(float)n; |
106: xx[0] = 0.f; |
107: yy[0] = 0.f; |
108: zz[0] = 0.f; |
109: mass[0] = 2.f; |
110: |
111: for ( i = 1; i < n; i++ ) |
112: { |
113: xx[i] = xx[i-1] + dx1; |
114: yy[i] = yy[i-1] + dy1; |
115: zz[i] = zz[i-1] + dz1; |
116: mass[i] = (float)i * 0.01f + xx[i]; |
117: } |
118: |
119: for ( i = 0; i < n; i++ ) |
120: { |
121: vx1[i] = 0.f; |
122: vy1[i] = 0.f; |
123: vz1[i] = 0.f; |
[...] |
136: t1 = mysecond(); |
137: #endif |
138: |
139: #pragma omp parallel for private( dx1, dy1, dz1 ) |
[...] |
152: t2 = mysecond(); |
[...] |
166: t3 = (t2 - t1) * 1e6; |
167: #endif |
168: |
169: elapsed = elapsed + t3; |
[...] |
183: if ( rank == 0 ) |
184: { |
185: printf( "\nKernel elapsed time, s: %18.8lf\n", elapsed*1e-6 ); |
[...] |
191: return 0; |
0x400cc0 STR D12, [SP, #368]! |
0x400cc4 STP D11, D10, [SP, #16] |
0x400cc8 STP D9, D8, [SP, #32] |
0x400ccc STP X29, X30, [SP, #48] |
0x400cd0 STP X28, X27, [SP, #64] |
0x400cd4 STP X26, X25, [SP, #80] |
0x400cd8 STP X24, X23, [SP, #96] |
0x400cdc STP X22, X21, [SP, #112] |
0x400ce0 STP X20, X19, [SP, #128] |
0x400ce4 ADD X29, SP, #48 |
0x400ce8 ADDVL SP, SP, #60 |
0x400cec SUB SP, SP, #32 |
0x400cf0 ORR X20, XZR, X1 |
0x400cf4 ORR W21, WZR, W0 |
0x400cf8 MOVZ W25, #34464 |
0x400cfc MOVZ W8, #3000 |
0x400d00 ADRP X0, |
0x400d04 ADD X0, X0, #2296 |
0x400d08 STP WZR, W8, [SP, #16] |
0x400d0c MOVZ W1, #3000 |
0x400d10 MOVK W25, #1 |
0x400d14 BL 400b30 |
0x400d18 ADRP X0, |
0x400d1c ADD X0, X0, #2313 |
0x400d20 MOVZ W1, #1 |
0x400d24 BL 400b30 |
0x400d28 CMP W21, #2 |
0x400d2c B.NE 400d50 |
0x400d30 LDR X0, [X20, #8] |
0x400d34 ADRP X1, |
0x400d38 ADD X1, X1, #2333 |
0x400d3c MOVZ W2, #2 |
0x400d40 BL 400b00 |
0x400d44 CMP W0, #0 |
0x400d48 MOVZ W8, #15000 |
0x400d4c CSEL X25, X8, X25, #0 |
0x400d50 ORR X1, XZR, X25 |
0x400d54 ADRP X0, |
0x400d58 ADD X0, X0, #2336 |
0x400d5c BL 400b30 |
0x400d60 ADRP X0, |
0x400d64 ADD X0, X0, #3336 |
0x400d68 ADRP X2, |
0x400d6c ADD X2, X2, #464 |
0x400d70 ADD X3, SP, #16 |
0x400d74 MOVZ W1, #1 |
0x400d78 BL 400b20 |
0x400d7c CNTW X9, ALL |
0x400d80 ADRP X28, |
0x400d84 ADD X28, X28, #116 |
0x400d88 ADRP X27, |
0x400d8c ADD X27, X27, #2804 |
0x400d90 INDEX Z0.S, #0, #1 |
0x400d94 MOVI D9, #0 |
0x400d98 FMOV S10, #1.0000000 |
0x400d9c ADRP X24, |
0x400da0 ADD X24, X24, #1396 |
0x400da4 MOVZ W10, #55050 |
0x400da8 FMOV S11, #3.0000000 |
0x400dac ADRP X19, |
0x400db0 ADD X19, X19, #4084 |
0x400db4 MOVZ W8, #400 |
0x400db8 STR W8, [SP, #24] |
0x400dbc MOVK W10, #15395 |
0x400dc0 SUB X11, X29, #48 |
0x400dc4 PTRUE P0.S, ALL |
0x400dc8 MOVPRFX Z1, Z0 |
0x400dcc UCVTF Z1.S, P0/M, Z0.S |
0x400dd0 STR Z1, [X11, #509, MUL VL] |
0x400dd4 ADD Z0.S, Z0.S, #1 |
0x400dd8 UCVTF S12, W9 |
0x400ddc DUP Z31.S, W9 |
0x400de0 ADDVL X9, X28, #1 |
0x400de4 ADD X26, X9, #4 |
0x400de8 ADDVL X9, X27, #1 |
0x400dec CNTH X16, ALL |
0x400df0 SUB X11, X29, #48 |
0x400df4 STR Z0, [X11, #508, MUL VL] |
0x400df8 ADD X20, X9, #4 |
0x400dfc ADDVL X9, X24, #1 |
0x400e00 DUP Z8.S, W10 |
0x400e04 MOVZ X23, #1 |
0x400e08 STR X25, [SP, #8] |
0x400e0c ADD X21, X9, #4 |
0x400e10 ADDVL X9, X19, #1 |
0x400e14 ADD X22, X9, #4 |
0x400e18 SUB X9, X29, #48 |
0x400e1c STR Z31, [X9, #511, MUL VL] |
0x400e20 SUB X9, X29, #48 |
0x400e24 STR Z8, [X9, #510, MUL VL] |
0x400e28 B 400ebc |
(4) 0x400e2c ORR W1, WZR, WZR |
(4) 0x400e30 ORR X2, XZR, X25 |
(4) 0x400e34 BL 400b60 |
(4) 0x400e38 LDR X25, [SP, #8] |
(1) 0x400e3c BL 4013d0 |
(1) 0x400e40 ADD X5, SP, #44 |
(1) 0x400e44 ADD X6, SP, #40 |
(1) 0x400e48 ADD X3, SP, #20 |
(1) 0x400e4c ADD X4, SP, #24 |
(1) 0x400e50 FMOV D8, D0 |
(1) 0x400e54 ADD X7, SP, #28 |
(1) 0x400e58 ADRP X0, |
(1) 0x400e5c ADD X0, X0, #3408 |
(1) 0x400e60 MOVZ W1, #5 |
(1) 0x400e64 ADRP X2, |
(1) 0x400e68 ADD X2, X2, #528 |
(1) 0x400e6c ADDVL X5, X5, #4 |
(1) 0x400e70 ADDVL X6, X6, #4 |
(1) 0x400e74 BL 400b20 |
(1) 0x400e78 BL 4013d0 |
(1) 0x400e7c LDRSW X8, [SP, #24] |
(1) 0x400e80 MOVZ X9, #33920 |
(1) 0x400e84 FSUB D0, D0, S8 |
(1) 0x400e88 CNTH X16, ALL |
(1) 0x400e8c PTRUE P0.S, ALL |
(1) 0x400e90 MOVK X9, #16686 |
(1) 0x400e94 FMOV D1, X9 |
(1) 0x400e98 SUB X9, X29, #48 |
(1) 0x400e9c ADD X8, X8, #20 |
(1) 0x400ea0 FMADD D9, D0, D1, D9 |
(1) 0x400ea4 STR W8, [SP, #24] |
(1) 0x400ea8 CMP X25, X8 |
(1) 0x400eac LDR Z31, [X9, #511, MUL VL] |
(1) 0x400eb0 SUB X9, X29, #48 |
(1) 0x400eb4 LDR Z8, [X9, #510, MUL VL] |
(1) 0x400eb8 B.LE 401174 |
(1) 0x400ebc MOVZ W9, #34079 |
(1) 0x400ec0 ADDVL X10, SP, #4 |
(1) 0x400ec4 CMP W8, #1 |
(1) 0x400ec8 MOVK W9, #15979 |
(1) 0x400ecc STR W9, [SP, #28] |
(1) 0x400ed0 MOVZ W9, #16128 |
(1) 0x400ed4 STR W9, [X10, #44] |
(1) 0x400ed8 MOVZ W9, #49807 |
(1) 0x400edc ADDVL X10, SP, #4 |
(1) 0x400ee0 MOVK W9, #15605 |
(1) 0x400ee4 STR W9, [X10, #40] |
(1) 0x400ee8 ADRP X9, |
(1) 0x400eec MOVZ W10, #16384 |
(1) 0x400ef0 STR WZR, [X9, #116] |
(1) 0x400ef4 ADRP X9, |
(1) 0x400ef8 STR WZR, [X9, #2804] |
(1) 0x400efc ADRP X9, |
(1) 0x400f00 STR WZR, [X9, #1396] |
(1) 0x400f04 ADRP X9, |
(1) 0x400f08 STR W10, [X9, #4084] |
(1) 0x400f0c B.LE 40107c |
(1) 0x400f10 SCVTF S0, W8 |
(1) 0x400f14 ORR W9, WZR, W8 |
(1) 0x400f18 SUB X10, X9, #1 |
(1) 0x400f1c FDIV S0, S10, S0 |
(1) 0x400f20 CMP X10, X16 |
(1) 0x400f24 FMUL S2, S0, S11 |
(1) 0x400f28 FADD S1, S0, S0 |
(1) 0x400f2c B.CS 400f44 |
(1) 0x400f30 MOVI D3, #0 |
(1) 0x400f34 MOVI D4, #0 |
(1) 0x400f38 MOVZ W10, #1 |
(1) 0x400f3c MOVI D5, #0 |
(1) 0x400f40 B 401040 |
(1) 0x400f44 UDIV X12, X10, X16 |
(1) 0x400f48 SUB X14, X29, #48 |
(1) 0x400f4c DUP Z6.S, Z2.S[0] |
(1) 0x400f50 DUP Z16.S, Z1.S[0] |
(1) 0x400f54 DUP Z18.S, Z0.S[0] |
(1) 0x400f58 FMUL S7, S2, S12 |
(1) 0x400f5c FMUL S17, S1, S12 |
(1) 0x400f60 ORR X11, XZR, XZR |
(1) 0x400f64 LDR Z19, [X14, #509, MUL VL] |
(1) 0x400f68 SUB X14, X29, #48 |
(1) 0x400f6c LDR Z22, [X14, #508, MUL VL] |
(1) 0x400f70 DUP Z7.S, Z7.S[0] |
(1) 0x400f74 DUP Z17.S, Z17.S[0] |
(1) 0x400f78 FMUL Z21.S, Z6.S, Z19.S |
(1) 0x400f7c FMUL Z23.S, Z16.S, Z19.S |
(1) 0x400f80 FMUL Z24.S, Z18.S, Z19.S |
(1) 0x400f84 FMUL S19, S0, S12 |
(1) 0x400f88 DUP Z19.S, Z19.S[0] |
(1) 0x400f8c MADD X13, X12, X16, XZR |
(1) 0x400f90 DUP Z20.S, W16 |
(1) 0x400f94 SUB X12, X10, X13 |
(1) 0x400f98 ADD X10, X13, #1 |
(1) 0x400f9c SCVTF S5, X13 |
(1) 0x400fa0 FMUL S3, S2, S5 |
(1) 0x400fa4 FMUL S4, S1, S5 |
(1) 0x400fa8 FMUL S5, S0, S5 |
(5) 0x400fac UBFM X14, X11, #62, #61 |
(5) 0x400fb0 FADD Z27.S, Z24.S, Z19.S |
(5) 0x400fb4 FADD Z24.S, Z24.S, Z18.S |
(5) 0x400fb8 ADD X15, X28, X14 |
(5) 0x400fbc FADD Z25.S, Z21.S, Z7.S |
(5) 0x400fc0 FADD Z26.S, Z23.S, Z17.S |
(5) 0x400fc4 FADD Z23.S, Z23.S, Z16.S |
(5) 0x400fc8 FADD Z21.S, Z21.S, Z6.S |
(5) 0x400fcc ADD Z29.S, Z22.S, Z31.S |
(5) 0x400fd0 FADD Z28.S, Z27.S, Z18.S |
(5) 0x400fd4 FADD Z30.S, Z26.S, Z16.S |
(5) 0x400fd8 ST1W {Z24.S}, P0, [X15, X23,LSL #2] |
(5) 0x400fdc ADD X15, X27, X14 |
(5) 0x400fe0 ST1W {Z28.S}, P0, [X26, X11,LSL #2] |
(5) 0x400fe4 ST1W {Z23.S}, P0, [X15, X23,LSL #2] |
(5) 0x400fe8 ADD X15, X24, X14 |
(5) 0x400fec ADD X14, X19, X14 |
(5) 0x400ff0 FADD Z23.S, Z25.S, Z6.S |
(5) 0x400ff4 ST1W {Z30.S}, P0, [X20, X11,LSL #2] |
(5) 0x400ff8 ST1W {Z21.S}, P0, [X15, X23,LSL #2] |
(5) 0x400ffc ST1W {Z23.S}, P0, [X21, X11,LSL #2] |
(5) 0x401000 MOVPRFX Z21, Z22 |
(5) 0x401004 SCVTF Z21.S, P0/M, Z22.S |
(5) 0x401008 MOVPRFX Z23, Z29 |
(5) 0x40100c SCVTF Z23.S, P0/M, Z29.S |
(5) 0x401010 FMAD Z21.S, P0/M, Z8.S, Z24.S |
(5) 0x401014 FMAD Z23.S, P0/M, Z8.S, Z28.S |
(5) 0x401018 FADD Z24.S, Z27.S, Z19.S |
(5) 0x40101c ADD Z22.S, Z20.S, Z22.S |
(5) 0x401020 ST1W {Z21.S}, P0, [X14, X23,LSL #2] |
(5) 0x401024 ST1W {Z23.S}, P0, [X22, X11,LSL #2] |
(5) 0x401028 ADD X11, X11, X16 |
(5) 0x40102c FADD Z21.S, Z25.S, Z7.S |
(5) 0x401030 FADD Z23.S, Z26.S, Z17.S |
(5) 0x401034 CMP X13, X11 |
(5) 0x401038 B.NE 400fac |
(1) 0x40103c CBZ X12, 40107c |
(1) 0x401040 MOVZ W11, #55050 |
(1) 0x401044 MOVK W11, #15395 |
(6) 0x401048 SCVTF S6, W10 |
(6) 0x40104c FADD S5, S5, S0 |
(6) 0x401050 FADD S4, S4, S1 |
(6) 0x401054 FADD S3, S3, S2 |
(6) 0x401058 STR S5, [X28, X10,LSL #2] |
(6) 0x40105c STR S4, [X27, X10,LSL #2] |
(6) 0x401060 STR S3, [X24, X10,LSL #2] |
(6) 0x401064 FMOV S7, W11 |
(6) 0x401068 FMADD S6, S6, S7, S5 |
(6) 0x40106c STR S6, [X19, X10,LSL #2] |
(6) 0x401070 ADD X10, X10, #1 |
(6) 0x401074 CMP X9, X10 |
(6) 0x401078 B.NE 401048 |
(1) 0x40107c CMP W8, #1 |
(1) 0x401080 B.LT 400e3c |
(4) 0x401084 UBFM X25, X8, #62, #31 |
(4) 0x401088 RDVL X8, #1 |
(4) 0x40108c CMP X8, #17 |
(4) 0x401090 B.CS 4010c0 |
(4) 0x401094 ORR W1, WZR, WZR |
(4) 0x401098 ORR X2, XZR, X25 |
(4) 0x40109c ADRP X0, |
(4) 0x4010a0 ADD X0, X0, #2676 |
(4) 0x4010a4 BL 400b60 |
(4) 0x4010a8 DUP Z0.B, #0 |
(4) 0x4010ac B 4010f0 |
0x4010b0 HINT #0 |
0x4010b4 HINT #0 |
0x4010b8 HINT #0 |
0x4010bc HINT #0 |
(4) 0x4010c0 WHILELO P0.B, XZR, X25 |
(4) 0x4010c4 ORR X8, XZR, XZR |
(4) 0x4010c8 DUP Z0.B, #0 |
(4) 0x4010cc ADRP X9, |
(4) 0x4010d0 ADD X9, X9, #2676 |
(4) 0x4010d4 HINT #0 |
(4) 0x4010d8 HINT #0 |
(4) 0x4010dc HINT #0 |
(2) 0x4010e0 ST1B {Z0.B}, P0, [X9, X8] |
(2) 0x4010e4 INCP X8, P0.B |
(2) 0x4010e8 WHILELO P0.B, X8, X25 |
(2) 0x4010ec B.MI 4010e0 |
(4) 0x4010f0 RDVL X8, #1 |
(4) 0x4010f4 ADRP X0, |
(4) 0x4010f8 ADD X0, X0, #1268 |
(4) 0x4010fc CMP X8, #17 |
(4) 0x401100 B.CS 401120 |
(4) 0x401104 ORR W1, WZR, WZR |
(4) 0x401108 ORR X2, XZR, X25 |
(4) 0x40110c BL 400b60 |
(4) 0x401110 DUP Z0.B, #0 |
(4) 0x401114 B 401138 |
0x401118 HINT #0 |
0x40111c HINT #0 |
(3) 0x401120 WHILELO P0.B, XZR, X25 |
(3) 0x401124 ORR X8, XZR, XZR |
(0) 0x401128 ST1B {Z0.B}, P0, [X0, X8] |
(0) 0x40112c INCP X8, P0.B |
(0) 0x401130 WHILELO P0.B, X8, X25 |
(0) 0x401134 B.MI 401128 |
(4) 0x401138 RDVL X8, #1 |
(4) 0x40113c ADRP X0, |
(4) 0x401140 ADD X0, X0, #3956 |
(4) 0x401144 CMP X8, #17 |
(4) 0x401148 B.CC 400e2c |
(4) 0x40114c WHILELO P0.B, XZR, X25 |
(4) 0x401150 ORR X8, XZR, XZR |
(4) 0x401154 HINT #0 |
(4) 0x401158 HINT #0 |
(4) 0x40115c HINT #0 |
(7) 0x401160 ST1B {Z0.B}, P0, [X0, X8] |
(7) 0x401164 INCP X8, P0.B |
(7) 0x401168 WHILELO P0.B, X8, X25 |
(7) 0x40116c B.MI 401160 |
(4) 0x401170 B 400e38 |
0x401174 LDR W8, [SP, #16] |
0x401178 CBNZ W8, 401194 |
0x40117c ADRP X8, 40117c |
0x401180 ADRP X0, 401180 |
0x401184 ADD X0, X0, #2644 |
0x401188 LDR D0, [X8, #2288] |
0x40118c FMUL D0, D9, D0 |
0x401190 BL 400b30 |
0x401194 ORR W0, WZR, WZR |
0x401198 ADDVL SP, SP, #4 |
0x40119c ADD SP, SP, #32 |
0x4011a0 LDP D9, D8, [SP, #32] |
0x4011a4 LDP D11, D10, [SP, #16] |
0x4011a8 LDP X20, X19, [SP, #128] |
0x4011ac LDP X22, X21, [SP, #112] |
0x4011b0 LDP X24, X23, [SP, #96] |
0x4011b4 LDP X26, X25, [SP, #80] |
0x4011b8 LDP X28, X27, [SP, #64] |
0x4011bc LDP X29, X30, [SP, #48] |
0x4011c0 LDR D12, [SP], #144 |
0x4011c4 RET |
0x4011c8 HINT #0 |
0x4011cc HINT #0 |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __libc_start_main | libc-2.31.so | |
○ | _start | exec |
Path / |
Source file and lines | main.c:50-191 |
Module | exec |
nb instructions | 120 |
loop length | 480 |
nb stack references | 0 |
front end | 14.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.00 | 5.00 | 18.25 | 18.25 | 18.25 | 18.25 | 3.75 | 3.75 | 3.75 | 3.75 | 9.33 | 9.33 | 9.33 | 4.50 | 4.50 |
cycles | 5.00 | 5.00 | 18.25 | 18.25 | 18.25 | 18.25 | 3.75 | 3.75 | 3.75 | 3.75 | 9.33 | 9.33 | 9.33 | 4.50 | 4.50 |
Cycles executing div or sqrt instructions | NA |
Front-end | 14.00 |
Overall L1 | 18.25 |
all | 16% |
load | 50% |
store | 85% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 3% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 4% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STR D12, [SP, #368]! | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP D11, D10, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP D9, D8, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP X29, X30, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X28, X27, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X26, X25, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X24, X23, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X22, X21, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X20, X19, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #48 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADDVL SP, SP, #60 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
SUB SP, SP, #32 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X20, XZR, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR W21, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W25, #34464 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W8, #3000 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X0, <401d00> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #2296 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP WZR, W8, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
MOVZ W1, #3000 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVK W25, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 400b30 <@plt_start@+0x70> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADRP X0, <401d18> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #2313 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W1, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 400b30 <@plt_start@+0x70> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP W21, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.NE 400d50 <main+0x90> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X0, [X20, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADRP X1, <401d34> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X1, X1, #2333 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W2, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 400b00 <@plt_start@+0x40> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP W0, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
MOVZ W8, #15000 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CSEL X25, X8, X25, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X1, XZR, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X0, <401d54> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #2336 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 400b30 <@plt_start@+0x70> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADRP X0, <412d60> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #3336 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X2, <401d68> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X2, X2, #464 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X3, SP, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W1, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 400b20 <@plt_start@+0x60> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CNTW X9, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ADRP X28, <413d80> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X28, X28, #116 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X27, <474d88> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X27, X27, #2804 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
INDEX Z0.S, #0, #1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 |
MOVI D9, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
FMOV S10, #1.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
ADRP X24, <4d6d9c> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X24, X24, #1396 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W10, #55050 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
FMOV S11, #3.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
ADRP X19, <537dac> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X19, X19, #4084 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W8, #400 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR W8, [SP, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
MOVK W10, #15395 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X11, X29, #48 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
PTRUE P0.S, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
MOVPRFX Z1, Z0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
UCVTF Z1.S, P0/M, Z0.S | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 2 |
STR Z1, [X11, #509, MUL VL] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
ADD Z0.S, Z0.S, #1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
UCVTF S12, W9 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DUP Z31.S, W9 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADDVL X9, X28, #1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ADD X26, X9, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADDVL X9, X27, #1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
CNTH X16, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
SUB X11, X29, #48 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR Z0, [X11, #508, MUL VL] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
ADD X20, X9, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADDVL X9, X24, #1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
DUP Z8.S, W10 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOVZ X23, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X25, [SP, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X21, X9, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADDVL X9, X19, #1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ADD X22, X9, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X9, X29, #48 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR Z31, [X9, #511, MUL VL] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
SUB X9, X29, #48 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR Z8, [X9, #510, MUL VL] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
B 400ebc <main+0x1fc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
LDR W8, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CBNZ W8, 401194 <main+0x4d4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADRP X8, 40117c <main+0x4bc> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X0, 401180 <main+0x4c0> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #2644 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR D0, [X8, #2288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
FMUL D0, D9, D0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
BL 400b30 <@plt_start@+0x70> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR W0, WZR, WZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADDVL SP, SP, #4 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ADD SP, SP, #32 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDP D9, D8, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDP D11, D10, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDP X20, X19, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X22, X21, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X24, X23, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X26, X25, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X28, X27, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X29, X30, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDR D12, [SP], #144 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
RET | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 |
Source file and lines | main.c:50-191 |
Module | exec |
nb instructions | 120 |
loop length | 480 |
nb stack references | 0 |
front end | 14.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.00 | 5.00 | 18.25 | 18.25 | 18.25 | 18.25 | 3.75 | 3.75 | 3.75 | 3.75 | 9.33 | 9.33 | 9.33 | 4.50 | 4.50 |
cycles | 5.00 | 5.00 | 18.25 | 18.25 | 18.25 | 18.25 | 3.75 | 3.75 | 3.75 | 3.75 | 9.33 | 9.33 | 9.33 | 4.50 | 4.50 |
Cycles executing div or sqrt instructions | NA |
Front-end | 14.00 |
Overall L1 | 18.25 |
all | 16% |
load | 50% |
store | 85% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 3% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 4% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STR D12, [SP, #368]! | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP D11, D10, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP D9, D8, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP X29, X30, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X28, X27, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X26, X25, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X24, X23, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X22, X21, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X20, X19, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #48 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADDVL SP, SP, #60 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
SUB SP, SP, #32 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X20, XZR, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR W21, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W25, #34464 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W8, #3000 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X0, <401d00> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #2296 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP WZR, W8, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
MOVZ W1, #3000 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVK W25, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 400b30 <@plt_start@+0x70> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADRP X0, <401d18> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #2313 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W1, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 400b30 <@plt_start@+0x70> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP W21, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.NE 400d50 <main+0x90> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X0, [X20, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADRP X1, <401d34> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X1, X1, #2333 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W2, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 400b00 <@plt_start@+0x40> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP W0, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
MOVZ W8, #15000 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CSEL X25, X8, X25, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ORR X1, XZR, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X0, <401d54> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #2336 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 400b30 <@plt_start@+0x70> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADRP X0, <412d60> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #3336 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X2, <401d68> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X2, X2, #464 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X3, SP, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W1, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
BL 400b20 <@plt_start@+0x60> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CNTW X9, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ADRP X28, <413d80> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X28, X28, #116 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X27, <474d88> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X27, X27, #2804 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
INDEX Z0.S, #0, #1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 |
MOVI D9, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
FMOV S10, #1.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
ADRP X24, <4d6d9c> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X24, X24, #1396 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W10, #55050 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
FMOV S11, #3.0000000 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
ADRP X19, <537dac> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X19, X19, #4084 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W8, #400 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR W8, [SP, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
MOVK W10, #15395 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X11, X29, #48 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
PTRUE P0.S, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
MOVPRFX Z1, Z0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
UCVTF Z1.S, P0/M, Z0.S | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 2 |
STR Z1, [X11, #509, MUL VL] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
ADD Z0.S, Z0.S, #1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
UCVTF S12, W9 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
DUP Z31.S, W9 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADDVL X9, X28, #1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ADD X26, X9, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADDVL X9, X27, #1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
CNTH X16, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
SUB X11, X29, #48 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR Z0, [X11, #508, MUL VL] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
ADD X20, X9, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADDVL X9, X24, #1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
DUP Z8.S, W10 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
MOVZ X23, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X25, [SP, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X21, X9, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADDVL X9, X19, #1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ADD X22, X9, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X9, X29, #48 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR Z31, [X9, #511, MUL VL] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
SUB X9, X29, #48 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR Z8, [X9, #510, MUL VL] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
B 400ebc <main+0x1fc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
LDR W8, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CBNZ W8, 401194 <main+0x4d4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ADRP X8, 40117c <main+0x4bc> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X0, 401180 <main+0x4c0> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #2644 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR D0, [X8, #2288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
FMUL D0, D9, D0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
BL 400b30 <@plt_start@+0x70> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
ORR W0, WZR, WZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADDVL SP, SP, #4 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ADD SP, SP, #32 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDP D9, D8, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDP D11, D10, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDP X20, X19, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X22, X21, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X24, X23, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X26, X25, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X28, X27, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X29, X30, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDR D12, [SP], #144 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
RET | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼main– | 0.03 | 0.01 |
▼Loop 3 - main.c:97-169 - exec– | 0 | 0 |
○Loop 0 - main.c:122-122 - exec | 0 | 0.03 |
▼Loop 4 - main.c:97-169 - exec– | 0 | 0 |
○Loop 2 - main.c:121-121 - exec | 0 | 0.06 |
○Loop 7 - main.c:123-123 - exec | 0 | 0.05 |
▼Loop 1 - main.c:97-169 - exec– | 0 | 0 |
○Loop 5 - main.c:113-116 - exec | 0.02 | 0.52 |
○Loop 6 - main.c:111-116 - exec | 0 | 0 |