Loop Id: 0 | Module: exec | Source: main.c:111-116 | Coverage: 0.06% |
---|
Loop Id: 0 | Module: exec | Source: main.c:111-116 | Coverage: 0.06% |
---|
0x4012be VADDSS %XMM10,%XMM0,%XMM14 |
0x4012c3 VADDSS %XMM6,%XMM2,%XMM15 |
0x4012c7 LEA 0x2(%R12),%RDI |
0x4012cc VADDSS %XMM11,%XMM1,%XMM3 |
0x4012d1 LEA 0x1(%R12),%RCX |
0x4012d6 LEA 0x3(%R12),%R9 |
0x4012db VADDSS %XMM10,%XMM14,%XMM12 |
0x4012e0 VMOVSS %XMM15,(%R14,%R12,4) [3] |
0x4012e6 VADDSS %XMM6,%XMM15,%XMM2 |
0x4012ea VCVTSI2SS %EDI,%XMM7,%XMM15 |
0x4012ee VMOVSS %XMM3,(%R15,%R12,4) [3] |
0x4012f4 VADDSS %XMM11,%XMM3,%XMM1 |
0x4012f9 VCVTSI2SS %R12D,%XMM7,%XMM5 |
0x4012fe VMOVSS %XMM14,(%R13,%R12,4) [3] |
0x401305 VADDSS %XMM10,%XMM12,%XMM0 |
0x40130a VMOVSS %XMM12,(%R13,%RCX,4) [2] |
0x401311 VADDSS %XMM6,%XMM2,%XMM13 |
0x401315 VCVTSI2SS %ECX,%XMM7,%XMM4 |
0x401319 VMOVSS %XMM2,(%R14,%RCX,4) [2] |
0x40131f VCVTSI2SS %R9D,%XMM7,%XMM3 |
0x401324 VMOVSS %XMM1,(%R15,%RCX,4) [2] |
0x40132a VFMADD132SS %XMM8,%XMM0,%XMM15 |
0x40132f VMOVSS %XMM0,(%R13,%RDI,4) [2] |
0x401336 VADDSS %XMM10,%XMM0,%XMM0 |
0x40133b VADDSS %XMM6,%XMM13,%XMM2 |
0x40133f VFMADD132SS %XMM8,%XMM14,%XMM5 |
0x401344 VADDSS %XMM11,%XMM1,%XMM14 |
0x401349 VMOVSS %XMM13,(%R14,%RDI,4) [2] |
0x40134f VFMADD132SS %XMM8,%XMM12,%XMM4 |
0x401354 VFMADD132SS %XMM8,%XMM0,%XMM3 |
0x401359 VMOVSS %XMM0,(%R13,%R9,4) [2] |
0x401360 VADDSS %XMM11,%XMM14,%XMM1 |
0x401365 VMOVSS %XMM14,(%R15,%RDI,4) [2] |
0x40136b VMOVSS %XMM2,(%R14,%R9,4) [2] |
0x401371 VMOVSS %XMM5,(%RAX,%R12,4) [1] |
0x401377 ADD $0x4,%R12 |
0x40137b VMOVSS %XMM4,(%RAX,%RCX,4) [4] |
0x401380 VMOVSS %XMM1,(%R15,%R9,4) [2] |
0x401386 VMOVSS %XMM15,(%RAX,%RDI,4) [4] |
0x40138b VMOVSS %XMM3,(%RAX,%R9,4) [4] |
0x401391 CMP %R11,%R12 |
0x401394 JNE 4012be |
/home/kcamus/qaas_runs/169-401-3406/intel/HACCmk/build/HACCmk/src/main.c: 111 - 116 |
-------------------------------------------------------------------------------- |
111: for ( i = 1; i < n; i++ ) |
112: { |
113: xx[i] = xx[i-1] + dx1; |
114: yy[i] = yy[i-1] + dy1; |
115: zz[i] = zz[i-1] + dz1; |
116: mass[i] = (float)i * 0.01f + xx[i]; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○100.00 | __libc_init_first | libc.so.6 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 16.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.39 |
Bottlenecks | P4, |
Function | main |
Source | main.c:111-116 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 16.00 |
CQA cycles if no scalar integer | 16.00 |
CQA cycles if FP arith vectorized | 16.00 |
CQA cycles if fully vectorized | 1.00 |
Front-end cycles | 11.25 |
DIV/SQRT cycles | 11.50 |
P0 cycles | 11.50 |
P1 cycles | 5.33 |
P2 cycles | 5.33 |
P3 cycles | 16.00 |
P4 cycles | 4.00 |
P5 cycles | 2.00 |
P6 cycles | 5.33 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | 16 |
FE+BE cycles (UFS) | 16.96 |
Stall cycles (UFS) | 5.33 |
Nb insns | 42.00 |
Nb uops | 45.00 |
Nb loads | 0.00 |
Nb stores | 16.00 |
Nb stack references | 0.00 |
FLOP/cycle | 1.25 |
Nb FLOP add-sub | 12.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 4.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 4.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 0.00 |
Bytes stored | 64.00 |
Stride 0 | 0.00 |
Stride 1 | 0.00 |
Stride n | 16.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 6.25 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | 6.25 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 6.25 |
Vector-efficiency ratio fma | 6.25 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 6.25 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 16.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.39 |
Bottlenecks | P4, |
Function | main |
Source | main.c:111-116 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 16.00 |
CQA cycles if no scalar integer | 16.00 |
CQA cycles if FP arith vectorized | 16.00 |
CQA cycles if fully vectorized | 1.00 |
Front-end cycles | 11.25 |
DIV/SQRT cycles | 11.50 |
P0 cycles | 11.50 |
P1 cycles | 5.33 |
P2 cycles | 5.33 |
P3 cycles | 16.00 |
P4 cycles | 4.00 |
P5 cycles | 2.00 |
P6 cycles | 5.33 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | 16 |
FE+BE cycles (UFS) | 16.96 |
Stall cycles (UFS) | 5.33 |
Nb insns | 42.00 |
Nb uops | 45.00 |
Nb loads | 0.00 |
Nb stores | 16.00 |
Nb stack references | 0.00 |
FLOP/cycle | 1.25 |
Nb FLOP add-sub | 12.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 4.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 4.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 0.00 |
Bytes stored | 64.00 |
Stride 0 | 0.00 |
Stride 1 | 0.00 |
Stride n | 16.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 6.25 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | 6.25 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 6.25 |
Vector-efficiency ratio fma | 6.25 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 6.25 |
Path / |
Function | main |
Source file and lines | main.c:111-116 |
Module | exec |
nb instructions | 42 |
nb uops | 45 |
loop length | 220 |
used x86 registers | 9 |
used mmx registers | 0 |
used xmm registers | 15 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 11.25 cycles |
front end | 11.25 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 11.50 | 11.50 | 5.33 | 5.33 | 16.00 | 4.00 | 2.00 | 5.33 |
cycles | 11.50 | 11.50 | 5.33 | 5.33 | 16.00 | 4.00 | 2.00 | 5.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 16.00 |
FE+BE cycles | 16.96 |
Stall cycles | 5.33 |
RS full (events) | 10.80 |
SB full (events) | 1.59 |
Front-end | 11.25 |
Dispatch | 16.00 |
Data deps. | 16.00 |
Overall L1 | 16.00 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 6% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 6% |
load | NA (no load vectorizable/vectorized instructions) |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | 6% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 6% |
load | NA (no load vectorizable/vectorized instructions) |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | 6% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 6% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VADDSS %XMM10,%XMM0,%XMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSS %XMM6,%XMM2,%XMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
LEA 0x2(%R12),%RDI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VADDSS %XMM11,%XMM1,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
LEA 0x1(%R12),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x3(%R12),%R9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VADDSS %XMM10,%XMM14,%XMM12 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSS %XMM15,(%R14,%R12,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VADDSS %XMM6,%XMM15,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTSI2SS %EDI,%XMM7,%XMM15 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 6 | 1 |
VMOVSS %XMM3,(%R15,%R12,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VADDSS %XMM11,%XMM3,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTSI2SS %R12D,%XMM7,%XMM5 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 6 | 1 |
VMOVSS %XMM14,(%R13,%R12,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VADDSS %XMM10,%XMM12,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSS %XMM12,(%R13,%RCX,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VADDSS %XMM6,%XMM2,%XMM13 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTSI2SS %ECX,%XMM7,%XMM4 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 6 | 1 |
VMOVSS %XMM2,(%R14,%RCX,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VCVTSI2SS %R9D,%XMM7,%XMM3 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 6 | 1 |
VMOVSS %XMM1,(%R15,%RCX,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VFMADD132SS %XMM8,%XMM0,%XMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSS %XMM0,(%R13,%RDI,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VADDSS %XMM10,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSS %XMM6,%XMM13,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132SS %XMM8,%XMM14,%XMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSS %XMM11,%XMM1,%XMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSS %XMM13,(%R14,%RDI,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VFMADD132SS %XMM8,%XMM12,%XMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132SS %XMM8,%XMM0,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSS %XMM0,(%R13,%R9,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VADDSS %XMM11,%XMM14,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSS %XMM14,(%R15,%RDI,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSS %XMM2,(%R14,%R9,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSS %XMM5,(%RAX,%R12,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
ADD $0x4,%R12 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVSS %XMM4,(%RAX,%RCX,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSS %XMM1,(%R15,%R9,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSS %XMM15,(%RAX,%RDI,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSS %XMM3,(%RAX,%R9,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CMP %R11,%R12 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JNE 4012be | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
Function | main |
Source file and lines | main.c:111-116 |
Module | exec |
nb instructions | 42 |
nb uops | 45 |
loop length | 220 |
used x86 registers | 9 |
used mmx registers | 0 |
used xmm registers | 15 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 11.25 cycles |
front end | 11.25 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 11.50 | 11.50 | 5.33 | 5.33 | 16.00 | 4.00 | 2.00 | 5.33 |
cycles | 11.50 | 11.50 | 5.33 | 5.33 | 16.00 | 4.00 | 2.00 | 5.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 16.00 |
FE+BE cycles | 16.96 |
Stall cycles | 5.33 |
RS full (events) | 10.80 |
SB full (events) | 1.59 |
Front-end | 11.25 |
Dispatch | 16.00 |
Data deps. | 16.00 |
Overall L1 | 16.00 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 6% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 6% |
load | NA (no load vectorizable/vectorized instructions) |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | 6% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 6% |
load | NA (no load vectorizable/vectorized instructions) |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | 6% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 6% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VADDSS %XMM10,%XMM0,%XMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSS %XMM6,%XMM2,%XMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
LEA 0x2(%R12),%RDI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VADDSS %XMM11,%XMM1,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
LEA 0x1(%R12),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x3(%R12),%R9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VADDSS %XMM10,%XMM14,%XMM12 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSS %XMM15,(%R14,%R12,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VADDSS %XMM6,%XMM15,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTSI2SS %EDI,%XMM7,%XMM15 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 6 | 1 |
VMOVSS %XMM3,(%R15,%R12,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VADDSS %XMM11,%XMM3,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTSI2SS %R12D,%XMM7,%XMM5 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 6 | 1 |
VMOVSS %XMM14,(%R13,%R12,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VADDSS %XMM10,%XMM12,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSS %XMM12,(%R13,%RCX,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VADDSS %XMM6,%XMM2,%XMM13 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTSI2SS %ECX,%XMM7,%XMM4 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 6 | 1 |
VMOVSS %XMM2,(%R14,%RCX,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VCVTSI2SS %R9D,%XMM7,%XMM3 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 6 | 1 |
VMOVSS %XMM1,(%R15,%RCX,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VFMADD132SS %XMM8,%XMM0,%XMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSS %XMM0,(%R13,%RDI,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VADDSS %XMM10,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSS %XMM6,%XMM13,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132SS %XMM8,%XMM14,%XMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDSS %XMM11,%XMM1,%XMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSS %XMM13,(%R14,%RDI,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VFMADD132SS %XMM8,%XMM12,%XMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132SS %XMM8,%XMM0,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSS %XMM0,(%R13,%R9,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VADDSS %XMM11,%XMM14,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSS %XMM14,(%R15,%RDI,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSS %XMM2,(%R14,%R9,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSS %XMM5,(%RAX,%R12,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
ADD $0x4,%R12 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVSS %XMM4,(%RAX,%RCX,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSS %XMM1,(%R15,%R9,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSS %XMM15,(%RAX,%RDI,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSS %XMM3,(%RAX,%R9,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CMP %R11,%R12 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JNE 4012be | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
Metric | run_0 |
---|---|
Coverage (% app. time) | 0.06 |
Time (s) | 0.02 |
Instance Count | 730 |
Iteration Count - min | 99 |
Iteration Count - avg | 1921.5 |
Iteration Count - max | 3744 |
Cycles per Iteration - min | 17.16 |
Cycles per Iteration - avg | 23 |
Cycles per Iteration - max | 277.43 |
Metric | Value |
---|---|
Bucket Coverage (% loop time) | 99.44 |
Instance Count | 730 |
ORIG CPI:min | 17.32 |
ORIG CPI:med | 17.82 |
ORIG CPI:max | 27.44 |
DL1 CPI:min | 20.81 |
DL1 CPI:med | 20.90 |
DL1 CPI:max | 21.12 |
ORIG (min) / DL1 (min) | 0.46 |
ORIG (med) / DL1 (med) | 0.45 |
ORIG (max) / DL1 (max) | 0.54 |
Nb Iteration:min | 104 |
Nb Iteration:med | 104.00 |
Nb Iteration:max | 104 |
ORIG: min (cycles) | 2660 |
ORIG: med (cycles) | 3318.00 |
ORIG: max (cycles) | 4858 |
DL1:min (cycles) | 5738 |
DL1:med (cycles) | 7366.00 |
DL1:max (cycles) | 8942 |
Metric (average per iteration except for Time and Iteration Count) | ORIG | DL1 | ||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Min (Thread) | Med (Thread) | Avg (Thread) | Max (Thread) | Min (Instances) | Med (Instances) | Max (Instances) | Min (Thread) | Med (Thread) | Avg (Thread) | Max (Thread) | Min (Instances) | Med (Instances) | Max (Instances) | |
Time | 3318.00 | 3318.00 | 3318.00 | 3318.00 | 2660.00 | 3318.00 | 4858.00 | 7366.00 | 7366.00 | 7366.00 | 7366.00 | 5738.00 | 7366.00 | 8942.00 |
CPI MIN | 17.32 | 20.81 | ||||||||||||
CPI MED | 17.82 | 17.82 | 17.82 | 17.82 | 17.32 | 17.82 | 27.44 | 20.90 | 20.90 | 20.90 | 20.90 | 20.81 | 20.90 | 21.12 |
CPI AVG | 19.06 | 20.91 | ||||||||||||
CPI MAX | 27.44 | 21.12 | ||||||||||||
Iteration Count | 104.00 | 104.00 | 104.00 | 104.00 | 104.00 | 104.00 | 104.00 | 104.00 | 104.00 | 104.00 | 104.00 | 104.00 | 104.00 | 104.00 |
ORIG | DL1 | Original Code |
---|---|---|
0x6b4268 ADDQ $0x1,-0xc70(%RIP) 0x6b4270 VADDSS %XMM10,%XMM0,%XMM14 | 0x6b4707 VADDSS %XMM10,%XMM0,%XMM14 | 0x4012be VADDSS %XMM10,%XMM0,%XMM14 |
0x6b4275 VADDSS %XMM6,%XMM2,%XMM15 | 0x6b470c VADDSS %XMM6,%XMM2,%XMM15 | 0x4012c3 VADDSS %XMM6,%XMM2,%XMM15 |
0x6b4279 LEA 0x2(%R12),%RDI | 0x6b4710 LEA 0x2(%R12),%RDI | 0x4012c7 LEA 0x2(%R12),%RDI |
0x6b427e VADDSS %XMM11,%XMM1,%XMM3 | 0x6b4715 VADDSS %XMM11,%XMM1,%XMM3 | 0x4012cc VADDSS %XMM11,%XMM1,%XMM3 |
0x6b4283 LEA 0x1(%R12),%RCX | 0x6b471a LEA 0x1(%R12),%RCX | 0x4012d1 LEA 0x1(%R12),%RCX |
0x6b4288 LEA 0x3(%R12),%R9 | 0x6b471f LEA 0x3(%R12),%R9 | 0x4012d6 LEA 0x3(%R12),%R9 |
0x6b428d VADDSS %XMM10,%XMM14,%XMM12 | 0x6b4724 VADDSS %XMM10,%XMM14,%XMM12 | 0x4012db VADDSS %XMM10,%XMM14,%XMM12 |
0x6b4292 VMOVSS %XMM15,(%R14,%R12,4) | 0x6b4729 VMOVSS %XMM15,-0x2331(%RIP) 0x6b4731 NOP | 0x4012e0 VMOVSS %XMM15,(%R14,%R12,4) |
0x6b4298 VADDSS %XMM6,%XMM15,%XMM2 | 0x6b4732 VADDSS %XMM6,%XMM15,%XMM2 | 0x4012e6 VADDSS %XMM6,%XMM15,%XMM2 |
0x6b429c VCVTSI2SS %EDI,%XMM7,%XMM15 | 0x6b4736 VCVTSI2SS %EDI,%XMM7,%XMM15 | 0x4012ea VCVTSI2SS %EDI,%XMM7,%XMM15 |
0x6b42a0 VMOVSS %XMM3,(%R15,%R12,4) | 0x6b473a VMOVSS %XMM3,-0x2302(%RIP) 0x6b4742 NOP | 0x4012ee VMOVSS %XMM3,(%R15,%R12,4) |
0x6b42a6 VADDSS %XMM11,%XMM3,%XMM1 | 0x6b4743 VADDSS %XMM11,%XMM3,%XMM1 | 0x4012f4 VADDSS %XMM11,%XMM3,%XMM1 |
0x6b42ab VCVTSI2SS %R12D,%XMM7,%XMM5 | 0x6b4748 VCVTSI2SS %R12D,%XMM7,%XMM5 | 0x4012f9 VCVTSI2SS %R12D,%XMM7,%XMM5 |
0x6b42b0 VMOVSS %XMM14,(%R13,%R12,4) | 0x6b474d VMOVSS %XMM14,-0x22d5(%RIP) 0x6b4755 NOP | 0x4012fe VMOVSS %XMM14,(%R13,%R12,4) |
0x6b42b7 VADDSS %XMM10,%XMM12,%XMM0 | 0x6b4756 VADDSS %XMM10,%XMM12,%XMM0 | 0x401305 VADDSS %XMM10,%XMM12,%XMM0 |
0x6b42bc VMOVSS %XMM12,(%R13,%RCX,4) | 0x6b475b VMOVSS %XMM12,-0x22a3(%RIP) 0x6b4763 NOP | 0x40130a VMOVSS %XMM12,(%R13,%RCX,4) |
0x6b42c3 VADDSS %XMM6,%XMM2,%XMM13 | 0x6b4764 VADDSS %XMM6,%XMM2,%XMM13 | 0x401311 VADDSS %XMM6,%XMM2,%XMM13 |
0x6b42c7 VCVTSI2SS %ECX,%XMM7,%XMM4 | 0x6b4768 VCVTSI2SS %ECX,%XMM7,%XMM4 | 0x401315 VCVTSI2SS %ECX,%XMM7,%XMM4 |
0x6b42cb VMOVSS %XMM2,(%R14,%RCX,4) | 0x6b476c VMOVSS %XMM2,-0x2274(%RIP) 0x6b4774 NOP | 0x401319 VMOVSS %XMM2,(%R14,%RCX,4) |
0x6b42d1 VCVTSI2SS %R9D,%XMM7,%XMM3 | 0x6b4775 VCVTSI2SS %R9D,%XMM7,%XMM3 | 0x40131f VCVTSI2SS %R9D,%XMM7,%XMM3 |
0x6b42d6 VMOVSS %XMM1,(%R15,%RCX,4) | 0x6b477a VMOVSS %XMM1,-0x2242(%RIP) 0x6b4782 NOP | 0x401324 VMOVSS %XMM1,(%R15,%RCX,4) |
0x6b42dc VFMADD132SS %XMM8,%XMM0,%XMM15 | 0x6b4783 VFMADD132SS %XMM8,%XMM0,%XMM15 | 0x40132a VFMADD132SS %XMM8,%XMM0,%XMM15 |
0x6b42e1 VMOVSS %XMM0,(%R13,%RDI,4) | 0x6b4788 VMOVSS %XMM0,-0x2210(%RIP) 0x6b4790 NOP | 0x40132f VMOVSS %XMM0,(%R13,%RDI,4) |
0x6b42e8 VADDSS %XMM10,%XMM0,%XMM0 | 0x6b4791 VADDSS %XMM10,%XMM0,%XMM0 | 0x401336 VADDSS %XMM10,%XMM0,%XMM0 |
0x6b42ed VADDSS %XMM6,%XMM13,%XMM2 | 0x6b4796 VADDSS %XMM6,%XMM13,%XMM2 | 0x40133b VADDSS %XMM6,%XMM13,%XMM2 |
0x6b42f1 VFMADD132SS %XMM8,%XMM14,%XMM5 | 0x6b479a VFMADD132SS %XMM8,%XMM14,%XMM5 | 0x40133f VFMADD132SS %XMM8,%XMM14,%XMM5 |
0x6b42f6 VADDSS %XMM11,%XMM1,%XMM14 | 0x6b479f VADDSS %XMM11,%XMM1,%XMM14 | 0x401344 VADDSS %XMM11,%XMM1,%XMM14 |
0x6b42fb VMOVSS %XMM13,(%R14,%RDI,4) | 0x6b47a4 VMOVSS %XMM13,-0x21ec(%RIP) 0x6b47ac NOP | 0x401349 VMOVSS %XMM13,(%R14,%RDI,4) |
0x6b4301 VFMADD132SS %XMM8,%XMM12,%XMM4 | 0x6b47ad VFMADD132SS %XMM8,%XMM12,%XMM4 | 0x40134f VFMADD132SS %XMM8,%XMM12,%XMM4 |
0x6b4306 VFMADD132SS %XMM8,%XMM0,%XMM3 | 0x6b47b2 VFMADD132SS %XMM8,%XMM0,%XMM3 | 0x401354 VFMADD132SS %XMM8,%XMM0,%XMM3 |
0x6b430b VMOVSS %XMM0,(%R13,%R9,4) | 0x6b47b7 VMOVSS %XMM0,-0x21bf(%RIP) 0x6b47bf NOP | 0x401359 VMOVSS %XMM0,(%R13,%R9,4) |
0x6b4312 VADDSS %XMM11,%XMM14,%XMM1 | 0x6b47c0 VADDSS %XMM11,%XMM14,%XMM1 | 0x401360 VADDSS %XMM11,%XMM14,%XMM1 |
0x6b4317 VMOVSS %XMM14,(%R15,%RDI,4) | 0x6b47c5 VMOVSS %XMM14,-0x218d(%RIP) 0x6b47cd NOP | 0x401365 VMOVSS %XMM14,(%R15,%RDI,4) |
0x6b431d VMOVSS %XMM2,(%R14,%R9,4) | 0x6b47ce VMOVSS %XMM2,-0x2156(%RIP) 0x6b47d6 NOP | 0x40136b VMOVSS %XMM2,(%R14,%R9,4) |
0x6b4323 VMOVSS %XMM5,(%RAX,%R12,4) | 0x6b47d7 VMOVSS %XMM5,-0x211f(%RIP) 0x6b47df NOP | 0x401371 VMOVSS %XMM5,(%RAX,%R12,4) |
0x6b4329 ADD $0x4,%R12 | 0x6b47e0 ADD $0x4,%R12 | 0x401377 ADD $0x4,%R12 |
0x6b432d VMOVSS %XMM4,(%RAX,%RCX,4) | 0x6b47e4 VMOVSS %XMM4,-0x20ec(%RIP) 0x6b47ec NOP | 0x40137b VMOVSS %XMM4,(%RAX,%RCX,4) |
0x6b4332 VMOVSS %XMM1,(%R15,%R9,4) | 0x6b47ed VMOVSS %XMM1,-0x20b5(%RIP) 0x6b47f5 NOP | 0x401380 VMOVSS %XMM1,(%R15,%R9,4) |
0x6b4338 VMOVSS %XMM15,(%RAX,%RDI,4) | 0x6b47f6 VMOVSS %XMM15,-0x207e(%RIP) 0x6b47fe NOP | 0x401386 VMOVSS %XMM15,(%RAX,%RDI,4) |
0x6b433d VMOVSS %XMM3,(%RAX,%R9,4) | 0x6b47ff VMOVSS %XMM3,-0x2047(%RIP) 0x6b4807 NOP | 0x40138b VMOVSS %XMM3,(%RAX,%R9,4) |
0x6b4343 CMP %R11,%R12 | 0x6b4808 CMP %R11,%R12 | 0x401391 CMP %R11,%R12 |
0x6b4346 JNE 6b4268 | 0x6b480b JNE 6b4707 | 0x401394 JNE 4012be |
Path / |
Metric | ORIG | DL1 | Original |
---|---|---|---|
FP operations per cycle L1 | 1.18, 1.18, | 1.25, 1.25, | 1.25, 1.25, |
cycles L1 CQA | 17.00 | 16.00 | 16.00 |
cycles UFS | 17.13 | 16.91 | 16.96 |
bytes loaded | 8.00 | 0.00 | 0.00 |
bytes stored | 72.00 | 64.00 | 64.00 |
nb loads | 1.00 | 0.00 | 0.00 |
nb stores | 17.00 | 16.00 | 16.00 |
cycles dispatch | 17.00 | 16.00 | 16.00 |
cycles front end | 11.75 | 15.25 | 11.25 |
cycles P0 | 11.50 | 11.50 | 11.50 |
cycles P1 | 11.50 | 11.50 | 11.50 |
cycles P2 | 6.17 | 5.33 | 5.33 |
cycles P3 | 5.83 | 5.33 | 5.33 |
cycles P4 | 17.00 | 16.00 | 16.00 |
cycles P5 | 4.00 | 4.00 | 4.00 |
cycles P6 | 3.00 | 2.00 | 2.00 |
cycles P7 | 6.00 | 5.33 | 5.33 |
stall cycles | 4.99 | 1.15 | 5.33 |
LB full | 0.00 | 0.00 | 0.00 |
LM full | 0.00 | 0.00 | 0.00 |
PRF full | 0.00 | 0.00 | 0.00 |
PRF_FLOAT full | 0.00 | 0.00 | 0.00 |
PRF_INT full | 0.00 | 0.00 | 0.00 |
ROB full | 0.00 | 0.00 | 0.00 |
RS full | 2.79 | 1.54 | 10.80 |
SB full | 7.28 | 1.58 | 1.59 |
nb uops | 47.00 | 61.00 | 45.00 |
uops P0 | 11.50 | 11.50 | 11.50 |
uops P1 | 11.50 | 11.50 | 11.50 |
uops P2 | 6.17 | 5.33 | 5.33 |
uops P3 | 5.83 | 5.33 | 5.33 |
uops P4 | 17.00 | 16.00 | 16.00 |
uops P5 | 4.00 | 4.00 | 4.00 |
uops P6 | 3.00 | 2.00 | 2.00 |
uops P7 | 6.00 | 5.33 | 5.33 |
ID | 2 | 4 | 0 |
Metric | ORIG | DL1 | Original |
---|---|---|---|
FP operations per cycle L1 | 1.18, 1.18, | 1.25, 1.25, | 1.25, 1.25, |
cycles L1 CQA | 17.00 | 16.00 | 16.00 |
cycles UFS | 17.13 | 16.91 | 16.96 |
bytes loaded | 8.00 | 0.00 | 0.00 |
bytes stored | 72.00 | 64.00 | 64.00 |
nb loads | 1.00 | 0.00 | 0.00 |
nb stores | 17.00 | 16.00 | 16.00 |
cycles dispatch | 17.00 | 16.00 | 16.00 |
cycles front end | 11.75 | 15.25 | 11.25 |
cycles P0 | 11.50 | 11.50 | 11.50 |
cycles P1 | 11.50 | 11.50 | 11.50 |
cycles P2 | 6.17 | 5.33 | 5.33 |
cycles P3 | 5.83 | 5.33 | 5.33 |
cycles P4 | 17.00 | 16.00 | 16.00 |
cycles P5 | 4.00 | 4.00 | 4.00 |
cycles P6 | 3.00 | 2.00 | 2.00 |
cycles P7 | 6.00 | 5.33 | 5.33 |
stall cycles | 4.99 | 1.15 | 5.33 |
LB full | 0.00 | 0.00 | 0.00 |
LM full | 0.00 | 0.00 | 0.00 |
PRF full | 0.00 | 0.00 | 0.00 |
PRF_FLOAT full | 0.00 | 0.00 | 0.00 |
PRF_INT full | 0.00 | 0.00 | 0.00 |
ROB full | 0.00 | 0.00 | 0.00 |
RS full | 2.79 | 1.54 | 10.80 |
SB full | 7.28 | 1.58 | 1.59 |
nb uops | 47.00 | 61.00 | 45.00 |
uops P0 | 11.50 | 11.50 | 11.50 |
uops P1 | 11.50 | 11.50 | 11.50 |
uops P2 | 6.17 | 5.33 | 5.33 |
uops P3 | 5.83 | 5.33 | 5.33 |
uops P4 | 17.00 | 16.00 | 16.00 |
uops P5 | 4.00 | 4.00 | 4.00 |
uops P6 | 3.00 | 2.00 | 2.00 |
uops P7 | 6.00 | 5.33 | 5.33 |
ID | 2 | 4 | 0 |