Function: main._omp_fn.1 | Module: exec | Source: main.c:139-146 | Coverage: 0.06% |
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Function: main._omp_fn.1 | Module: exec | Source: main.c:139-146 | Coverage: 0.06% |
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/home/kcamus/qaas_runs/169-401-3406/intel/HACCmk/build/HACCmk/src/main.c: 139 - 146 |
-------------------------------------------------------------------------------- |
139: #pragma omp parallel for private( dx1, dy1, dz1 ) |
140: for ( i = 0; i < count; ++i) |
141: { |
142: Step10_orig( n, xx[i], yy[i], zz[i], fsrrmax2, mp_rsm2, xx, yy, zz, mass, &dx1, &dy1, &dz1 ); |
143: |
144: vx1[i] = vx1[i] + dx1 * fcoeff; |
145: vy1[i] = vy1[i] + dy1 * fcoeff; |
146: vz1[i] = vz1[i] + dz1 * fcoeff; |
0x4015b0 PUSH %RBP |
0x4015b1 MOV %RSP,%RBP |
0x4015b4 PUSH %R15 |
0x4015b6 PUSH %R14 |
0x4015b8 PUSH %R13 |
0x4015ba PUSH %R12 |
0x4015bc MOV %RDI,%R12 |
0x4015bf PUSH %RBX |
0x4015c0 SUB $0x68,%RSP |
0x4015c4 MOV %FS:0x28,%RAX |
0x4015cd MOV %RAX,-0x38(%RBP) |
0x4015d1 XOR %EAX,%EAX |
0x4015d3 CALL 401050 <omp_get_num_threads@plt> |
0x4015d8 MOV %EAX,%R13D |
0x4015db CALL 401080 <omp_get_thread_num@plt> |
0x4015e0 MOV %EAX,%EBX |
0x4015e2 MOV 0x10(%R12),%EAX |
0x4015e7 CLTD |
0x4015e8 IDIV %R13D |
0x4015eb CMP %EDX,%EBX |
0x4015ed JL 4018c8 |
0x4015f3 IMUL %EAX,%EBX |
0x4015f6 ADD %EBX,%EDX |
0x4015f8 LEA (%RAX,%RDX,1),%ECX |
0x4015fb CMP %ECX,%EDX |
0x4015fd JGE 401800 |
0x401603 MOV 0xc(%R12),%ESI |
0x401608 MOVSXD %EDX,%RBX |
0x40160b MOV %EAX,%EDI |
0x40160d LEA 0x24d96c(%RIP),%R9 |
0x401614 SAL $0x2,%RBX |
0x401618 LEA 0x1ebee1(%RIP),%R11 |
0x40161f VMOVSS 0x8(%R12),%XMM5 |
0x401626 VMOVSS 0x4(%R12),%XMM4 |
0x40162d LEA (%R11,%RBX,1),%R14 |
0x401631 LEA (%R9,%RBX,1),%R10 |
0x401635 MOV %ESI,-0x54(%RBP) |
0x401638 VMOVSS (%R12),%XMM3 |
0x40163e LEA (,%RDI,4),%R8 |
0x401646 LEA 0x18a433(%RIP),%R15 |
0x40164d MOV %R14,-0x68(%RBP) |
0x401651 XOR %R14D,%R14D |
0x401654 LEA 0xc6f25(%RIP),%R13 |
0x40165b LEA 0x6549e(%RIP),%R12 |
0x401662 MOV %R8,-0x90(%RBP) |
0x401669 LEA 0x3a10(%RIP),%RAX |
0x401670 LEA -0x44(%RBP),%RDX |
0x401674 ADD %RBX,%R13 |
0x401677 ADD %RBX,%R12 |
0x40167a LEA -0x3c(%RBP),%RCX |
0x40167e LEA -0x40(%RBP),%RSI |
0x401682 MOV %R10,-0x60(%RBP) |
0x401686 LEA (%R15,%RBX,1),%R15 |
0x40168a MOV %RDX,-0x78(%RBP) |
0x40168e ADD %RAX,%RBX |
0x401691 MOV %RCX,-0x70(%RBP) |
0x401695 MOV %RSI,-0x80(%RBP) |
0x401699 TEST $0x1,%DIL |
0x40169d JNE 401828 |
0x4016a3 NOPL (%RAX,%RAX,1) |
(2) 0x4016a8 VMOVSS (%R15,%R14,1),%XMM0 |
(2) 0x4016ae VMOVSS %XMM5,-0x88(%RBP) |
(2) 0x4016b6 MOV -0x60(%RBP),%R11 |
(2) 0x4016ba LEA 0x12893f(%RIP),%R8 |
(2) 0x4016c1 PUSHQ -0x70(%RBP) |
(2) 0x4016c4 MOV -0x68(%RBP),%RAX |
(2) 0x4016c8 LEA 0x24d8b1(%RIP),%RCX |
(2) 0x4016cf LEA 0x1ebe2a(%RIP),%RDX |
(2) 0x4016d6 VMOVSS (%R11,%R14,1),%XMM2 |
(2) 0x4016dc LEA 0x18a39d(%RIP),%RSI |
(2) 0x4016e3 VMOVSS (%RAX,%R14,1),%XMM1 |
(2) 0x4016e9 MOV -0x78(%RBP),%R9 |
(2) 0x4016ed PUSHQ -0x80(%RBP) |
(2) 0x4016f0 MOV -0x54(%RBP),%EDI |
(2) 0x4016f3 VMOVSS %XMM4,-0x84(%RBP) |
(2) 0x4016fb VMOVSS %XMM3,-0x58(%RBP) |
(2) 0x401700 CALL 4019e0 <Step10_orig> |
(2) 0x401705 VMOVSS -0x88(%RBP),%XMM4 |
(2) 0x40170d VMOVSS -0x44(%RBP),%XMM3 |
(2) 0x401712 LEA 0x1288e7(%RIP),%R8 |
(2) 0x401719 VMOVSS -0x40(%RBP),%XMM6 |
(2) 0x40171e VMOVSS -0x3c(%RBP),%XMM7 |
(2) 0x401723 LEA 0x1ebdd6(%RIP),%RDX |
(2) 0x40172a VFMADD213SS (%R13,%R14,1),%XMM4,%XMM3 |
(2) 0x401731 VMOVSS 0x4(%R15,%R14,1),%XMM0 |
(2) 0x401738 VFMADD213SS (%R12,%R14,1),%XMM4,%XMM6 |
(2) 0x40173e VFMADD213SS (%RBX,%R14,1),%XMM4,%XMM7 |
(2) 0x401744 MOV -0x60(%RBP),%RDI |
(2) 0x401748 MOV -0x68(%RBP),%R10 |
(2) 0x40174c MOV -0x78(%RBP),%R9 |
(2) 0x401750 VMOVSS -0x84(%RBP),%XMM4 |
(2) 0x401758 VMOVSS 0x4(%RDI,%R14,1),%XMM2 |
(2) 0x40175f VMOVSS 0x4(%R10,%R14,1),%XMM1 |
(2) 0x401766 VMOVSS %XMM3,(%R13,%R14,1) |
(2) 0x40176d MOV -0x54(%RBP),%EDI |
(2) 0x401770 VMOVSS -0x58(%RBP),%XMM3 |
(2) 0x401775 VMOVSS %XMM6,(%R12,%R14,1) |
(2) 0x40177b VMOVSS %XMM7,(%RBX,%R14,1) |
(2) 0x401781 POP %RCX |
(2) 0x401782 LEA 0x24d7f7(%RIP),%RCX |
(2) 0x401789 POP %RSI |
(2) 0x40178a LEA 0x18a2ef(%RIP),%RSI |
(2) 0x401791 PUSHQ -0x70(%RBP) |
(2) 0x401794 PUSHQ -0x80(%RBP) |
(2) 0x401797 CALL 4019e0 <Step10_orig> |
(2) 0x40179c VMOVSS -0x88(%RBP),%XMM5 |
(2) 0x4017a4 VMOVSS -0x44(%RBP),%XMM8 |
(2) 0x4017a9 VMOVSS -0x40(%RBP),%XMM9 |
(2) 0x4017ae VMOVSS -0x3c(%RBP),%XMM10 |
(2) 0x4017b3 VFMADD213SS 0x4(%R13,%R14,1),%XMM5,%XMM8 |
(2) 0x4017ba VFMADD213SS 0x4(%R12,%R14,1),%XMM5,%XMM9 |
(2) 0x4017c1 VFMADD213SS 0x4(%RBX,%R14,1),%XMM5,%XMM10 |
(2) 0x4017c8 VMOVSS %XMM8,0x4(%R13,%R14,1) |
(2) 0x4017cf VMOVSS %XMM9,0x4(%R12,%R14,1) |
(2) 0x4017d6 VMOVSS %XMM10,0x4(%RBX,%R14,1) |
(2) 0x4017dd ADD $0x8,%R14 |
(2) 0x4017e1 MOV -0x90(%RBP),%R8 |
(2) 0x4017e8 POP %RAX |
(2) 0x4017e9 VMOVSS -0x58(%RBP),%XMM3 |
(2) 0x4017ee VMOVSS -0x84(%RBP),%XMM4 |
(2) 0x4017f6 CMP %R8,%R14 |
(2) 0x4017f9 POP %RDX |
(2) 0x4017fa JNE 4016a8 |
0x401800 MOV -0x38(%RBP),%RAX |
0x401804 SUB %FS:0x28,%RAX |
0x40180d JNE 4018d1 |
0x401813 LEA -0x28(%RBP),%RSP |
0x401817 POP %RBX |
0x401818 POP %R12 |
0x40181a POP %R13 |
0x40181c POP %R14 |
0x40181e POP %R15 |
0x401820 POP %RBP |
0x401821 RET |
0x401822 NOPW (%RAX,%RAX,1) |
0x401828 VMOVSS (%R15),%XMM0 |
0x40182d VMOVSS %XMM5,-0x88(%RBP) |
0x401835 MOV -0x60(%RBP),%RDI |
0x401839 LEA 0x1287c0(%RIP),%R8 |
0x401840 PUSHQ -0x70(%RBP) |
0x401843 MOV -0x68(%RBP),%R10 |
0x401847 LEA 0x24d732(%RIP),%RCX |
0x40184e LEA 0x1ebcab(%RIP),%RDX |
0x401855 VMOVSS (%RDI),%XMM2 |
0x401859 LEA 0x18a220(%RIP),%RSI |
0x401860 MOV $0x4,%R14D |
0x401866 VMOVSS (%R10),%XMM1 |
0x40186b MOV -0x78(%RBP),%R9 |
0x40186f PUSHQ -0x80(%RBP) |
0x401872 MOV -0x54(%RBP),%EDI |
0x401875 VMOVSS %XMM4,-0x84(%RBP) |
0x40187d VMOVSS %XMM3,-0x58(%RBP) |
0x401882 CALL 4019e0 <Step10_orig> |
0x401887 VMOVSS -0x88(%RBP),%XMM5 |
0x40188f VMOVSS -0x44(%RBP),%XMM0 |
0x401894 VMOVSS -0x40(%RBP),%XMM1 |
0x401899 VMOVSS -0x3c(%RBP),%XMM2 |
0x40189e VFMADD213SS (%R13),%XMM5,%XMM0 |
0x4018a4 VFMADD213SS (%R12),%XMM5,%XMM1 |
0x4018aa VFMADD213SS (%RBX),%XMM5,%XMM2 |
0x4018af VMOVSS %XMM0,(%R13) |
0x4018b5 VMOVSS %XMM1,(%R12) |
0x4018bb VMOVSS %XMM2,(%RBX) |
0x4018bf JMP 4017e1 |
0x4018c4 NOPL (%RAX) |
0x4018c8 INC %EAX |
0x4018ca XOR %EDX,%EDX |
0x4018cc JMP 4015f3 |
0x4018d1 CALL 4010a0 <__stack_chk_fail@plt> |
0x4018d6 NOPW %CS:(%RAX,%RAX,1) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○100.00 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Source file and lines | main.c:139-146 |
Module | exec |
nb instructions | 107 |
nb uops | 122 |
loop length | 472 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 6 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 15 |
micro-operation queue | 30.50 cycles |
front end | 30.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 14.50 | 14.50 | 19.00 | 19.00 | 26.00 | 14.50 | 14.50 | 19.00 |
cycles | 14.50 | 16.00 | 19.00 | 19.00 | 26.00 | 14.50 | 14.50 | 19.00 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 28.07 |
Stall cycles | 0.00 |
Front-end | 30.50 |
Dispatch | 26.00 |
DIV/SQRT | 6.00 |
Overall L1 | 30.50 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
all | 9% |
load | 6% |
store | 11% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 6% |
load | 6% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 6% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 7% |
load | 6% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | 6% |
div/sqrt | 6% |
other | 6% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
PUSH %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
PUSH %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
SUB $0x68,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV %FS:0x28,%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %RAX,-0x38(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CALL 401050 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CALL 401080 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x10(%R12),%EAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
IDIV %R13D | 10 | 2.50 | 2.50 | 0 | 0 | 0 | 2.50 | 2.50 | 0 | 26 | 6 |
CMP %EDX,%EBX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JL 4018c8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
IMUL %EAX,%EBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EBX,%EDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA (%RAX,%RDX,1),%ECX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%EDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JGE 401800 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV 0xc(%R12),%ESI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOVSXD %EDX,%RBX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
LEA 0x24d96c(%RIP),%R9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x2,%RBX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
LEA 0x1ebee1(%RIP),%R11 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSS 0x8(%R12),%XMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS 0x4(%R12),%XMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA (%R11,%RBX,1),%R14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R9,%RBX,1),%R10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,-0x54(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSS (%R12),%XMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA (,%RDI,4),%R8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x18a433(%RIP),%R15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,-0x68(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
XOR %R14D,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
LEA 0xc6f25(%RIP),%R13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x6549e(%RIP),%R12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,-0x90(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
LEA 0x3a10(%RIP),%RAX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x44(%RBP),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RBX,%R13 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
ADD %RBX,%R12 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA -0x3c(%RBP),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x40(%RBP),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,-0x60(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
LEA (%R15,%RBX,1),%R15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,-0x78(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
ADD %RAX,%RBX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV %RCX,-0x70(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RSI,-0x80(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
TEST $0x1,%DIL | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JNE 401828 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV -0x38(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
SUB %FS:0x28,%RAX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JNE 4018d1 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
POP %RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %RBP | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
RET | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 | 0 | 1 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVSS (%R15),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS %XMM5,-0x88(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x60(%RBP),%RDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x1287c0(%RIP),%R8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
PUSHQ -0x70(%RBP) | 2 | 0 | 0 | 0.83 | 0.83 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x68(%RBP),%R10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x24d732(%RIP),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x1ebcab(%RIP),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSS (%RDI),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x18a220(%RIP),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x4,%R14D | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVSS (%R10),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0x78(%RBP),%R9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
PUSHQ -0x80(%RBP) | 2 | 0 | 0 | 0.83 | 0.83 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x54(%RBP),%EDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS %XMM4,-0x84(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSS %XMM3,-0x58(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CALL 4019e0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
VMOVSS -0x88(%RBP),%XMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS -0x44(%RBP),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS -0x40(%RBP),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS -0x3c(%RBP),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VFMADD213SS (%R13),%XMM5,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SS (%R12),%XMM5,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SS (%RBX),%XMM5,%XMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSS %XMM0,(%R13) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSS %XMM1,(%R12) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSS %XMM2,(%RBX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
JMP 4017e1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
INC %EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 4015f3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
CALL 4010a0 <__stack_chk_fail@plt> | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
Source file and lines | main.c:139-146 |
Module | exec |
nb instructions | 107 |
nb uops | 122 |
loop length | 472 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 6 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 15 |
micro-operation queue | 30.50 cycles |
front end | 30.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 14.50 | 14.50 | 19.00 | 19.00 | 26.00 | 14.50 | 14.50 | 19.00 |
cycles | 14.50 | 16.00 | 19.00 | 19.00 | 26.00 | 14.50 | 14.50 | 19.00 |
Cycles executing div or sqrt instructions | 6.00 |
FE+BE cycles | 28.07 |
Stall cycles | 0.00 |
Front-end | 30.50 |
Dispatch | 26.00 |
DIV/SQRT | 6.00 |
Overall L1 | 30.50 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | 0% |
other | 0% |
all | 9% |
load | 6% |
store | 11% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 6% |
load | 6% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 6% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 7% |
load | 6% |
store | 9% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | 6% |
div/sqrt | 6% |
other | 6% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
PUSH %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSH %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
PUSH %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
SUB $0x68,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV %FS:0x28,%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV %RAX,-0x38(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CALL 401050 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
MOV %EAX,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
CALL 401080 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV 0x10(%R12),%EAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
IDIV %R13D | 10 | 2.50 | 2.50 | 0 | 0 | 0 | 2.50 | 2.50 | 0 | 26 | 6 |
CMP %EDX,%EBX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JL 4018c8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
IMUL %EAX,%EBX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %EBX,%EDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA (%RAX,%RDX,1),%ECX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %ECX,%EDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JGE 401800 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
MOV 0xc(%R12),%ESI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOVSXD %EDX,%RBX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV %EAX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
LEA 0x24d96c(%RIP),%R9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x2,%RBX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
LEA 0x1ebee1(%RIP),%R11 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSS 0x8(%R12),%XMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS 0x4(%R12),%XMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA (%R11,%RBX,1),%R14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%R9,%RBX,1),%R10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %ESI,-0x54(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSS (%R12),%XMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA (,%RDI,4),%R8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x18a433(%RIP),%R15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,-0x68(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
XOR %R14D,%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
LEA 0xc6f25(%RIP),%R13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x6549e(%RIP),%R12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,-0x90(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
LEA 0x3a10(%RIP),%RAX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x44(%RBP),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RBX,%R13 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
ADD %RBX,%R12 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
LEA -0x3c(%RBP),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA -0x40(%RBP),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,-0x60(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
LEA (%R15,%RBX,1),%R15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,-0x78(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
ADD %RAX,%RBX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV %RCX,-0x70(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV %RSI,-0x80(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
TEST $0x1,%DIL | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
JNE 401828 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
MOV -0x38(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
SUB %FS:0x28,%RAX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
JNE 4018d1 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
POP %RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
POP %RBP | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
RET | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 | 0 | 1 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
VMOVSS (%R15),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS %XMM5,-0x88(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x60(%RBP),%RDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x1287c0(%RIP),%R8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
PUSHQ -0x70(%RBP) | 2 | 0 | 0 | 0.83 | 0.83 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x68(%RBP),%R10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x24d732(%RIP),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x1ebcab(%RIP),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSS (%RDI),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x18a220(%RIP),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x4,%R14D | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
VMOVSS (%R10),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0x78(%RBP),%R9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
PUSHQ -0x80(%RBP) | 2 | 0 | 0 | 0.83 | 0.83 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x54(%RBP),%EDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS %XMM4,-0x84(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSS %XMM3,-0x58(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CALL 4019e0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
VMOVSS -0x88(%RBP),%XMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS -0x44(%RBP),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS -0x40(%RBP),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS -0x3c(%RBP),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VFMADD213SS (%R13),%XMM5,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SS (%R12),%XMM5,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SS (%RBX),%XMM5,%XMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSS %XMM0,(%R13) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSS %XMM1,(%R12) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSS %XMM2,(%RBX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
JMP 4017e1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
INC %EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
JMP 4015f3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
CALL 4010a0 <__stack_chk_fail@plt> | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼main._omp_fn.1– | 0.06 | 0.02 |
○Loop 2 - main.c:142-146 - exec | 0.06 | 0.02 |