Loop Id: 2 | Module: exec | Source: main.c:142-146 | Coverage: 0.06% |
---|
Loop Id: 2 | Module: exec | Source: main.c:142-146 | Coverage: 0.06% |
---|
0x4016a8 VMOVSS (%R15,%R14,1),%XMM0 [3] |
0x4016ae VMOVSS %XMM5,-0x88(%RBP) [6] |
0x4016b6 MOV -0x60(%RBP),%R11 [6] |
0x4016ba LEA 0x12893f(%RIP),%R8 |
0x4016c1 PUSHQ -0x70(%RBP) [6] |
0x4016c4 MOV -0x68(%RBP),%RAX [6] |
0x4016c8 LEA 0x24d8b1(%RIP),%RCX |
0x4016cf LEA 0x1ebe2a(%RIP),%RDX |
0x4016d6 VMOVSS (%R11,%R14,1),%XMM2 [5] |
0x4016dc LEA 0x18a39d(%RIP),%RSI |
0x4016e3 VMOVSS (%RAX,%R14,1),%XMM1 [4] |
0x4016e9 MOV -0x78(%RBP),%R9 [6] |
0x4016ed PUSHQ -0x80(%RBP) [6] |
0x4016f0 MOV -0x54(%RBP),%EDI [6] |
0x4016f3 VMOVSS %XMM4,-0x84(%RBP) [6] |
0x4016fb VMOVSS %XMM3,-0x58(%RBP) [6] |
0x401700 CALL 4019e0 <Step10_orig> |
0x401705 VMOVSS -0x88(%RBP),%XMM4 [6] |
0x40170d VMOVSS -0x44(%RBP),%XMM3 [6] |
0x401712 LEA 0x1288e7(%RIP),%R8 |
0x401719 VMOVSS -0x40(%RBP),%XMM6 [6] |
0x40171e VMOVSS -0x3c(%RBP),%XMM7 [6] |
0x401723 LEA 0x1ebdd6(%RIP),%RDX |
0x40172a VFMADD213SS (%R13,%R14,1),%XMM4,%XMM3 [7] |
0x401731 VMOVSS 0x4(%R15,%R14,1),%XMM0 [3] |
0x401738 VFMADD213SS (%R12,%R14,1),%XMM4,%XMM6 [2] |
0x40173e VFMADD213SS (%RBX,%R14,1),%XMM4,%XMM7 [1] |
0x401744 MOV -0x60(%RBP),%RDI [6] |
0x401748 MOV -0x68(%RBP),%R10 [6] |
0x40174c MOV -0x78(%RBP),%R9 [6] |
0x401750 VMOVSS -0x84(%RBP),%XMM4 [6] |
0x401758 VMOVSS 0x4(%RDI,%R14,1),%XMM2 [5] |
0x40175f VMOVSS 0x4(%R10,%R14,1),%XMM1 [4] |
0x401766 VMOVSS %XMM3,(%R13,%R14,1) [7] |
0x40176d MOV -0x54(%RBP),%EDI [6] |
0x401770 VMOVSS -0x58(%RBP),%XMM3 [6] |
0x401775 VMOVSS %XMM6,(%R12,%R14,1) [2] |
0x40177b VMOVSS %XMM7,(%RBX,%R14,1) [1] |
0x401781 POP %RCX |
0x401782 LEA 0x24d7f7(%RIP),%RCX |
0x401789 POP %RSI |
0x40178a LEA 0x18a2ef(%RIP),%RSI |
0x401791 PUSHQ -0x70(%RBP) [6] |
0x401794 PUSHQ -0x80(%RBP) [6] |
0x401797 CALL 4019e0 <Step10_orig> |
0x40179c VMOVSS -0x88(%RBP),%XMM5 [6] |
0x4017a4 VMOVSS -0x44(%RBP),%XMM8 [6] |
0x4017a9 VMOVSS -0x40(%RBP),%XMM9 [6] |
0x4017ae VMOVSS -0x3c(%RBP),%XMM10 [6] |
0x4017b3 VFMADD213SS 0x4(%R13,%R14,1),%XMM5,%XMM8 [7] |
0x4017ba VFMADD213SS 0x4(%R12,%R14,1),%XMM5,%XMM9 [2] |
0x4017c1 VFMADD213SS 0x4(%RBX,%R14,1),%XMM5,%XMM10 [1] |
0x4017c8 VMOVSS %XMM8,0x4(%R13,%R14,1) [7] |
0x4017cf VMOVSS %XMM9,0x4(%R12,%R14,1) [2] |
0x4017d6 VMOVSS %XMM10,0x4(%RBX,%R14,1) [1] |
0x4017dd ADD $0x8,%R14 |
0x4017e1 MOV -0x90(%RBP),%R8 [6] |
0x4017e8 POP %RAX |
0x4017e9 VMOVSS -0x58(%RBP),%XMM3 [6] |
0x4017ee VMOVSS -0x84(%RBP),%XMM4 [6] |
0x4017f6 CMP %R8,%R14 |
0x4017f9 POP %RDX |
0x4017fa JNE 4016a8 |
/home/kcamus/qaas_runs/169-401-3406/intel/HACCmk/build/HACCmk/src/main.c: 142 - 146 |
-------------------------------------------------------------------------------- |
142: Step10_orig( n, xx[i], yy[i], zz[i], fsrrmax2, mp_rsm2, xx, yy, zz, mass, &dx1, &dy1, &dz1 ); |
143: |
144: vx1[i] = vx1[i] + dx1 * fcoeff; |
145: vy1[i] = vy1[i] + dy1 * fcoeff; |
146: vz1[i] = vz1[i] + dz1 * fcoeff; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○100.00 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.64 |
CQA speedup if FP arith vectorized | 1.52 |
CQA speedup if fully vectorized | 15.26 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.09 |
Bottlenecks | P2, P3, |
Function | main._omp_fn.1 |
Source | main.c:142-146 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 20.50 |
CQA cycles if no scalar integer | 12.50 |
CQA cycles if FP arith vectorized | 13.47 |
CQA cycles if fully vectorized | 1.34 |
Front-end cycles | 18.75 |
DIV/SQRT cycles | 5.00 |
P0 cycles | 5.00 |
P1 cycles | 20.50 |
P2 cycles | 20.50 |
P3 cycles | 15.00 |
P4 cycles | 4.50 |
P5 cycles | 4.50 |
P6 cycles | 15.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 20.68 |
Stall cycles (UFS) | 2.20 |
Nb insns | 63.00 |
Nb uops | 69.00 |
Nb loads | 41.00 |
Nb stores | 9.00 |
Nb stack references | 13.00 |
FLOP/cycle | 0.59 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 6.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 11.12 |
Bytes prefetched | 0.00 |
Bytes loaded | 192.00 |
Bytes stored | 36.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 6.61 |
Vector-efficiency ratio load | 6.73 |
Vector-efficiency ratio store | 6.25 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | 6.25 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.64 |
CQA speedup if FP arith vectorized | 1.52 |
CQA speedup if fully vectorized | 15.26 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.09 |
Bottlenecks | P2, P3, |
Function | main._omp_fn.1 |
Source | main.c:142-146 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 20.50 |
CQA cycles if no scalar integer | 12.50 |
CQA cycles if FP arith vectorized | 13.47 |
CQA cycles if fully vectorized | 1.34 |
Front-end cycles | 18.75 |
DIV/SQRT cycles | 5.00 |
P0 cycles | 5.00 |
P1 cycles | 20.50 |
P2 cycles | 20.50 |
P3 cycles | 15.00 |
P4 cycles | 4.50 |
P5 cycles | 4.50 |
P6 cycles | 15.00 |
P7 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 20.68 |
Stall cycles (UFS) | 2.20 |
Nb insns | 63.00 |
Nb uops | 69.00 |
Nb loads | 41.00 |
Nb stores | 9.00 |
Nb stack references | 13.00 |
FLOP/cycle | 0.59 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 6.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 11.12 |
Bytes prefetched | 0.00 |
Bytes loaded | 192.00 |
Bytes stored | 36.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 6.61 |
Vector-efficiency ratio load | 6.73 |
Vector-efficiency ratio store | 6.25 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | 6.25 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Path / |
Function | main._omp_fn.1 |
Source file and lines | main.c:142-146 |
Module | exec |
nb instructions | 63 |
nb uops | 69 |
loop length | 344 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 11 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 13 |
micro-operation queue | 18.75 cycles |
front end | 18.75 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 5.00 | 5.00 | 20.50 | 20.50 | 15.00 | 4.50 | 4.50 | 15.00 |
cycles | 5.00 | 5.00 | 20.50 | 20.50 | 15.00 | 4.50 | 4.50 | 15.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 20.68 |
Stall cycles | 2.20 |
LM full (events) | 4.40 |
Front-end | 18.75 |
Dispatch | 20.50 |
Overall L1 | 20.50 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 6% |
load | 6% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 6% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 6% |
load | 6% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 6% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VMOVSS (%R15,%R14,1),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS %XMM5,-0x88(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x60(%RBP),%R11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x12893f(%RIP),%R8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
PUSHQ -0x70(%RBP) | 2 | 0 | 0 | 0.83 | 0.83 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x68(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x24d8b1(%RIP),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x1ebe2a(%RIP),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSS (%R11,%R14,1),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x18a39d(%RIP),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSS (%RAX,%R14,1),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0x78(%RBP),%R9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
PUSHQ -0x80(%RBP) | 2 | 0 | 0 | 0.83 | 0.83 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x54(%RBP),%EDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS %XMM4,-0x84(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSS %XMM3,-0x58(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CALL 4019e0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
VMOVSS -0x88(%RBP),%XMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS -0x44(%RBP),%XMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x1288e7(%RIP),%R8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSS -0x40(%RBP),%XMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS -0x3c(%RBP),%XMM7 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x1ebdd6(%RIP),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VFMADD213SS (%R13,%R14,1),%XMM4,%XMM3 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSS 0x4(%R15,%R14,1),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VFMADD213SS (%R12,%R14,1),%XMM4,%XMM6 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SS (%RBX,%R14,1),%XMM4,%XMM7 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV -0x60(%RBP),%RDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0x68(%RBP),%R10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0x78(%RBP),%R9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS -0x84(%RBP),%XMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS 0x4(%RDI,%R14,1),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS 0x4(%R10,%R14,1),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS %XMM3,(%R13,%R14,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x54(%RBP),%EDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS -0x58(%RBP),%XMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS %XMM6,(%R12,%R14,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSS %XMM7,(%RBX,%R14,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
POP %RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
LEA 0x24d7f7(%RIP),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
POP %RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
LEA 0x18a2ef(%RIP),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
PUSHQ -0x70(%RBP) | 2 | 0 | 0 | 0.83 | 0.83 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSHQ -0x80(%RBP) | 2 | 0 | 0 | 0.83 | 0.83 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CALL 4019e0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
VMOVSS -0x88(%RBP),%XMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS -0x44(%RBP),%XMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS -0x40(%RBP),%XMM9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS -0x3c(%RBP),%XMM10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VFMADD213SS 0x4(%R13,%R14,1),%XMM5,%XMM8 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SS 0x4(%R12,%R14,1),%XMM5,%XMM9 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SS 0x4(%RBX,%R14,1),%XMM5,%XMM10 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSS %XMM8,0x4(%R13,%R14,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSS %XMM9,0x4(%R12,%R14,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSS %XMM10,0x4(%RBX,%R14,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
ADD $0x8,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV -0x90(%RBP),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
POP %RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
VMOVSS -0x58(%RBP),%XMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS -0x84(%RBP),%XMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
CMP %R8,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
POP %RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
JNE 4016a8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
Function | main._omp_fn.1 |
Source file and lines | main.c:142-146 |
Module | exec |
nb instructions | 63 |
nb uops | 69 |
loop length | 344 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 11 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 13 |
micro-operation queue | 18.75 cycles |
front end | 18.75 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
---|---|---|---|---|---|---|---|---|
uops | 5.00 | 5.00 | 20.50 | 20.50 | 15.00 | 4.50 | 4.50 | 15.00 |
cycles | 5.00 | 5.00 | 20.50 | 20.50 | 15.00 | 4.50 | 4.50 | 15.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 20.68 |
Stall cycles | 2.20 |
LM full (events) | 4.40 |
Front-end | 18.75 |
Dispatch | 20.50 |
Overall L1 | 20.50 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 6% |
load | 6% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 6% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 6% |
load | 6% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 6% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|
VMOVSS (%R15,%R14,1),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS %XMM5,-0x88(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x60(%RBP),%R11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x12893f(%RIP),%R8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
PUSHQ -0x70(%RBP) | 2 | 0 | 0 | 0.83 | 0.83 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x68(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x24d8b1(%RIP),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x1ebe2a(%RIP),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSS (%R11,%R14,1),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x18a39d(%RIP),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSS (%RAX,%R14,1),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0x78(%RBP),%R9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
PUSHQ -0x80(%RBP) | 2 | 0 | 0 | 0.83 | 0.83 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x54(%RBP),%EDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS %XMM4,-0x84(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSS %XMM3,-0x58(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CALL 4019e0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
VMOVSS -0x88(%RBP),%XMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS -0x44(%RBP),%XMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x1288e7(%RIP),%R8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSS -0x40(%RBP),%XMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS -0x3c(%RBP),%XMM7 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
LEA 0x1ebdd6(%RIP),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
VFMADD213SS (%R13,%R14,1),%XMM4,%XMM3 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSS 0x4(%R15,%R14,1),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VFMADD213SS (%R12,%R14,1),%XMM4,%XMM6 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SS (%RBX,%R14,1),%XMM4,%XMM7 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV -0x60(%RBP),%RDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0x68(%RBP),%R10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
MOV -0x78(%RBP),%R9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS -0x84(%RBP),%XMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS 0x4(%RDI,%R14,1),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS 0x4(%R10,%R14,1),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS %XMM3,(%R13,%R14,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
MOV -0x54(%RBP),%EDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS -0x58(%RBP),%XMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS %XMM6,(%R12,%R14,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSS %XMM7,(%RBX,%R14,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
POP %RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
LEA 0x24d7f7(%RIP),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
POP %RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
LEA 0x18a2ef(%RIP),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
PUSHQ -0x70(%RBP) | 2 | 0 | 0 | 0.83 | 0.83 | 1 | 0 | 0 | 0.33 | 3 | 1 |
PUSHQ -0x80(%RBP) | 2 | 0 | 0 | 0.83 | 0.83 | 1 | 0 | 0 | 0.33 | 3 | 1 |
CALL 4019e0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
VMOVSS -0x88(%RBP),%XMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS -0x44(%RBP),%XMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS -0x40(%RBP),%XMM9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS -0x3c(%RBP),%XMM10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VFMADD213SS 0x4(%R13,%R14,1),%XMM5,%XMM8 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SS 0x4(%R12,%R14,1),%XMM5,%XMM9 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SS 0x4(%RBX,%R14,1),%XMM5,%XMM10 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSS %XMM8,0x4(%R13,%R14,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSS %XMM9,0x4(%R12,%R14,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
VMOVSS %XMM10,0x4(%RBX,%R14,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
ADD $0x8,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
MOV -0x90(%RBP),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
POP %RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
VMOVSS -0x58(%RBP),%XMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
VMOVSS -0x84(%RBP),%XMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
CMP %R8,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
POP %RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
JNE 4016a8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
Metric | run_0 |
---|---|
Coverage (% app. time) | 0.06 |
Time (s) | 0.02 |
Instance Count | 730 |
Iteration Count - min | 183 |
Iteration Count - avg | 183 |
Iteration Count - max | 183 |
Cycles per Iteration - min | 57956.61 |
Cycles per Iteration - avg | 660517.67 |
Cycles per Iteration - max | 1273332.49 |