Loop Id: 4 | Module: exec | Source: Step10_orig.c:19-31 | Coverage: 91.87% |
---|
Loop Id: 4 | Module: exec | Source: Step10_orig.c:19-31 | Coverage: 91.87% |
---|
0x401a60 VMOVUPS (%RDX,%R11,1),%ZMM0 [1] |
0x401a67 VMOVUPS (%RSI,%R11,1),%ZMM6 [3] |
0x401a6e VMOVUPS (%RCX,%R11,1),%ZMM5 [2] |
0x401a75 VSUBPS %ZMM25,%ZMM0,%ZMM8 |
0x401a7b VSUBPS %ZMM26,%ZMM6,%ZMM9 |
0x401a81 VSUBPS %ZMM24,%ZMM5,%ZMM30 |
0x401a87 VMULPS %ZMM8,%ZMM8,%ZMM28 |
0x401a8d VFMADD231PS %ZMM9,%ZMM9,%ZMM28 |
0x401a93 VFMADD231PS %ZMM30,%ZMM30,%ZMM28 |
0x401a99 VCMPPS $0xe,%ZMM15,%ZMM28,%K2 |
0x401aa0 VCMPPS $0x1,%ZMM23,%ZMM28,%K1 |
0x401aa7 VADDPS %ZMM22,%ZMM28,%ZMM0 |
0x401aad VCVTPS2PD %YMM0,%ZMM6 |
0x401ab3 VEXTRACTF32X8 $0x1,%ZMM0,%YMM5 |
0x401aba VMOVAPS %ZMM28,%ZMM0 |
0x401ac0 VSQRTPD %ZMM6,%ZMM29 |
0x401ac6 VMOVUPS (%R8,%R11,1),%ZMM13{%K1} [4] |
0x401acd ADD $0x40,%R11 |
0x401ad1 VCVTPS2PD %YMM5,%ZMM5 |
0x401ad7 VMULPD %ZMM29,%ZMM6,%ZMM6 |
0x401add VFMADD132PS %ZMM21,%ZMM20,%ZMM0 |
0x401ae3 VSQRTPD %ZMM5,%ZMM31 |
0x401ae9 VMOVAPS %ZMM13,%ZMM27{%K1}{z} |
0x401aef VMULPD %ZMM31,%ZMM5,%ZMM5 |
0x401af5 VFMADD132PS %ZMM28,%ZMM19,%ZMM0 |
0x401afb VDIVPD %ZMM6,%ZMM14,%ZMM6 |
0x401b01 VDIVPD %ZMM5,%ZMM14,%ZMM5 |
0x401b07 VFMADD132PS %ZMM28,%ZMM18,%ZMM0 |
0x401b0d VFMADD132PS %ZMM28,%ZMM17,%ZMM0 |
0x401b13 VFMADD132PS %ZMM28,%ZMM16,%ZMM0 |
0x401b19 VCVTPS2PD %YMM0,%ZMM28 |
0x401b1f VEXTRACTF32X8 $0x1,%ZMM0,%YMM0 |
0x401b26 VADDPD %ZMM28,%ZMM6,%ZMM6 |
0x401b2c VCVTPS2PD %YMM0,%ZMM0 |
0x401b32 VADDPD %ZMM0,%ZMM5,%ZMM5 |
0x401b38 VCVTPD2PS %ZMM6,%YMM6 |
0x401b3e VCVTPD2PS %ZMM5,%YMM0 |
0x401b44 VINSERTF64X4 $0x1,%YMM0,%ZMM6,%ZMM5 |
0x401b4b VMULPS %ZMM27,%ZMM5,%ZMM6 |
0x401b51 VMULPS %ZMM6,%ZMM9,%ZMM0{%K2}{z} |
0x401b57 VMULPS %ZMM6,%ZMM8,%ZMM9{%K2}{z} |
0x401b5d VMULPS %ZMM6,%ZMM30,%ZMM8{%K2}{z} |
0x401b63 VADDPS %ZMM0,%ZMM10,%ZMM10 |
0x401b69 VADDPS %ZMM9,%ZMM11,%ZMM11 |
0x401b6f VADDPS %ZMM8,%ZMM12,%ZMM12 |
0x401b75 CMP %R11,%RBX |
0x401b78 JNE 401a60 |
/scratch_na/users/xoserete/qaas_runs/171-317-5776/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19 - 31 |
-------------------------------------------------------------------------------- |
19: for ( j = 0; j < count1; j++ ) |
20: { |
21: dxc = xx1[j] - xxi; |
22: dyc = yy1[j] - yyi; |
23: dzc = zz1[j] - zzi; |
24: |
25: r2 = dxc * dxc + dyc * dyc + dzc * dzc; |
26: |
27: m = ( r2 < fsrrmax2 ) ? mass1[j] : 0.0f; |
28: |
29: f = pow( r2 + mp_rsm2, -1.5 ) - ( ma0 + r2*(ma1 + r2*(ma2 + r2*(ma3 + r2*(ma4 + r2*ma5))))); |
30: |
31: f = ( r2 > 0.0f ) ? m * f : 0.0f; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 2.62 |
Bottlenecks | P0, |
Function | Step10_orig |
Source | Step10_orig.c:19-31 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 68.00 |
CQA cycles if no scalar integer | 68.00 |
CQA cycles if FP arith vectorized | 68.00 |
CQA cycles if fully vectorized | 68.00 |
Front-end cycles | 10.00 |
DIV/SQRT cycles | 26.00 |
P0 cycles | 11.50 |
P1 cycles | 1.33 |
P2 cycles | 1.33 |
P3 cycles | 0.00 |
P4 cycles | 26.00 |
P5 cycles | 1.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 1.33 |
P11 cycles | 68.00 |
Inter-iter dependencies cycles | 3 |
FE+BE cycles (UFS) | 69.98 - 69.04 |
Stall cycles (UFS) | 59.37 - 58.43 |
Nb insns | 47.00 |
Nb uops | 60.00 |
Nb loads | 4.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 7.06 |
Nb FLOP add-sub | 128.00 |
Nb FLOP mul | 96.00 |
Nb FLOP fma | 112.00 |
Nb FLOP div | 16.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 16.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 3.76 |
Bytes prefetched | 0.00 |
Bytes loaded | 256.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 4.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | 100.00 |
Vector-efficiency ratio all | 92.05 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | 100.00 |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | 100.00 |
Vector-efficiency ratio div_sqrt | 100.00 |
Vector-efficiency ratio other | 73.08 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 2.62 |
Bottlenecks | P0, |
Function | Step10_orig |
Source | Step10_orig.c:19-31 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 68.00 |
CQA cycles if no scalar integer | 68.00 |
CQA cycles if FP arith vectorized | 68.00 |
CQA cycles if fully vectorized | 68.00 |
Front-end cycles | 10.00 |
DIV/SQRT cycles | 26.00 |
P0 cycles | 11.50 |
P1 cycles | 1.33 |
P2 cycles | 1.33 |
P3 cycles | 0.00 |
P4 cycles | 26.00 |
P5 cycles | 1.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 1.33 |
P11 cycles | 68.00 |
Inter-iter dependencies cycles | 3 |
FE+BE cycles (UFS) | 69.98 - 69.04 |
Stall cycles (UFS) | 59.37 - 58.43 |
Nb insns | 47.00 |
Nb uops | 60.00 |
Nb loads | 4.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 7.06 |
Nb FLOP add-sub | 128.00 |
Nb FLOP mul | 96.00 |
Nb FLOP fma | 112.00 |
Nb FLOP div | 16.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 16.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 3.76 |
Bytes prefetched | 0.00 |
Bytes loaded | 256.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 4.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | 100.00 |
Vector-efficiency ratio all | 92.05 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | 100.00 |
Vector-efficiency ratio add_sub | 100.00 |
Vector-efficiency ratio fma | 100.00 |
Vector-efficiency ratio div_sqrt | 100.00 |
Vector-efficiency ratio other | 73.08 |
Path / |
Function | Step10_orig |
Source file and lines | Step10_orig.c:19-31 |
Module | exec |
nb instructions | 47 |
nb uops | 60 |
loop length | 286 |
used x86 registers | 6 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 3 |
used zmm registers | 27 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 1.29 |
micro-operation queue | 10.00 cycles |
front end | 10.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 26.00 | 0.00 | 1.33 | 1.33 | 0.00 | 26.00 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 1.33 |
cycles | 26.00 | 11.50 | 1.33 | 1.33 | 0.00 | 26.00 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 1.33 |
Cycles executing div or sqrt instructions | 68.00 |
Longest recurrence chain latency (RecMII) | 3.00 |
FE+BE cycles | 69.98-69.04 |
Stall cycles | 59.37-58.43 |
RS full (events) | 0.56-0.55 |
PRF_FLOAT full (events) | 63.00-62.07 |
Front-end | 10.00 |
Dispatch | 26.00 |
DIV/SQRT | 68.00 |
Data deps. | 3.00 |
Overall L1 | 68.00 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 100% |
all | 92% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 73% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPS (%RDX,%R11,1),%ZMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPS (%RSI,%R11,1),%ZMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPS (%RCX,%R11,1),%ZMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VSUBPS %ZMM25,%ZMM0,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSUBPS %ZMM26,%ZMM6,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSUBPS %ZMM24,%ZMM5,%ZMM30 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPS %ZMM8,%ZMM8,%ZMM28 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PS %ZMM9,%ZMM9,%ZMM28 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PS %ZMM30,%ZMM30,%ZMM28 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCMPPS $0xe,%ZMM15,%ZMM28,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VCMPPS $0x1,%ZMM23,%ZMM28,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPS %ZMM22,%ZMM28,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VCVTPS2PD %YMM0,%ZMM6 | 2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VEXTRACTF32X8 $0x1,%ZMM0,%YMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVAPS %ZMM28,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VSQRTPD %ZMM6,%ZMM29 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 23-32 | 18 |
VMOVUPS (%R8,%R11,1),%ZMM13{%K1} | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
ADD $0x40,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VCVTPS2PD %YMM5,%ZMM5 | 2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VMULPD %ZMM29,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132PS %ZMM21,%ZMM20,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VSQRTPD %ZMM5,%ZMM31 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 23-32 | 18 |
VMOVAPS %ZMM13,%ZMM27{%K1}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMULPD %ZMM31,%ZMM5,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132PS %ZMM28,%ZMM19,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VDIVPD %ZMM6,%ZMM14,%ZMM6 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
VDIVPD %ZMM5,%ZMM14,%ZMM5 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
VFMADD132PS %ZMM28,%ZMM18,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132PS %ZMM28,%ZMM17,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132PS %ZMM28,%ZMM16,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTPS2PD %YMM0,%ZMM28 | 2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VEXTRACTF32X8 $0x1,%ZMM0,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD %ZMM28,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VCVTPS2PD %YMM0,%ZMM0 | 2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VADDPD %ZMM0,%ZMM5,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VCVTPD2PS %ZMM6,%YMM6 | 2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VCVTPD2PS %ZMM5,%YMM0 | 2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VINSERTF64X4 $0x1,%YMM0,%ZMM6,%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMULPS %ZMM27,%ZMM5,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPS %ZMM6,%ZMM9,%ZMM0{%K2}{z} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPS %ZMM6,%ZMM8,%ZMM9{%K2}{z} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPS %ZMM6,%ZMM30,%ZMM8{%K2}{z} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDPS %ZMM0,%ZMM10,%ZMM10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPS %ZMM9,%ZMM11,%ZMM11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPS %ZMM8,%ZMM12,%ZMM12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
CMP %R11,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 401a60 <Step10_orig+0xb0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | Step10_orig |
Source file and lines | Step10_orig.c:19-31 |
Module | exec |
nb instructions | 47 |
nb uops | 60 |
loop length | 286 |
used x86 registers | 6 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 3 |
used zmm registers | 27 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 1.29 |
micro-operation queue | 10.00 cycles |
front end | 10.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 26.00 | 0.00 | 1.33 | 1.33 | 0.00 | 26.00 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 1.33 |
cycles | 26.00 | 11.50 | 1.33 | 1.33 | 0.00 | 26.00 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 1.33 |
Cycles executing div or sqrt instructions | 68.00 |
Longest recurrence chain latency (RecMII) | 3.00 |
FE+BE cycles | 69.98-69.04 |
Stall cycles | 59.37-58.43 |
RS full (events) | 0.56-0.55 |
PRF_FLOAT full (events) | 63.00-62.07 |
Front-end | 10.00 |
Dispatch | 26.00 |
DIV/SQRT | 68.00 |
Data deps. | 3.00 |
Overall L1 | 68.00 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 100% |
all | 92% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 73% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPS (%RDX,%R11,1),%ZMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPS (%RSI,%R11,1),%ZMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VMOVUPS (%RCX,%R11,1),%ZMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
VSUBPS %ZMM25,%ZMM0,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSUBPS %ZMM26,%ZMM6,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VSUBPS %ZMM24,%ZMM5,%ZMM30 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPS %ZMM8,%ZMM8,%ZMM28 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PS %ZMM9,%ZMM9,%ZMM28 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PS %ZMM30,%ZMM30,%ZMM28 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCMPPS $0xe,%ZMM15,%ZMM28,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VCMPPS $0x1,%ZMM23,%ZMM28,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPS %ZMM22,%ZMM28,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VCVTPS2PD %YMM0,%ZMM6 | 2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VEXTRACTF32X8 $0x1,%ZMM0,%YMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVAPS %ZMM28,%ZMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VSQRTPD %ZMM6,%ZMM29 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 23-32 | 18 |
VMOVUPS (%R8,%R11,1),%ZMM13{%K1} | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
ADD $0x40,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VCVTPS2PD %YMM5,%ZMM5 | 2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VMULPD %ZMM29,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132PS %ZMM21,%ZMM20,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VSQRTPD %ZMM5,%ZMM31 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 23-32 | 18 |
VMOVAPS %ZMM13,%ZMM27{%K1}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMULPD %ZMM31,%ZMM5,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132PS %ZMM28,%ZMM19,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VDIVPD %ZMM6,%ZMM14,%ZMM6 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
VDIVPD %ZMM5,%ZMM14,%ZMM5 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
VFMADD132PS %ZMM28,%ZMM18,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132PS %ZMM28,%ZMM17,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD132PS %ZMM28,%ZMM16,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTPS2PD %YMM0,%ZMM28 | 2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VEXTRACTF32X8 $0x1,%ZMM0,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VADDPD %ZMM28,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VCVTPS2PD %YMM0,%ZMM0 | 2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VADDPD %ZMM0,%ZMM5,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VCVTPD2PS %ZMM6,%YMM6 | 2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VCVTPD2PS %ZMM5,%YMM0 | 2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VINSERTF64X4 $0x1,%YMM0,%ZMM6,%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMULPS %ZMM27,%ZMM5,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPS %ZMM6,%ZMM9,%ZMM0{%K2}{z} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPS %ZMM6,%ZMM8,%ZMM9{%K2}{z} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMULPS %ZMM6,%ZMM30,%ZMM8{%K2}{z} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VADDPS %ZMM0,%ZMM10,%ZMM10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPS %ZMM9,%ZMM11,%ZMM11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VADDPS %ZMM8,%ZMM12,%ZMM12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
CMP %R11,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 401a60 <Step10_orig+0xb0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |