Function: main | Module: exec | Source: main.c:50-191 [...] | Coverage: 0.05% |
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Function: main | Module: exec | Source: main.c:50-191 [...] | Coverage: 0.05% |
---|
/scratch_na/users/xoserete/qaas_runs/171-415-1813/intel/HACCmk/build/HACCmk/src/main.c: 50 - 191 |
-------------------------------------------------------------------------------- |
50: { |
[...] |
73: printf( "count is set %d\n", count ); |
74: printf( "Total MPI ranks %d\n", nprocs ); |
75: } |
76: |
77: if (argc == 2 && strncmp(argv[1], "-s", 2) == 0) |
78: NN = 15000; |
79: |
80: printf( "N is set %ld\n", NN ); |
81: |
82: #pragma omp parallel |
[...] |
97: for ( n = 400; n < NN; n = n + 20 ) |
[...] |
103: dx1 = 1.0f/(float)n; |
104: dy1 = 2.0f/(float)n; |
105: dz1 = 3.0f/(float)n; |
106: xx[0] = 0.f; |
107: yy[0] = 0.f; |
108: zz[0] = 0.f; |
109: mass[0] = 2.f; |
110: |
111: for ( i = 1; i < n; i++ ) |
112: { |
113: xx[i] = xx[i-1] + dx1; |
114: yy[i] = yy[i-1] + dy1; |
115: zz[i] = zz[i-1] + dz1; |
116: mass[i] = (float)i * 0.01f + xx[i]; |
117: } |
118: |
119: for ( i = 0; i < n; i++ ) |
120: { |
121: vx1[i] = 0.f; |
122: vy1[i] = 0.f; |
123: vz1[i] = 0.f; |
[...] |
136: t1 = mysecond(); |
137: #endif |
138: |
139: #pragma omp parallel for private( dx1, dy1, dz1 ) |
[...] |
152: t2 = mysecond(); |
[...] |
166: t3 = (t2 - t1) * 1e6; |
167: #endif |
168: |
169: elapsed = elapsed + t3; |
[...] |
185: printf( "\nKernel elapsed time, s: %18.8lf\n", elapsed*1e-6 ); |
[...] |
191: return 0; |
0x401380 PUSH %RBP |
0x401381 MOV %RSP,%RBP |
0x401384 PUSH %R15 |
0x401386 PUSH %R14 |
0x401388 PUSH %R13 |
0x40138a PUSH %R12 |
0x40138c PUSH %RBX |
0x40138d SUB $0x18,%RSP |
0x401391 MOV %RSI,%R14 |
0x401394 MOV %EDI,%R15D |
0x401397 MOV $0x10111ce4199d9fee,%RSI |
0x4013a1 MOV $0x3,%EDI |
0x4013a6 CALL 402170 <__intel_new_feature_proc_init> |
0x4013ab MOV $0x405b10,%EDI |
0x4013b0 MOV $0xbb8,%ESI |
0x4013b5 XOR %EAX,%EAX |
0x4013b7 CALL 400e30 <printf@plt> |
0x4013bc MOV $0x405b21,%EDI |
0x4013c1 MOV $0x1,%ESI |
0x4013c6 XOR %EAX,%EAX |
0x4013c8 CALL 400e30 <printf@plt> |
0x4013cd MOV $0x186a0,%EBX |
0x4013d2 CMP $0x2,%R15D |
0x4013d6 JNE 4013f6 |
0x4013d8 MOV 0x8(%R14),%RDI |
0x4013dc MOV $0x405b35,%ESI |
0x4013e1 MOV $0x2,%EDX |
0x4013e6 CALL 400eb0 <strncmp@plt> |
0x4013eb TEST %EAX,%EAX |
0x4013ed MOV $0x3a98,%EAX |
0x4013f2 CMOVE %RAX,%RBX |
0x4013f6 MOV $0x405b38,%EDI |
0x4013fb MOV %RBX,%RSI |
0x4013fe XOR %EAX,%EAX |
0x401400 CALL 400e30 <printf@plt> |
0x401405 MOV $0x6090e0,%EDI |
0x40140a MOV $0x4017b0,%EDX |
0x40140f MOV $0x1,%ESI |
0x401414 XOR %ECX,%ECX |
0x401416 XOR %EAX,%EAX |
0x401418 CALL 400f10 <__kmpc_fork_call@plt> |
0x40141d ADD $-0x191,%EBX |
0x401423 MOV $-0x33333333,%R14D |
0x401429 IMUL %RBX,%R14 |
0x40142d SHR $0x24,%R14 |
0x401431 INC %R14D |
0x401434 VXORPS %XMM0,%XMM0,%XMM0 |
0x401438 MOV $0x190,%R15D |
0x40143e MOV $0x18c,%R12D |
0x401444 VMOVSS 0x4648(%RIP),%XMM15 |
0x40144c VMOVDQU64 0x468a(%RIP),%YMM16 |
0x401456 VBROADCASTSS 0x4634(%RIP),%YMM17 |
0x401460 XOR %R13D,%R13D |
0x401463 JMP 401542 |
0x401468 NOPW %CS:(%RAX,%RAX,1) |
0x401477 NOPW (%RAX,%RAX,1) |
(2) 0x401480 MOV $0x78fbb0,%EDI |
(2) 0x401485 XOR %ESI,%ESI |
(2) 0x401487 MOV %RBX,%RDX |
(2) 0x40148a VZEROUPPER |
(2) 0x40148d CALL 4022c0 <__intel_avx_rep_memset> |
(2) 0x401492 MOV $0x7f1630,%EDI |
(2) 0x401497 XOR %ESI,%ESI |
(2) 0x401499 MOV %RBX,%RDX |
(2) 0x40149c CALL 4022c0 <__intel_avx_rep_memset> |
(2) 0x4014a1 MOV $0x8530b0,%EDI |
(2) 0x4014a6 XOR %ESI,%ESI |
(2) 0x4014a8 MOV %RBX,%RDX |
(2) 0x4014ab CALL 4022c0 <__intel_avx_rep_memset> |
(2) 0x4014b0 XOR %EAX,%EAX |
(2) 0x4014b2 CALL 401950 <mysecond> |
(2) 0x4014b7 VMOVSD %XMM0,-0x30(%RBP) |
(2) 0x4014bc SUB $0x8,%RSP |
(2) 0x4014c0 MOV $0x609140,%EDI |
(2) 0x4014c5 MOV $0x4017e0,%EDX |
(2) 0x4014ca MOV $0x3e6b851f,%ECX |
(2) 0x4014cf MOV $0x3f000000,%R8D |
(2) 0x4014d5 MOV $0x3cf5c28f,%R9D |
(2) 0x4014db MOV $0x6,%ESI |
(2) 0x4014e0 XOR %EAX,%EAX |
(2) 0x4014e2 PUSH $0xbb7 |
(2) 0x4014e7 PUSH $0 |
(2) 0x4014e9 PUSH %R15 |
(2) 0x4014eb CALL 400f10 <__kmpc_fork_call@plt> |
(2) 0x4014f0 ADD $0x20,%RSP |
(2) 0x4014f4 XOR %EAX,%EAX |
(2) 0x4014f6 CALL 401950 <mysecond> |
(2) 0x4014fb VMOVSS 0x4591(%RIP),%XMM15 |
(2) 0x401503 VSUBSD -0x30(%RBP),%XMM0,%XMM0 |
(2) 0x401508 VMOVSD -0x38(%RBP),%XMM1 |
(2) 0x40150d VFMADD231SD 0x45ea(%RIP),%XMM0,%XMM1 |
(2) 0x401516 VMOVAPD %XMM1,%XMM0 |
(2) 0x40151a ADD $0x14,%R15 |
(2) 0x40151e INC %R13 |
(2) 0x401521 ADD $0x14,%R12 |
(2) 0x401525 CMP %R14,%R13 |
(2) 0x401528 VMOVDQU64 0x45ae(%RIP),%YMM16 |
(2) 0x401532 VBROADCASTSS 0x4558(%RIP),%YMM17 |
(2) 0x40153c JE 401780 |
(2) 0x401542 VMOVSD %XMM0,-0x38(%RBP) |
(2) 0x401547 LEA (,%R12,4),%RAX |
(2) 0x40154f AND $-0x20,%RAX |
(2) 0x401553 MOV %R12,%RCX |
(2) 0x401556 AND $-0x8,%RCX |
(2) 0x40155a MOV %R12D,%EDX |
(2) 0x40155d AND $0x7,%EDX |
(2) 0x401560 LEA (%R13,%R13,4),%RBX |
(2) 0x401565 SAL $0x4,%RBX |
(2) 0x401569 ADD $0x640,%RBX |
(2) 0x401570 VCVTSI2SS %R15D,%XMM18,%XMM0 |
(2) 0x401576 VMOVSS 0x4512(%RIP),%XMM1 |
(2) 0x40157e VDIVSS %XMM0,%XMM1,%XMM0 |
(2) 0x401582 VBROADCASTSS %XMM0,%XMM1 |
(2) 0x401587 VMULPS 0x4521(%RIP),%XMM1,%XMM1 |
(2) 0x40158f MOVL $0,0x207c17(%RIP) |
(2) 0x401599 MOVL $0,0x26968d(%RIP) |
(2) 0x4015a3 MOVL $0,0x2cb103(%RIP) |
(2) 0x4015ad MOVL $0x40000000,0x32cb79(%RIP) |
(2) 0x4015b7 LEA -0x1(%R15),%RSI |
(2) 0x4015bb VXORPS %XMM3,%XMM3,%XMM3 |
(2) 0x4015bf VXORPS %XMM2,%XMM2,%XMM2 |
(2) 0x4015c3 MOV $-0x3,%RDI |
(2) 0x4015ca NOPW (%RAX,%RAX,1) |
(0) 0x4015d0 VADDSS %XMM0,%XMM2,%XMM2 |
(0) 0x4015d4 VMOVSS %XMM2,0x6091c0(,%RDI,4) |
(0) 0x4015dd VADDPS %XMM1,%XMM3,%XMM3 |
(0) 0x4015e1 VEXTRACTPS $0x1,%XMM3,0x66ac40(,%RDI,4) |
(0) 0x4015ec VMOVSS %XMM3,0x6cc6c0(,%RDI,4) |
(0) 0x4015f5 LEA 0x4(%RDI),%R8D |
(0) 0x4015f9 VCVTSI2SS %R8D,%XMM18,%XMM4 |
(0) 0x4015ff VFMADD132SS %XMM15,%XMM2,%XMM4 |
(0) 0x401604 VMOVSS %XMM4,0x72e140(,%RDI,4) |
(0) 0x40160d INC %RDI |
(0) 0x401610 JNE 4015d0 |
(2) 0x401612 LEA -0x4(%R15),%RDI |
(2) 0x401616 AND $-0x8,%RDI |
(2) 0x40161a VBROADCASTSS %XMM0,%YMM4 |
(2) 0x40161f VBROADCASTSS %XMM2,%YMM10 |
(2) 0x401624 VMOVUPS 0x4494(%RIP),%YMM9 |
(2) 0x40162c VFMADD231PS %YMM9,%YMM4,%YMM10 |
(2) 0x401631 VMOVSS 0x445f(%RIP),%XMM13 |
(2) 0x401639 VMULSS %XMM0,%XMM13,%XMM7 |
(2) 0x40163d VMOVSHDUP %XMM1,%XMM6 |
(2) 0x401641 VBROADCASTSD %XMM6,%YMM5 |
(2) 0x401646 VBROADCASTSS 0x444d(%RIP),%YMM8 |
(2) 0x40164f VPERMPS %YMM3,%YMM8,%YMM12 |
(2) 0x401654 VFMADD231PS %YMM9,%YMM5,%YMM12 |
(2) 0x401659 VMULSS %XMM6,%XMM13,%XMM8 |
(2) 0x40165d VBROADCASTSS %XMM1,%YMM6 |
(2) 0x401662 VBROADCASTSS %XMM3,%YMM11 |
(2) 0x401667 VFMADD231PS %YMM9,%YMM6,%YMM11 |
(2) 0x40166c VMULSS %XMM1,%XMM13,%XMM9 |
(2) 0x401670 LEA 0x3(%RDI),%R8 |
(2) 0x401674 OR $0x2,%RDI |
(2) 0x401678 VBROADCASTSS %XMM7,%YMM7 |
(2) 0x40167d VBROADCASTSS %XMM8,%YMM8 |
(2) 0x401682 VBROADCASTSS %XMM9,%YMM9 |
(2) 0x401687 MOV $0x3,%R9D |
(2) 0x40168d NOPL (%RAX) |
(1) 0x401690 VADDPS %YMM4,%YMM10,%YMM13 |
(1) 0x401694 VADDPS %YMM7,%YMM10,%YMM10 |
(1) 0x401698 VMOVUPS %YMM13,0x6091b4(,%R9,4) |
(1) 0x4016a2 VADDPS %YMM5,%YMM12,%YMM14 |
(1) 0x4016a6 VADDPS %YMM8,%YMM12,%YMM12 |
(1) 0x4016ab VMOVUPS %YMM14,0x66ac34(,%R9,4) |
(1) 0x4016b5 VADDPS %YMM6,%YMM11,%YMM14 |
(1) 0x4016b9 VADDPS %YMM9,%YMM11,%YMM11 |
(1) 0x4016be VMOVUPS %YMM14,0x6cc6b4(,%R9,4) |
(1) 0x4016c8 VPBROADCASTD %R9D,%YMM14 |
(1) 0x4016ce VPADDD %YMM16,%YMM14,%YMM14 |
(1) 0x4016d4 VCVTDQ2PS %YMM14,%YMM14 |
(1) 0x4016d9 VFMADD132PS %YMM17,%YMM13,%YMM14 |
(1) 0x4016df VMOVUPS %YMM14,0x72e134(,%R9,4) |
(1) 0x4016e9 ADD $0x8,%R9 |
(1) 0x4016ed CMP %RDI,%R9 |
(1) 0x4016f0 JLE 401690 |
(2) 0x4016f2 CMP %R8,%RSI |
(2) 0x4016f5 JE 401480 |
(2) 0x4016fb VCVTSI2SS %R8,%XMM18,%XMM4 |
(2) 0x401701 VADDSS 0x4397(%RIP),%XMM4,%XMM5 |
(2) 0x401709 VBROADCASTSS %XMM5,%XMM4 |
(2) 0x40170e VFMADD213PS %XMM3,%XMM1,%XMM4 |
(2) 0x401713 VFMADD231SS %XMM5,%XMM0,%XMM2 |
(2) 0x401718 XOR %ESI,%ESI |
(2) 0x40171a NOPW (%RAX,%RAX,1) |
(3) 0x401720 VADDSS %XMM0,%XMM2,%XMM2 |
(3) 0x401724 VMOVSS %XMM2,0x6091c0(%RAX,%RSI,4) |
(3) 0x40172d VADDPS %XMM1,%XMM4,%XMM4 |
(3) 0x401731 VEXTRACTPS $0x1,%XMM4,0x66ac40(%RAX,%RSI,4) |
(3) 0x40173c VMOVSS %XMM4,0x6cc6c0(%RAX,%RSI,4) |
(3) 0x401745 LEA 0x4(%RCX,%RSI,1),%EDI |
(3) 0x401749 VCVTSI2SS %EDI,%XMM18,%XMM3 |
(3) 0x40174f VFMADD132SS %XMM15,%XMM2,%XMM3 |
(3) 0x401754 VMOVSS %XMM3,0x72e140(%RAX,%RSI,4) |
(3) 0x40175d INC %RSI |
(3) 0x401760 CMP %RSI,%RDX |
(3) 0x401763 JNE 401720 |
(2) 0x401765 JMP 401480 |
0x40176a NOPW %CS:(%RAX,%RAX,1) |
0x401779 NOPL (%RAX) |
0x401780 VMULSD 0x4380(%RIP),%XMM0,%XMM0 |
0x401788 MOV $0x1,%EAX |
0x40178d MOV $0x405b61,%EDI |
0x401792 CALL 400e30 <printf@plt> |
0x401797 XOR %EAX,%EAX |
0x401799 ADD $0x18,%RSP |
0x40179d POP %RBX |
0x40179e POP %R12 |
0x4017a0 POP %R13 |
0x4017a2 POP %R14 |
0x4017a4 POP %R15 |
0x4017a6 POP %RBP |
0x4017a7 RET |
0x4017a8 NOPL (%RAX,%RAX,1) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○100.00 | __libc_start_main | libc-2.28.so |
Path / |
Source file and lines | main.c:50-191 |
Module | exec |
nb instructions | 72 |
nb uops | 79 |
loop length | 326 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 2 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 13.17 cycles |
front end | 13.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.90 | 5.70 | 4.00 | 4.00 | 6.50 | 5.80 | 5.80 | 6.50 | 6.50 | 6.50 | 5.80 | 4.00 |
cycles | 5.90 | 5.70 | 4.00 | 4.00 | 6.50 | 5.80 | 5.80 | 6.50 | 6.50 | 6.50 | 5.80 | 4.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 12.12 |
Stall cycles | 0.00 |
Front-end | 13.17 |
Dispatch | 6.50 |
Overall L1 | 13.17 |
all | 3% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 25% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
all | 6% |
load | 20% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 3% |
all | 9% |
load | 31% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 7% |
all | 12% |
load | 8% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
all | 9% |
load | 17% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 7% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x18,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EDI,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x10111ce4199d9fee,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
MOV $0x3,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 402170 <__intel_new_feature_proc_init> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x405b10,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0xbb8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 400e30 <printf@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x405b21,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 400e30 <printf@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x186a0,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP $0x2,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 4013f6 <main+0x76> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x8(%R14),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x405b35,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 400eb0 <strncmp@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
TEST %EAX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV $0x3a98,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVE %RAX,%RBX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV $0x405b38,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 400e30 <printf@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x6090e0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x4017b0,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 400f10 <__kmpc_fork_call@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $-0x191,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $-0x33333333,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
IMUL %RBX,%R14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SHR $0x24,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
INC %R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VXORPS %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x190,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x18c,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVSS 0x4648(%RIP),%XMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVDQU64 0x468a(%RIP),%YMM16 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VBROADCASTSS 0x4634(%RIP),%YMM17 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 401542 <main+0x1c2> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMULSD 0x4380(%RIP),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
MOV $0x1,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x405b61,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 400e30 <printf@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x18,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | main.c:50-191 |
Module | exec |
nb instructions | 72 |
nb uops | 79 |
loop length | 326 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 2 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 13.17 cycles |
front end | 13.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.90 | 5.70 | 4.00 | 4.00 | 6.50 | 5.80 | 5.80 | 6.50 | 6.50 | 6.50 | 5.80 | 4.00 |
cycles | 5.90 | 5.70 | 4.00 | 4.00 | 6.50 | 5.80 | 5.80 | 6.50 | 6.50 | 6.50 | 5.80 | 4.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 12.12 |
Stall cycles | 0.00 |
Front-end | 13.17 |
Dispatch | 6.50 |
Overall L1 | 13.17 |
all | 3% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 25% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
all | 6% |
load | 20% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 3% |
all | 9% |
load | 31% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 7% |
all | 12% |
load | 8% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
all | 9% |
load | 17% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 7% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
SUB $0x18,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %EDI,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x10111ce4199d9fee,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
MOV $0x3,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 402170 <__intel_new_feature_proc_init> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x405b10,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0xbb8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 400e30 <printf@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x405b21,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 400e30 <printf@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x186a0,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP $0x2,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 4013f6 <main+0x76> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x8(%R14),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV $0x405b35,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x2,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 400eb0 <strncmp@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
TEST %EAX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV $0x3a98,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVE %RAX,%RBX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV $0x405b38,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 400e30 <printf@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV $0x6090e0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x4017b0,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x1,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 400f10 <__kmpc_fork_call@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
ADD $-0x191,%EBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $-0x33333333,%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
IMUL %RBX,%R14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SHR $0x24,%R14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
INC %R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VXORPS %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x190,%R15D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x18c,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVSS 0x4648(%RIP),%XMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVDQU64 0x468a(%RIP),%YMM16 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VBROADCASTSS 0x4634(%RIP),%YMM17 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 401542 <main+0x1c2> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMULSD 0x4380(%RIP),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
MOV $0x1,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV $0x405b61,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CALL 400e30 <printf@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD $0x18,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼main– | 0.05 | 0.01 |
▼Loop 2 - main.c:77-169 - exec– | 0 | 0 |
○Loop 1 - main.c:111-116 - exec | 0.05 | 0.89 |
○Loop 3 - main.c:111-116 - exec | 0 | 0 |
○Loop 0 - main.c:111-116 - exec | 0 | 0 |