Loop Id: 5 | Module: exec | Source: Step10_orig.c:19-35 | Coverage: 89.2% |
---|
Loop Id: 5 | Module: exec | Source: Step10_orig.c:19-35 | Coverage: 89.2% |
---|
0x401a60 VMOVUPS (%RSI,%RBX,4),%YMM21 [2] |
0x401a67 VSUBPS %YMM5,%YMM21,%YMM21 |
0x401a6d VMOVUPS (%RDX,%RBX,4),%YMM22 [4] |
0x401a74 VSUBPS %YMM7,%YMM22,%YMM22 |
0x401a7a VMOVUPS (%RCX,%RBX,4),%YMM23 [1] |
0x401a81 VSUBPS %YMM8,%YMM23,%YMM23 |
0x401a87 VMULPS %YMM21,%YMM21,%YMM24 |
0x401a8d VFMADD231PS %YMM22,%YMM22,%YMM24 |
0x401a93 VFMADD231PS %YMM23,%YMM23,%YMM24 |
0x401a99 VCMPPS $0x1,%YMM9,%YMM24,%K1 |
0x401aa0 VMOVUPS (%R8,%RBX,4),%YMM25{%K1}{z} [3] |
0x401aa7 VADDPS %YMM10,%YMM24,%YMM26 |
0x401aad VEXTRACTF32X4 $0x1,%YMM26,%XMM27 |
0x401ab4 VCVTPS2PD %XMM27,%YMM27 |
0x401aba VCVTPS2PD %XMM26,%YMM26 |
0x401ac0 VSQRTPD %YMM26,%YMM28 |
0x401ac6 VSQRTPD %YMM27,%YMM29 |
0x401acc VMULPD %YMM26,%YMM26,%YMM26 |
0x401ad2 VDIVPD %YMM26,%YMM13,%YMM26 |
0x401ad8 VMULPD %YMM27,%YMM27,%YMM27 |
0x401ade VMOVAPS %YMM14,%YMM30 |
0x401ae4 VFMADD213PS %YMM15,%YMM24,%YMM30 |
0x401aea VFMADD213PS %YMM16,%YMM24,%YMM30 |
0x401af0 VFMADD213PS %YMM17,%YMM24,%YMM30 |
0x401af6 VFMADD213PS %YMM19,%YMM24,%YMM30 |
0x401afc VFMADD213PS %YMM20,%YMM24,%YMM30 |
0x401b02 VCVTPS2PD %XMM30,%YMM31 |
0x401b08 VDIVPD %YMM27,%YMM13,%YMM27 |
0x401b0e VFMADD231PD %YMM26,%YMM28,%YMM31 |
0x401b14 VEXTRACTF32X4 $0x1,%YMM30,%XMM26 |
0x401b1b VCVTPS2PD %XMM26,%YMM26 |
0x401b21 VFMADD231PD %YMM27,%YMM29,%YMM26 |
0x401b27 VCVTPD2PS %YMM31,%XMM27 |
0x401b2d VCVTPD2PS %YMM26,%XMM26 |
0x401b33 VINSERTF32X4 $0x1,%XMM26,%YMM27,%YMM26 |
0x401b3a VCMPPS $0x1,%YMM24,%YMM11,%K1 |
0x401b41 VMULPS %YMM26,%YMM25,%YMM24{%K1}{z} |
0x401b47 VFMADD231PS %YMM21,%YMM24,%YMM18 |
0x401b4d VFMADD231PS %YMM22,%YMM24,%YMM12 |
0x401b53 VFMADD231PS %YMM23,%YMM24,%YMM6 |
0x401b59 ADD $0x8,%RBX |
0x401b5d CMP %RDI,%RBX |
0x401b60 JB 401a60 |
/scratch_na/users/xoserete/qaas_runs/171-415-1813/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19 - 35 |
-------------------------------------------------------------------------------- |
19: for ( j = 0; j < count1; j++ ) |
20: { |
21: dxc = xx1[j] - xxi; |
22: dyc = yy1[j] - yyi; |
23: dzc = zz1[j] - zzi; |
24: |
25: r2 = dxc * dxc + dyc * dyc + dzc * dzc; |
26: |
27: m = ( r2 < fsrrmax2 ) ? mass1[j] : 0.0f; |
28: |
29: f = pow( r2 + mp_rsm2, -1.5 ) - ( ma0 + r2*(ma1 + r2*(ma2 + r2*(ma3 + r2*(ma4 + r2*ma5))))); |
30: |
31: f = ( r2 > 0.0f ) ? m * f : 0.0f; |
32: |
33: xi = xi + f * dxc; |
34: yi = yi + f * dyc; |
35: zi = zi + f * dzc; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | main.extracted.8 | main.c:142 | exec |
○ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_invoke_task_func | libiomp5.so |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 2.27 |
Bottlenecks | P0, |
Function | Step10_orig |
Source | Step10_orig.c:19-35 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 34.00 |
CQA cycles if no scalar integer | 34.00 |
CQA cycles if FP arith vectorized | 34.00 |
CQA cycles if fully vectorized | 34.00 |
Front-end cycles | 8.00 |
DIV/SQRT cycles | 15.00 |
P0 cycles | 15.00 |
P1 cycles | 1.33 |
P2 cycles | 1.33 |
P3 cycles | 0.00 |
P4 cycles | 11.00 |
P5 cycles | 1.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 1.33 |
P11 cycles | 34.00 |
Inter-iter dependencies cycles | 4 |
FE+BE cycles (UFS) | 35.28 - 34.81 |
Stall cycles (UFS) | 26.67 - 26.20 |
Nb insns | 43.00 |
Nb uops | 48.00 |
Nb loads | 4.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 7.29 |
Nb FLOP add-sub | 32.00 |
Nb FLOP mul | 24.00 |
Nb FLOP fma | 88.00 |
Nb FLOP div | 8.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 8.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 3.76 |
Bytes prefetched | 0.00 |
Bytes loaded | 128.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 4.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | 100.00 |
Vector-efficiency ratio all | 45.63 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | 50.00 |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | 50.00 |
Vector-efficiency ratio div_sqrt | 50.00 |
Vector-efficiency ratio other | 35.42 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 2.27 |
Bottlenecks | P0, |
Function | Step10_orig |
Source | Step10_orig.c:19-35 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 34.00 |
CQA cycles if no scalar integer | 34.00 |
CQA cycles if FP arith vectorized | 34.00 |
CQA cycles if fully vectorized | 34.00 |
Front-end cycles | 8.00 |
DIV/SQRT cycles | 15.00 |
P0 cycles | 15.00 |
P1 cycles | 1.33 |
P2 cycles | 1.33 |
P3 cycles | 0.00 |
P4 cycles | 11.00 |
P5 cycles | 1.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 1.33 |
P11 cycles | 34.00 |
Inter-iter dependencies cycles | 4 |
FE+BE cycles (UFS) | 35.28 - 34.81 |
Stall cycles (UFS) | 26.67 - 26.20 |
Nb insns | 43.00 |
Nb uops | 48.00 |
Nb loads | 4.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 7.29 |
Nb FLOP add-sub | 32.00 |
Nb FLOP mul | 24.00 |
Nb FLOP fma | 88.00 |
Nb FLOP div | 8.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 8.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 3.76 |
Bytes prefetched | 0.00 |
Bytes loaded | 128.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 4.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | 100.00 |
Vectorization ratio other | 100.00 |
Vector-efficiency ratio all | 45.63 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | 50.00 |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | 50.00 |
Vector-efficiency ratio div_sqrt | 50.00 |
Vector-efficiency ratio other | 35.42 |
Path / |
Function | Step10_orig |
Source file and lines | Step10_orig.c:19-35 |
Module | exec |
nb instructions | 43 |
nb uops | 48 |
loop length | 262 |
used x86 registers | 6 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 27 |
used zmm registers | 0 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 1.00 |
micro-operation queue | 8.00 cycles |
front end | 8.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 15.00 | 15.00 | 1.33 | 1.33 | 0.00 | 11.00 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 1.33 |
cycles | 15.00 | 15.00 | 1.33 | 1.33 | 0.00 | 11.00 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 1.33 |
Cycles executing div or sqrt instructions | 34.00 |
Longest recurrence chain latency (RecMII) | 4.00 |
FE+BE cycles | 35.28-34.81 |
Stall cycles | 26.67-26.20 |
RS full (events) | 0.30-0.28 |
PRF_FLOAT full (events) | 28.51-28.05 |
Front-end | 8.00 |
Dispatch | 15.00 |
DIV/SQRT | 34.00 |
Data deps. | 4.00 |
Overall L1 | 34.00 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 100% |
all | 45% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | 50% |
div/sqrt | 50% |
other | 35% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPS (%RSI,%RBX,4),%YMM21 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VSUBPS %YMM5,%YMM21,%YMM21 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVUPS (%RDX,%RBX,4),%YMM22 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VSUBPS %YMM7,%YMM22,%YMM22 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVUPS (%RCX,%RBX,4),%YMM23 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VSUBPS %YMM8,%YMM23,%YMM23 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPS %YMM21,%YMM21,%YMM24 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PS %YMM22,%YMM22,%YMM24 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PS %YMM23,%YMM23,%YMM24 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCMPPS $0x1,%YMM9,%YMM24,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPS (%R8,%RBX,4),%YMM25{%K1}{z} | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VADDPS %YMM10,%YMM24,%YMM26 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VEXTRACTF32X4 $0x1,%YMM26,%XMM27 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VCVTPS2PD %XMM27,%YMM27 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VCVTPS2PD %XMM26,%YMM26 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VSQRTPD %YMM26,%YMM28 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-19 | 9 |
VSQRTPD %YMM27,%YMM29 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-19 | 9 |
VMULPD %YMM26,%YMM26,%YMM26 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VDIVPD %YMM26,%YMM13,%YMM26 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 8 |
VMULPD %YMM27,%YMM27,%YMM27 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVAPS %YMM14,%YMM30 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VFMADD213PS %YMM15,%YMM24,%YMM30 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213PS %YMM16,%YMM24,%YMM30 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213PS %YMM17,%YMM24,%YMM30 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213PS %YMM19,%YMM24,%YMM30 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213PS %YMM20,%YMM24,%YMM30 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTPS2PD %XMM30,%YMM31 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VDIVPD %YMM27,%YMM13,%YMM27 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 8 |
VFMADD231PD %YMM26,%YMM28,%YMM31 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VEXTRACTF32X4 $0x1,%YMM30,%XMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VCVTPS2PD %XMM26,%YMM26 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VFMADD231PD %YMM27,%YMM29,%YMM26 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTPD2PS %YMM31,%XMM27 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VCVTPD2PS %YMM26,%XMM26 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VINSERTF32X4 $0x1,%XMM26,%YMM27,%YMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VCMPPS $0x1,%YMM24,%YMM11,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMULPS %YMM26,%YMM25,%YMM24{%K1}{z} | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PS %YMM21,%YMM24,%YMM18 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PS %YMM22,%YMM24,%YMM12 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PS %YMM23,%YMM24,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
ADD $0x8,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RDI,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 401a60 <Step10_orig+0xa0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | Step10_orig |
Source file and lines | Step10_orig.c:19-35 |
Module | exec |
nb instructions | 43 |
nb uops | 48 |
loop length | 262 |
used x86 registers | 6 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 27 |
used zmm registers | 0 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 1.00 |
micro-operation queue | 8.00 cycles |
front end | 8.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 15.00 | 15.00 | 1.33 | 1.33 | 0.00 | 11.00 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 1.33 |
cycles | 15.00 | 15.00 | 1.33 | 1.33 | 0.00 | 11.00 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 1.33 |
Cycles executing div or sqrt instructions | 34.00 |
Longest recurrence chain latency (RecMII) | 4.00 |
FE+BE cycles | 35.28-34.81 |
Stall cycles | 26.67-26.20 |
RS full (events) | 0.30-0.28 |
PRF_FLOAT full (events) | 28.51-28.05 |
Front-end | 8.00 |
Dispatch | 15.00 |
DIV/SQRT | 34.00 |
Data deps. | 4.00 |
Overall L1 | 34.00 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | 100% |
div/sqrt | 100% |
other | 100% |
all | 45% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | 50% |
div/sqrt | 50% |
other | 35% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPS (%RSI,%RBX,4),%YMM21 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VSUBPS %YMM5,%YMM21,%YMM21 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVUPS (%RDX,%RBX,4),%YMM22 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VSUBPS %YMM7,%YMM22,%YMM22 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVUPS (%RCX,%RBX,4),%YMM23 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VSUBPS %YMM8,%YMM23,%YMM23 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMULPS %YMM21,%YMM21,%YMM24 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PS %YMM22,%YMM22,%YMM24 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PS %YMM23,%YMM23,%YMM24 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCMPPS $0x1,%YMM9,%YMM24,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPS (%R8,%RBX,4),%YMM25{%K1}{z} | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VADDPS %YMM10,%YMM24,%YMM26 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VEXTRACTF32X4 $0x1,%YMM26,%XMM27 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VCVTPS2PD %XMM27,%YMM27 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VCVTPS2PD %XMM26,%YMM26 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VSQRTPD %YMM26,%YMM28 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-19 | 9 |
VSQRTPD %YMM27,%YMM29 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-19 | 9 |
VMULPD %YMM26,%YMM26,%YMM26 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VDIVPD %YMM26,%YMM13,%YMM26 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 8 |
VMULPD %YMM27,%YMM27,%YMM27 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVAPS %YMM14,%YMM30 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VFMADD213PS %YMM15,%YMM24,%YMM30 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213PS %YMM16,%YMM24,%YMM30 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213PS %YMM17,%YMM24,%YMM30 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213PS %YMM19,%YMM24,%YMM30 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213PS %YMM20,%YMM24,%YMM30 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTPS2PD %XMM30,%YMM31 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VDIVPD %YMM27,%YMM13,%YMM27 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 8 |
VFMADD231PD %YMM26,%YMM28,%YMM31 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VEXTRACTF32X4 $0x1,%YMM30,%XMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VCVTPS2PD %XMM26,%YMM26 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VFMADD231PD %YMM27,%YMM29,%YMM26 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTPD2PS %YMM31,%XMM27 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VCVTPD2PS %YMM26,%XMM26 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 |
VINSERTF32X4 $0x1,%XMM26,%YMM27,%YMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VCMPPS $0x1,%YMM24,%YMM11,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMULPS %YMM26,%YMM25,%YMM24{%K1}{z} | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PS %YMM21,%YMM24,%YMM18 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PS %YMM22,%YMM24,%YMM12 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PS %YMM23,%YMM24,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
ADD $0x8,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RDI,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 401a60 <Step10_orig+0xa0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |