Loop Id: 3 | Module: exec | Source: Step10_orig.c:19-35 | Coverage: 19.19% |
---|
Loop Id: 3 | Module: exec | Source: Step10_orig.c:19-35 | Coverage: 19.19% |
---|
0x202280 VMOVSS %XMM0,-0x44(%RBP) [6] |
0x202285 VADDSS -0x3c(%RBP),%XMM2,%XMM0 [6] |
0x20228a VMOVSD -0x1952(%RIP),%XMM1 [4] |
0x202292 VMOVSS %XMM2,-0x40(%RBP) [6] |
0x202297 VCVTSS2SD %XMM0,%XMM0,%XMM0 |
0x20229b CALL 2024a0 <@plt_start@+0xa0> |
0x2022a0 VMOVSS -0x40(%RBP),%XMM2 [6] |
0x2022a5 VMOVSS -0x19b5(%RIP),%XMM1 [4] |
0x2022ad INC %R14 |
0x2022b0 VFMADD213SS -0x19b1(%RIP),%XMM2,%XMM1 [4] |
0x2022b9 VFMADD213SS -0x19b6(%RIP),%XMM2,%XMM1 [4] |
0x2022c2 VFMADD213SS -0x19cb(%RIP),%XMM2,%XMM1 [4] |
0x2022cb VFMADD213SS -0x19e4(%RIP),%XMM2,%XMM1 [4] |
0x2022d4 VFMADD213SS -0x19d9(%RIP),%XMM2,%XMM1 [4] |
0x2022dd VCVTSS2SD %XMM1,%XMM1,%XMM1 |
0x2022e1 VSUBSD %XMM1,%XMM0,%XMM0 |
0x2022e5 VCVTSD2SS %XMM0,%XMM0,%XMM0 |
0x2022e9 VMULSS -0x44(%RBP),%XMM0,%XMM0 [6] |
0x2022ee VCMPSS $0xe,-0x19fd(%RIP),%XMM2,%K1 [4] |
0x2022f9 VMOVSS -0x58(%RBP),%XMM2 [6] |
0x2022fe VMOVSS -0x54(%RBP),%XMM3 [6] |
0x202303 VMOVSS -0x5c(%RBP),%XMM1 [6] |
0x202308 VMOVSS %XMM0,%XMM0,%XMM0{%K1}{z} |
0x20230e VFMADD231SS -0x50(%RBP),%XMM0,%XMM2 [6] |
0x202314 VFMADD231SS -0x4c(%RBP),%XMM0,%XMM3 [6] |
0x20231a VFMADD231SS -0x48(%RBP),%XMM0,%XMM1 [6] |
0x202320 VMOVAPS %XMM1,%XMM0 |
0x202324 CMP %R14,%RBX |
0x202327 JE 2023a5 |
0x202329 VMOVSS %XMM0,-0x5c(%RBP) [6] |
0x20232e VMOVSS (%R13,%R14,4),%XMM0 [2] |
0x202335 VMOVSS %XMM2,-0x58(%RBP) [6] |
0x20233a VMOVSS %XMM3,-0x54(%RBP) [6] |
0x20233f VSUBSS -0x2c(%RBP),%XMM0,%XMM1 [6] |
0x202344 VMOVSS (%R12,%R14,4),%XMM0 [5] |
0x20234a VSUBSS -0x30(%RBP),%XMM0,%XMM2 [6] |
0x20234f VMOVSS (%R15,%R14,4),%XMM0 [1] |
0x202355 VSUBSS -0x34(%RBP),%XMM0,%XMM0 [6] |
0x20235a VMOVSS %XMM1,-0x50(%RBP) [6] |
0x20235f VMOVSS %XMM2,-0x4c(%RBP) [6] |
0x202364 VMULSS %XMM2,%XMM2,%XMM2 |
0x202368 VMOVSS %XMM0,-0x48(%RBP) [6] |
0x20236d VFMADD231SS %XMM1,%XMM1,%XMM2 |
0x202372 VFMADD231SS %XMM0,%XMM0,%XMM2 |
0x202377 VMOVSS -0x38(%RBP),%XMM0 [6] |
0x20237c VUCOMISS %XMM2,%XMM0 |
0x202380 VXORPS %XMM0,%XMM0,%XMM0 |
0x202384 JBE 202280 |
0x20238a MOV -0x70(%RBP),%RAX [6] |
0x20238e VMOVSS (%RAX,%R14,4),%XMM0 [3] |
0x202394 JMP 202280 |
/beegfs/hackathon/users/eoseret/qaas_runs/171-094-7986/intel/HACCmk/build/HACCmk/src/Step10_orig.c: 19 - 35 |
-------------------------------------------------------------------------------- |
19: for ( j = 0; j < count1; j++ ) |
20: { |
21: dxc = xx1[j] - xxi; |
22: dyc = yy1[j] - yyi; |
23: dzc = zz1[j] - zzi; |
24: |
25: r2 = dxc * dxc + dyc * dyc + dzc * dzc; |
26: |
27: m = ( r2 < fsrrmax2 ) ? mass1[j] : 0.0f; |
28: |
29: f = pow( r2 + mp_rsm2, -1.5 ) - ( ma0 + r2*(ma1 + r2*(ma2 + r2*(ma3 + r2*(ma4 + r2*ma5))))); |
30: |
31: f = ( r2 > 0.0f ) ? m * f : 0.0f; |
32: |
33: xi = xi + f * dxc; |
34: yi = yi + f * dyc; |
35: zi = zi + f * dzc; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.05 |
CQA speedup if FP arith vectorized | 1.04 |
CQA speedup if fully vectorized | 8.77 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.30 |
Bottlenecks | |
Function | Step10_orig |
Source | Step10_orig.c:19-35 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 11.33 |
CQA cycles if no scalar integer | 10.83 |
CQA cycles if FP arith vectorized | 10.90 |
CQA cycles if fully vectorized | 1.29 |
Front-end cycles | 8.75 |
DIV/SQRT cycles | 1.75 |
P0 cycles | 0.75 |
P1 cycles | 0.75 |
P2 cycles | 0.50 |
P3 cycles | 1.75 |
P4 cycles | 11.33 |
P5 cycles | 11.33 |
P6 cycles | 11.33 |
P7 cycles | 6.50 |
P8 cycles | 6.50 |
P9 cycles | 5.00 |
P10 cycles | 5.00 |
P11 cycles | 4.50 |
P12 cycles | 4.50 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | 0 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 49.50 |
Nb uops | 52.50 |
Nb loads | 25.00 |
Nb stores | 8.00 |
Nb stack references | 13.50 |
FLOP/cycle | 2.38 |
Nb FLOP add-sub | 5.00 |
Nb FLOP mul | 2.00 |
Nb FLOP fma | 10.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 12.17 |
Bytes prefetched | 0.00 |
Bytes loaded | 106.00 |
Bytes stored | 32.00 |
Stride 0 | 2.00 |
Stride 1 | 3.50 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 4.60 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 25.00 |
Vector-efficiency ratio all | 7.54 |
Vector-efficiency ratio load | 6.51 |
Vector-efficiency ratio store | 6.25 |
Vector-efficiency ratio mul | 6.25 |
Vector-efficiency ratio add_sub | 7.50 |
Vector-efficiency ratio fma | 6.25 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 11.72 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.06 |
CQA speedup if FP arith vectorized | 1.05 |
CQA speedup if fully vectorized | 8.62 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.30 |
Bottlenecks | P5, P6, P7, |
Function | Step10_orig |
Source | Step10_orig.c:19-35 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 11.67 |
CQA cycles if no scalar integer | 11.00 |
CQA cycles if FP arith vectorized | 11.10 |
CQA cycles if fully vectorized | 1.35 |
Front-end cycles | 9.00 |
DIV/SQRT cycles | 2.00 |
P0 cycles | 0.75 |
P1 cycles | 0.75 |
P2 cycles | 0.50 |
P3 cycles | 2.00 |
P4 cycles | 11.67 |
P5 cycles | 11.67 |
P6 cycles | 11.67 |
P7 cycles | 6.50 |
P8 cycles | 6.50 |
P9 cycles | 5.00 |
P10 cycles | 5.00 |
P11 cycles | 4.50 |
P12 cycles | 4.50 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | 0 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 51.00 |
Nb uops | 54.00 |
Nb loads | 26.00 |
Nb stores | 8.00 |
Nb stack references | 14.00 |
FLOP/cycle | 2.31 |
Nb FLOP add-sub | 5.00 |
Nb FLOP mul | 2.00 |
Nb FLOP fma | 10.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 12.34 |
Bytes prefetched | 0.00 |
Bytes loaded | 112.00 |
Bytes stored | 32.00 |
Stride 0 | 2.00 |
Stride 1 | 4.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 4.55 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 25.00 |
Vector-efficiency ratio all | 7.53 |
Vector-efficiency ratio load | 6.50 |
Vector-efficiency ratio store | 6.25 |
Vector-efficiency ratio mul | 6.25 |
Vector-efficiency ratio add_sub | 7.50 |
Vector-efficiency ratio fma | 6.25 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 11.72 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.03 |
CQA speedup if FP arith vectorized | 1.03 |
CQA speedup if fully vectorized | 8.95 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.29 |
Bottlenecks | P5, P6, P7, |
Function | Step10_orig |
Source | Step10_orig.c:19-35 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 11.00 |
CQA cycles if no scalar integer | 10.67 |
CQA cycles if FP arith vectorized | 10.69 |
CQA cycles if fully vectorized | 1.23 |
Front-end cycles | 8.50 |
DIV/SQRT cycles | 1.50 |
P0 cycles | 0.75 |
P1 cycles | 0.75 |
P2 cycles | 0.50 |
P3 cycles | 1.50 |
P4 cycles | 11.00 |
P5 cycles | 11.00 |
P6 cycles | 11.00 |
P7 cycles | 6.50 |
P8 cycles | 6.50 |
P9 cycles | 5.00 |
P10 cycles | 5.00 |
P11 cycles | 4.50 |
P12 cycles | 4.50 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | 0 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 48.00 |
Nb uops | 51.00 |
Nb loads | 24.00 |
Nb stores | 8.00 |
Nb stack references | 13.00 |
FLOP/cycle | 2.45 |
Nb FLOP add-sub | 5.00 |
Nb FLOP mul | 2.00 |
Nb FLOP fma | 10.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 12.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 100.00 |
Bytes stored | 32.00 |
Stride 0 | 2.00 |
Stride 1 | 3.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 4.65 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 25.00 |
Vector-efficiency ratio all | 7.56 |
Vector-efficiency ratio load | 6.51 |
Vector-efficiency ratio store | 6.25 |
Vector-efficiency ratio mul | 6.25 |
Vector-efficiency ratio add_sub | 7.50 |
Vector-efficiency ratio fma | 6.25 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 11.72 |
Path / |
Function | Step10_orig |
Source file and lines | Step10_orig.c:19-35 |
Module | exec |
nb instructions | 49.50 |
nb uops | 52.50 |
loop length | 273.50 |
used x86 registers | 6.50 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 13.50 |
ADD-SUB / MUL ratio | 2.50 |
micro-operation queue | 8.75 cycles |
front end | 8.75 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.75 | 0.75 | 0.75 | 0.50 | 1.75 | 11.33 | 11.33 | 11.33 | 6.50 | 6.50 | 5.00 | 5.00 | 4.50 | 4.50 |
cycles | 1.75 | 0.75 | 0.75 | 0.50 | 1.75 | 11.33 | 11.33 | 11.33 | 6.50 | 6.50 | 5.00 | 5.00 | 4.50 | 4.50 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 0.00 |
Front-end | 8.75 |
Dispatch | 11.33 |
Data deps. | 0.00 |
Overall L1 | 11.33 |
all | 4% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 7% |
load | 6% |
store | 6% |
mul | 6% |
add-sub | 7% |
fma | 6% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
Function | Step10_orig |
Source file and lines | Step10_orig.c:19-35 |
Module | exec |
nb instructions | 51 |
nb uops | 54 |
loop length | 281 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 14 |
ADD-SUB / MUL ratio | 2.50 |
micro-operation queue | 9.00 cycles |
front end | 9.00 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.00 | 0.75 | 0.75 | 0.50 | 2.00 | 11.67 | 11.67 | 11.67 | 6.50 | 6.50 | 5.00 | 5.00 | 4.50 | 4.50 |
cycles | 2.00 | 0.75 | 0.75 | 0.50 | 2.00 | 11.67 | 11.67 | 11.67 | 6.50 | 6.50 | 5.00 | 5.00 | 4.50 | 4.50 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 0.00 |
Front-end | 9.00 |
Dispatch | 11.67 |
Data deps. | 0.00 |
Overall L1 | 11.67 |
all | 4% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 7% |
load | 6% |
store | 6% |
mul | 6% |
add-sub | 7% |
fma | 6% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVSS %XMM0,-0x44(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VADDSS -0x3c(%RBP),%XMM2,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VMOVSD -0x1952(%RIP),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSS %XMM2,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VCVTSS2SD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
CALL 2024a0 <@plt_start@+0xa0> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSS -0x40(%RBP),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSS -0x19b5(%RIP),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
INC %R14 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VFMADD213SS -0x19b1(%RIP),%XMM2,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SS -0x19b6(%RIP),%XMM2,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SS -0x19cb(%RIP),%XMM2,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SS -0x19e4(%RIP),%XMM2,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SS -0x19d9(%RIP),%XMM2,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTSS2SD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VSUBSD %XMM1,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VCVTSD2SS %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VMULSS -0x44(%RBP),%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VCMPSS $0xe,-0x19fd(%RIP),%XMM2,%K1 | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVSS -0x58(%RBP),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSS -0x54(%RBP),%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSS -0x5c(%RBP),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSS %XMM0,%XMM0,%XMM0{%K1}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VFMADD231SS -0x50(%RBP),%XMM0,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SS -0x4c(%RBP),%XMM0,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SS -0x48(%RBP),%XMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVAPS %XMM1,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R14,%RBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JE 2023a5 <Step10_orig+0x185> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
VMOVSS %XMM0,-0x5c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVSS (%R13,%R14,4),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSS %XMM2,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVSS %XMM3,-0x54(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VSUBSS -0x2c(%RBP),%XMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VMOVSS (%R12,%R14,4),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VSUBSS -0x30(%RBP),%XMM0,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VMOVSS (%R15,%R14,4),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VSUBSS -0x34(%RBP),%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VMOVSS %XMM1,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVSS %XMM2,-0x4c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMULSS %XMM2,%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVSS %XMM0,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VFMADD231SS %XMM1,%XMM1,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SS %XMM0,%XMM0,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSS -0x38(%RBP),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VUCOMISS %XMM2,%XMM0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0.50 | 6 | 1 |
VXORPS %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JBE 202280 <Step10_orig+0x60> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV -0x70(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVSS (%RAX,%R14,4),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
JMP 202280 <Step10_orig+0x60> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
Function | Step10_orig |
Source file and lines | Step10_orig.c:19-35 |
Module | exec |
nb instructions | 48 |
nb uops | 51 |
loop length | 266 |
used x86 registers | 6 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 13 |
ADD-SUB / MUL ratio | 2.50 |
micro-operation queue | 8.50 cycles |
front end | 8.50 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.50 | 0.75 | 0.75 | 0.50 | 1.50 | 11.00 | 11.00 | 11.00 | 6.50 | 6.50 | 5.00 | 5.00 | 4.50 | 4.50 |
cycles | 1.50 | 0.75 | 0.75 | 0.50 | 1.50 | 11.00 | 11.00 | 11.00 | 6.50 | 6.50 | 5.00 | 5.00 | 4.50 | 4.50 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 0.00 |
Front-end | 8.50 |
Dispatch | 11.00 |
Data deps. | 0.00 |
Overall L1 | 11.00 |
all | 4% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 7% |
load | 6% |
store | 6% |
mul | 6% |
add-sub | 7% |
fma | 6% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVSS %XMM0,-0x44(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VADDSS -0x3c(%RBP),%XMM2,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VMOVSD -0x1952(%RIP),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSS %XMM2,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VCVTSS2SD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
CALL 2024a0 <@plt_start@+0xa0> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSS -0x40(%RBP),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSS -0x19b5(%RIP),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
INC %R14 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VFMADD213SS -0x19b1(%RIP),%XMM2,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SS -0x19b6(%RIP),%XMM2,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SS -0x19cb(%RIP),%XMM2,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SS -0x19e4(%RIP),%XMM2,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD213SS -0x19d9(%RIP),%XMM2,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCVTSS2SD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VSUBSD %XMM1,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VCVTSD2SS %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VMULSS -0x44(%RBP),%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VCMPSS $0xe,-0x19fd(%RIP),%XMM2,%K1 | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVSS -0x58(%RBP),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSS -0x54(%RBP),%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSS -0x5c(%RBP),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSS %XMM0,%XMM0,%XMM0{%K1}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 |
VFMADD231SS -0x50(%RBP),%XMM0,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SS -0x4c(%RBP),%XMM0,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SS -0x48(%RBP),%XMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVAPS %XMM1,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R14,%RBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JE 2023a5 <Step10_orig+0x185> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
VMOVSS %XMM0,-0x5c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVSS (%R13,%R14,4),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSS %XMM2,-0x58(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVSS %XMM3,-0x54(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VSUBSS -0x2c(%RBP),%XMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VMOVSS (%R12,%R14,4),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VSUBSS -0x30(%RBP),%XMM0,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VMOVSS (%R15,%R14,4),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VSUBSS -0x34(%RBP),%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
VMOVSS %XMM1,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVSS %XMM2,-0x4c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMULSS %XMM2,%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVSS %XMM0,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VFMADD231SS %XMM1,%XMM1,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231SS %XMM0,%XMM0,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSS -0x38(%RBP),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VUCOMISS %XMM2,%XMM0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0.50 | 6 | 1 |
VXORPS %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JBE 202280 <Step10_orig+0x60> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |