Function: main | Module: exec | Source: main.c:50-191 [...] | Coverage: 0.22% |
---|
Function: main | Module: exec | Source: main.c:50-191 [...] | Coverage: 0.22% |
---|
/home/eoseret/qaas_runs_CPU_9468/172-289-8348/intel/HACCmk/build/HACCmk/src/main.c: 50 - 191 |
-------------------------------------------------------------------------------- |
50: { |
[...] |
73: printf( "count is set %d\n", count ); |
74: printf( "Total MPI ranks %d\n", nprocs ); |
75: } |
76: |
77: if (argc == 2 && strncmp(argv[1], "-s", 2) == 0) |
78: NN = 15000; |
79: |
80: printf( "N is set %ld\n", NN ); |
81: |
82: #pragma omp parallel |
[...] |
97: for ( n = 400; n < NN; n = n + 20 ) |
[...] |
103: dx1 = 1.0f/(float)n; |
104: dy1 = 2.0f/(float)n; |
105: dz1 = 3.0f/(float)n; |
106: xx[0] = 0.f; |
107: yy[0] = 0.f; |
108: zz[0] = 0.f; |
109: mass[0] = 2.f; |
110: |
111: for ( i = 1; i < n; i++ ) |
112: { |
113: xx[i] = xx[i-1] + dx1; |
114: yy[i] = yy[i-1] + dy1; |
115: zz[i] = zz[i-1] + dz1; |
116: mass[i] = (float)i * 0.01f + xx[i]; |
117: } |
118: |
119: for ( i = 0; i < n; i++ ) |
120: { |
121: vx1[i] = 0.f; |
122: vy1[i] = 0.f; |
123: vz1[i] = 0.f; |
[...] |
136: t1 = mysecond(); |
137: #endif |
138: |
139: #pragma omp parallel for private( dx1, dy1, dz1 ) |
[...] |
152: t2 = mysecond(); |
[...] |
166: t3 = (t2 - t1) * 1e6; |
167: #endif |
168: |
169: elapsed = elapsed + t3; |
[...] |
185: printf( "\nKernel elapsed time, s: %18.8lf\n", elapsed*1e-6 ); |
[...] |
191: return 0; |
0x401550 PUSH %RBP |
0x401551 MOV %RSP,%RBP |
0x401554 PUSH %R15 |
0x401556 PUSH %R14 |
0x401558 PUSH %R13 |
0x40155a PUSH %R12 |
0x40155c PUSH %RBX |
0x40155d SUB $0x18,%RSP |
0x401561 VSTMXCSR -0x2c(%RBP) |
0x401566 MOV %RSI,%R14 |
0x401569 MOV %EDI,%R15D |
0x40156c MOV $0x4092e0,%EDI |
0x401571 MOV $0xbb8,%ESI |
0x401576 XOR %EAX,%EAX |
0x401578 ORL $0x8040,-0x2c(%RBP) |
0x40157f VLDMXCSR -0x2c(%RBP) |
0x401584 CALL 401030 <printf@plt> |
0x401589 MOV $0x4092f1,%EDI |
0x40158e MOV $0x1,%ESI |
0x401593 XOR %EAX,%EAX |
0x401595 CALL 401030 <printf@plt> |
0x40159a MOV $0x186a0,%EBX |
0x40159f CMP $0x2,%R15D |
0x4015a3 JNE 4015c3 |
0x4015a5 MOV 0x8(%R14),%RDI |
0x4015a9 MOV $0x409305,%ESI |
0x4015ae MOV $0x2,%EDX |
0x4015b3 CALL 4010a0 <strncmp@plt> |
0x4015b8 TEST %EAX,%EAX |
0x4015ba MOV $0x3a98,%EAX |
0x4015bf CMOVE %RAX,%RBX |
0x4015c3 MOV $0x409308,%EDI |
0x4015c8 MOV %RBX,%RSI |
0x4015cb XOR %EAX,%EAX |
0x4015cd CALL 401030 <printf@plt> |
0x4015d2 MOV $0x40d0c0,%EDI |
0x4015d7 MOV $0x401a80,%EDX |
0x4015dc MOV $0x1,%ESI |
0x4015e1 XOR %ECX,%ECX |
0x4015e3 XOR %EAX,%EAX |
0x4015e5 CALL 4010e0 <__kmpc_fork_call@plt> |
0x4015ea VBROADCASTSS 0x7a20(%RIP),%ZMM21 |
0x4015f4 VMOVSS 0x7a18(%RIP),%XMM1 |
0x4015fc VMOVDQU64 0x7aba(%RIP),%ZMM20 |
0x401606 VMOVDQU64 0x7af0(%RIP),%ZMM22 |
0x401610 VMOVDQU64 0x7b26(%RIP),%ZMM23 |
0x40161a ADD $-0x191,%EBX |
0x401620 MOV $-0x33333333,%R14D |
0x401626 VXORPS %XMM0,%XMM0,%XMM0 |
0x40162a MOV $0x190,%R15D |
0x401630 MOV $0x18c,%R12D |
0x401636 VPTERNLOGD $-0x1,%ZMM24,%ZMM24,%ZMM24 |
0x40163d XOR %R13D,%R13D |
0x401640 IMUL %RBX,%R14 |
0x401644 SHR $0x24,%R14 |
0x401648 INC %R14D |
0x40164b JMP 40172d |
(2) 0x401650 MOV $0x593b90,%EDI |
(2) 0x401655 XOR %ESI,%ESI |
(2) 0x401657 MOV %RBX,%RDX |
(2) 0x40165a VZEROUPPER |
(2) 0x40165d CALL 402100 <_intel_fast_memset> |
(2) 0x401662 MOV $0x5f5610,%EDI |
(2) 0x401667 XOR %ESI,%ESI |
(2) 0x401669 MOV %RBX,%RDX |
(2) 0x40166c CALL 402100 <_intel_fast_memset> |
(2) 0x401671 MOV $0x657090,%EDI |
(2) 0x401676 XOR %ESI,%ESI |
(2) 0x401678 MOV %RBX,%RDX |
(2) 0x40167b CALL 402100 <_intel_fast_memset> |
(2) 0x401680 XOR %EAX,%EAX |
(2) 0x401682 CALL 401c20 <mysecond> |
(2) 0x401687 VMOVSD %XMM0,-0x38(%RBP) |
(2) 0x40168c SUB $0x8,%RSP |
(2) 0x401690 MOV $0x40d120,%EDI |
(2) 0x401695 MOV $0x401ab0,%EDX |
(2) 0x40169a MOV $0x3e6b851f,%ECX |
(2) 0x40169f MOV $0x3f000000,%R8D |
(2) 0x4016a5 MOV $0x3cf5c28f,%R9D |
(2) 0x4016ab MOV $0x6,%ESI |
(2) 0x4016b0 XOR %EAX,%EAX |
(2) 0x4016b2 PUSH $0xbb7 |
(2) 0x4016b7 PUSH $0 |
(2) 0x4016b9 PUSH %R15 |
(2) 0x4016bb CALL 4010e0 <__kmpc_fork_call@plt> |
(2) 0x4016c0 ADD $0x20,%RSP |
(2) 0x4016c4 XOR %EAX,%EAX |
(2) 0x4016c6 CALL 401c20 <mysecond> |
(2) 0x4016cb VSUBSD -0x38(%RBP),%XMM0,%XMM0 |
(2) 0x4016d0 VMOVSD -0x40(%RBP),%XMM1 |
(2) 0x4016d5 VBROADCASTSS 0x7935(%RIP),%ZMM21 |
(2) 0x4016df VMOVDQU64 0x7a57(%RIP),%ZMM23 |
(2) 0x4016e9 VMOVDQU64 0x7a0d(%RIP),%ZMM22 |
(2) 0x4016f3 VMOVDQU64 0x79c3(%RIP),%ZMM20 |
(2) 0x4016fd VPTERNLOGD $-0x1,%ZMM24,%ZMM24,%ZMM24 |
(2) 0x401704 ADD $0x14,%R15 |
(2) 0x401708 INC %R13 |
(2) 0x40170b ADD $0x14,%R12 |
(2) 0x40170f VFMADD231SD 0x7bb8(%RIP),%XMM0,%XMM1 |
(2) 0x401718 VMOVAPD %XMM1,%XMM0 |
(2) 0x40171c VMOVSS 0x78f0(%RIP),%XMM1 |
(2) 0x401724 CMP %R14,%R13 |
(2) 0x401727 JE 401a57 |
(2) 0x40172d VMOVSD %XMM0,-0x40(%RBP) |
(2) 0x401732 VCVTSI2SS %R15D,%XMM27,%XMM4 |
(2) 0x401738 VMOVSS 0x78d0(%RIP),%XMM0 |
(2) 0x401740 LEA (%R13,%R13,4),%RBX |
(2) 0x401745 MOV %R12,%RAX |
(2) 0x401748 SHR $0x4,%RAX |
(2) 0x40174c LEA -0x1(%R15),%RCX |
(2) 0x401750 VXORPS %XMM5,%XMM5,%XMM5 |
(2) 0x401754 VXORPS %XMM6,%XMM6,%XMM6 |
(2) 0x401758 MOV $-0x3,%RDX |
(2) 0x40175f MOVL $0,0xba27(%RIP) |
(2) 0x401769 MOVL $0,0x6d49d(%RIP) |
(2) 0x401773 MOVL $0,0xcef13(%RIP) |
(2) 0x40177d MOVL $0x40000000,0x130989(%RIP) |
(2) 0x401787 SAL $0x6,%RAX |
(2) 0x40178b SAL $0x4,%RBX |
(2) 0x40178f ADD $0x640,%RBX |
(2) 0x401796 VDIVSS %XMM4,%XMM0,%XMM2 |
(2) 0x40179a VBROADCASTSS %XMM2,%XMM0 |
(2) 0x40179f VMULPS 0x7889(%RIP),%XMM0,%XMM3 |
(2) 0x4017a7 NOPW (%RAX,%RAX,1) |
(0) 0x4017b0 LEA 0x4(%RDX),%ESI |
(0) 0x4017b3 VADDSS %XMM2,%XMM6,%XMM6 |
(0) 0x4017b7 VADDPS %XMM3,%XMM5,%XMM5 |
(0) 0x4017bb VCVTSI2SS %ESI,%XMM27,%XMM0 |
(0) 0x4017c1 VMOVSHDUP %XMM5,%XMM10 |
(0) 0x4017c5 VMOVSS %XMM6,0x40d1a0(,%RDX,4) |
(0) 0x4017ce VMOVSS %XMM5,0x4d06a0(,%RDX,4) |
(0) 0x4017d7 VFMADD132SS %XMM1,%XMM6,%XMM0 |
(0) 0x4017dc VMOVSS %XMM10,0x46ec20(,%RDX,4) |
(0) 0x4017e5 VMOVSS %XMM0,0x532120(,%RDX,4) |
(0) 0x4017ee INC %RDX |
(0) 0x4017f1 JNE 4017b0 |
(2) 0x4017f3 VRCP14PS %XMM4,%XMM9 |
(2) 0x4017f9 VMOVSS 0x7819(%RIP),%XMM17 |
(2) 0x401803 VMOVUPS 0x7873(%RIP),%ZMM14 |
(2) 0x40180d VMOVSS 0x7801(%RIP),%XMM18 |
(2) 0x401817 VBROADCASTSS %XMM2,%ZMM0 |
(2) 0x40181d VBROADCASTSS %XMM6,%ZMM1 |
(2) 0x401823 VMOVSHDUP %XMM3,%XMM12 |
(2) 0x401827 VBROADCASTSD %XMM10,%ZMM8 |
(2) 0x40182d LEA -0x4(%R15),%RSI |
(2) 0x401831 MOV $0x3,%EDI |
(2) 0x401836 AND $-0x10,%RSI |
(2) 0x40183a LEA 0x3(%RSI),%RDX |
(2) 0x40183e OR $0x2,%RSI |
(2) 0x401842 VFMSUB213PS 0x409040,%XMM9,%XMM4 |
(2) 0x40184c VMULPS %XMM17,%XMM9,%XMM9 |
(2) 0x401852 VMULPS %ZMM14,%ZMM0,%ZMM11 |
(2) 0x401858 VMULSS %XMM18,%XMM2,%XMM7 |
(2) 0x40185e VADDPS %ZMM11,%ZMM1,%ZMM15 |
(2) 0x401864 VBROADCASTSD %XMM12,%ZMM1 |
(2) 0x40186a VMULPS %ZMM14,%ZMM1,%ZMM13 |
(2) 0x401870 VBROADCASTSS %XMM7,%ZMM7 |
(2) 0x401876 VADDPS %ZMM13,%ZMM8,%ZMM16 |
(2) 0x40187c VMULSS %XMM18,%XMM12,%XMM8 |
(2) 0x401882 VFNMADD213PS %XMM9,%XMM4,%XMM9 |
(2) 0x401887 VBROADCASTSS %XMM8,%ZMM8 |
(2) 0x40188d VBROADCASTSS %XMM9,%ZMM4 |
(2) 0x401893 VBROADCASTSS %XMM5,%ZMM9 |
(2) 0x401899 VMULPS %ZMM14,%ZMM4,%ZMM14 |
(2) 0x40189f VADDPS %ZMM14,%ZMM9,%ZMM17 |
(2) 0x4018a5 VMULSS %XMM18,%XMM3,%XMM9 |
(2) 0x4018ab VBROADCASTSS %XMM9,%ZMM9 |
(2) 0x4018b1 NOPW %CS:(%RAX,%RAX,1) |
(1) 0x4018c0 VPBROADCASTD %EDI,%ZMM25 |
(1) 0x4018c6 VADDPS %ZMM1,%ZMM16,%ZMM19 |
(1) 0x4018cc VADDPS %ZMM0,%ZMM15,%ZMM18 |
(1) 0x4018d2 VADDPS %ZMM4,%ZMM17,%ZMM26 |
(1) 0x4018d8 VADDPS %ZMM7,%ZMM15,%ZMM15 |
(1) 0x4018de VADDPS %ZMM8,%ZMM16,%ZMM16 |
(1) 0x4018e4 VADDPS %ZMM9,%ZMM17,%ZMM17 |
(1) 0x4018ea VMOVUPS %ZMM19,0x46ec14(,%RDI,4) |
(1) 0x4018f5 VMOVUPS %ZMM18,0x40d194(,%RDI,4) |
(1) 0x401900 VMOVUPS %ZMM26,0x4d0694(,%RDI,4) |
(1) 0x40190b VPADDD %ZMM20,%ZMM25,%ZMM19 |
(1) 0x401911 VCVTDQ2PS %ZMM19,%ZMM19 |
(1) 0x401917 VFMADD132PS %ZMM21,%ZMM18,%ZMM19 |
(1) 0x40191d VMOVUPS %ZMM19,0x532114(,%RDI,4) |
(1) 0x401928 ADD $0x10,%RDI |
(1) 0x40192c CMP %RSI,%RDI |
(1) 0x40192f JLE 4018c0 |
(2) 0x401931 SUB %RDX,%RCX |
(2) 0x401934 JE 401650 |
(2) 0x40193a VCVTSI2SS %RDX,%XMM27,%XMM15 |
(2) 0x401940 VADDSS 0x76d8(%RIP),%XMM15,%XMM15 |
(2) 0x401948 VFMADD213SS %XMM6,%XMM15,%XMM2 |
(2) 0x40194d VFMADD213SS %XMM10,%XMM15,%XMM12 |
(2) 0x401952 VFMADD213SS %XMM5,%XMM3,%XMM15 |
(2) 0x401957 VPBROADCASTQ %RCX,%ZMM6 |
(2) 0x40195d DEC %RCX |
(2) 0x401960 VBROADCASTSS %XMM12,%ZMM3 |
(2) 0x401966 VBROADCASTSS %XMM2,%ZMM2 |
(2) 0x40196c VBROADCASTSS %XMM15,%ZMM5 |
(2) 0x401972 VPBROADCASTQ %RDX,%ZMM12 |
(2) 0x401978 XOR %EDX,%EDX |
(2) 0x40197a VADDPS %ZMM11,%ZMM2,%ZMM2 |
(2) 0x401980 VADDPS %ZMM13,%ZMM3,%ZMM3 |
(2) 0x401986 VADDPS %ZMM14,%ZMM5,%ZMM5 |
(2) 0x40198c VPADDQ %ZMM22,%ZMM12,%ZMM10 |
(2) 0x401992 VPADDQ %ZMM23,%ZMM12,%ZMM11 |
(2) 0x401998 NOPL (%RAX,%RAX,1) |
(3) 0x4019a0 VPBROADCASTQ %RDX,%ZMM12 |
(3) 0x4019a6 VADDPS %ZMM4,%ZMM5,%ZMM15 |
(3) 0x4019ac VPADDQ %ZMM22,%ZMM12,%ZMM13 |
(3) 0x4019b2 VPADDQ %ZMM23,%ZMM12,%ZMM14 |
(3) 0x4019b8 VPCMPLTUQ %ZMM6,%ZMM14,%K0 |
(3) 0x4019bf VPCMPLTUQ %ZMM6,%ZMM13,%K1 |
(3) 0x4019c6 VADDPS %ZMM1,%ZMM3,%ZMM14 |
(3) 0x4019cc VADDPS %ZMM0,%ZMM2,%ZMM13 |
(3) 0x4019d2 KUNPCKBW %K0,%K1,%K1 |
(3) 0x4019d6 VMOVUPS %ZMM14,0x46ec20(%RAX,%RDX,4){%K1} |
(3) 0x4019e1 VPADDQ %ZMM12,%ZMM10,%ZMM14 |
(3) 0x4019e7 VPADDQ %ZMM12,%ZMM11,%ZMM12 |
(3) 0x4019ed VMOVUPS %ZMM13,0x40d1a0(%RAX,%RDX,4){%K1} |
(3) 0x4019f8 VMOVUPS %ZMM15,0x4d06a0(%RAX,%RDX,4){%K1} |
(3) 0x401a03 VADDPS %ZMM7,%ZMM2,%ZMM2{%K1} |
(3) 0x401a09 VADDPS %ZMM8,%ZMM3,%ZMM3{%K1} |
(3) 0x401a0f VADDPS %ZMM9,%ZMM5,%ZMM5{%K1} |
(3) 0x401a15 VPMOVQD %ZMM12,%YMM12 |
(3) 0x401a1b VPMOVQD %ZMM14,%YMM14 |
(3) 0x401a21 VINSERTI64X4 $0x1,%YMM14,%ZMM12,%ZMM12 |
(3) 0x401a28 VPSUBD %ZMM24,%ZMM12,%ZMM12 |
(3) 0x401a2e VCVTDQ2PS %ZMM12,%ZMM12 |
(3) 0x401a34 VFMADD132PS %ZMM21,%ZMM13,%ZMM12 |
(3) 0x401a3a VMOVUPS %ZMM12,0x532120(%RAX,%RDX,4){%K1} |
(3) 0x401a45 ADD $0x10,%RDX |
(3) 0x401a49 CMP %RCX,%RDX |
(3) 0x401a4c JLE 4019a0 |
(2) 0x401a52 JMP 401650 |
0x401a57 VMULSD 0x7879(%RIP),%XMM0,%XMM0 |
0x401a5f MOV $0x409331,%EDI |
0x401a64 MOV $0x1,%AL |
0x401a66 CALL 401030 <printf@plt> |
0x401a6b XOR %EAX,%EAX |
0x401a6d ADD $0x18,%RSP |
0x401a71 POP %RBX |
0x401a72 POP %R12 |
0x401a74 POP %R13 |
0x401a76 POP %R14 |
0x401a78 POP %R15 |
0x401a7a POP %RBP |
0x401a7b RET |
0x401a7c NOPL (%RAX) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○100.00 | __libc_start_call_main | libc.so.6 |
Path / |
Source file and lines | main.c:50-191 |
Module | exec |
nb instructions | 71 |
nb uops | 78 |
loop length | 297 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 5 |
nb stack references | 1 |
micro-operation queue | 13.00 cycles |
front end | 13.00 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 8.00 | 8.00 | 7.75 | 7.75 | 4.50 | 5.00 | 5.00 | 5.00 | 1.50 | 1.50 | 1.00 | 1.00 | 0.50 | 0.50 |
cycles | 8.00 | 8.00 | 7.75 | 7.75 | 4.50 | 6.00 | 6.00 | 6.00 | 1.50 | 1.50 | 1.00 | 1.00 | 0.50 | 0.50 |
Cycles executing div or sqrt instructions | NA |
Front-end | 13.00 |
Dispatch | 8.00 |
Overall L1 | 13.00 |
all | 14% |
load | 60% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 4% |
all | 25% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
all | 15% |
load | 37% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 8% |
all | 20% |
load | 63% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 12% |
load | 8% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
all | 19% |
load | 42% |
store | 6% |
mul | 12% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput | Vectorization |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
SUB $0x18,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
VSTMXCSR -0x2c(%RBP) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 20 | 15 | N/A |
MOV %RSI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
MOV %EDI,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | scal (6.3%) |
MOV $0x4092e0,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0xbb8,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
ORL $0x8040,-0x2c(%RBP) | 2 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
VLDMXCSR -0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 2 | N/A |
CALL 401030 <printf@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV $0x4092f1,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x1,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
CALL 401030 <printf@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV $0x186a0,%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
CMP $0x2,%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
JNE 4015c3 <main+0x73> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
MOV 0x8(%R14),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | scal (12.5%) |
MOV $0x409305,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x2,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
CALL 4010a0 <strncmp@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
TEST %EAX,%EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x3a98,%EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
CMOVE %RAX,%RBX | 1 | 0.50 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV $0x409308,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV %RBX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | scal (12.5%) |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
CALL 401030 <printf@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV $0x40d0c0,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x401a80,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x1,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (6.3%) |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
CALL 4010e0 <__kmpc_fork_call@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
VBROADCASTSS 0x7a20(%RIP),%ZMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 5 | 1 | scal (6.3%) |
VMOVSS 0x7a18(%RIP),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
VMOVDQU64 0x7aba(%RIP),%ZMM20 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (100.0%) |
VMOVDQU64 0x7af0(%RIP),%ZMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (100.0%) |
VMOVDQU64 0x7b26(%RIP),%ZMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (100.0%) |
ADD $-0x191,%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $-0x33333333,%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
VXORPS %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
MOV $0x190,%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x18c,%R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
VPTERNLOGD $-0x1,%ZMM24,%ZMM24,%ZMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 | vect (100.0%) |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (6.3%) |
IMUL %RBX,%R14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
SHR $0x24,%R14 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
INC %R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
JMP 40172d <main+0x1dd> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | N/A |
VMULSD 0x7879(%RIP),%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
MOV $0x409331,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x1,%AL | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
CALL 401030 <printf@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
ADD $0x18,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 | N/A |
Source file and lines | main.c:50-191 |
Module | exec |
nb instructions | 71 |
nb uops | 78 |
loop length | 297 |
used x86 registers | 12 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 5 |
nb stack references | 1 |
micro-operation queue | 13.00 cycles |
front end | 13.00 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 8.00 | 8.00 | 7.75 | 7.75 | 4.50 | 5.00 | 5.00 | 5.00 | 1.50 | 1.50 | 1.00 | 1.00 | 0.50 | 0.50 |
cycles | 8.00 | 8.00 | 7.75 | 7.75 | 4.50 | 6.00 | 6.00 | 6.00 | 1.50 | 1.50 | 1.00 | 1.00 | 0.50 | 0.50 |
Cycles executing div or sqrt instructions | NA |
Front-end | 13.00 |
Dispatch | 8.00 |
Overall L1 | 13.00 |
all | 14% |
load | 60% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 4% |
all | 25% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
all | 15% |
load | 37% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 8% |
all | 20% |
load | 63% |
store | 6% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 11% |
all | 12% |
load | 8% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
all | 19% |
load | 42% |
store | 6% |
mul | 12% |
add-sub | 6% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 11% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput | Vectorization |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
SUB $0x18,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
VSTMXCSR -0x2c(%RBP) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 20 | 15 | N/A |
MOV %RSI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
MOV %EDI,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | scal (6.3%) |
MOV $0x4092e0,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0xbb8,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
ORL $0x8040,-0x2c(%RBP) | 2 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
VLDMXCSR -0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 2 | N/A |
CALL 401030 <printf@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV $0x4092f1,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x1,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
CALL 401030 <printf@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV $0x186a0,%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
CMP $0x2,%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
JNE 4015c3 <main+0x73> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 | N/A |
MOV 0x8(%R14),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 | scal (12.5%) |
MOV $0x409305,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x2,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
CALL 4010a0 <strncmp@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
TEST %EAX,%EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x3a98,%EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
CMOVE %RAX,%RBX | 1 | 0.50 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV $0x409308,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV %RBX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | scal (12.5%) |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
CALL 401030 <printf@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV $0x40d0c0,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x401a80,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x1,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (6.3%) |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
CALL 4010e0 <__kmpc_fork_call@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
VBROADCASTSS 0x7a20(%RIP),%ZMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 5 | 1 | scal (6.3%) |
VMOVSS 0x7a18(%RIP),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
VMOVDQU64 0x7aba(%RIP),%ZMM20 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (100.0%) |
VMOVDQU64 0x7af0(%RIP),%ZMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (100.0%) |
VMOVDQU64 0x7b26(%RIP),%ZMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (100.0%) |
ADD $-0x191,%EBX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $-0x33333333,%R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
VXORPS %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
MOV $0x190,%R15D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x18c,%R12D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
VPTERNLOGD $-0x1,%ZMM24,%ZMM24,%ZMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 | vect (100.0%) |
XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (6.3%) |
IMUL %RBX,%R14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
SHR $0x24,%R14 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
INC %R14D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
JMP 40172d <main+0x1dd> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | N/A |
VMULSD 0x7879(%RIP),%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (12.5%) |
MOV $0x409331,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
MOV $0x1,%AL | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
CALL 401030 <printf@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
ADD $0x18,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 | N/A |
Name | Coverage (%) | Time (s) |
---|---|---|
▼main– | 0.22 | 0.02 |
▼Loop 2 - main.c:77-169 - exec– | 0.00 | 0.00 |
○Loop 1 - main.c:111-116 - exec | 0.22 | 3.25 |
○Loop 3 - main.c:77-116 - exec | 0.00 | 0.00 |
○Loop 0 - main.c:111-116 - exec | 0.00 | 0.00 |