Function: .omp_outlined.#0x43cbc0 | Module: exec | Source: Collapse.hpp:81-84 [...] | Coverage: 8.55% |
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Function: .omp_outlined.#0x43cbc0 | Module: exec | Source: Collapse.hpp:81-84 [...] | Coverage: 8.55% |
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/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/src/Kripke/Kernel/LTimes.cpp: 62 - 62 |
-------------------------------------------------------------------------------- |
62: phi(nm,g,z) += ell(nm, d) * psi(d, g, z); |
/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59 |
-------------------------------------------------------------------------------- |
59: for (decltype(distance_it) i = 0; i < distance_it; ++i) { |
/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp: 79 - 79 |
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79: : layout(V.layout), data(V.data) |
/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp: 55 - 55 |
-------------------------------------------------------------------------------- |
55: : val(rhs.val) |
/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp: 81 - 84 |
-------------------------------------------------------------------------------- |
81: #pragma omp parallel for private(i0, i1) firstprivate(privatizer) \ |
82: RAJA_COLLAPSE(2) |
83: for (i0 = 0; i0 < l0; ++i0) { |
84: for (i1 = 0; i1 < l1; ++i1) { |
0x43cbc0 SUB SP, SP, #192 |
0x43cbc4 STP X29, X30, [SP, #96] |
0x43cbc8 STP X28, X27, [SP, #112] |
0x43cbcc STP X26, X25, [SP, #128] |
0x43cbd0 STP X24, X23, [SP, #144] |
0x43cbd4 STP X22, X21, [SP, #160] |
0x43cbd8 STP X20, X19, [SP, #176] |
0x43cbdc ADD X29, SP, #96 |
0x43cbe0 LDR X8, [X2] |
0x43cbe4 LDR X20, [X3] |
0x43cbe8 CMP X8, #1 |
0x43cbec CCMP X20, #1, #8, #10 |
0x43cbf0 B.LT 43cc98 |
0x43cbf4 LDR X9, [X4] |
0x43cbf8 LDR X11, [X4, #32] |
0x43cbfc LDR W1, [X0] |
0x43cc00 MOVZ W10, #1 |
0x43cc04 ADRP X0, |
0x43cc08 ADD X0, X0, #328 |
0x43cc0c SUB X3, X29, #28 |
0x43cc10 SUB X5, X29, #16 |
0x43cc14 LDP X22, X28, [X4, #16] |
0x43cc18 LDP X27, X25, [X4, #48] |
0x43cc1c LDR X19, [X4, #168] |
0x43cc20 SUB X6, X29, #24 |
0x43cc24 MOVZ W2, #34 |
0x43cc28 MOVZ W7, #1 |
0x43cc2c LDR X23, [X4, #200] |
0x43cc30 LDR X24, [X4, #240] |
0x43cc34 STUR WZR, [X29, #484] |
0x43cc38 STUR X10, [X29, #488] |
0x43cc3c STUR X9, [X29, #472] |
0x43cc40 MOVN X9, #0 |
0x43cc44 STUR W1, [X29, #468] |
0x43cc48 MADD X21, X20, X8, X9 |
0x43cc4c LDR X9, [X4, #96] |
0x43cc50 LDR X8, [X4, #104] |
0x43cc54 STP X21, XZR, [X29, #1008] |
0x43cc58 STP X8, X9, [SP, #16] |
0x43cc5c LDP X26, X8, [X4, #272] |
0x43cc60 STP X8, X11, [SP, #32] |
0x43cc64 LDR X8, [X4, #344] |
0x43cc68 SUB X4, X29, #8 |
0x43cc6c STP X10, X8, [SP] |
0x43cc70 BL 402ca0 |
0x43cc74 LDP X8, X9, [X29, #1008] |
0x43cc78 CMP X8, X21 |
0x43cc7c CSEL X8, X8, X21, #11 |
0x43cc80 CMP X9, X8 |
0x43cc84 B.LE 43ccb8 |
(36) 0x43cc88 LDUR W1, [X29, #468] |
(36) 0x43cc8c ADRP X0, |
(36) 0x43cc90 ADD X0, X0, #352 |
(36) 0x43cc94 BL 402bc0 |
(36) 0x43cc98 LDP X20, X19, [SP, #176] |
(36) 0x43cc9c LDP X22, X21, [SP, #160] |
(36) 0x43cca0 LDP X24, X23, [SP, #144] |
(36) 0x43cca4 LDP X26, X25, [SP, #128] |
(36) 0x43cca8 LDP X28, X27, [SP, #112] |
(36) 0x43ccac LDP X29, X30, [SP, #96] |
(36) 0x43ccb0 ADD SP, SP, #192 |
(36) 0x43ccb4 RET |
(36) 0x43ccb8 MADD X2, X26, X22, XZR |
(36) 0x43ccbc UBFM X1, X27, #61, #60 |
(36) 0x43ccc0 LDP X3, X0, [SP, #32] |
(36) 0x43ccc4 SUB X11, X25, X27 |
(36) 0x43ccc8 LDP X18, X17, [SP, #16] |
(36) 0x43cccc UBFM X4, X26, #61, #60 |
(36) 0x43ccd0 AND X14, X11, #8062 |
(36) 0x43ccd4 ADD X15, X19, X1 |
(36) 0x43ccd8 ADD X1, X1, X2,LSL #3 |
(36) 0x43ccdc LDR X2, [SP, #8] |
(36) 0x43cce0 ORN X12, XZR, X27 |
(36) 0x43cce4 SUB X10, X28, X22 |
(36) 0x43cce8 AND X13, X11, #4160 |
(36) 0x43ccec ADD X16, X15, #16 |
(36) 0x43ccf0 ADD X12, X25, X12 |
(36) 0x43ccf4 SUB X14, XZR, X14 |
(36) 0x43ccf8 UBFM X17, X17, #61, #60 |
(36) 0x43ccfc ADD X0, X0, X9 |
(36) 0x43cd00 UBFM X18, X18, #61, #60 |
(36) 0x43cd04 UBFM X3, X3, #61, #60 |
(36) 0x43cd08 ADD X1, X2, X1 |
(36) 0x43cd0c ADD X2, X1, #16 |
(36) 0x43cd10 B 43cd30 |
0x43cd14 HINT #0 |
0x43cd18 HINT #0 |
0x43cd1c HINT #0 |
(36) 0x43cd20 CMP X9, X8 |
(36) 0x43cd24 ADD X9, X9, #1 |
(36) 0x43cd28 ADD X0, X0, #1 |
(36) 0x43cd2c B.EQ 43cc88 |
(36) 0x43cd30 CMP X10, #1 |
(36) 0x43cd34 B.LT 43cd20 |
(37) 0x43cd38 SDIV X7, X9, X20 |
(37) 0x43cd3c LDUR X6, [X29, #472] |
(37) 0x43cd40 ORR X5, XZR, XZR |
(37) 0x43cd44 ADD X19, X7, X6 |
(37) 0x43cd48 MSUB X7, X7, X20, X0 |
(37) 0x43cd4c ADD X6, X24, X19,LSL #3 |
(37) 0x43cd50 MADD X19, X17, X19, XZR |
(37) 0x43cd54 MADD X25, X3, X7, X2 |
(37) 0x43cd58 MADD X27, X3, X7, X1 |
(37) 0x43cd5c MADD X19, X18, X7, X19 |
(37) 0x43cd60 ADD X21, X16, X19 |
(37) 0x43cd64 ADD X26, X15, X19 |
(37) 0x43cd68 B 43cd80 |
(37) 0x43cd6c ADD X5, X5, #1 |
(37) 0x43cd70 ADD X25, X25, X4 |
(37) 0x43cd74 ADD X27, X27, X4 |
(37) 0x43cd78 CMP X5, X10 |
(37) 0x43cd7c B.EQ 43cd20 |
(37) 0x43cd80 CMP X11, #1 |
(37) 0x43cd84 B.LT 43cd6c |
(37) 0x43cd88 ADD X7, X5, X22 |
(37) 0x43cd8c CMP X12, #3 |
(37) 0x43cd90 MADD X28, X23, X7, XZR |
(37) 0x43cd94 B.CS 43cda4 |
(37) 0x43cd98 ORR X7, XZR, XZR |
(37) 0x43cd9c CBNZ X13, 43ce24 |
0x43cda0 B 43cd6c |
(37) 0x43cda4 ORR X19, XZR, XZR |
(37) 0x43cda8 ORR X30, XZR, X25 |
(37) 0x43cdac ORR X7, XZR, X21 |
(37) 0x43cdb0 HINT #0 |
(37) 0x43cdb4 HINT #0 |
(37) 0x43cdb8 HINT #0 |
(37) 0x43cdbc HINT #0 |
(38) 0x43cdc0 LDR D0, [X6, X28,LSL #3] |
(38) 0x43cdc4 LDUR D1, [X30, #496] |
(38) 0x43cdc8 LDP D2, D3, [X7, #1008] |
(38) 0x43cdcc SUB X19, X19, #4 |
(38) 0x43cdd0 CMP X14, X19 |
(38) 0x43cdd4 FMADD D0, D0, D1, D2 |
(38) 0x43cdd8 STUR D0, [X7, #496] |
(38) 0x43cddc LDR D0, [X6, X28,LSL #3] |
(38) 0x43cde0 LDUR D1, [X30, #504] |
(38) 0x43cde4 FMADD D0, D0, D1, D3 |
(38) 0x43cde8 LDP D2, D3, [X7] |
(38) 0x43cdec STUR D0, [X7, #504] |
(38) 0x43cdf0 LDR D0, [X6, X28,LSL #3] |
(38) 0x43cdf4 LDR D1, [X30] |
(38) 0x43cdf8 FMADD D0, D0, D1, D2 |
(38) 0x43cdfc STR D0, [X7] |
(38) 0x43ce00 LDR D0, [X6, X28,LSL #3] |
(38) 0x43ce04 LDR D1, [X30, #8] |
(38) 0x43ce08 ADD X30, X30, #32 |
(38) 0x43ce0c FMADD D0, D0, D1, D3 |
(38) 0x43ce10 STR D0, [X7, #8] |
(38) 0x43ce14 ADD X7, X7, #32 |
(38) 0x43ce18 B.NE 43cdc0 |
(37) 0x43ce1c SUB X7, XZR, X19 |
(37) 0x43ce20 CBZ X13, 43cd6c |
(37) 0x43ce24 UBFM X19, X7, #61, #60 |
(37) 0x43ce28 ORR X30, XZR, X13 |
(37) 0x43ce2c ADD X7, X26, X19 |
(37) 0x43ce30 ADD X19, X27, X19 |
(37) 0x43ce34 HINT #0 |
(37) 0x43ce38 HINT #0 |
(37) 0x43ce3c HINT #0 |
(39) 0x43ce40 LDR D0, [X6, X28,LSL #3] |
(39) 0x43ce44 LDR D2, [X7] |
(39) 0x43ce48 LDR D1, [X19], #8 |
(39) 0x43ce4c SUBS X30, X30, #1 |
(39) 0x43ce50 FMADD D0, D0, D1, D2 |
(39) 0x43ce54 STR D0, [X7], #8 |
(39) 0x43ce58 B.NE 43ce40 |
(37) 0x43ce5c B 43cd6c |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○100.00 | __kmp_invoke_microtask | libomp.so |
Path / |
Source file and lines | Collapse.hpp:81-84 |
Module | exec |
nb instructions | 54 |
loop length | 216 |
nb stack references | 0 |
front end | 6.38 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.00 | 2.00 | 4.75 | 4.75 | 4.75 | 4.75 | 0.00 | 0.00 | 0.00 | 0.00 | 9.67 | 9.67 | 9.67 | 7.00 | 7.00 |
cycles | 2.00 | 2.00 | 4.75 | 4.75 | 4.75 | 4.75 | 0.00 | 0.00 | 0.00 | 0.00 | 9.67 | 9.67 | 9.67 | 7.00 | 7.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 6.38 |
Overall L1 | 9.67 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SUB SP, SP, #192 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X29, X30, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X28, X27, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X26, X25, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X24, X23, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X22, X21, [SP, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X20, X19, [SP, #176] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #96 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X8, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X20, [X3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CCMP X20, #1, #8, #10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
B.LT 43cc98 <.omp_outlined.+0xd8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X9, [X4] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X11, [X4, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR W1, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
MOVZ W10, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X0, <4acc04> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #328 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X3, X29, #28 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X5, X29, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDP X22, X28, [X4, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X27, X25, [X4, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDR X19, [X4, #168] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUB X6, X29, #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X23, [X4, #200] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X24, [X4, #240] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STUR WZR, [X29, #484] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STUR X10, [X29, #488] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STUR X9, [X29, #472] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
MOVN X9, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STUR W1, [X29, #468] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
MADD X21, X20, X8, X9 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
LDR X9, [X4, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X8, [X4, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STP X21, XZR, [X29, #1008] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X8, X9, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDP X26, X8, [X4, #272] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
STP X8, X11, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X8, [X4, #344] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUB X4, X29, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X10, X8, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
BL 402ca0 <@plt_start@+0x4e0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDP X8, X9, [X29, #1008] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
CMP X8, X21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CSEL X8, X8, X21, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X9, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LE 43ccb8 <.omp_outlined.+0xf8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
B 43cd6c <.omp_outlined.+0x1ac> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Source file and lines | Collapse.hpp:81-84 |
Module | exec |
nb instructions | 54 |
loop length | 216 |
nb stack references | 0 |
front end | 6.38 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.00 | 2.00 | 4.75 | 4.75 | 4.75 | 4.75 | 0.00 | 0.00 | 0.00 | 0.00 | 9.67 | 9.67 | 9.67 | 7.00 | 7.00 |
cycles | 2.00 | 2.00 | 4.75 | 4.75 | 4.75 | 4.75 | 0.00 | 0.00 | 0.00 | 0.00 | 9.67 | 9.67 | 9.67 | 7.00 | 7.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 6.38 |
Overall L1 | 9.67 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SUB SP, SP, #192 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X29, X30, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X28, X27, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X26, X25, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X24, X23, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X22, X21, [SP, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X20, X19, [SP, #176] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #96 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X8, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X20, [X3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CCMP X20, #1, #8, #10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
B.LT 43cc98 <.omp_outlined.+0xd8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X9, [X4] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X11, [X4, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR W1, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
MOVZ W10, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADRP X0, <4acc04> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #328 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X3, X29, #28 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X5, X29, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDP X22, X28, [X4, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDP X27, X25, [X4, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDR X19, [X4, #168] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUB X6, X29, #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X23, [X4, #200] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X24, [X4, #240] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STUR WZR, [X29, #484] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STUR X10, [X29, #488] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STUR X9, [X29, #472] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
MOVN X9, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STUR W1, [X29, #468] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
MADD X21, X20, X8, X9 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
LDR X9, [X4, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X8, [X4, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STP X21, XZR, [X29, #1008] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X8, X9, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDP X26, X8, [X4, #272] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
STP X8, X11, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X8, [X4, #344] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUB X4, X29, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X10, X8, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
BL 402ca0 <@plt_start@+0x4e0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDP X8, X9, [X29, #1008] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
CMP X8, X21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CSEL X8, X8, X21, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X9, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LE 43ccb8 <.omp_outlined.+0xf8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
HINT #0 | ||||||||||||||||||
B 43cd6c <.omp_outlined.+0x1ac> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼.omp_outlined.#0x43cbc0– | 8.55 | 3.09 |
▼Loop 37 - forall.hpp:59-59 - exec– | 0 | 0.01 |
○Loop 38 - forall.hpp:59-59 - exec | 8.54 | 3.08 |
○Loop 36 - forall.hpp:59-59 - exec | 0 | 0.01 |
○Loop 39 - forall.hpp:59-59 - exec | 0 | 0 |