Function: .omp_outlined.#0x4429f0 | Module: exec | Source: Collapse.hpp:81-84 [...] | Coverage: 0.34% |
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Function: .omp_outlined.#0x4429f0 | Module: exec | Source: Collapse.hpp:81-84 [...] | Coverage: 0.34% |
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/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/src/Kripke/Kernel/Population.cpp: 58 - 58 |
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58: part_red += w(d) * psi(d,g,z) * volume(z); |
/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/reduce.hpp: 59 - 60 |
-------------------------------------------------------------------------------- |
59: #pragma omp critical(ompReduceCritical) |
60: Reduce()(Base::parent->local(), Base::my_data); |
/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59 |
-------------------------------------------------------------------------------- |
59: for (decltype(distance_it) i = 0; i < distance_it; ++i) { |
/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp: 79 - 79 |
-------------------------------------------------------------------------------- |
79: : layout(V.layout), data(V.data) |
/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp: 55 - 55 |
-------------------------------------------------------------------------------- |
55: : val(rhs.val) |
/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp: 81 - 84 |
-------------------------------------------------------------------------------- |
81: #pragma omp parallel for private(i0, i1) firstprivate(privatizer) \ |
82: RAJA_COLLAPSE(2) |
83: for (i0 = 0; i0 < l0; ++i0) { |
84: for (i1 = 0; i1 < l1; ++i1) { |
/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/detail/reduce.hpp: 74 - 271 |
-------------------------------------------------------------------------------- |
74: val = operator_type::operator()(val, v); |
[...] |
261: : parent{other.parent ? other.parent : &other}, |
262: identity{other.identity}, |
[...] |
271: if (parent && my_data != identity) { |
/home/hbollore/qaas-runs/170-289-7893/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp: 307 - 307 |
-------------------------------------------------------------------------------- |
307: return Ret{lhs} + rhs; |
0x4429f0 SUB SP, SP, #176 |
0x4429f4 STP D9, D8, [SP, #64] |
0x4429f8 STP X29, X30, [SP, #80] |
0x4429fc STP X28, X27, [SP, #96] |
0x442a00 STP X26, X25, [SP, #112] |
0x442a04 STP X24, X23, [SP, #128] |
0x442a08 STP X22, X21, [SP, #144] |
0x442a0c STP X20, X19, [SP, #160] |
0x442a10 ADD X29, SP, #80 |
0x442a14 LDR X8, [X2] |
0x442a18 LDR X20, [X3] |
0x442a1c CMP X8, #1 |
0x442a20 CCMP X20, #1, #8, #10 |
0x442a24 B.LT 442b20 |
0x442a28 MOVN X9, #0 |
0x442a2c LDR D8, [X4, #64] |
0x442a30 LDR X11, [X4, #16] |
0x442a34 LDR W1, [X0] |
0x442a38 ADRP X0, |
0x442a3c ADD X0, X0, #760 |
0x442a40 ADD X3, SP, #36 |
0x442a44 SUB X5, X29, #32 |
0x442a48 LDR X21, [X4] |
0x442a4c ADD X6, SP, #40 |
0x442a50 MADD X24, X20, X8, X9 |
0x442a54 ORR X9, XZR, X4 |
0x442a58 LDP X27, X19, [X4, #32] |
0x442a5c LDR X23, [X4, #112] |
0x442a60 LDP X28, X22, [X4, #144] |
0x442a64 MOVZ W8, #1 |
0x442a68 MOVZ W2, #34 |
0x442a6c LDR X25, [X4, #216] |
0x442a70 LDR X26, [X4, #256] |
0x442a74 SUB X4, X29, #24 |
0x442a78 MOVZ W7, #1 |
0x442a7c STR X8, [SP, #40] |
0x442a80 STR WZR, [SP, #36] |
0x442a84 LDR X10, [X9, #56]! |
0x442a88 CMP X10, #0 |
0x442a8c STP X24, XZR, [X29, #992] |
0x442a90 STP X8, X11, [SP] |
0x442a94 STR W1, [SP, #20] |
0x442a98 CSEL X9, X9, X10, #0 |
0x442a9c STR X9, [SP, #24] |
0x442aa0 BL 402ca0 |
0x442aa4 LDP X8, X9, [X29, #992] |
0x442aa8 FMOV D9, D8 |
0x442aac CMP X8, X24 |
0x442ab0 CSEL X8, X8, X24, #11 |
0x442ab4 CMP X9, X8 |
0x442ab8 B.LE 442b44 |
(33) 0x442abc LDR W1, [SP, #20] |
(33) 0x442ac0 ADRP X0, |
(33) 0x442ac4 ADD X0, X0, #784 |
(33) 0x442ac8 BL 402bc0 |
(33) 0x442acc ADRP X19, |
(33) 0x442ad0 ADD X19, X19, #832 |
(33) 0x442ad4 ORR X0, XZR, X19 |
(33) 0x442ad8 BL 402990 |
(33) 0x442adc ADRP X21, |
(33) 0x442ae0 ORR W20, WZR, W0 |
(33) 0x442ae4 ORR X0, XZR, X19 |
(33) 0x442ae8 LDR X21, [X21, #4024] |
(33) 0x442aec ORR W1, WZR, W20 |
(33) 0x442af0 ORR X2, XZR, X21 |
(33) 0x442af4 BL 402a80 |
(33) 0x442af8 LDR X22, [SP, #24] |
(33) 0x442afc ORR X0, XZR, X19 |
(33) 0x442b00 ORR W1, WZR, W20 |
(33) 0x442b04 LDR D0, [X22, #16] |
(33) 0x442b08 ORR X2, XZR, X21 |
(33) 0x442b0c FADD D0, D9, D0 |
(33) 0x442b10 STR D0, [X22, #16] |
(33) 0x442b14 BL 402930 |
(33) 0x442b18 FCMP D8, D8 |
(33) 0x442b1c B.VS 442c80 |
(33) 0x442b20 LDP D9, D8, [SP, #64] |
(33) 0x442b24 LDP X20, X19, [SP, #160] |
(33) 0x442b28 LDP X22, X21, [SP, #144] |
(33) 0x442b2c LDP X24, X23, [SP, #128] |
(33) 0x442b30 LDP X26, X25, [SP, #112] |
(33) 0x442b34 LDP X28, X27, [SP, #96] |
(33) 0x442b38 LDP X29, X30, [SP, #80] |
(33) 0x442b3c ADD SP, SP, #176 |
(33) 0x442b40 RET |
(33) 0x442b44 LDR X18, [SP, #8] |
(33) 0x442b48 SUB X10, X19, X27 |
(33) 0x442b4c ORN X11, XZR, X27 |
(33) 0x442b50 UBFM X1, X27, #61, #60 |
(33) 0x442b54 FMOV D9, D8 |
(33) 0x442b58 UBFM X16, X28, #61, #60 |
(33) 0x442b5c UBFM X17, X22, #61, #60 |
(33) 0x442b60 ADD X15, X1, #16 |
(33) 0x442b64 ADD X0, X26, X1 |
(33) 0x442b68 ADD X1, X25, X1 |
(33) 0x442b6c AND X13, X10, #8062 |
(33) 0x442b70 ADD X11, X19, X11 |
(33) 0x442b74 ADD X14, X26, X15 |
(33) 0x442b78 AND X12, X10, #4160 |
(33) 0x442b7c ADD X15, X25, X15 |
(33) 0x442b80 SUB X13, XZR, X13 |
(33) 0x442b84 ADD X18, X18, X9 |
(33) 0x442b88 B 442b9c |
(33) 0x442b8c CMP X9, X8 |
(33) 0x442b90 ADD X9, X9, #1 |
(33) 0x442b94 ADD X18, X18, #1 |
(33) 0x442b98 B.EQ 442abc |
(33) 0x442b9c CMP X10, #1 |
(33) 0x442ba0 B.LT 442b8c |
(33) 0x442ba4 SDIV X2, X9, X20 |
(33) 0x442ba8 CMP X11, #3 |
(33) 0x442bac MADD X3, X2, X20, XZR |
(33) 0x442bb0 ADD X2, X2, X21 |
(33) 0x442bb4 LDR D0, [X23, X2,LSL #3] |
(33) 0x442bb8 B.CS 442bc8 |
(33) 0x442bbc ORR X4, XZR, XZR |
(33) 0x442bc0 CBNZ X12, 442c34 |
0x442bc4 B 442b8c |
(33) 0x442bc8 SUB X5, X18, X3 |
(33) 0x442bcc ORR X4, XZR, XZR |
(33) 0x442bd0 ORR X6, XZR, X14 |
(33) 0x442bd4 MADD X5, X17, X5, XZR |
(33) 0x442bd8 MADD X5, X16, X2, X5 |
(33) 0x442bdc ADD X5, X15, X5 |
(34) 0x442be0 LDP D1, D2, [X5, #1008] |
(34) 0x442be4 LDP D3, D4, [X6, #1008] |
(34) 0x442be8 SUB X4, X4, #4 |
(34) 0x442bec CMP X13, X4 |
(34) 0x442bf0 FMUL D2, D0, D2 |
(34) 0x442bf4 FMUL D1, D0, D1 |
(34) 0x442bf8 FMUL D2, D2, D4 |
(34) 0x442bfc FMUL D1, D1, D3 |
(34) 0x442c00 LDP D4, D5, [X6], #32 |
(34) 0x442c04 FADD D1, D9, D1 |
(34) 0x442c08 FADD D1, D1, D2 |
(34) 0x442c0c LDP D2, D3, [X5], #32 |
(34) 0x442c10 FMUL D2, D0, D2 |
(34) 0x442c14 FMUL D2, D2, D4 |
(34) 0x442c18 FADD D1, D1, D2 |
(34) 0x442c1c FMUL D2, D0, D3 |
(34) 0x442c20 FMUL D2, D2, D5 |
(34) 0x442c24 FADD D9, D1, D2 |
(34) 0x442c28 B.NE 442be0 |
(33) 0x442c2c SUB X4, XZR, X4 |
(33) 0x442c30 CBZ X12, 442b8c |
(33) 0x442c34 SUB X3, X18, X3 |
(33) 0x442c38 UBFM X5, X4, #61, #60 |
(33) 0x442c3c ADD X4, X0, X5 |
(33) 0x442c40 MADD X3, X17, X3, XZR |
(33) 0x442c44 MADD X2, X16, X2, X3 |
(33) 0x442c48 ADD X3, X1, X5 |
(33) 0x442c4c ADD X2, X3, X2 |
(33) 0x442c50 ORR X3, XZR, X12 |
(33) 0x442c54 HINT #0 |
(33) 0x442c58 HINT #0 |
(33) 0x442c5c HINT #0 |
(35) 0x442c60 LDR D1, [X2], #8 |
(35) 0x442c64 LDR D2, [X4], #8 |
(35) 0x442c68 FMUL D1, D0, D1 |
(35) 0x442c6c SUBS X3, X3, #1 |
(35) 0x442c70 FMUL D1, D1, D2 |
(35) 0x442c74 FADD D9, D9, D1 |
(35) 0x442c78 B.NE 442c60 |
(33) 0x442c7c B 442b8c |
(33) 0x442c80 LDR D0, [X22, #16] |
(33) 0x442c84 FADD D0, D8, D0 |
(33) 0x442c88 STR D0, [X22, #16] |
(33) 0x442c8c B 442b20 |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○100.00 | __kmp_invoke_microtask | libomp.so |
Path / |
Source file and lines | Collapse.hpp:81-84 |
Module | exec |
nb instructions | 52 |
loop length | 208 |
nb stack references | 0 |
front end | 6.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.00 | 2.00 | 5.75 | 5.75 | 5.75 | 5.75 | 0.50 | 0.50 | 0.50 | 0.50 | 8.83 | 8.50 | 8.67 | 6.00 | 6.00 |
cycles | 2.00 | 2.00 | 5.75 | 5.75 | 5.75 | 5.75 | 0.50 | 0.50 | 0.50 | 0.50 | 8.83 | 8.50 | 8.67 | 6.00 | 6.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 6.50 |
Overall L1 | 8.83 |
all | 10% |
load | 0% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SUB SP, SP, #176 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP D9, D8, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP X29, X30, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X28, X27, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X26, X25, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X24, X23, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X22, X21, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X20, X19, [SP, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #80 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X8, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X20, [X3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CCMP X20, #1, #8, #10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
B.LT 442b20 <.omp_outlined.+0x130> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOVN X9, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR D8, [X4, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDR X11, [X4, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR W1, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADRP X0, <4aca38> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #760 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X3, SP, #36 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X5, X29, #32 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X21, [X4] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X6, SP, #40 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MADD X24, X20, X8, X9 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ORR X9, XZR, X4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDP X27, X19, [X4, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDR X23, [X4, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDP X28, X22, [X4, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X25, [X4, #216] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X26, [X4, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUB X4, X29, #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X8, [SP, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR WZR, [SP, #36] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X10, [X9, #56]! | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X10, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
STP X24, XZR, [X29, #992] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X8, X11, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR W1, [SP, #20] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
CSEL X9, X9, X10, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X9, [SP, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
BL 402ca0 <@plt_start@+0x4e0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDP X8, X9, [X29, #992] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
FMOV D9, D8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
CMP X8, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CSEL X8, X8, X24, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X9, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LE 442b44 <.omp_outlined.+0x154> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
B 442b8c <.omp_outlined.+0x19c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Source file and lines | Collapse.hpp:81-84 |
Module | exec |
nb instructions | 52 |
loop length | 208 |
nb stack references | 0 |
front end | 6.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.00 | 2.00 | 5.75 | 5.75 | 5.75 | 5.75 | 0.50 | 0.50 | 0.50 | 0.50 | 8.83 | 8.50 | 8.67 | 6.00 | 6.00 |
cycles | 2.00 | 2.00 | 5.75 | 5.75 | 5.75 | 5.75 | 0.50 | 0.50 | 0.50 | 0.50 | 8.83 | 8.50 | 8.67 | 6.00 | 6.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 6.50 |
Overall L1 | 8.83 |
all | 10% |
load | 0% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SUB SP, SP, #176 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP D9, D8, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP X29, X30, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X28, X27, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X26, X25, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X24, X23, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X22, X21, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X20, X19, [SP, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #80 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X8, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X20, [X3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CCMP X20, #1, #8, #10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
B.LT 442b20 <.omp_outlined.+0x130> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOVN X9, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR D8, [X4, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDR X11, [X4, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR W1, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADRP X0, <4aca38> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #760 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X3, SP, #36 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SUB X5, X29, #32 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X21, [X4] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X6, SP, #40 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MADD X24, X20, X8, X9 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
ORR X9, XZR, X4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDP X27, X19, [X4, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
LDR X23, [X4, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDP X28, X22, [X4, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X25, [X4, #216] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X26, [X4, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
SUB X4, X29, #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X8, [SP, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR WZR, [SP, #36] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
LDR X10, [X9, #56]! | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X10, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
STP X24, XZR, [X29, #992] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X8, X11, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR W1, [SP, #20] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
CSEL X9, X9, X10, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X9, [SP, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
BL 402ca0 <@plt_start@+0x4e0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDP X8, X9, [X29, #992] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
FMOV D9, D8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
CMP X8, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CSEL X8, X8, X24, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X9, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LE 442b44 <.omp_outlined.+0x154> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
B 442b8c <.omp_outlined.+0x19c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼.omp_outlined.#0x4429f0– | 0.34 | 0.12 |
▼Loop 33 - forall.hpp:59-59 - exec– | 0 | 0 |
○Loop 34 - forall.hpp:59-59 - exec | 0.34 | 0.12 |
○Loop 35 - forall.hpp:59-59 - exec | 0 | 0 |