Function: .omp_outlined.#0x445c50 | Module: exec | Source: Collapse.hpp:81-84 [...] | Coverage: 1.53% |
---|
Function: .omp_outlined.#0x445c50 | Module: exec | Source: Collapse.hpp:81-84 [...] | Coverage: 1.53% |
---|
/home/hbollore/qaas/qaas-runs/169-817-5851/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp: 81 - 84 |
-------------------------------------------------------------------------------- |
81: #pragma omp parallel for private(i0, i1) firstprivate(privatizer) \ |
82: RAJA_COLLAPSE(2) |
83: for (i0 = 0; i0 < l0; ++i0) { |
84: for (i1 = 0; i1 < l1; ++i1) { |
/home/hbollore/qaas/qaas-runs/169-817-5851/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/detail/reduce.hpp: 74 - 271 |
-------------------------------------------------------------------------------- |
74: val = operator_type::operator()(val, v); |
[...] |
261: : parent{other.parent ? other.parent : &other}, |
262: identity{other.identity}, |
[...] |
271: if (parent && my_data != identity) { |
/home/hbollore/qaas/qaas-runs/169-817-5851/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp: 307 - 307 |
-------------------------------------------------------------------------------- |
307: return Ret{lhs} + rhs; |
/home/hbollore/qaas/qaas-runs/169-817-5851/intel/Kripke/build/Kripke/src/Kripke/Kernel/Population.cpp: 58 - 58 |
-------------------------------------------------------------------------------- |
58: part_red += w(d) * psi(d,g,z) * volume(z); |
/home/hbollore/qaas/qaas-runs/169-817-5851/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59 |
-------------------------------------------------------------------------------- |
59: for (decltype(distance_it) i = 0; i < distance_it; ++i) { |
/home/hbollore/qaas/qaas-runs/169-817-5851/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp: 55 - 55 |
-------------------------------------------------------------------------------- |
55: : val(rhs.val) |
/home/hbollore/qaas/qaas-runs/169-817-5851/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/reduce.hpp: 59 - 60 |
-------------------------------------------------------------------------------- |
59: #pragma omp critical(ompReduceCritical) |
60: Reduce()(Base::parent->local(), Base::my_data); |
/home/hbollore/qaas/qaas-runs/169-817-5851/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp: 79 - 79 |
-------------------------------------------------------------------------------- |
79: : layout(V.layout), data(V.data) |
0x445c50 STR D8, [SP, #400]! |
0x445c54 STP X29, X30, [SP, #16] |
0x445c58 STP X28, X27, [SP, #32] |
0x445c5c STP X26, X25, [SP, #48] |
0x445c60 STP X24, X23, [SP, #64] |
0x445c64 STP X22, X21, [SP, #80] |
0x445c68 STP X20, X19, [SP, #96] |
0x445c6c ADD X29, SP, #16 |
0x445c70 ADDVL SP, SP, #63 |
0x445c74 SUB SP, SP, #64 |
0x445c78 LDR X8, [X2] |
0x445c7c LDR X20, [X3] |
0x445c80 CMP X8, #1 |
0x445c84 CCMP X20, #1, #8, #10 |
0x445c88 B.LT 445da8 |
0x445c8c MOVN X9, #0 |
0x445c90 LDR D8, [X4, #64] |
0x445c94 LDR W1, [X0] |
0x445c98 LDR X21, [X4] |
0x445c9c ADRP X0, |
0x445ca0 ADD X0, X0, #744 |
0x445ca4 ADD X3, SP, #44 |
0x445ca8 ADD X5, SP, #56 |
0x445cac LDP X25, X26, [X4, #32] |
0x445cb0 MADD X24, X20, X8, X9 |
0x445cb4 LDR X9, [X4, #16] |
0x445cb8 ADDVL X8, SP, #1 |
0x445cbc LDR X23, [X4, #112] |
0x445cc0 ADD X6, SP, #48 |
0x445cc4 MOVZ W2, #34 |
0x445cc8 LDP X27, X28, [X4, #144] |
0x445ccc MOVZ W7, #1 |
0x445cd0 LDR X22, [X4, #216] |
0x445cd4 LDR X19, [X4, #256] |
0x445cd8 STR WZR, [SP, #44] |
0x445cdc STR XZR, [X8, #72] |
0x445ce0 MOVZ W8, #1 |
0x445ce4 STP X8, X24, [SP, #48] |
0x445ce8 STR W1, [SP, #28] |
0x445cec STR X9, [SP, #16] |
0x445cf0 ORR X9, XZR, X4 |
0x445cf4 ADD X4, SP, #72 |
0x445cf8 ADDVL X4, X4, #1 |
0x445cfc LDR X10, [X9, #56]! |
0x445d00 STR X8, [SP] |
0x445d04 CMP X10, #0 |
0x445d08 CSEL X9, X9, X10, #0 |
0x445d0c STR X9, [SP, #32] |
0x445d10 BL 402c90 |
0x445d14 LDR X8, [SP, #56] |
0x445d18 ADDVL X9, SP, #1 |
0x445d1c FMOV D6, D8 |
0x445d20 LDR X9, [X9, #72] |
0x445d24 CMP X8, X24 |
0x445d28 CSEL X8, X8, X24, #11 |
0x445d2c CMP X9, X8 |
0x445d30 B.LE 445dd0 |
(33) 0x445d34 SUB X8, X29, #16 |
(33) 0x445d38 ADRP X0, |
(33) 0x445d3c ADD X0, X0, #768 |
(33) 0x445d40 STR Z6, [X8, #511, MUL VL] |
(33) 0x445d44 LDR W1, [SP, #28] |
(33) 0x445d48 BL 402bb0 |
(33) 0x445d4c ADRP X19, |
(33) 0x445d50 ADD X19, X19, #816 |
(33) 0x445d54 ORR X0, XZR, X19 |
(33) 0x445d58 BL 402980 |
(33) 0x445d5c ADRP X21, |
(33) 0x445d60 ORR W20, WZR, W0 |
(33) 0x445d64 ORR X0, XZR, X19 |
(33) 0x445d68 LDR X21, [X21, #4024] |
(33) 0x445d6c ORR W1, WZR, W20 |
(33) 0x445d70 ORR X2, XZR, X21 |
(33) 0x445d74 BL 402a70 |
(33) 0x445d78 LDR X22, [SP, #32] |
(33) 0x445d7c SUB X8, X29, #16 |
(33) 0x445d80 ORR X0, XZR, X19 |
(33) 0x445d84 ORR W1, WZR, W20 |
(33) 0x445d88 LDR D0, [X22, #16] |
(33) 0x445d8c LDR Z1, [X8, #511, MUL VL] |
(33) 0x445d90 ORR X2, XZR, X21 |
(33) 0x445d94 FADD D0, D1, D0 |
(33) 0x445d98 STR D0, [X22, #16] |
(33) 0x445d9c BL 402920 |
(33) 0x445da0 FCMP D8, D8 |
(33) 0x445da4 B.VS 445ee4 |
(33) 0x445da8 ADDVL SP, SP, #1 |
(33) 0x445dac ADD SP, SP, #64 |
(33) 0x445db0 LDP X20, X19, [SP, #96] |
(33) 0x445db4 LDP X22, X21, [SP, #80] |
(33) 0x445db8 LDP X24, X23, [SP, #64] |
(33) 0x445dbc LDP X26, X25, [SP, #48] |
(33) 0x445dc0 LDP X28, X27, [SP, #32] |
(33) 0x445dc4 LDP X29, X30, [SP, #16] |
(33) 0x445dc8 LDR D8, [SP], #112 |
(33) 0x445dcc RET |
(33) 0x445dd0 LDR X15, [SP, #16] |
(33) 0x445dd4 UBFM X12, X25, #61, #60 |
(33) 0x445dd8 SUB X10, X26, X25 |
(33) 0x445ddc SUB X16, X25, X26 |
(33) 0x445de0 FMOV D6, D8 |
(33) 0x445de4 UBFM X13, X27, #61, #60 |
(33) 0x445de8 UBFM X14, X28, #61, #60 |
(33) 0x445dec CNTW X17, ALL |
(33) 0x445df0 PTRUE P0.D, ALL |
(33) 0x445df4 ADD X11, X19, X12 |
(33) 0x445df8 ADD X12, X22, X12 |
(33) 0x445dfc ADDVL X18, X11, #1 |
(33) 0x445e00 ADD X15, X15, X9 |
(33) 0x445e04 B 445e18 |
(34) 0x445e08 CMP X9, X8 |
(34) 0x445e0c ADD X9, X9, #1 |
(34) 0x445e10 ADD X15, X15, #1 |
(34) 0x445e14 B.EQ 445d34 |
(34) 0x445e18 CMP X10, #1 |
(34) 0x445e1c B.LT 445e08 |
(34) 0x445e20 SDIV X0, X9, X20 |
(34) 0x445e24 CMP X10, X17 |
(34) 0x445e28 MADD X1, X0, X20, XZR |
(34) 0x445e2c ADD X0, X0, X21 |
(34) 0x445e30 LDR D0, [X23, X0,LSL #3] |
(34) 0x445e34 B.CS 445e40 |
(34) 0x445e38 ORR X2, XZR, XZR |
(34) 0x445e3c B 445ea4 |
(34) 0x445e40 UDIV X2, X10, X17 |
(34) 0x445e44 SUB X5, X15, X1 |
(34) 0x445e48 ORR X4, XZR, XZR |
(34) 0x445e4c DUP Z1.D, Z0.D[0] |
(34) 0x445e50 MADD X5, X14, X5, XZR |
(34) 0x445e54 MADD X6, X13, X0, X5 |
(34) 0x445e58 ADD X5, X12, X6 |
(34) 0x445e5c ADDVL X6, X6, #1 |
(34) 0x445e60 ADD X6, X12, X6 |
(34) 0x445e64 MADD X2, X2, X17, XZR |
(34) 0x445e68 SUB X3, X10, X2 |
(35) 0x445e6c LD1D {Z2.D}, P0/Z, [X5, X4,LSL #3] |
(35) 0x445e70 LD1D {Z4.D}, P0/Z, [X11, X4,LSL #3] |
(35) 0x445e74 FMUL Z2.D, Z1.D, Z2.D |
(35) 0x445e78 LD1D {Z3.D}, P0/Z, [X6, X4,LSL #3] |
(35) 0x445e7c LD1D {Z5.D}, P0/Z, [X18, X4,LSL #3] |
(35) 0x445e80 FMUL Z3.D, Z1.D, Z3.D |
(35) 0x445e84 ADD X4, X4, X17 |
(35) 0x445e88 CMP X2, X4 |
(35) 0x445e8c FMUL Z2.D, Z2.D, Z4.D |
(35) 0x445e90 FMUL Z3.D, Z3.D, Z5.D |
(35) 0x445e94 FADDA D6, P0, D6, Z2.D |
(35) 0x445e98 FADDA D6, P0, D6, Z3.D |
(35) 0x445e9c B.NE 445e6c |
(34) 0x445ea0 CBZ X3, 445e08 |
(34) 0x445ea4 SUB X1, X15, X1 |
(34) 0x445ea8 UBFM X4, X2, #61, #60 |
(34) 0x445eac ADD X3, X16, X2 |
(34) 0x445eb0 ADD X2, X11, X4 |
(34) 0x445eb4 MADD X1, X14, X1, XZR |
(34) 0x445eb8 MADD X0, X13, X0, X1 |
(34) 0x445ebc ADD X1, X12, X4 |
(34) 0x445ec0 ADD X0, X1, X0 |
(36) 0x445ec4 LDR D1, [X0], #8 |
(36) 0x445ec8 LDR D2, [X2], #8 |
(36) 0x445ecc FMUL D1, D0, D1 |
(36) 0x445ed0 ADDS X3, X3, #1 |
(36) 0x445ed4 FMUL D1, D1, D2 |
(36) 0x445ed8 FADD D6, D6, D1 |
(36) 0x445edc B.CC 445ec4 |
(34) 0x445ee0 B 445e08 |
(33) 0x445ee4 LDR D0, [X22, #16] |
(33) 0x445ee8 FADD D0, D8, D0 |
(33) 0x445eec STR D0, [X22, #16] |
(33) 0x445ef0 B 445da8 |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○100.00 | __kmp_invoke_microtask | libomp.so |
Path / |
Source file and lines | Collapse.hpp:81-84 |
Module | exec |
nb instructions | 57 |
loop length | 228 |
nb stack references | 0 |
front end | 7.13 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.50 | 1.50 | 6.75 | 6.75 | 6.75 | 6.75 | 0.50 | 0.50 | 0.50 | 0.50 | 9.33 | 9.33 | 9.33 | 6.50 | 6.50 |
cycles | 1.50 | 1.50 | 6.75 | 6.75 | 6.75 | 6.75 | 0.50 | 0.50 | 0.50 | 0.50 | 9.33 | 9.33 | 9.33 | 6.50 | 6.50 |
Cycles executing div or sqrt instructions | NA |
Front-end | 7.13 |
Overall L1 | 9.33 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STR D8, [SP, #400]! | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP X29, X30, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X28, X27, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X26, X25, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X24, X23, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X22, X21, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X20, X19, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADDVL SP, SP, #63 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
SUB SP, SP, #64 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X8, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X20, [X3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CCMP X20, #1, #8, #10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
B.LT 445da8 <.omp_outlined.+0x158> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOVN X9, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR D8, [X4, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDR W1, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X21, [X4] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADRP X0, <4b3c9c> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #744 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X3, SP, #44 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X5, SP, #56 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDP X25, X26, [X4, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
MADD X24, X20, X8, X9 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
LDR X9, [X4, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADDVL X8, SP, #1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
LDR X23, [X4, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X6, SP, #48 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDP X27, X28, [X4, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X22, [X4, #216] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X19, [X4, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STR WZR, [SP, #44] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR XZR, [X8, #72] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X8, X24, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR W1, [SP, #28] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X9, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ORR X9, XZR, X4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X4, SP, #72 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADDVL X4, X4, #1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
LDR X10, [X9, #56]! | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STR X8, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
CMP X10, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CSEL X9, X9, X10, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X9, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
BL 402c90 <@plt_start@+0x4e0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X8, [SP, #56] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADDVL X9, SP, #1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
FMOV D6, D8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
LDR X9, [X9, #72] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X8, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CSEL X8, X8, X24, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X9, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LE 445dd0 <.omp_outlined.+0x180> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Source file and lines | Collapse.hpp:81-84 |
Module | exec |
nb instructions | 57 |
loop length | 228 |
nb stack references | 0 |
front end | 7.13 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.50 | 1.50 | 6.75 | 6.75 | 6.75 | 6.75 | 0.50 | 0.50 | 0.50 | 0.50 | 9.33 | 9.33 | 9.33 | 6.50 | 6.50 |
cycles | 1.50 | 1.50 | 6.75 | 6.75 | 6.75 | 6.75 | 0.50 | 0.50 | 0.50 | 0.50 | 9.33 | 9.33 | 9.33 | 6.50 | 6.50 |
Cycles executing div or sqrt instructions | NA |
Front-end | 7.13 |
Overall L1 | 9.33 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | 0% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STR D8, [SP, #400]! | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
STP X29, X30, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X28, X27, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X26, X25, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X24, X23, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X22, X21, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STP X20, X19, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ADD X29, SP, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADDVL SP, SP, #63 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
SUB SP, SP, #64 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X8, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X20, [X3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CCMP X20, #1, #8, #10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
B.LT 445da8 <.omp_outlined.+0x158> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOVN X9, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR D8, [X4, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
LDR W1, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X21, [X4] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADRP X0, <4b3c9c> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X0, X0, #744 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X3, SP, #44 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X5, SP, #56 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDP X25, X26, [X4, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
MADD X24, X20, X8, X9 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
LDR X9, [X4, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADDVL X8, SP, #1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
LDR X23, [X4, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADD X6, SP, #48 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOVZ W2, #34 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDP X27, X28, [X4, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
MOVZ W7, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
LDR X22, [X4, #216] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
LDR X19, [X4, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STR WZR, [SP, #44] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR XZR, [X8, #72] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
MOVZ W8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STP X8, X24, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR W1, [SP, #28] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
STR X9, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
ORR X9, XZR, X4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD X4, SP, #72 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADDVL X4, X4, #1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
LDR X10, [X9, #56]! | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
STR X8, [SP] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
CMP X10, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CSEL X9, X9, X10, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
STR X9, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
BL 402c90 <@plt_start@+0x4e0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LDR X8, [SP, #56] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
ADDVL X9, SP, #1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
FMOV D6, D8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
LDR X9, [X9, #72] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
CMP X8, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
CSEL X8, X8, X24, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP X9, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
B.LE 445dd0 <.omp_outlined.+0x180> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼.omp_outlined.#0x445c50– | 1.53 | 0.21 |
▼Loop 33 - reduce.hpp:74-271 - exec– | 0 | 0 |
▼Loop 34 - forall.hpp:59-59 - exec– | 0 | 0 |
○Loop 35 - forall.hpp:59-59 - exec | 1.53 | 0.21 |
○Loop 36 - forall.hpp:59-59 - exec | 0 | 0 |