Function: void RAJA::internal::StatementExecutor<RAJA::statement::Collapse<RAJA::omp_parallel_collap ... | Module: libkripke.so | Source: Collapse.hpp:81-81 [...] | Coverage: 3.26% |
---|
Function: void RAJA::internal::StatementExecutor<RAJA::statement::Collapse<RAJA::omp_parallel_collap ... | Module: libkripke.so | Source: Collapse.hpp:81-81 [...] | Coverage: 3.26% |
---|
/home/eoseret/qaas_runs_CPU_9468/171-147-9160/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp: 79 - 110 |
-------------------------------------------------------------------------------- |
79: : layout(V.layout), data(V.data) |
[...] |
110: return data[idx]; |
/home/eoseret/qaas_runs_CPU_9468/171-147-9160/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp: 81 - 81 |
-------------------------------------------------------------------------------- |
81: #pragma omp parallel for private(i0, i1) firstprivate(privatizer) \ |
/home/eoseret/qaas_runs_CPU_9468/171-147-9160/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp: 55 - 55 |
-------------------------------------------------------------------------------- |
55: return a * b; |
/home/eoseret/qaas_runs_CPU_9468/171-147-9160/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp: 307 - 307 |
-------------------------------------------------------------------------------- |
307: return Ret{lhs} + rhs; |
/home/eoseret/qaas_runs_CPU_9468/171-147-9160/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/index/RangeSegment.hpp: 120 - 120 |
-------------------------------------------------------------------------------- |
120: RAJA_HOST_DEVICE RAJA_INLINE ~TypedRangeSegment() {} |
/home/eoseret/qaas_runs_CPU_9468/171-147-9160/intel/Kripke/build/Kripke/src/Kripke/Kernel/LPlusTimes.cpp: 57 - 57 |
-------------------------------------------------------------------------------- |
57: rhs(d,g,z) += ell_plus(d, nm) * phi_out(nm, g, z); |
/home/eoseret/qaas_runs_CPU_9468/171-147-9160/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59 |
-------------------------------------------------------------------------------- |
59: for (decltype(distance_it) i = 0; i < distance_it; ++i) { |
/home/eoseret/qaas_runs_CPU_9468/171-147-9160/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp: 55 - 177 |
-------------------------------------------------------------------------------- |
55: : val(rhs.val) |
[...] |
142: return val - rhs.val; |
[...] |
177: return value_type(val + rhs); |
0x42c40 PUSH %RBP |
0x42c41 MOV %RSP,%RBP |
0x42c44 PUSH %R15 |
0x42c46 PUSH %R14 |
0x42c48 PUSH %R13 |
0x42c4a PUSH %R12 |
0x42c4c PUSH %RBX |
0x42c4d AND $-0x20,%RSP |
0x42c51 SUB $0xe0,%RSP |
0x42c58 MOV 0x10(%RDI),%RAX |
0x42c5c MOV (%RAX),%RBX |
0x42c5f MOV 0x110(%RAX),%R13 |
0x42c66 MOV 0x10(%RAX),%RDX |
0x42c6a MOV 0x18(%RAX),%RCX |
0x42c6e MOV 0x20(%RAX),%RSI |
0x42c72 MOV 0x38(%RAX),%R8 |
0x42c76 MOV %RBX,0x8(%RSP) |
0x42c7b MOV 0x60(%RAX),%R9 |
0x42c7f MOV 0x68(%RAX),%R10 |
0x42c83 MOV %R13,0xd0(%RSP) |
0x42c8b MOV 0xc0(%RAX),%R11 |
0x42c92 MOV 0xf0(%RAX),%R12 |
0x42c99 MOV %RDX,0x70(%RSP) |
0x42c9e MOV 0x118(%RAX),%R15 |
0x42ca5 MOV 0x30(%RAX),%RBX |
0x42ca9 MOV %RCX,0x68(%RSP) |
0x42cae MOV 0xa8(%RAX),%R14 |
0x42cb5 MOV %RSI,0x58(%RSP) |
0x42cba MOV %R8,0x60(%RSP) |
0x42cbf MOV %R9,0x30(%RSP) |
0x42cc4 MOV %R10,0x38(%RSP) |
0x42cc9 MOV %R11,0x48(%RSP) |
0x42cce MOV %R12,0x50(%RSP) |
0x42cd3 MOV %R15,0x40(%RSP) |
0x42cd8 MOV 0x158(%RAX),%R15 |
0x42cdf MOV (%RDI),%R13 |
0x42ce2 MOV 0x8(%RDI),%RAX |
0x42ce6 TEST %R13,%R13 |
0x42ce9 JLE 43187 |
0x42cef MOV %RAX,0x78(%RSP) |
0x42cf4 TEST %RAX,%RAX |
0x42cf7 JLE 43187 |
0x42cfd CALL 9760 <omp_get_num_threads@plt> |
0x42d02 MOVSXD %EAX,%R12 |
0x42d05 CALL 9650 <omp_get_thread_num@plt> |
0x42d0a XOR %EDX,%EDX |
0x42d0c MOVSXD %EAX,%RDI |
0x42d0f MOV 0x78(%RSP),%RAX |
0x42d14 IMUL %R13,%RAX |
0x42d18 DIV %R12 |
0x42d1b MOV %RAX,%RCX |
0x42d1e CMP %RDX,%RDI |
0x42d21 JB 433ad |
0x42d27 IMUL %RCX,%RDI |
0x42d2b LEA (%RDI,%RDX,1),%RAX |
0x42d2f LEA (%RCX,%RAX,1),%RSI |
0x42d33 CMP %RSI,%RAX |
0x42d36 JAE 43187 |
0x42d3c XOR %EDX,%EDX |
0x42d3e MOV 0x60(%RSP),%R12 |
0x42d43 MOV 0x70(%RSP),%R9 |
0x42d48 DIVQ 0x78(%RSP) |
0x42d4d SUB %RBX,%R12 |
0x42d50 MOV %RAX,0x10(%RSP) |
0x42d55 MOV %RDX,%R8 |
0x42d58 CMP %R9,0x68(%RSP) |
0x42d5d JLE 43187 |
0x42d63 TEST %R12,%R12 |
0x42d66 JLE 43187 |
0x42d6c MOV 0xd0(%RSP),%R11 |
0x42d74 LEA -0x1(%RCX),%R10 |
0x42d78 MOV 0x10(%RSP),%RSI |
0x42d7d MOV %R12,%RCX |
0x42d80 MOV 0x8(%RSP),%RDX |
0x42d85 MOV %R10,0x20(%RSP) |
0x42d8a SHR $0x2,%RCX |
0x42d8e MOV %R12,%RAX |
0x42d91 IMUL %R11,%R9 |
0x42d95 MOV %R12,%R10 |
0x42d98 LEA (,%R11,8),%R13 |
0x42da0 SAL $0x5,%RCX |
0x42da4 LEA -0x1(%R12),%RDI |
0x42da9 AND $-0x4,%RAX |
0x42dad ADD %RDX,%RSI |
0x42db0 AND $0x3,%R10D |
0x42db4 MOV %R13,0xc0(%RSP) |
0x42dbc XOR %R11D,%R11D |
0x42dbf MOV %R9,0x18(%RSP) |
0x42dc4 MOV %R12,%R9 |
0x42dc7 AND $0x3,%R9D |
0x42dcb MOV %RDI,0xa8(%RSP) |
0x42dd3 MOV %RCX,0xc8(%RSP) |
0x42ddb MOV %RAX,0x98(%RSP) |
0x42de3 MOV %RSI,0x28(%RSP) |
0x42de8 MOV %R9,0xa0(%RSP) |
0x42df0 MOV %R10,0x90(%RSP) |
0x42df8 NOPL (%RAX,%RAX,1) |
(327) 0x42e00 MOV 0x58(%RSP),%R13 |
(327) 0x42e05 MOV 0x28(%RSP),%RCX |
(327) 0x42e0a MOV %R8,0x88(%RSP) |
(327) 0x42e12 MOV 0x38(%RSP),%R10 |
(327) 0x42e17 MOV 0x30(%RSP),%RSI |
(327) 0x42e1c MOV %R11,0x80(%RSP) |
(327) 0x42e24 LEA (%R8,%R13,1),%RDI |
(327) 0x42e28 MOV 0x48(%RSP),%RAX |
(327) 0x42e2d MOV 0x70(%RSP),%RDX |
(327) 0x42e32 IMUL %RCX,%RSI |
(327) 0x42e36 MOV 0x50(%RSP),%R9 |
(327) 0x42e3b IMUL %RDI,%R10 |
(327) 0x42e3f IMUL %RCX,%RAX |
(327) 0x42e43 ADD %RSI,%R10 |
(327) 0x42e46 MOV 0x40(%RSP),%RSI |
(327) 0x42e4b LEA (%RAX,%RDX,1),%R13 |
(327) 0x42e4f MOV 0x18(%RSP),%RDX |
(327) 0x42e54 IMUL %RSI,%RDI |
(327) 0x42e58 LEA (%R9,%R13,8),%RCX |
(327) 0x42e5c ADD %RDX,%RDI |
(327) 0x42e5f MOV 0x68(%RSP),%RDX |
(327) 0x42e64 LEA (%RBX,%RDI,1),%R13 |
(327) 0x42e68 ADD %RDX,%RAX |
(327) 0x42e6b LEA (%R15,%R13,8),%RSI |
(327) 0x42e6f MOV 0x60(%RSP),%R13 |
(327) 0x42e74 LEA (%R9,%RAX,8),%RAX |
(327) 0x42e78 LEA (%R10,%RBX,1),%R9 |
(327) 0x42e7c MOV %R9,0xb8(%RSP) |
(327) 0x42e84 ADD %R10,%R13 |
(327) 0x42e87 MOV %RAX,0xd8(%RSP) |
(327) 0x42e8f LEA (%R14,%R13,8),%R13 |
(327) 0x42e93 LEA (%R14,%R9,8),%RAX |
(327) 0x42e97 NOPW (%RAX,%RAX,1) |
(326) 0x42ea0 CMP $0x1,%R12 |
(326) 0x42ea4 JE 43350 |
(326) 0x42eaa LEA 0x8(%RCX),%R9 |
(326) 0x42eae CMP %R9,%RAX |
(326) 0x42eb1 SETAE %R8B |
(326) 0x42eb5 CMP %R13,%RCX |
(326) 0x42eb8 SETAE %R11B |
(326) 0x42ebc OR %R8B,%R11B |
(326) 0x42ebf JE 431a0 |
(326) 0x42ec5 LEA 0x8(%RSI),%R8 |
(326) 0x42ec9 MOV %RAX,%RDX |
(326) 0x42ecc SUB %R8,%RDX |
(326) 0x42ecf CMP $0x10,%RDX |
(326) 0x42ed3 JBE 431a0 |
(326) 0x42ed9 CMPQ $0x2,0xa8(%RSP) |
(326) 0x42ee2 JBE 4336a |
(326) 0x42ee8 MOV 0xc8(%RSP),%R11 |
(326) 0x42ef0 VBROADCASTSD (%RCX),%YMM2 |
(326) 0x42ef5 XOR %EDX,%EDX |
(326) 0x42ef7 LEA -0x20(%R11),%R8 |
(326) 0x42efb SHR $0x5,%R8 |
(326) 0x42eff INC %R8 |
(326) 0x42f02 AND $0x7,%R8D |
(326) 0x42f06 JE 42fcc |
(326) 0x42f0c CMP $0x1,%R8 |
(326) 0x42f10 JE 42faa |
(326) 0x42f16 CMP $0x2,%R8 |
(326) 0x42f1a JE 42f96 |
(326) 0x42f1c CMP $0x3,%R8 |
(326) 0x42f20 JE 42f82 |
(326) 0x42f22 CMP $0x4,%R8 |
(326) 0x42f26 JE 42f6e |
(326) 0x42f28 CMP $0x5,%R8 |
(326) 0x42f2c JE 42f5a |
(326) 0x42f2e CMP $0x6,%R8 |
(326) 0x42f32 JE 42f46 |
(326) 0x42f34 VMOVUPD (%RSI),%YMM1 |
(326) 0x42f38 MOV $0x20,%EDX |
(326) 0x42f3d VFMADD213PD (%RAX),%YMM2,%YMM1 |
(326) 0x42f42 VMOVUPD %YMM1,(%RAX) |
(326) 0x42f46 VMOVUPD (%RSI,%RDX,1),%YMM3 |
(326) 0x42f4b VFMADD213PD (%RAX,%RDX,1),%YMM2,%YMM3 |
(326) 0x42f51 VMOVUPD %YMM3,(%RAX,%RDX,1) |
(326) 0x42f56 ADD $0x20,%RDX |
(326) 0x42f5a VMOVUPD (%RSI,%RDX,1),%YMM5 |
(326) 0x42f5f VFMADD213PD (%RAX,%RDX,1),%YMM2,%YMM5 |
(326) 0x42f65 VMOVUPD %YMM5,(%RAX,%RDX,1) |
(326) 0x42f6a ADD $0x20,%RDX |
(326) 0x42f6e VMOVUPD (%RSI,%RDX,1),%YMM6 |
(326) 0x42f73 VFMADD213PD (%RAX,%RDX,1),%YMM2,%YMM6 |
(326) 0x42f79 VMOVUPD %YMM6,(%RAX,%RDX,1) |
(326) 0x42f7e ADD $0x20,%RDX |
(326) 0x42f82 VMOVUPD (%RSI,%RDX,1),%YMM7 |
(326) 0x42f87 VFMADD213PD (%RAX,%RDX,1),%YMM2,%YMM7 |
(326) 0x42f8d VMOVUPD %YMM7,(%RAX,%RDX,1) |
(326) 0x42f92 ADD $0x20,%RDX |
(326) 0x42f96 VMOVUPD (%RSI,%RDX,1),%YMM8 |
(326) 0x42f9b VFMADD213PD (%RAX,%RDX,1),%YMM2,%YMM8 |
(326) 0x42fa1 VMOVUPD %YMM8,(%RAX,%RDX,1) |
(326) 0x42fa6 ADD $0x20,%RDX |
(326) 0x42faa VMOVUPD (%RSI,%RDX,1),%YMM9 |
(326) 0x42faf VFMADD213PD (%RAX,%RDX,1),%YMM2,%YMM9 |
(326) 0x42fb5 VMOVUPD %YMM9,(%RAX,%RDX,1) |
(326) 0x42fba ADD $0x20,%RDX |
(326) 0x42fbe CMP %RDX,0xc8(%RSP) |
(326) 0x42fc6 JE 4309a |
(329) 0x42fcc VMOVUPD (%RSI,%RDX,1),%YMM10 |
(329) 0x42fd1 VFMADD213PD (%RAX,%RDX,1),%YMM2,%YMM10 |
(329) 0x42fd7 VMOVUPD %YMM10,(%RAX,%RDX,1) |
(329) 0x42fdc VMOVUPD 0x20(%RDX,%RSI,1),%YMM11 |
(329) 0x42fe2 VFMADD213PD 0x20(%RAX,%RDX,1),%YMM2,%YMM11 |
(329) 0x42fe9 VMOVUPD %YMM11,0x20(%RAX,%RDX,1) |
(329) 0x42fef VMOVUPD 0x40(%RDX,%RSI,1),%YMM12 |
(329) 0x42ff5 VFMADD213PD 0x40(%RAX,%RDX,1),%YMM2,%YMM12 |
(329) 0x42ffc VMOVUPD %YMM12,0x40(%RAX,%RDX,1) |
(329) 0x43002 VMOVUPD 0x60(%RDX,%RSI,1),%YMM13 |
(329) 0x43008 VFMADD213PD 0x60(%RAX,%RDX,1),%YMM2,%YMM13 |
(329) 0x4300f VMOVUPD %YMM13,0x60(%RAX,%RDX,1) |
(329) 0x43015 VMOVUPD 0x80(%RDX,%RSI,1),%YMM14 |
(329) 0x4301e VFMADD213PD 0x80(%RAX,%RDX,1),%YMM2,%YMM14 |
(329) 0x43028 VMOVUPD %YMM14,0x80(%RAX,%RDX,1) |
(329) 0x43031 VMOVUPD 0xa0(%RDX,%RSI,1),%YMM15 |
(329) 0x4303a VFMADD213PD 0xa0(%RAX,%RDX,1),%YMM2,%YMM15 |
(329) 0x43044 VMOVUPD %YMM15,0xa0(%RAX,%RDX,1) |
(329) 0x4304d VMOVUPD 0xc0(%RDX,%RSI,1),%YMM0 |
(329) 0x43056 VFMADD213PD 0xc0(%RAX,%RDX,1),%YMM2,%YMM0 |
(329) 0x43060 VMOVUPD %YMM0,0xc0(%RAX,%RDX,1) |
(329) 0x43069 VMOVUPD 0xe0(%RDX,%RSI,1),%YMM4 |
(329) 0x43072 VFMADD213PD 0xe0(%RAX,%RDX,1),%YMM2,%YMM4 |
(329) 0x4307c VMOVUPD %YMM4,0xe0(%RAX,%RDX,1) |
(329) 0x43085 ADD $0x100,%RDX |
(329) 0x4308c CMP %RDX,0xc8(%RSP) |
(329) 0x43094 JNE 42fcc |
(326) 0x4309a CMPQ $0,0xa0(%RSP) |
(326) 0x430a3 JE 4312d |
(326) 0x430a9 MOV 0x90(%RSP),%R11 |
(326) 0x430b1 MOV %R11,%RDX |
(326) 0x430b4 CMP $0x1,%R11 |
(326) 0x430b8 JE 43381 |
(326) 0x430be MOV 0x98(%RSP),%R8 |
(326) 0x430c6 MOV %R8,0xb0(%RSP) |
(326) 0x430ce MOV 0xb8(%RSP),%R11 |
(326) 0x430d6 VMOVDDUP (%RCX),%XMM2 |
(326) 0x430da ADD %R8,%R11 |
(326) 0x430dd ADD %RBX,%R8 |
(326) 0x430e0 LEA (%R14,%R11,8),%R11 |
(326) 0x430e4 ADD %RDI,%R8 |
(326) 0x430e7 VMOVUPD (%R11),%XMM1 |
(326) 0x430ec VFMADD132PD (%R15,%R8,8),%XMM1,%XMM2 |
(326) 0x430f2 VMOVUPD %XMM2,(%R11) |
(326) 0x430f7 TEST $0x1,%DL |
(326) 0x430fa JE 4312d |
(326) 0x430fc MOV 0xb0(%RSP),%R8 |
(326) 0x43104 AND $-0x2,%RDX |
(326) 0x43108 ADD %R8,%RDX |
(326) 0x4310b ADD %RBX,%RDX |
(326) 0x4310e VMOVSD (%RCX),%XMM3 |
(326) 0x43112 LEA (%R10,%RDX,1),%R11 |
(326) 0x43116 ADD %RDI,%RDX |
(326) 0x43119 LEA (%R14,%R11,8),%R8 |
(326) 0x4311d VMOVSD (%R8),%XMM5 |
(326) 0x43122 VFMADD132SD (%R15,%RDX,8),%XMM5,%XMM3 |
(326) 0x43128 VMOVSD %XMM3,(%R8) |
(326) 0x4312d MOV 0xc0(%RSP),%R8 |
(326) 0x43135 MOV %R9,%RCX |
(326) 0x43138 MOV 0xd8(%RSP),%R11 |
(326) 0x43140 MOV 0xd0(%RSP),%R9 |
(326) 0x43148 ADD %R8,%RSI |
(326) 0x4314b ADD %R9,%RDI |
(326) 0x4314e CMP %R11,%RCX |
(326) 0x43151 JNE 42ea0 |
(327) 0x43157 MOV 0x80(%RSP),%R11 |
(327) 0x4315f MOV 0x88(%RSP),%R8 |
(327) 0x43167 CMP %R11,0x20(%RSP) |
(327) 0x4316c JE 43184 |
(327) 0x4316e INC %R8 |
(327) 0x43171 CMP %R8,0x78(%RSP) |
(327) 0x43176 JLE 4338e |
(327) 0x4317c INC %R11 |
(327) 0x4317f JMP 42e00 |
0x43184 VZEROUPPER |
0x43187 LEA -0x28(%RBP),%RSP |
0x4318b POP %RBX |
0x4318c POP %R12 |
0x4318e POP %R13 |
0x43190 POP %R14 |
0x43192 POP %R15 |
0x43194 POP %RBP |
0x43195 RET |
0x43196 NOPW %CS:(%RAX,%RAX,1) |
(326) 0x431a0 MOV %R12,%R11 |
(326) 0x431a3 XOR %EDX,%EDX |
(326) 0x431a5 AND $0x7,%R11D |
(326) 0x431a9 JE 43284 |
(326) 0x431af CMP $0x1,%R11 |
(326) 0x431b3 JE 43264 |
(326) 0x431b9 CMP $0x2,%R11 |
(326) 0x431bd JE 4324d |
(326) 0x431c3 CMP $0x3,%R11 |
(326) 0x431c7 JE 43236 |
(326) 0x431c9 CMP $0x4,%R11 |
(326) 0x431cd JE 4321f |
(326) 0x431cf CMP $0x5,%R11 |
(326) 0x431d3 JE 43208 |
(326) 0x431d5 CMP $0x6,%R11 |
(326) 0x431d9 JE 431f1 |
(326) 0x431db VMOVSD (%RSI),%XMM7 |
(326) 0x431df VMOVSD (%RAX),%XMM6 |
(326) 0x431e3 MOV $0x1,%EDX |
(326) 0x431e8 VFMADD132SD (%RCX),%XMM6,%XMM7 |
(326) 0x431ed VMOVSD %XMM7,(%RAX) |
(326) 0x431f1 VMOVSD (%RSI,%RDX,8),%XMM8 |
(326) 0x431f6 VMOVSD (%RAX,%RDX,8),%XMM9 |
(326) 0x431fb VFMADD132SD (%RCX),%XMM9,%XMM8 |
(326) 0x43200 VMOVSD %XMM8,(%RAX,%RDX,8) |
(326) 0x43205 INC %RDX |
(326) 0x43208 VMOVSD (%RSI,%RDX,8),%XMM10 |
(326) 0x4320d VMOVSD (%RAX,%RDX,8),%XMM11 |
(326) 0x43212 VFMADD132SD (%RCX),%XMM11,%XMM10 |
(326) 0x43217 VMOVSD %XMM10,(%RAX,%RDX,8) |
(326) 0x4321c INC %RDX |
(326) 0x4321f VMOVSD (%RSI,%RDX,8),%XMM12 |
(326) 0x43224 VMOVSD (%RAX,%RDX,8),%XMM13 |
(326) 0x43229 VFMADD132SD (%RCX),%XMM13,%XMM12 |
(326) 0x4322e VMOVSD %XMM12,(%RAX,%RDX,8) |
(326) 0x43233 INC %RDX |
(326) 0x43236 VMOVSD (%RSI,%RDX,8),%XMM14 |
(326) 0x4323b VMOVSD (%RAX,%RDX,8),%XMM15 |
(326) 0x43240 VFMADD132SD (%RCX),%XMM15,%XMM14 |
(326) 0x43245 VMOVSD %XMM14,(%RAX,%RDX,8) |
(326) 0x4324a INC %RDX |
(326) 0x4324d VMOVSD (%RSI,%RDX,8),%XMM0 |
(326) 0x43252 VMOVSD (%RAX,%RDX,8),%XMM4 |
(326) 0x43257 VFMADD132SD (%RCX),%XMM4,%XMM0 |
(326) 0x4325c VMOVSD %XMM0,(%RAX,%RDX,8) |
(326) 0x43261 INC %RDX |
(326) 0x43264 VMOVSD (%RSI,%RDX,8),%XMM2 |
(326) 0x43269 VMOVSD (%RAX,%RDX,8),%XMM1 |
(326) 0x4326e VFMADD132SD (%RCX),%XMM1,%XMM2 |
(326) 0x43273 VMOVSD %XMM2,(%RAX,%RDX,8) |
(326) 0x43278 INC %RDX |
(326) 0x4327b CMP %RDX,%R12 |
(326) 0x4327e JE 4312d |
(328) 0x43284 VMOVSD (%RSI,%RDX,8),%XMM3 |
(328) 0x43289 VMOVSD (%RAX,%RDX,8),%XMM5 |
(328) 0x4328e VMOVSD 0x8(%RAX,%RDX,8),%XMM6 |
(328) 0x43294 VMOVSD 0x10(%RAX,%RDX,8),%XMM9 |
(328) 0x4329a VFMADD132SD (%RCX),%XMM5,%XMM3 |
(328) 0x4329f VMOVSD 0x18(%RAX,%RDX,8),%XMM11 |
(328) 0x432a5 VMOVSD 0x20(%RAX,%RDX,8),%XMM13 |
(328) 0x432ab VMOVSD 0x28(%RAX,%RDX,8),%XMM15 |
(328) 0x432b1 VMOVSD 0x30(%RAX,%RDX,8),%XMM4 |
(328) 0x432b7 VMOVSD 0x38(%RAX,%RDX,8),%XMM1 |
(328) 0x432bd VMOVSD %XMM3,(%RAX,%RDX,8) |
(328) 0x432c2 VMOVSD 0x8(%RSI,%RDX,8),%XMM7 |
(328) 0x432c8 VFMADD132SD (%RCX),%XMM6,%XMM7 |
(328) 0x432cd VMOVSD %XMM7,0x8(%RAX,%RDX,8) |
(328) 0x432d3 VMOVSD 0x10(%RSI,%RDX,8),%XMM8 |
(328) 0x432d9 VFMADD132SD (%RCX),%XMM9,%XMM8 |
(328) 0x432de VMOVSD %XMM8,0x10(%RAX,%RDX,8) |
(328) 0x432e4 VMOVSD 0x18(%RSI,%RDX,8),%XMM10 |
(328) 0x432ea VFMADD132SD (%RCX),%XMM11,%XMM10 |
(328) 0x432ef VMOVSD %XMM10,0x18(%RAX,%RDX,8) |
(328) 0x432f5 VMOVSD 0x20(%RSI,%RDX,8),%XMM12 |
(328) 0x432fb VFMADD132SD (%RCX),%XMM13,%XMM12 |
(328) 0x43300 VMOVSD %XMM12,0x20(%RAX,%RDX,8) |
(328) 0x43306 VMOVSD 0x28(%RSI,%RDX,8),%XMM14 |
(328) 0x4330c VFMADD132SD (%RCX),%XMM15,%XMM14 |
(328) 0x43311 VMOVSD %XMM14,0x28(%RAX,%RDX,8) |
(328) 0x43317 VMOVSD 0x30(%RSI,%RDX,8),%XMM0 |
(328) 0x4331d VFMADD132SD (%RCX),%XMM4,%XMM0 |
(328) 0x43322 VMOVSD %XMM0,0x30(%RAX,%RDX,8) |
(328) 0x43328 VMOVSD 0x38(%RSI,%RDX,8),%XMM2 |
(328) 0x4332e VFMADD132SD (%RCX),%XMM1,%XMM2 |
(328) 0x43333 VMOVSD %XMM2,0x38(%RAX,%RDX,8) |
(328) 0x43339 ADD $0x8,%RDX |
(328) 0x4333d CMP %RDX,%R12 |
(328) 0x43340 JNE 43284 |
(326) 0x43346 JMP 4312d |
0x4334b NOPL (%RAX,%RAX,1) |
(326) 0x43350 VMOVSD (%RCX),%XMM0 |
(326) 0x43354 VMOVSD (%RAX),%XMM4 |
(326) 0x43358 LEA 0x8(%RCX),%R9 |
(326) 0x4335c VFMADD132SD (%RSI),%XMM4,%XMM0 |
(326) 0x43361 VMOVSD %XMM0,(%RAX) |
(326) 0x43365 JMP 4312d |
(326) 0x4336a MOVQ $0,0xb0(%RSP) |
(326) 0x43376 MOV %R12,%RDX |
(326) 0x43379 XOR %R8D,%R8D |
(326) 0x4337c JMP 430ce |
(326) 0x43381 MOV 0x98(%RSP),%RDX |
(326) 0x43389 JMP 4310b |
(327) 0x4338e INCQ 0x10(%RSP) |
(327) 0x43393 MOV 0x8(%RSP),%RDI |
(327) 0x43398 XOR %R8D,%R8D |
(327) 0x4339b MOV 0x10(%RSP),%R10 |
(327) 0x433a0 ADD %RDI,%R10 |
(327) 0x433a3 MOV %R10,0x28(%RSP) |
(327) 0x433a8 JMP 4317c |
0x433ad INC %RCX |
0x433b0 XOR %EDX,%EDX |
0x433b2 JMP 42d27 |
0x433b7 NOPW (%RAX,%RAX,1) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○97.82 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
○2.18 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Source file and lines | Collapse.hpp:81-81 |
Module | libkripke.so |
nb instructions | 112 |
nb uops | 123 |
loop length | 500 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 23 |
micro-operation queue | 20.50 cycles |
front end | 20.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 9.00 | 10.67 | 10.67 | 15.00 | 6.00 | 5.90 | 15.00 | 15.00 | 15.00 | 6.00 | 10.67 |
cycles | 6.10 | 12.27 | 10.67 | 10.67 | 15.00 | 6.00 | 5.90 | 15.00 | 15.00 | 15.00 | 6.00 | 10.67 |
Cycles executing div or sqrt instructions | 20.00 |
Front-end | 20.50 |
Dispatch | 15.00 |
DIV/SQRT | 20.00 |
Overall L1 | 20.50 |
all | 1% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 8% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput | Vectorization |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
AND $-0x20,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
SUB $0xe0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
MOV 0x10(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
MOV (%RAX),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
MOV 0x110(%RAX),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
MOV 0x10(%RAX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
MOV 0x18(%RAX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
MOV 0x20(%RAX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
MOV 0x38(%RAX),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
MOV %RBX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV 0x60(%RAX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
MOV 0x68(%RAX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
MOV %R13,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV 0xc0(%RAX),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
MOV 0xf0(%RAX),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
MOV %RDX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV 0x118(%RAX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
MOV 0x30(%RAX),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
MOV %RCX,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV 0xa8(%RAX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
MOV %RSI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV %R8,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV %R9,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV %R10,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV %R11,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV %R12,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV %R15,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV 0x158(%RAX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
MOV (%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
MOV 0x8(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
TEST %R13,%R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 | scal (12.5%) |
JLE 43187 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x547> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV %RAX,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
TEST %RAX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 | scal (12.5%) |
JLE 43187 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x547> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
CALL 9760 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | N/A |
MOVSXD %EAX,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 | N/A |
CALL 9650 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | N/A |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
MOVSXD %EAX,%RDI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 | N/A |
MOV 0x78(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
IMUL %R13,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
DIV %R12 | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 | scal (12.5%) |
MOV %RAX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
CMP %RDX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (12.5%) |
JB 433ad <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x76d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
IMUL %RCX,%RDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
LEA (%RDI,%RDX,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
LEA (%RCX,%RAX,1),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
CMP %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (12.5%) |
JAE 43187 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x547> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
MOV 0x60(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
MOV 0x70(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
DIVQ 0x78(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 10 | scal (12.5%) |
SUB %RBX,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
MOV %RAX,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV %RDX,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
CMP %R9,0x68(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | scal (12.5%) |
JLE 43187 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x547> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 | scal (12.5%) |
JLE 43187 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x547> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV 0xd0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
LEA -0x1(%RCX),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
MOV 0x10(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
MOV %R12,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
MOV 0x8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
MOV %R10,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
SHR $0x2,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 | N/A |
MOV %R12,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
IMUL %R11,%R9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (12.5%) |
MOV %R12,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
LEA (,%R11,8),%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
SAL $0x5,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 | N/A |
LEA -0x1(%R12),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
AND $-0x4,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (12.5%) |
AND $0x3,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (6.3%) |
MOV %R13,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
XOR %R11D,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
MOV %R9,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV %R12,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
AND $0x3,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (6.3%) |
MOV %RDI,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV %RCX,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV %RAX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV %RSI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV %R9,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV %R10,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | vect (25.0%) |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 | N/A |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 | N/A |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 | N/A |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 | N/A |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 | N/A |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 | N/A |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 | N/A |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
INC %RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
JMP 42d27 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0xe7> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 | N/A |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
Source file and lines | Collapse.hpp:81-81 |
Module | libkripke.so |
nb instructions | 112 |
nb uops | 123 |
loop length | 500 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 23 |
micro-operation queue | 20.50 cycles |
front end | 20.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.10 | 9.00 | 10.67 | 10.67 | 15.00 | 6.00 | 5.90 | 15.00 | 15.00 | 15.00 | 6.00 | 10.67 |
cycles | 6.10 | 12.27 | 10.67 | 10.67 | 15.00 | 6.00 | 5.90 | 15.00 | 15.00 | 15.00 | 6.00 | 10.67 |
Cycles executing div or sqrt instructions | 20.00 |
Front-end | 20.50 |
Dispatch | 15.00 |
DIV/SQRT | 20.00 |
Overall L1 | 20.50 |
all | 1% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 8% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput | Vectorization |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 | N/A |
AND $-0x20,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
SUB $0xe0,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
MOV 0x10(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
MOV (%RAX),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
MOV 0x110(%RAX),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
MOV 0x10(%RAX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
MOV 0x18(%RAX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
MOV 0x20(%RAX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
MOV 0x38(%RAX),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
MOV %RBX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV 0x60(%RAX),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
MOV 0x68(%RAX),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
MOV %R13,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV 0xc0(%RAX),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
MOV 0xf0(%RAX),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
MOV %RDX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV 0x118(%RAX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
MOV 0x30(%RAX),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
MOV %RCX,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV 0xa8(%RAX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
MOV %RSI,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV %R8,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV %R9,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV %R10,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV %R11,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV %R12,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV %R15,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV 0x158(%RAX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
MOV (%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
MOV 0x8(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
TEST %R13,%R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 | scal (12.5%) |
JLE 43187 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x547> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV %RAX,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
TEST %RAX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 | scal (12.5%) |
JLE 43187 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x547> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
CALL 9760 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | N/A |
MOVSXD %EAX,%R12 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 | N/A |
CALL 9650 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | N/A |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
MOVSXD %EAX,%RDI | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 | N/A |
MOV 0x78(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
IMUL %R13,%RAX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
DIV %R12 | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 | scal (12.5%) |
MOV %RAX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
CMP %RDX,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (12.5%) |
JB 433ad <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x76d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
IMUL %RCX,%RDI | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | N/A |
LEA (%RDI,%RDX,1),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
LEA (%RCX,%RAX,1),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
CMP %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (12.5%) |
JAE 43187 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x547> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
MOV 0x60(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
MOV 0x70(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
DIVQ 0x78(%RSP) | 5 | 0 | 3 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 11-16 | 10 | scal (12.5%) |
SUB %RBX,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
MOV %RAX,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV %RDX,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
CMP %R9,0x68(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | scal (12.5%) |
JLE 43187 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x547> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 | scal (12.5%) |
JLE 43187 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0x547> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
MOV 0xd0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
LEA -0x1(%RCX),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
MOV 0x10(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
MOV %R12,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
MOV 0x8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
MOV %R10,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
SHR $0x2,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 | N/A |
MOV %R12,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
IMUL %R11,%R9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (12.5%) |
MOV %R12,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
LEA (,%R11,8),%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
SAL $0x5,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 | N/A |
LEA -0x1(%R12),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
AND $-0x4,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
ADD %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (12.5%) |
AND $0x3,%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (6.3%) |
MOV %R13,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
XOR %R11D,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
MOV %R9,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV %R12,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
AND $0x3,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (6.3%) |
MOV %RDI,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV %RCX,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV %RAX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV %RSI,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV %R9,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
MOV %R10,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | vect (25.0%) |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 | N/A |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 | N/A |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 | N/A |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 | N/A |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 | N/A |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 | N/A |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 | N/A |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
INC %RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
JMP 42d27 <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl2EEEEJNS2_3ForILl1ENS_6policy4loop9loop_execEJNS8_ILl3ESB_JNS2_6LambdaILl0EJEEEEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSG_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSS_EESS_EENSO_INSQ_INSR_6MomentElPSW_EESW_EENSO_INSQ_INSR_5GroupElPS10_EES10_EENSO_INSQ_INSR_4ZoneElPS14_EES14_EEEEENSM_IJEEEJZNK14LPlusTimesSdomclINSR_11ArchLayoutTINSR_12ArchT_OpenMPENSR_11LayoutT_DGZEEEEEvT_NSR_6SdomIdERKNSR_4Core3SetES1L_S1L_S1L_RNS1I_5FieldIdJSW_S10_S14_EEERNS1M_IdJSS_S10_S14_EEERNS1M_IdJSS_SW_EEEEUlSS_SW_S10_S14_E_EEEEEvOS1G_._omp_fn.0+0xe7> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 | N/A |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
Name | Coverage (%) | Time (s) |
---|---|---|
▼void RAJA::internal::StatementExecutor | 3.26 | 1.89 |
▼Loop 327 - RangeSegment.hpp:120-120 - libkripke.so– | 0.00 | 0.00 |
▼Loop 326 - forall.hpp:59-59 - libkripke.so– | 0.00 | 0.00 |
○Loop 329 - forall.hpp:59-59 - libkripke.so | 3.25 | 1.50 |
○Loop 328 - forall.hpp:59-59 - libkripke.so | 0.00 | 0.00 |