Loop Id: 428 | Module: libkripke.so | Source: forall.hpp:59-59 [...] | Coverage: 0.15% |
---|
Loop Id: 428 | Module: libkripke.so | Source: forall.hpp:59-59 [...] | Coverage: 0.15% |
---|
0x4f0eb VMOVUPD (%RSI,%RAX,1),%YMM13 [1] |
0x4f0f0 VMOVUPD 0x20(%RSI,%RAX,1),%YMM4 [1] |
0x4f0f6 VMOVUPD 0x40(%RSI,%RAX,1),%YMM7 [1] |
0x4f0fc VMULPD (%R9,%RAX,1),%YMM13,%YMM14 [2] |
0x4f102 VMULPD 0x20(%R9,%RAX,1),%YMM4,%YMM5 [2] |
0x4f109 VMULPD 0x40(%R9,%RAX,1),%YMM7,%YMM10 [2] |
0x4f110 VMULPD %YMM9,%YMM14,%YMM15 |
0x4f115 VMULPD %YMM9,%YMM5,%YMM6 |
0x4f11a VMULPD %YMM9,%YMM10,%YMM11 |
0x4f11f VADDPD %YMM15,%YMM0,%YMM3 |
0x4f124 VMOVUPD 0x60(%RSI,%RAX,1),%YMM0 [1] |
0x4f12a VMULPD 0x60(%R9,%RAX,1),%YMM0,%YMM13 [2] |
0x4f131 VADDPD %YMM6,%YMM3,%YMM1 |
0x4f135 VMOVUPD 0x80(%RSI,%RAX,1),%YMM3 [1] |
0x4f13e VMULPD 0x80(%R9,%RAX,1),%YMM3,%YMM4 [2] |
0x4f148 VADDPD %YMM11,%YMM1,%YMM12 |
0x4f14d VMOVUPD 0xa0(%RSI,%RAX,1),%YMM1 [1] |
0x4f156 VMULPD %YMM9,%YMM13,%YMM14 |
0x4f15b VMULPD 0xa0(%R9,%RAX,1),%YMM1,%YMM7 [2] |
0x4f165 VMULPD %YMM9,%YMM4,%YMM5 |
0x4f16a VADDPD %YMM14,%YMM12,%YMM15 |
0x4f16f VMOVUPD 0xc0(%RSI,%RAX,1),%YMM12 [1] |
0x4f178 VMULPD %YMM9,%YMM7,%YMM10 |
0x4f17d VMULPD 0xc0(%R9,%RAX,1),%YMM12,%YMM0 [2] |
0x4f187 VADDPD %YMM5,%YMM15,%YMM6 |
0x4f18b VMOVUPD 0xe0(%RSI,%RAX,1),%YMM15 [1] |
0x4f194 VMULPD 0xe0(%R9,%RAX,1),%YMM15,%YMM3 [2] |
0x4f19e ADD $0x100,%RAX |
0x4f1a4 VADDPD %YMM10,%YMM6,%YMM11 |
0x4f1a9 VMULPD %YMM9,%YMM0,%YMM13 |
0x4f1ae VMULPD %YMM9,%YMM3,%YMM4 |
0x4f1b3 VADDPD %YMM13,%YMM11,%YMM14 |
0x4f1b8 VADDPD %YMM4,%YMM14,%YMM0 |
0x4f1bc CMP %RAX,%R14 |
0x4f1bf JNE 4f0eb |
/home/eoseret/qaas_runs_CPU_9468/171-147-9160/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp: 307 - 307 |
-------------------------------------------------------------------------------- |
307: return Ret{lhs} + rhs; |
/home/eoseret/qaas_runs_CPU_9468/171-147-9160/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59 |
-------------------------------------------------------------------------------- |
59: for (decltype(distance_it) i = 0; i < distance_it; ++i) { |
/home/eoseret/qaas_runs_CPU_9468/171-147-9160/intel/Kripke/build/Kripke/src/Kripke/Kernel/Population.cpp: 58 - 58 |
-------------------------------------------------------------------------------- |
58: part_red += w(d) * psi(d,g,z) * volume(z); |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○98.17 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
○1.83 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.49 |
CQA speedup if fully vectorized | 2.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 2.00 |
Bottlenecks | |
Function | void RAJA::internal::StatementExecutor |
Source | Operators.hpp:307-307,forall.hpp:59-59,Population.cpp:58-58 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 24.00 |
CQA cycles if no scalar integer | 24.00 |
CQA cycles if FP arith vectorized | 16.11 |
CQA cycles if fully vectorized | 12.00 |
Front-end cycles | 7.00 |
DIV/SQRT cycles | 8.00 |
P0 cycles | 12.00 |
P1 cycles | 5.33 |
P2 cycles | 5.33 |
P3 cycles | 0.00 |
P4 cycles | 8.00 |
P5 cycles | 1.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 1.00 |
P10 cycles | 5.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 24 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 35.00 |
Nb uops | 34.00 |
Nb loads | 16.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 4.00 |
Nb FLOP add-sub | 32.00 |
Nb FLOP mul | 64.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 21.33 |
Bytes prefetched | 0.00 |
Bytes loaded | 512.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 2.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 50.00 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | 50.00 |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.49 |
CQA speedup if fully vectorized | 2.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 2.00 |
Bottlenecks | |
Function | void RAJA::internal::StatementExecutor |
Source | Operators.hpp:307-307,forall.hpp:59-59,Population.cpp:58-58 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 24.00 |
CQA cycles if no scalar integer | 24.00 |
CQA cycles if FP arith vectorized | 16.11 |
CQA cycles if fully vectorized | 12.00 |
Front-end cycles | 7.00 |
DIV/SQRT cycles | 8.00 |
P0 cycles | 12.00 |
P1 cycles | 5.33 |
P2 cycles | 5.33 |
P3 cycles | 0.00 |
P4 cycles | 8.00 |
P5 cycles | 1.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 1.00 |
P10 cycles | 5.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 24 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 35.00 |
Nb uops | 34.00 |
Nb loads | 16.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 4.00 |
Nb FLOP add-sub | 32.00 |
Nb FLOP mul | 64.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 21.33 |
Bytes prefetched | 0.00 |
Bytes loaded | 512.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 2.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 50.00 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | 50.00 |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Path / |
nb instructions | 35 |
nb uops | 34 |
loop length | 218 |
used x86 registers | 4 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 14 |
used zmm registers | 0 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 0.50 |
micro-operation queue | 7.00 cycles |
front end | 7.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 8.00 | 8.00 | 5.33 | 5.33 | 0.00 | 8.00 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 5.33 |
cycles | 8.00 | 12.00 | 5.33 | 5.33 | 0.00 | 8.00 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 5.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 24.00 |
Front-end | 7.00 |
Dispatch | 12.00 |
Data deps. | 24.00 |
Overall L1 | 24.00 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput | Vectorization |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%RSI,%RAX,1),%YMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
VMOVUPD 0x20(%RSI,%RAX,1),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
VMOVUPD 0x40(%RSI,%RAX,1),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
VMULPD (%R9,%RAX,1),%YMM13,%YMM14 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
VMULPD 0x20(%R9,%RAX,1),%YMM4,%YMM5 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
VMULPD 0x40(%R9,%RAX,1),%YMM7,%YMM10 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
VMULPD %YMM9,%YMM14,%YMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
VMULPD %YMM9,%YMM5,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
VMULPD %YMM9,%YMM10,%YMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
VADDPD %YMM15,%YMM0,%YMM3 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
VMOVUPD 0x60(%RSI,%RAX,1),%YMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
VMULPD 0x60(%R9,%RAX,1),%YMM0,%YMM13 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
VADDPD %YMM6,%YMM3,%YMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
VMOVUPD 0x80(%RSI,%RAX,1),%YMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
VMULPD 0x80(%R9,%RAX,1),%YMM3,%YMM4 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
VADDPD %YMM11,%YMM1,%YMM12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
VMOVUPD 0xa0(%RSI,%RAX,1),%YMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
VMULPD %YMM9,%YMM13,%YMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
VMULPD 0xa0(%R9,%RAX,1),%YMM1,%YMM7 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
VMULPD %YMM9,%YMM4,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
VADDPD %YMM14,%YMM12,%YMM15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
VMOVUPD 0xc0(%RSI,%RAX,1),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
VMULPD %YMM9,%YMM7,%YMM10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
VMULPD 0xc0(%R9,%RAX,1),%YMM12,%YMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
VADDPD %YMM5,%YMM15,%YMM6 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
VMOVUPD 0xe0(%RSI,%RAX,1),%YMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
VMULPD 0xe0(%R9,%RAX,1),%YMM15,%YMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
ADD $0x100,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
VADDPD %YMM10,%YMM6,%YMM11 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
VMULPD %YMM9,%YMM0,%YMM13 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
VMULPD %YMM9,%YMM3,%YMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
VADDPD %YMM13,%YMM11,%YMM14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
VADDPD %YMM4,%YMM14,%YMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
CMP %RAX,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
JNE 4f0eb <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS2_6LambdaILl0EJEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSF_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSR_EESR_EENSN_INSP_INSQ_5GroupElPSV_EESV_EENSN_INSP_INSQ_4ZoneElPSZ_EESZ_EEEEENSL_IJEEEJZNK14PopulationSdomclINSQ_11ArchLayoutTINSQ_12ArchT_OpenMPENSQ_11LayoutT_DGZEEEEEvT_NSQ_6SdomIdERKNSQ_4Core3SetES1G_S1G_RNS1D_5FieldIdJSR_SV_SZ_EEERNS1H_IdJSR_EEERNS1H_IdJSZ_EEEPdEUlSR_SV_SZ_E_EEEEEvOS1B_._omp_fn.0+0x27b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
nb instructions | 35 |
nb uops | 34 |
loop length | 218 |
used x86 registers | 4 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 14 |
used zmm registers | 0 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 0.50 |
micro-operation queue | 7.00 cycles |
front end | 7.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 8.00 | 8.00 | 5.33 | 5.33 | 0.00 | 8.00 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 5.33 |
cycles | 8.00 | 12.00 | 5.33 | 5.33 | 0.00 | 8.00 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 5.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 24.00 |
Front-end | 7.00 |
Dispatch | 12.00 |
Data deps. | 24.00 |
Overall L1 | 24.00 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput | Vectorization |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%RSI,%RAX,1),%YMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
VMOVUPD 0x20(%RSI,%RAX,1),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
VMOVUPD 0x40(%RSI,%RAX,1),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
VMULPD (%R9,%RAX,1),%YMM13,%YMM14 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
VMULPD 0x20(%R9,%RAX,1),%YMM4,%YMM5 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
VMULPD 0x40(%R9,%RAX,1),%YMM7,%YMM10 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
VMULPD %YMM9,%YMM14,%YMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
VMULPD %YMM9,%YMM5,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
VMULPD %YMM9,%YMM10,%YMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
VADDPD %YMM15,%YMM0,%YMM3 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
VMOVUPD 0x60(%RSI,%RAX,1),%YMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
VMULPD 0x60(%R9,%RAX,1),%YMM0,%YMM13 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
VADDPD %YMM6,%YMM3,%YMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
VMOVUPD 0x80(%RSI,%RAX,1),%YMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
VMULPD 0x80(%R9,%RAX,1),%YMM3,%YMM4 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
VADDPD %YMM11,%YMM1,%YMM12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
VMOVUPD 0xa0(%RSI,%RAX,1),%YMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
VMULPD %YMM9,%YMM13,%YMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
VMULPD 0xa0(%R9,%RAX,1),%YMM1,%YMM7 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
VMULPD %YMM9,%YMM4,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
VADDPD %YMM14,%YMM12,%YMM15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
VMOVUPD 0xc0(%RSI,%RAX,1),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
VMULPD %YMM9,%YMM7,%YMM10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
VMULPD 0xc0(%R9,%RAX,1),%YMM12,%YMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
VADDPD %YMM5,%YMM15,%YMM6 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
VMOVUPD 0xe0(%RSI,%RAX,1),%YMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
VMULPD 0xe0(%R9,%RAX,1),%YMM15,%YMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | vect (50.0%) |
ADD $0x100,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
VADDPD %YMM10,%YMM6,%YMM11 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
VMULPD %YMM9,%YMM0,%YMM13 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
VMULPD %YMM9,%YMM3,%YMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
VADDPD %YMM13,%YMM11,%YMM14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
VADDPD %YMM4,%YMM14,%YMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (50.0%) |
CMP %RAX,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
JNE 4f0eb <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS2_6LambdaILl0EJEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSF_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSR_EESR_EENSN_INSP_INSQ_5GroupElPSV_EESV_EENSN_INSP_INSQ_4ZoneElPSZ_EESZ_EEEEENSL_IJEEEJZNK14PopulationSdomclINSQ_11ArchLayoutTINSQ_12ArchT_OpenMPENSQ_11LayoutT_DGZEEEEEvT_NSQ_6SdomIdERKNSQ_4Core3SetES1G_S1G_RNS1D_5FieldIdJSR_SV_SZ_EEERNS1H_IdJSR_EEERNS1H_IdJSZ_EEEPdEUlSR_SV_SZ_E_EEEEEvOS1B_._omp_fn.0+0x27b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |