OV - exec - Function hypre_BoomerAMGCoarsenPMIS.omp

	Function: hypre_BoomerAMGCoarsenPMIS.omp_outlined.18	Module: exec	Source: par_coarsen.c:2354-2381	Coverage (incl. loops): 0.66% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2354 - 2381

--------------------------------------------------------------------------------

2354: #pragma omp parallel for private(ig, i, jS, j, jj) HYPRE_SMP_SCHEDULE

2355: #endif

2356:         for (ig = 0; ig < graph_size; ig++)

2357:         {

2358:            i = graph_array[ig];

2359:            if (measure_array[i] > 1)

2360:            {

2361:               for (jS = S_diag_i[i]; jS < S_diag_i[i+1]; jS++)

2362:               {

2363:                  j = S_diag_j[jS];

2364:                  if (measure_array[j] > 1)

2365:                  {

2366:                     if (measure_array[i] > measure_array[j])

2367:                        CF_marker[j] = 0;

2368:                     else if (measure_array[j] > measure_array[i])

2369:                        CF_marker[i] = 0;

2370:                  }

2371:               } /* for each local neighbor j of i */

2372:               for (jS = S_offd_i[i]; jS < S_offd_i[i+1]; jS++)

2373:               {

2374:                  jj = S_offd_j[jS];

2375:                  j = num_variables+jj;

2376:                  if (measure_array[j] > 1)

2377:                  {

2378:                     if (measure_array[i] > measure_array[j])

2379:                        CF_marker_offd[jj] = 0;

2380:                     else if (measure_array[j] > measure_array[i])

2381:                        CF_marker[i] = 0;

0x422320 SUB	SP, SP, #112

0x422324 STP	X29, X30, [SP, #32]

0x422328 STR	X25, [SP, #48]

0x42232c STP	X24, X23, [SP, #64]

0x422330 STP	X22, X21, [SP, #80]

0x422334 STP	X20, X19, [SP, #96]

0x422338 ADD	X29, SP, #32

0x42233c LDR	X8, [X2]

0x422340 SUBS	X25, X8, #1

0x422344 B.LT	4223cc

0x422348 LDR	W20, [X0]

0x42234c ORR	X19, XZR, X7

0x422350 ORR	X21, XZR, X6

0x422354 ORR	X22, XZR, X5

0x422358 ORR	X23, XZR, X4

0x42235c ORR	X24, XZR, X3

0x422360 MOVZ	W8, #1

0x422364 ADRP	X0,

0x422368 ADD	X0, X0, #1064

0x42236c ADD	X3, SP, #12

0x422370 ADD	X4, X29, #24

0x422374 SUB	X5, X29, #8

0x422378 ADD	X6, SP, #16

0x42237c MOVZ	W2, #34

0x422380 STR	XZR, [X29, #24]

0x422384 MOVZ	W7, #1

0x422388 STUR	X25, [X29, #504]

0x42238c STR	X8, [SP, #16]

0x422390 STR	WZR, [SP, #12]

0x422394 ORR	W1, WZR, W20

0x422398 STR	X8, [SP]

0x42239c BL	4103d0

0x4223a0 LDUR	X8, [X29, #504]

0x4223a4 CMP	X8, X25

0x4223a8 CSEL	X9, X8, X25, #11

0x4223ac LDR	X8, [X29, #24]

0x4223b0 STUR	X9, [X29, #504]

0x4223b4 CMP	X8, X9

0x4223b8 B.LE	4223e8

0x4223bc ADRP	X0,

0x4223c0 ADD	X0, X0, #1088

0x4223c4 ORR	W1, WZR, W20

0x4223c8 BL	410150

0x4223cc LDP	X20, X19, [SP, #96]

0x4223d0 LDP	X22, X21, [SP, #80]

0x4223d4 LDR	X25, [SP, #48]

0x4223d8 LDP	X24, X23, [SP, #64]

0x4223dc LDP	X29, X30, [SP, #32]

0x4223e0 ADD	SP, SP, #112

0x4223e4 RET

0x4223e8 LDP	X15, X16, [X29, #80]

0x4223ec LDP	X10, X9, [X29, #96]

0x4223f0 FMOV	D0, #1.0000000

0x4223f4 LDR	X11, [X24]

0x4223f8 LDR	X12, [X23]

0x4223fc LDR	X13, [X22]

0x422400 LDR	X14, [X21]

0x422404 LDR	X15, [X15]

0x422408 LDR	X16, [X16]

0x42240c B	422430

0x422410 HINT	#0

0x422414 HINT	#0

0x422418 HINT	#0

0x42241c HINT	#0

    (245) 0x422420 LDUR	X17, [X29, #504]

    (245) 0x422424 CMP	X8, X17

    (245) 0x422428 ADD	X8, X8, #1

    (245) 0x42242c B.GE	4223bc

    (245) 0x422430 LDR	X17, [X11, X8,LSL #3]

    (245) 0x422434 LDR	D1, [X12, X17,LSL #3]

    (245) 0x422438 FCMP	D1, D0

    (245) 0x42243c B.LE	422420

    (245) 0x422440 ADD	X18, X17, #1

    (245) 0x422444 LDR	X0, [X13, X17,LSL #3]

    (245) 0x422448 LDR	X1, [X13, X18,LSL #3]

    (245) 0x42244c CMP	X0, X1

    (245) 0x422450 B.GE	4224a0

    (245) 0x422454 LDR	X1, [X19]

    (245) 0x422458 B	422474

0x42245c HINT	#0

      (248) 0x422460 STR	XZR, [X1, X2,LSL #3]

      (248) 0x422464 LDR	X2, [X13, X18,LSL #3]

      (248) 0x422468 ADD	X0, X0, #1

      (248) 0x42246c CMP	X0, X2

      (248) 0x422470 B.GE	4224a0

      (248) 0x422474 LDR	X2, [X14, X0,LSL #3]

      (248) 0x422478 LDR	D2, [X12, X2,LSL #3]

      (248) 0x42247c FCMP	D2, D0

      (248) 0x422480 B.LE	422464

      (248) 0x422484 FCMP	D1, D2

      (248) 0x422488 B.GT	422460

      (248) 0x42248c FCMP	D2, D1

      (248) 0x422490 B.LE	422464

      (248) 0x422494 STR	XZR, [X1, X17,LSL #3]

      (248) 0x422498 B	422464

0x42249c HINT	#0

    (245) 0x4224a0 LDR	X0, [X15, X17,LSL #3]

    (245) 0x4224a4 LDR	X1, [X15, X18,LSL #3]

    (245) 0x4224a8 CMP	X0, X1

    (245) 0x4224ac B.GE	422420

  (246) 0x4224b0 LDR	X1, [X19]

  (246) 0x4224b4 LDR	X2, [X9]

  (246) 0x4224b8 B	4224d4

0x4224bc HINT	#0

(247) 0x4224c0 STR	XZR, [X2, X3,LSL #3]

  (246) 0x4224c4 LDR	X3, [X15, X18,LSL #3]

  (246) 0x4224c8 ADD	X0, X0, #1

  (246) 0x4224cc CMP	X0, X3

  (246) 0x4224d0 B.GE	422420

  (246) 0x4224d4 LDR	X4, [X10]

  (246) 0x4224d8 LDR	X3, [X16, X0,LSL #3]

  (246) 0x4224dc ADD	X4, X12, X4,LSL #3

  (246) 0x4224e0 LDR	D2, [X4, X3,LSL #3]

  (246) 0x4224e4 FCMP	D2, D0

  (246) 0x4224e8 B.LE	4224c4

  (246) 0x4224ec FCMP	D1, D2

  (246) 0x4224f0 B.GT	4224c0

  (246) 0x4224f4 FCMP	D2, D1

  (246) 0x4224f8 B.LE	4224c4

  (246) 0x4224fc STR	XZR, [X1, X17,LSL #3]

  (246) 0x422500 B	4224c4

0x422504 HINT	#0

0x422508 HINT	#0

0x42250c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.75+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.21+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_BoomerAMGCoarsenPMIS	par_coarsen.c:2393	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:598	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_coarsen.c:2354-2381
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354-2381.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 27% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 9.50 to 2.52 cycles (3.77x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes. The binary function is storing 3 bytes.

General properties

nb instructions	70
nb uops	60
loop length	280
used w registers	6
used x registers	26
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	0
used z registers	0
nb stack references	13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.50 cycles
front end	7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	6.75	6.75	6.75	6.75	0.25	0.25	0.25	0.25	9.50	9.17	9.33	5.50	5.50
cycles	3.00	3.00	6.75	6.75	6.75	6.75	0.25	0.25	0.25	0.25	9.50	9.17	9.33	5.50	5.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.50
Dispatch	9.50
Overall L1	9.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	27%
load	28%
store	32%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	27%
load	28%
store	32%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.50 cycles. At this rate:

0% of peak load performance is reached (0.32 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.32 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 422320

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X25, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X24, X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUBS X25, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4223cc <hypre_BoomerAMGCoarsenPMIS.omp_outlined.18+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR X19, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X21, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X23, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <4eb364>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1064	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, SP, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STUR X25, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4103d0 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X9, X8, X25, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STUR X9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4223e8 <hypre_BoomerAMGCoarsenPMIS.omp_outlined.18+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4eb3bc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1088	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410150 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X25, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X24, X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X15, X16, [X29, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X9, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
FMOV D0, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X11, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X14, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 422430 <hypre_BoomerAMGCoarsenPMIS.omp_outlined.18+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_coarsen.c:2354-2381
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354-2381.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes. The binary function is storing 3 bytes.

General properties

nb instructions	70
nb uops	60
loop length	280
used w registers	6
used x registers	26
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	0
used z registers	0
nb stack references	13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.50 cycles
front end	7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	6.75	6.75	6.75	6.75	0.25	0.25	0.25	0.25	9.50	9.17	9.33	5.50	5.50
cycles	3.00	3.00	6.75	6.75	6.75	6.75	0.25	0.25	0.25	0.25	9.50	9.17	9.33	5.50	5.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.50
Dispatch	9.50
Overall L1	9.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	27%
load	28%
store	32%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	27%
load	28%
store	32%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.50 cycles. At this rate:

0% of peak load performance is reached (0.32 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.32 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 422320

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X25, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X24, X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUBS X25, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4223cc <hypre_BoomerAMGCoarsenPMIS.omp_outlined.18+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR X19, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X21, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X23, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <4eb364>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1064	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, SP, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STUR X25, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4103d0 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X9, X8, X25, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STUR X9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4223e8 <hypre_BoomerAMGCoarsenPMIS.omp_outlined.18+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4eb3bc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1088	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410150 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X25, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X24, X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X15, X16, [X29, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X9, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
FMOV D0, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X11, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X14, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 422430 <hypre_BoomerAMGCoarsenPMIS.omp_outlined.18+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCoarsenPMIS.omp_outlined.18–	0.66	0.31
▼Loop 247 - par_coarsen.c:2356-2381 - exec–	0.00	0.00
▼Loop 246 - par_coarsen.c:2356-2381 - exec–	0.00	0.00
▼Loop 245 - par_coarsen.c:2356-2372 - exec–	0.04	0.01
○Loop 248 - par_coarsen.c:2361-2369 - exec	0.62	0.21

Report Configuration

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code