OV - exec - Function hypre_BoomerAMGBuildMultipass.omp

	Function: hypre_BoomerAMGBuildMultipass.omp_outlined.9	Module: exec	Source: par_multi_interp.c:891-1134 [...]	Coverage (incl. loops): 1.00% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 891 - 1134

--------------------------------------------------------------------------------

891:       #pragma omp parallel private(i,my_thread_num,num_threads,thread_start,thread_stop,cnt_nz,cnt_nz_offd,i1,j,j1,j_start,j_end,k1,k,P_marker,P_marker_offd)

[...]

900:           my_thread_num = hypre_GetThreadNum();

901:           num_threads = hypre_NumActiveThreads();

902:           thread_start = (pass_length/num_threads)*my_thread_num;

903:           if (my_thread_num == num_threads-1)

904:           {  thread_stop = pass_length; }

905:           else

906:           {  thread_stop = (pass_length/num_threads)*(my_thread_num+1); }

907:           thread_start += pass_pointer[pass];

[...]

916:           P_marker = hypre_CTAlloc(HYPRE_Int, n_coarse); /* marks points to see if they're counted */

917:           for (i=0; i < n_coarse; i++)

918:           {   P_marker[i] = -1; }

919:           if (new_num_cols_offd == local_index+1)

920:           {

921:              P_marker_offd = hypre_CTAlloc(HYPRE_Int,new_num_cols_offd);

922:              for (i=0; i < new_num_cols_offd; i++)

923:              {   P_marker_offd[i] = -1; }

924:           }

925:           else if (n_coarse_offd)

926:           {

927:              P_marker_offd = hypre_CTAlloc(HYPRE_Int, n_coarse_offd);

928:              for (i=0; i < n_coarse_offd; i++)

929:              {   P_marker_offd[i] = -1; }

[...]

939:           for (i=thread_start; i < thread_stop; i++)

940:           {

941:              i1 = pass_array[i];

942:              P_diag_start[i1] = cnt_nz;

943:              P_offd_start[i1] = cnt_nz_offd;

944:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

945:              {

946:                 j1 = S_diag_j[j];

947:                 if (assigned[j1] == pass-1)

948:                 {

949:                    j_start = P_diag_start[j1];

950:                    j_end = j_start+P_diag_i[j1+1];

951:                    for (k=j_start; k < j_end; k++)

952:                    {

953:                       k1 = P_diag_pass[pass-1][k];

954:                       if (P_marker[k1] != i1)

955:                       {

956:                          cnt_nz++;

957:                          P_diag_i[i1+1]++;

958:                          P_marker[k1] = i1;

959:                       }

960:                    }

961:                    j_start = P_offd_start[j1];

962:                    j_end = j_start+P_offd_i[j1+1];

963:                    for (k=j_start; k < j_end; k++)

964:                    {

965:                       k1 = P_offd_pass[pass-1][k];

966:                       if (P_marker_offd[k1] != i1)

967:                       {

968:                          cnt_nz_offd++;

969:                          P_offd_i[i1+1]++;

970:                          P_marker_offd[k1] = i1;

[...]

976:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

977:              {

978:                 j1 = S_offd_j[j];

979:                 if (assigned_offd[j1] == pass-1)

980:                 {

981:                    j_start = Pext_start[j1];

982:                    j_end = j_start+Pext_i[j1+1];

983:                    for (k=j_start; k < j_end; k++)

984:                    {

985:                       k1 = Pext_pass[pass][k];

986:                       if (k1 < 0)

987:                       {

988:                          if (P_marker[-k1-1] != i1)

989:                          {

990:                             cnt_nz++;

991:                             P_diag_i[i1+1]++;

992:                             P_marker[-k1-1] = i1;

993:                          }

994:                       }

995:                       else if (P_marker_offd[k1] != i1)

996:                       {

997:                          cnt_nz_offd++;

998:                          P_offd_i[i1+1]++;

999:                          P_marker_offd[k1] = i1;

[...]

1008:           if(my_thread_num == 0)

1009:           {   max_num_threads[0] = num_threads; }

1010:           cnt_nz_offd_per_thread[my_thread_num] = cnt_nz_offd;

1011:           cnt_nz_per_thread[my_thread_num] = cnt_nz;

1012: #ifdef HYPRE_USING_OPENMP

1013: #pragma omp barrier

1014: #endif

1015:           if(my_thread_num == 0)

1016:           {

1017:               for(i = 1; i < max_num_threads[0]; i++)

1018:               {

1019:                   cnt_nz_offd_per_thread[i] += cnt_nz_offd_per_thread[i-1];

1020:                   cnt_nz_per_thread[i] += cnt_nz_per_thread[i-1];

1021:               }

1022:           }

1023: #ifdef HYPRE_USING_OPENMP

1024: #pragma omp barrier

1025: #endif

1026:           if(my_thread_num > 0)

1027:           {

1028:               /* update this thread's section of P_diag_start and P_offd_start

1029:                * with the num of nz's counted by previous threads */

1030:               for (i=thread_start; i < thread_stop; i++)

1031:                {

1032:                    i1 = pass_array[i];

1033:                    P_diag_start[i1] += cnt_nz_per_thread[my_thread_num-1];

1034:                    P_offd_start[i1] += cnt_nz_offd_per_thread[my_thread_num-1];

[...]

1040:               cnt_nz = cnt_nz_per_thread[max_num_threads[0]-1];

1041:               cnt_nz_offd = cnt_nz_offd_per_thread[max_num_threads[0]-1];

1042:

1043:               /* Updated total nz count */

1044:               total_nz += cnt_nz;

1045:               total_nz_offd += cnt_nz_offd;

1046:

1047:               /* Allocate P_diag_pass and P_offd_pass for all threads */

1048:               P_diag_pass[pass] = hypre_CTAlloc(HYPRE_Int, cnt_nz);

1049:               if (cnt_nz_offd)

1050:                  P_offd_pass[pass] = hypre_CTAlloc(HYPRE_Int, cnt_nz_offd);

1051:               else if (num_procs > 1)

1052:                  P_offd_pass[pass] = NULL;

1053:           }

1054: #ifdef HYPRE_USING_OPENMP

1055: #pragma omp barrier

1056: #endif

1057:

1058:           /* offset cnt_nz and cnt_nz_offd to point to the starting

1059:            * point in P_diag_pass and P_offd_pass for each thread */

1060:           if(my_thread_num > 0)

1061:           {

1062:               cnt_nz = cnt_nz_per_thread[my_thread_num-1];

1063:               cnt_nz_offd = cnt_nz_offd_per_thread[my_thread_num-1];

[...]

1072:           for (i=thread_start; i < thread_stop; i++)

1073:           {

1074:              i1 = pass_array[i];

1075:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1076:              {

1077:                 j1 = S_diag_j[j];

1078:                 if (assigned[j1] == pass-1)

1079:                 {

1080:                    j_start = P_diag_start[j1];

1081:                    j_end = j_start+P_diag_i[j1+1];

1082:                    for (k=j_start; k < j_end; k++)

1083:                    {

1084:                       k1 = P_diag_pass[pass-1][k];

1085:                       if (P_marker[k1] != -i1-1)

1086:                       {

1087:                           P_diag_pass[pass][cnt_nz++] = k1;

1088:                           P_marker[k1] = -i1-1;

1089:                       }

1090:                    }

1091:                    j_start = P_offd_start[j1];

1092:                    j_end = j_start+P_offd_i[j1+1];

1093:                    for (k=j_start; k < j_end; k++)

1094:                    {

1095:                       k1 = P_offd_pass[pass-1][k];

1096:                       if (P_marker_offd[k1] != -i1-1)

1097:                       {

1098:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1099:                          P_marker_offd[k1] = -i1-1;

1100:                       }

1101:                    }

1102:                 }

1103:              }

1104:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1105:              {

1106:                 j1 = S_offd_j[j];

1107:                 if (assigned_offd[j1] == pass-1)

1108:                 {

1109:                    j_start = Pext_start[j1];

1110:                    j_end = j_start+Pext_i[j1+1];

1111:                    for (k=j_start; k < j_end; k++)

1112:                    {

1113:                       k1 = Pext_pass[pass][k];

1114:                       if (k1 < 0)

1115:                       {

1116:                          if (P_marker[-k1-1] != -i1-1)

1117:                          {

1118:                             P_diag_pass[pass][cnt_nz++] = -k1-1;

1119:                             P_marker[-k1-1] = -i1-1;

1120:                          }

1121:                       }

1122:                       else if (P_marker_offd[k1] != -i1-1)

1123:                       {

1124:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1125:                          P_marker_offd[k1] = -i1-1;

[...]

1132:           hypre_TFree(P_marker);

1133:           if ( (n_coarse_offd) || (new_num_cols_offd  == local_index+1) )

1134:           {    hypre_TFree(P_marker_offd); }

0x4356a0 SUB	SP, SP, #352

0x4356a4 STP	X29, X30, [SP, #256]

0x4356a8 STP	X28, X27, [SP, #272]

0x4356ac STP	X26, X25, [SP, #288]

0x4356b0 STP	X24, X23, [SP, #304]

0x4356b4 STP	X22, X21, [SP, #320]

0x4356b8 STP	X20, X19, [SP, #336]

0x4356bc ADD	X29, SP, #256

0x4356c0 STR	X7, [SP, #112]

0x4356c4 STR	X6, [SP, #128]

0x4356c8 ORR	X23, XZR, X5

0x4356cc ORR	X21, XZR, X4

0x4356d0 ORR	X22, XZR, X3

0x4356d4 ORR	X27, XZR, X2

0x4356d8 STR	X0, [SP, #40]

0x4356dc LDR	X8, [X29, #272]

0x4356e0 STR	X8, [SP, #8]

0x4356e4 LDR	X8, [X29, #264]

0x4356e8 STR	X8, [SP, #32]

0x4356ec LDR	X8, [X29, #256]

0x4356f0 STR	X8, [SP, #24]

0x4356f4 LDP	X8, X9, [X29, #240]

0x4356f8 STP	X9, X8, [X29, #904]

0x4356fc LDR	X8, [X29, #232]

0x435700 STR	X8, [SP, #96]

0x435704 LDP	X8, X9, [X29, #216]

0x435708 STP	X8, X9, [X29, #968]

0x43570c LDP	X8, X9, [X29, #200]

0x435710 STUR	X9, [X29, #448]

0x435714 STR	X8, [SP, #48]

0x435718 LDR	X8, [X29, #192]

0x43571c STR	X8, [SP, #88]

0x435720 LDR	X8, [X29, #184]

0x435724 STR	X8, [SP, #80]

0x435728 LDP	X8, X9, [X29, #168]

0x43572c STP	X8, X9, [X29, #1000]

0x435730 LDP	X8, X19, [X29, #152]

0x435734 STUR	X8, [X29, #480]

0x435738 LDR	X8, [X29, #144]

0x43573c STR	X8, [SP, #72]

0x435740 LDR	X8, [X29, #136]

0x435744 STR	X8, [SP, #64]

0x435748 LDR	X8, [X29, #128]

0x43574c STR	X8, [SP, #56]

0x435750 LDP	X8, X9, [X29, #112]

0x435754 STP	X8, X9, [X29, #936]

0x435758 LDR	X8, [X29, #104]

0x43575c STR	X8, [SP, #104]

0x435760 LDR	X8, [X29, #96]

0x435764 STR	X8, [SP, #120]

0x435768 BL	4acc50

0x43576c ORR	X20, XZR, X0

0x435770 BL	4acc30

0x435774 LDR	X8, [X27]

0x435778 SUB	X10, X0, #1

0x43577c STR	X0, [SP, #16]

0x435780 MOVZ	W1, #8

0x435784 SDIV	X9, X8, X0

0x435788 LDR	X0, [X23]

0x43578c MUL	X11, X9, X20

0x435790 ADD	X9, X9, X11

0x435794 CMP	X20, X10

0x435798 CSEL	X8, X8, X9, #0

0x43579c LDR	X9, [X21]

0x4357a0 ORR	X24, XZR, X11

0x4357a4 STP	X8, X20, [X29, #920]

0x4357a8 LDR	X8, [X22]

0x4357ac LDR	X25, [X8, X9,LSL #3]

0x4357b0 BL	4aaf00

0x4357b4 LDR	X8, [X23]

0x4357b8 ORR	X22, XZR, X0

0x4357bc CMP	X8, #1

0x4357c0 B.LT	4357e0

0x4357c4 MOVN	X9, #0

0x4357c8 ORR	X8, XZR, XZR

(707) 0x4357cc STR	X9, [X22, X8,LSL #3]

(707) 0x4357d0 ADD	X8, X8, #1

(707) 0x4357d4 LDR	X10, [X23]

(707) 0x4357d8 CMP	X8, X10

(707) 0x4357dc B.LT	4357cc

0x4357e0 LDR	X8, [SP, #128]

0x4357e4 ADD	X27, X25, X24

0x4357e8 LDR	X0, [X8]

0x4357ec LDR	X8, [SP, #112]

0x4357f0 LDR	X8, [X8]

0x4357f4 ADD	X8, X8, #1

0x4357f8 CMP	X0, X8

0x4357fc B.NE	43583c

0x435800 MOVZ	W1, #8

0x435804 BL	4aaf00

0x435808 LDR	X11, [SP, #128]

0x43580c ORR	X23, XZR, X0

0x435810 LDR	X8, [X11]

0x435814 CMP	X8, #1

0x435818 B.LT	435880

0x43581c MOVN	X9, #0

0x435820 ORR	X8, XZR, XZR

(706) 0x435824 STR	X9, [X23, X8,LSL #3]

(706) 0x435828 ADD	X8, X8, #1

(706) 0x43582c LDR	X10, [X11]

(706) 0x435830 CMP	X8, X10

(706) 0x435834 B.LT	435824

0x435838 B	435880

0x43583c LDR	X8, [SP, #120]

0x435840 LDR	X0, [X8]

0x435844 CBZ	X0, 435b28

0x435848 MOVZ	W1, #8

0x43584c BL	4aaf00

0x435850 LDR	X11, [SP, #120]

0x435854 ORR	X23, XZR, X0

0x435858 LDR	X8, [X11]

0x43585c CMP	X8, #1

0x435860 B.LT	435880

0x435864 MOVN	X9, #0

0x435868 ORR	X8, XZR, XZR

(705) 0x43586c STR	X9, [X23, X8,LSL #3]

(705) 0x435870 ADD	X8, X8, #1

(705) 0x435874 LDR	X10, [X11]

(705) 0x435878 CMP	X8, X10

(705) 0x43587c B.LT	43586c

0x435880 LDUR	X9, [X29, #408]

0x435884 ADD	X8, X25, X9

0x435888 CMP	X24, X9

0x43588c STUR	X8, [X29, #472]

0x435890 B.GE	435b3c

0x435894 LDR	X10, [SP, #104]

0x435898 ORR	X9, XZR, XZR

0x43589c ORR	X8, XZR, XZR

0x4358a0 ORR	X18, XZR, X27

0x4358a4 LDR	X10, [X10]

0x4358a8 STUR	X10, [X29, #440]

0x4358ac LDUR	X10, [X29, #424]

0x4358b0 LDR	X11, [X10]

0x4358b4 LDUR	X10, [X29, #432]

0x4358b8 LDR	X12, [X10]

0x4358bc LDR	X10, [SP, #56]

0x4358c0 LDR	X13, [X10]

0x4358c4 LDR	X10, [SP, #64]

0x4358c8 LDR	X14, [X10]

0x4358cc LDR	X10, [SP, #72]

0x4358d0 LDR	X15, [X10]

0x4358d4 LDR	X10, [SP, #80]

0x4358d8 LDR	X16, [X10]

0x4358dc LDR	X10, [SP, #88]

0x4358e0 LDR	X17, [X10]

0x4358e4 LDR	X10, [SP, #48]

0x4358e8 LDR	X0, [X10]

0x4358ec B	435910

0x4358f0 HINT	#0

0x4358f4 HINT	#0

0x4358f8 HINT	#0

0x4358fc HINT	#0

    (699) 0x435900 LDUR	X10, [X29, #472]

    (699) 0x435904 ADD	X18, X18, #1

    (699) 0x435908 CMP	X18, X10

    (699) 0x43590c B.GE	435b44

    (699) 0x435910 LDUR	X10, [X29, #440]

    (699) 0x435914 LDR	X1, [X10, X18,LSL #3]

    (699) 0x435918 STR	X8, [X11, X1,LSL #3]

    (699) 0x43591c STR	X9, [X12, X1,LSL #3]

    (699) 0x435920 ADD	X2, X1, #1

    (699) 0x435924 LDR	X3, [X13, X1,LSL #3]

    (699) 0x435928 LDR	X10, [X13, X2,LSL #3]

    (699) 0x43592c CMP	X3, X10

    (699) 0x435930 B.GE	435a40

  (700) 0x435934 LDUR	X10, [X29, #480]

  (700) 0x435938 LDR	X5, [X19]

  (700) 0x43593c LDR	X4, [X10]

  (700) 0x435940 LDUR	X10, [X29, #488]

  (700) 0x435944 LDR	X6, [X10]

  (700) 0x435948 LDUR	X10, [X29, #496]

  (700) 0x43594c LDR	X7, [X10]

  (700) 0x435950 B	435970

0x435954 HINT	#0

0x435958 HINT	#0

0x43595c HINT	#0

  (700) 0x435960 LDR	X10, [X13, X2,LSL #3]

  (700) 0x435964 ADD	X3, X3, #1

  (700) 0x435968 CMP	X3, X10

  (700) 0x43596c B.GE	435a40

  (700) 0x435970 LDR	X10, [X14, X3,LSL #3]

  (700) 0x435974 LDR	X25, [X21]

  (700) 0x435978 LDR	X20, [X15, X10,LSL #3]

  (700) 0x43597c SUB	X25, X25, #1

  (700) 0x435980 CMP	X20, X25

  (700) 0x435984 B.NE	435960

  (700) 0x435988 ADD	X26, X10, #1

  (700) 0x43598c LDR	X20, [X4, X26,LSL #3]

  (700) 0x435990 CMP	X20, #1

  (700) 0x435994 B.LT	4359e4

  (700) 0x435998 LDR	X30, [X11, X10,LSL #3]

  (700) 0x43599c ADD	X25, X20, X30

  (700) 0x4359a0 B	4359b0

    (702) 0x4359a4 ADD	X30, X30, #1

    (702) 0x4359a8 CMP	X30, X25

    (702) 0x4359ac B.GE	4359e4

    (702) 0x4359b0 LDR	X20, [X21]

    (702) 0x4359b4 ADD	X20, X5, X20,LSL #3

    (702) 0x4359b8 LDUR	X20, [X20, #504]

    (702) 0x4359bc LDR	X28, [X20, X30,LSL #3]

    (702) 0x4359c0 LDR	X20, [X22, X28,LSL #3]

    (702) 0x4359c4 CMP	X20, X1

    (702) 0x4359c8 B.EQ	4359a4

    (702) 0x4359cc LDR	X20, [X4, X2,LSL #3]

    (702) 0x4359d0 ADD	X8, X8, #1

    (702) 0x4359d4 ADD	X20, X20, #1

    (702) 0x4359d8 STR	X20, [X4, X2,LSL #3]

    (702) 0x4359dc STR	X1, [X22, X28,LSL #3]

    (702) 0x4359e0 B	4359a4

  (700) 0x4359e4 LDR	X20, [X6, X26,LSL #3]

  (700) 0x4359e8 CMP	X20, #1

  (700) 0x4359ec B.LT	435960

(701) 0x4359f0 LDR	X10, [X12, X10,LSL #3]

(701) 0x4359f4 ADD	X25, X20, X10

(701) 0x4359f8 B	435a0c

0x4359fc HINT	#0

(701) 0x435a00 ADD	X10, X10, #1

(701) 0x435a04 CMP	X10, X25

(701) 0x435a08 B.GE	435960

(701) 0x435a0c LDR	X20, [X21]

(701) 0x435a10 ADD	X20, X7, X20,LSL #3

(701) 0x435a14 LDUR	X20, [X20, #504]

(701) 0x435a18 LDR	X26, [X20, X10,LSL #3]

(701) 0x435a1c LDR	X20, [X23, X26,LSL #3]

(701) 0x435a20 CMP	X20, X1

(701) 0x435a24 B.EQ	435a00

(701) 0x435a28 LDR	X20, [X6, X2,LSL #3]

(701) 0x435a2c ADD	X9, X9, #1

(701) 0x435a30 ADD	X20, X20, #1

(701) 0x435a34 STR	X20, [X6, X2,LSL #3]

(701) 0x435a38 STR	X1, [X23, X26,LSL #3]

(701) 0x435a3c B	435a00

    (699) 0x435a40 LDR	X3, [X16, X1,LSL #3]

    (699) 0x435a44 LDR	X10, [X16, X2,LSL #3]

    (699) 0x435a48 CMP	X3, X10

    (699) 0x435a4c B.GE	435900

    (699) 0x435a50 LDP	X4, X5, [X29, #960]

    (699) 0x435a54 LDUR	X6, [X29, #464]

    (699) 0x435a58 LDR	X4, [X4]

    (699) 0x435a5c LDR	X5, [X5]

    (699) 0x435a60 LDR	X6, [X6]

    (699) 0x435a64 B	435a78

      (703) 0x435a68 LDR	X10, [X16, X2,LSL #3]

      (703) 0x435a6c ADD	X3, X3, #1

      (703) 0x435a70 CMP	X3, X10

      (703) 0x435a74 B.GE	435900

      (703) 0x435a78 LDR	X7, [X17, X3,LSL #3]

      (703) 0x435a7c LDR	X25, [X21]

      (703) 0x435a80 LDR	X20, [X0, X7,LSL #3]

      (703) 0x435a84 SUB	X25, X25, #1

      (703) 0x435a88 CMP	X20, X25

      (703) 0x435a8c B.NE	435a6c

      (703) 0x435a90 ADD	X20, X5, X7,LSL #3

      (703) 0x435a94 LDR	X20, [X20, #8]

      (703) 0x435a98 CMP	X20, #1

      (703) 0x435a9c B.LT	435a6c

      (703) 0x435aa0 UBFM	X10, X7, #61, #60

      (703) 0x435aa4 LDR	X7, [X4, X10]

      (703) 0x435aa8 LDUR	X10, [X29, #488]

      (703) 0x435aac LDR	X26, [X10]

      (703) 0x435ab0 LDUR	X10, [X29, #480]

      (703) 0x435ab4 ADD	X30, X20, X7

      (703) 0x435ab8 LDR	X10, [X10]

      (703) 0x435abc B	435acc

        (704) 0x435ac0 ADD	X7, X7, #1

        (704) 0x435ac4 CMP	X7, X30

        (704) 0x435ac8 B.GE	435a68

        (704) 0x435acc LDR	X20, [X21]

        (704) 0x435ad0 LDR	X20, [X6, X20,LSL #3]

        (704) 0x435ad4 LDR	X25, [X20, X7,LSL #3]

        (704) 0x435ad8 TBNZ	X25, #63, 435b00

        (704) 0x435adc LDR	X20, [X23, X25,LSL #3]

        (704) 0x435ae0 CMP	X20, X1

        (704) 0x435ae4 B.EQ	435ac0

        (704) 0x435ae8 LDR	X20, [X26, X2,LSL #3]

        (704) 0x435aec ADD	X9, X9, #1

        (704) 0x435af0 ADD	X20, X20, #1

        (704) 0x435af4 STR	X20, [X26, X2,LSL #3]

        (704) 0x435af8 STR	X1, [X23, X25,LSL #3]

        (704) 0x435afc B	435ac0

        (704) 0x435b00 ORN	X25, XZR, X25

        (704) 0x435b04 LDR	X20, [X22, X25,LSL #3]

        (704) 0x435b08 CMP	X20, X1

        (704) 0x435b0c B.EQ	435ac0

        (704) 0x435b10 LDR	X20, [X10, X2,LSL #3]

        (704) 0x435b14 ADD	X8, X8, #1

        (704) 0x435b18 ADD	X20, X20, #1

        (704) 0x435b1c STR	X20, [X10, X2,LSL #3]

        (704) 0x435b20 STR	X1, [X22, X25,LSL #3]

        (704) 0x435b24 B	435ac0

0x435b28 LDUR	X9, [X29, #408]

0x435b2c ADD	X8, X25, X9

0x435b30 CMP	X24, X9

0x435b34 STUR	X8, [X29, #472]

0x435b38 B.LT	435894

0x435b3c ORR	X8, XZR, XZR

0x435b40 ORR	X9, XZR, XZR

0x435b44 LDUR	X11, [X29, #416]

0x435b48 CBNZ	X11, 435b5c

0x435b4c LDR	X10, [SP, #96]

0x435b50 LDR	X12, [SP, #16]

0x435b54 LDR	X10, [X10]

0x435b58 STR	X12, [X10]

0x435b5c LDUR	X10, [X29, #400]

0x435b60 ADRP	X0,

0x435b64 ADD	X0, X0, #832

0x435b68 ORR	X20, XZR, X11

0x435b6c LDR	X10, [X10]

0x435b70 STR	X9, [X10, X11,LSL #3]

0x435b74 LDUR	X9, [X29, #392]

0x435b78 LDR	X9, [X9]

0x435b7c STR	X8, [X9, X11,LSL #3]

0x435b80 LDR	X8, [SP, #40]

0x435b84 LDR	W25, [X8]

0x435b88 ORR	W1, WZR, W25

0x435b8c BL	4104c0

0x435b90 CBNZ	X20, 435be8

0x435b94 LDR	X8, [SP, #96]

0x435b98 LDR	X8, [X8]

0x435b9c LDR	X9, [X8]

0x435ba0 CMP	X9, #1

0x435ba4 B.LE	435be8

0x435ba8 LDP	X9, X11, [X29, #904]

0x435bac LDR	X10, [X11]

0x435bb0 LDR	X9, [X9]

0x435bb4 MOVZ	W11, #1

0x435bb8 ADD	X9, X9, #8

0x435bbc ADD	X10, X10, #8

(698) 0x435bc0 LDP	X12, X13, [X10, #1016]

(698) 0x435bc4 ADD	X11, X11, #1

(698) 0x435bc8 ADD	X12, X13, X12

(698) 0x435bcc STR	X12, [X10], #8

(698) 0x435bd0 LDP	X12, X13, [X9, #1016]

(698) 0x435bd4 ADD	X12, X13, X12

(698) 0x435bd8 STR	X12, [X9], #8

(698) 0x435bdc LDR	X12, [X8]

(698) 0x435be0 CMP	X11, X12

(698) 0x435be4 B.LT	435bc0

0x435be8 ADRP	X0,

0x435bec ADD	X0, X0, #856

0x435bf0 ORR	W1, WZR, W25

0x435bf4 BL	4104c0

0x435bf8 LDUR	X8, [X29, #416]

0x435bfc SUBS	X8, X8, #1

0x435c00 B.LT	435c74

0x435c04 LDUR	X9, [X29, #408]

0x435c08 LDUR	X18, [X29, #472]

0x435c0c CMP	X24, X9

0x435c10 B.GE	435d10

0x435c14 LDR	X9, [SP, #104]

0x435c18 LDP	X10, X12, [X29, #904]

0x435c1c ORR	X13, XZR, X27

0x435c20 LDR	X9, [X9]

0x435c24 LDP	X11, X14, [X29, #936]

0x435c28 LDR	X10, [X10]

0x435c2c LDR	X11, [X11]

0x435c30 LDR	X12, [X12]

0x435c34 LDR	X14, [X14]

0x435c38 HINT	#0

0x435c3c HINT	#0

(697) 0x435c40 LDR	X15, [X9, X13,LSL #3]

(697) 0x435c44 LDR	X16, [X10, X8,LSL #3]

(697) 0x435c48 ADD	X13, X13, #1

(697) 0x435c4c CMP	X13, X18

(697) 0x435c50 LDR	X17, [X11, X15,LSL #3]

(697) 0x435c54 ADD	X16, X17, X16

(697) 0x435c58 STR	X16, [X11, X15,LSL #3]

(697) 0x435c5c LDR	X16, [X12, X8,LSL #3]

(697) 0x435c60 LDR	X17, [X14, X15,LSL #3]

(697) 0x435c64 ADD	X16, X17, X16

(697) 0x435c68 STR	X16, [X14, X15,LSL #3]

(697) 0x435c6c B.LT	435c40

0x435c70 B	435d10

0x435c74 LDR	X9, [SP, #96]

0x435c78 LDUR	X8, [X29, #392]

0x435c7c MOVZ	W1, #8

0x435c80 LDR	X9, [X9]

0x435c84 LDR	X8, [X8]

0x435c88 LDR	X9, [X9]

0x435c8c UBFM	X9, X9, #61, #60

0x435c90 SUB	X9, X9, #8

0x435c94 LDR	X0, [X8, X9]

0x435c98 LDUR	X8, [X29, #400]

0x435c9c LDR	X8, [X8]

0x435ca0 LDR	X26, [X8, X9]

0x435ca4 LDP	X10, X9, [SP, #24]

0x435ca8 LDR	X8, [X10]

0x435cac ADD	X8, X8, X0

0x435cb0 STR	X8, [X10]

0x435cb4 LDR	X8, [X9]

0x435cb8 ADD	X8, X8, X26

0x435cbc STR	X8, [X9]

0x435cc0 BL	4aaf00

0x435cc4 LDR	X9, [X19]

0x435cc8 LDR	X8, [X21]

0x435ccc STR	X0, [X9, X8,LSL #3]

0x435cd0 CBZ	X26, 435cf4

0x435cd4 MOVZ	W1, #8

0x435cd8 ORR	X0, XZR, X26

0x435cdc BL	4aaf00

0x435ce0 LDUR	X8, [X29, #496]

0x435ce4 LDR	X9, [X21]

0x435ce8 LDR	X8, [X8]

0x435cec STR	X0, [X8, X9,LSL #3]

0x435cf0 B	435d10

0x435cf4 LDR	X9, [SP, #8]

0x435cf8 LDR	X9, [X9]

0x435cfc CMP	X9, #1

0x435d00 B.LE	435d10

0x435d04 LDUR	X9, [X29, #496]

0x435d08 LDR	X9, [X9]

0x435d0c STR	XZR, [X9, X8,LSL #3]

0x435d10 ADRP	X0,

0x435d14 ADD	X0, X0, #880

0x435d18 ORR	W1, WZR, W25

0x435d1c BL	4104c0

0x435d20 LDUR	X9, [X29, #416]

0x435d24 CMP	X9, #1

0x435d28 B.LT	435d58

0x435d2c LDP	X8, X10, [X29, #904]

0x435d30 UBFM	X9, X9, #61, #60

0x435d34 SUB	X9, X9, #8

0x435d38 LDR	X8, [X8]

0x435d3c LDR	X10, [X10]

0x435d40 LDR	X8, [X8, X9]

0x435d44 LDR	X9, [X10, X9]

0x435d48 LDUR	X10, [X29, #408]

0x435d4c CMP	X24, X10

0x435d50 B.LT	435d6c

0x435d54 B	436004

0x435d58 ORR	X8, XZR, XZR

0x435d5c ORR	X9, XZR, XZR

0x435d60 LDUR	X10, [X29, #408]

0x435d64 CMP	X24, X10

0x435d68 B.GE	436004

0x435d6c LDR	X10, [SP, #104]

0x435d70 LDR	X10, [X10]

0x435d74 STUR	X10, [X29, #440]

0x435d78 LDR	X10, [SP, #56]

0x435d7c LDR	X11, [X10]

0x435d80 LDR	X10, [SP, #64]

0x435d84 LDR	X12, [X10]

0x435d88 LDR	X10, [SP, #72]

0x435d8c LDR	X13, [X10]

0x435d90 LDR	X10, [SP, #80]

0x435d94 LDR	X14, [X10]

0x435d98 LDR	X10, [SP, #88]

0x435d9c LDR	X15, [X10]

0x435da0 LDR	X10, [SP, #48]

0x435da4 LDR	X16, [X10]

0x435da8 B	435dbc

      (690) 0x435dac LDUR	X10, [X29, #472]

      (690) 0x435db0 ADD	X27, X27, #1

      (690) 0x435db4 CMP	X27, X10

      (690) 0x435db8 B.GE	436004

      (690) 0x435dbc LDUR	X10, [X29, #440]

      (690) 0x435dc0 LDR	X18, [X10, X27,LSL #3]

      (690) 0x435dc4 ADD	X17, X18, #1

      (690) 0x435dc8 LDR	X0, [X11, X18,LSL #3]

      (690) 0x435dcc LDR	X10, [X11, X17,LSL #3]

      (690) 0x435dd0 CMP	X0, X10

      (690) 0x435dd4 B.GE	435f00

      (690) 0x435dd8 LDUR	X10, [X29, #424]

      (690) 0x435ddc LDR	X3, [X19]

      (690) 0x435de0 ORN	X4, XZR, X18

      (690) 0x435de4 LDR	X1, [X10]

      (690) 0x435de8 LDUR	X10, [X29, #480]

      (690) 0x435dec LDR	X2, [X10]

      (690) 0x435df0 LDUR	X10, [X29, #432]

      (690) 0x435df4 LDR	X5, [X10]

      (690) 0x435df8 LDUR	X10, [X29, #488]

      (690) 0x435dfc LDR	X6, [X10]

      (690) 0x435e00 LDUR	X10, [X29, #496]

      (690) 0x435e04 LDR	X7, [X10]

      (690) 0x435e08 B	435e1c

        (694) 0x435e0c LDR	X10, [X11, X17,LSL #3]

        (694) 0x435e10 ADD	X0, X0, #1

        (694) 0x435e14 CMP	X0, X10

        (694) 0x435e18 B.GE	435f00

        (694) 0x435e1c LDR	X26, [X12, X0,LSL #3]

        (694) 0x435e20 LDR	X20, [X21]

        (694) 0x435e24 LDR	X10, [X13, X26,LSL #3]

        (694) 0x435e28 SUB	X20, X20, #1

        (694) 0x435e2c CMP	X10, X20

        (694) 0x435e30 B.NE	435e0c

        (694) 0x435e34 ADD	X30, X26, #1

        (694) 0x435e38 LDR	X20, [X2, X30,LSL #3]

        (694) 0x435e3c CMP	X20, #1

        (694) 0x435e40 B.LT	435ea0

        (694) 0x435e44 LDR	X10, [X1, X26,LSL #3]

        (694) 0x435e48 ADD	X25, X20, X10

        (694) 0x435e4c B	435e6c

0x435e50 HINT	#0

0x435e54 HINT	#0

0x435e58 HINT	#0

0x435e5c HINT	#0

          (696) 0x435e60 ADD	X10, X10, #1

          (696) 0x435e64 CMP	X10, X25

          (696) 0x435e68 B.GE	435ea0

          (696) 0x435e6c LDR	X20, [X21]

          (696) 0x435e70 ADD	X20, X3, X20,LSL #3

          (696) 0x435e74 LDUR	X28, [X20, #504]

          (696) 0x435e78 LDR	X28, [X28, X10,LSL #3]

          (696) 0x435e7c LDR	X24, [X22, X28,LSL #3]

          (696) 0x435e80 CMP	X24, X4

          (696) 0x435e84 B.EQ	435e60

          (696) 0x435e88 LDR	X20, [X20]

          (696) 0x435e8c STR	X28, [X20, X8,LSL #3]

          (696) 0x435e90 ADD	X8, X8, #1

          (696) 0x435e94 STR	X4, [X22, X28,LSL #3]

          (696) 0x435e98 B	435e60

0x435e9c HINT	#0

        (694) 0x435ea0 LDR	X20, [X6, X30,LSL #3]

        (694) 0x435ea4 CMP	X20, #1

        (694) 0x435ea8 B.LT	435e0c

        (694) 0x435eac LDR	X10, [X5, X26,LSL #3]

        (694) 0x435eb0 ADD	X25, X20, X10

        (694) 0x435eb4 B	435ecc

0x435eb8 HINT	#0

0x435ebc HINT	#0

          (695) 0x435ec0 ADD	X10, X10, #1

          (695) 0x435ec4 CMP	X10, X25

          (695) 0x435ec8 B.GE	435e0c

          (695) 0x435ecc LDR	X20, [X21]

          (695) 0x435ed0 ADD	X20, X7, X20,LSL #3

          (695) 0x435ed4 LDUR	X24, [X20, #504]

          (695) 0x435ed8 LDR	X26, [X24, X10,LSL #3]

          (695) 0x435edc LDR	X24, [X23, X26,LSL #3]

          (695) 0x435ee0 CMP	X24, X4

          (695) 0x435ee4 B.EQ	435ec0

          (695) 0x435ee8 LDR	X20, [X20]

          (695) 0x435eec STR	X26, [X20, X9,LSL #3]

          (695) 0x435ef0 ADD	X9, X9, #1

          (695) 0x435ef4 STR	X4, [X23, X26,LSL #3]

          (695) 0x435ef8 B	435ec0

0x435efc HINT	#0

      (690) 0x435f00 LDR	X0, [X14, X18,LSL #3]

      (690) 0x435f04 LDR	X4, [X14, X17,LSL #3]

      (690) 0x435f08 CMP	X0, X4

      (690) 0x435f0c B.GE	435dac

    (691) 0x435f10 LDUR	X10, [X29, #448]

    (691) 0x435f14 ORN	X18, XZR, X18

    (691) 0x435f18 LDR	X1, [X10]

    (691) 0x435f1c LDUR	X10, [X29, #456]

    (691) 0x435f20 LDR	X2, [X10]

    (691) 0x435f24 LDUR	X10, [X29, #464]

    (691) 0x435f28 LDR	X3, [X10]

    (691) 0x435f2c B	435f50

0x435f30 HINT	#0

0x435f34 HINT	#0

0x435f38 HINT	#0

0x435f3c HINT	#0

  (693) 0x435f40 LDR	X4, [X14, X17,LSL #3]

    (691) 0x435f44 ADD	X0, X0, #1

    (691) 0x435f48 CMP	X0, X4

    (691) 0x435f4c B.GE	435dac

    (691) 0x435f50 LDR	X10, [X15, X0,LSL #3]

    (691) 0x435f54 LDR	X6, [X21]

    (691) 0x435f58 LDR	X5, [X16, X10,LSL #3]

    (691) 0x435f5c SUB	X6, X6, #1

    (691) 0x435f60 CMP	X5, X6

    (691) 0x435f64 B.NE	435f44

    (691) 0x435f68 ADD	X5, X2, X10,LSL #3

    (691) 0x435f6c LDR	X5, [X5, #8]

    (691) 0x435f70 CMP	X5, #1

    (691) 0x435f74 B.LT	435f44

  (693) 0x435f78 UBFM	X10, X10, #61, #60

  (693) 0x435f7c LDR	X7, [X19]

  (693) 0x435f80 LDR	X4, [X1, X10]

  (693) 0x435f84 LDUR	X10, [X29, #496]

  (693) 0x435f88 LDR	X6, [X10]

  (693) 0x435f8c ADD	X5, X5, X4

  (693) 0x435f90 B	435fac

0x435f94 HINT	#0

0x435f98 HINT	#0

0x435f9c HINT	#0

  (693) 0x435fa0 ADD	X4, X4, #1

  (693) 0x435fa4 CMP	X4, X5

  (693) 0x435fa8 B.GE	435f40

  (693) 0x435fac LDR	X10, [X21]

  (693) 0x435fb0 LDR	X20, [X3, X10,LSL #3]

  (693) 0x435fb4 LDR	X25, [X20, X4,LSL #3]

  (693) 0x435fb8 TBNZ	X25, #63, 435fe0

  (693) 0x435fbc LDR	X20, [X23, X25,LSL #3]

  (693) 0x435fc0 CMP	X20, X18

  (693) 0x435fc4 B.EQ	435fa0

  (693) 0x435fc8 LDR	X10, [X6, X10,LSL #3]

  (693) 0x435fcc STR	X25, [X10, X9,LSL #3]

  (693) 0x435fd0 ADD	X9, X9, #1

  (693) 0x435fd4 STR	X18, [X23, X25,LSL #3]

  (693) 0x435fd8 B	435fa0

0x435fdc HINT	#0

(692) 0x435fe0 ORN	X25, XZR, X25

(692) 0x435fe4 LDR	X20, [X22, X25,LSL #3]

(692) 0x435fe8 CMP	X20, X18

(692) 0x435fec B.EQ	435fa0

(692) 0x435ff0 LDR	X10, [X7, X10,LSL #3]

(692) 0x435ff4 STR	X25, [X10, X8,LSL #3]

(692) 0x435ff8 ADD	X8, X8, #1

(692) 0x435ffc STR	X18, [X22, X25,LSL #3]

(692) 0x436000 B	435fa0

0x436004 ORR	X0, XZR, X22

0x436008 BL	4ab000

0x43600c LDR	X8, [SP, #120]

0x436010 LDR	X8, [X8]

0x436014 CBNZ	X8, 436034

0x436018 LDR	X9, [SP, #112]

0x43601c LDR	X8, [SP, #128]

0x436020 LDR	X9, [X9]

0x436024 LDR	X8, [X8]

0x436028 ADD	X9, X9, #1

0x43602c CMP	X8, X9

0x436030 B.NE	436058

0x436034 ORR	X0, XZR, X23

0x436038 LDP	X20, X19, [SP, #336]

0x43603c LDP	X22, X21, [SP, #320]

0x436040 LDP	X24, X23, [SP, #304]

0x436044 LDP	X26, X25, [SP, #288]

0x436048 LDP	X28, X27, [SP, #272]

0x43604c LDP	X29, X30, [SP, #256]

0x436050 ADD	SP, SP, #352

0x436054 B	4ab000

0x436058 LDP	X20, X19, [SP, #336]

0x43605c LDP	X22, X21, [SP, #320]

0x436060 LDP	X24, X23, [SP, #304]

0x436064 LDP	X26, X25, [SP, #288]

0x436068 LDP	X28, X27, [SP, #272]

0x43606c LDP	X29, X30, [SP, #256]

0x436070 ADD	SP, SP, #352

0x436074 RET

0x436078 HINT	#0

0x43607c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.51+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.49+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:693	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:785	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_multi_interp.c:891-1134
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:891,900-907,916-929,939-970,976-999,1008-1034,1040-1063,1072-1125,1132-1134.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 27% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 60.83 to 11.08 cycles (5.49x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_CAlloc: 5 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:916
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:921
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:927
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1048
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1050
hypre_Free: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1132
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:900
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:901
unknown: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1013
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1024
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes.

General properties

nb instructions	327
nb uops	299
loop length	1308
used w registers	4
used x registers	31
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	64

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	37.38 cycles
front end	37.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	19.00	19.00	22.50	22.50	22.50	22.50	0.00	0.00	0.00	0.00	60.83	60.50	60.67	20.50	20.50
cycles	19.00	19.00	22.50	22.50	22.50	22.50	0.00	0.00	0.00	0.00	60.83	60.50	60.67	20.50	20.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	37.38
Dispatch	60.83
DIV/SQRT	5.00-20.00
Overall L1	60.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	27%
load	27%
store	31%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 60.83 cycles. At this rate:

0% of peak load performance is reached (0.05 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4356a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X7, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X23, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X27, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X0, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X9, X8, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X9, [X29, #968]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X9, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X19, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X9, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4acc50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4acc30 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X10, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X0, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SDIV X9, X8, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
LDR X0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MUL X11, X9, X20	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X9, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X20, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X8, X8, X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X24, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X8, X20, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4357e0 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X27, X25, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 43583c <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x19c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 435880 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 435880 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBZ X0, 435b28 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x488>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 435880 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X25, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X24, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GE 435b3c <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x49c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X18, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 435910 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X25, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X24, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LT 435894 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X11, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X11, 435b5c <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x4bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X10, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4ecb60>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #832	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X20, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [X10, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X9, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X9, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W25, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ X20, 435be8 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x548>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 435be8 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x548>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X11, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <4ecbe8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #856	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 435c74 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x5d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X18, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X24, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 435d10 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x670>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X10, X12, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X13, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X11, X14, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
HINT #0																			N/A
HINT #0																			N/A
B 435d10 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x670>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X9, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X9, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X8, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X26, [X8, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X10, X9, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X8, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X8, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBZ X26, 435cf4 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x654>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X0, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 435d10 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x670>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 435d10 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x670>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADRP X0, <4ecd10>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #880	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 435d58 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x6b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X10, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
UBFM X9, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X9, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X10, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X24, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 435d6c <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x6cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 436004 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x964>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X10, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X24, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 436004 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x964>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 435dbc <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x71c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ab000 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X8, 436034 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x994>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 436058 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x9b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4ab000 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_multi_interp.c:891-1134
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_CAlloc: 5 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:916
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:921
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:927
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1048
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1050
hypre_Free: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1132
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:900
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:901
unknown: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1013
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1024
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes.

General properties

nb instructions	327
nb uops	299
loop length	1308
used w registers	4
used x registers	31
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	64

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	37.38 cycles
front end	37.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	19.00	19.00	22.50	22.50	22.50	22.50	0.00	0.00	0.00	0.00	60.83	60.50	60.67	20.50	20.50
cycles	19.00	19.00	22.50	22.50	22.50	22.50	0.00	0.00	0.00	0.00	60.83	60.50	60.67	20.50	20.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	37.38
Dispatch	60.83
DIV/SQRT	5.00-20.00
Overall L1	60.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	27%
load	27%
store	31%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 60.83 cycles. At this rate:

0% of peak load performance is reached (0.05 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4356a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X7, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X23, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X27, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X0, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X9, X8, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X9, [X29, #968]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X9, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X19, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X9, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4acc50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4acc30 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X10, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X0, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SDIV X9, X8, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
LDR X0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MUL X11, X9, X20	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X9, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X20, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X8, X8, X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X24, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X8, X20, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4357e0 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X27, X25, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 43583c <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x19c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 435880 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 435880 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBZ X0, 435b28 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x488>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 435880 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X25, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X24, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GE 435b3c <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x49c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X18, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 435910 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X25, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X24, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LT 435894 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X11, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X11, 435b5c <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x4bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X10, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4ecb60>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #832	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X20, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [X10, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X9, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X9, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W25, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ X20, 435be8 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x548>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 435be8 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x548>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X11, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <4ecbe8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #856	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 435c74 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x5d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X18, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X24, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 435d10 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x670>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X10, X12, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X13, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X11, X14, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
HINT #0																			N/A
HINT #0																			N/A
B 435d10 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x670>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X9, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X9, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X8, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X26, [X8, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X10, X9, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X8, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X8, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBZ X26, 435cf4 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x654>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X0, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 435d10 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x670>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 435d10 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x670>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADRP X0, <4ecd10>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #880	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 435d58 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x6b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X10, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
UBFM X9, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X9, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X10, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X24, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 435d6c <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x6cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 436004 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x964>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X10, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X24, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 436004 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x964>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 435dbc <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x71c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ab000 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X8, 436034 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x994>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 436058 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x9b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4ab000 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass.omp_outlined.9–	1.00	0.48
○Loop 697 - par_multi_interp.c:1030-1034 - exec	0.03	0.01
○Loop 707 - par_multi_interp.c:917-918 - exec	0.00	0.01
○Loop 705 - par_multi_interp.c:928-929 - exec	0.00	0.00
▼Loop 692 - par_multi_interp.c:1072-1125 - exec–	0.00	0.00
▼Loop 693 - par_multi_interp.c:1072-1125 - exec–	0.00	0.00
▼Loop 691 - par_multi_interp.c:1072-1111 - exec–	0.00	0.00
▼Loop 690 - par_multi_interp.c:1072-1104 - exec–	0.04	0.02
▼Loop 694 - par_multi_interp.c:1075-1099 - exec–	0.29	0.10
○Loop 696 - par_multi_interp.c:1082-1088 - exec	0.14	0.05
○Loop 695 - par_multi_interp.c:1093-1099 - exec	0.00	0.00
○Loop 698 - par_multi_interp.c:1017-1020 - exec	0.00	0.00
○Loop 706 - par_multi_interp.c:922-923 - exec	0.00	0.00
▼Loop 701 - par_multi_interp.c:939-999 - exec–	0.00	0.00
▼Loop 700 - par_multi_interp.c:939-999 - exec–	0.30	0.10
○Loop 702 - par_multi_interp.c:951-958 - exec	0.15	0.05
▼Loop 699 - par_multi_interp.c:939-999 - exec–	0.04	0.02
▼Loop 703 - par_multi_interp.c:976-999 - exec–	0.00	0.00
○Loop 704 - par_multi_interp.c:983-999 - exec	0.00	0.00

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Matching between your function (in the source code) and the binary function

General properties

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code