OV - exec - Function hypre_BoomerAMGBuildMultipass.omp

	Function: hypre_BoomerAMGBuildMultipass.omp_outlined.17	Module: exec	Source: par_multi_interp.c:1575-1663 [...]	Coverage (incl. loops): 0.26% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1575 - 1663

--------------------------------------------------------------------------------

1575: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa)

[...]

1585:            if (n_fine)

1586:            {   tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); }

1587:            tmp_marker_offd = NULL;

1588:            if (num_cols_offd)

1589:            {   tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); }

1590:            for (i=0; i < n_fine; i++)

1591:            {   tmp_marker[i] = -1; }

1592:            for (i=0; i < num_cols_offd; i++)

1593:            {   tmp_marker_offd[i] = -1; }

1594:

1595:            /* Compute this thread's range of pass_length */

1596:            my_thread_num = hypre_GetThreadNum();

1597:            num_threads = hypre_NumActiveThreads();

1598:            thread_start = pass_pointer[1] + (pass_length/num_threads)*my_thread_num;

1599:            if (my_thread_num == num_threads-1)

[...]

1605:            for (i=thread_start; i < thread_stop; i++)

1606:            {

1607:              i1 = pass_array[i];

1608:              sum_C = 0;

1609:              sum_N = 0;

1610:              j_start = P_diag_start[i1];

1611:              j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1612:              for (j=j_start; j < j_end; j++)

1613:              {

1614:                 k1 = P_diag_pass[1][j];

1615:                 tmp_marker[C_array[k1]] = i1;

1616:              }

1617:              cnt = P_diag_i[i1];

1618:              for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1619:              {

1620:                 j1 = A_diag_j[j];

1621:                 if (CF_marker[j1] != -3 &&

1622:                    (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1623:                    sum_N += A_diag_data[j];

1624:                 if (j1 != -1 && tmp_marker[j1] == i1)

1625:                 {

1626:                    P_diag_data[cnt] = A_diag_data[j];

1627:                    P_diag_j[cnt++] = fine_to_coarse[j1];

1628:                    sum_C += A_diag_data[j];

1629:                 }

1630:              }

1631:              j_start = P_offd_start[i1];

1632:              j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1633:              for (j=j_start; j < j_end; j++)

1634:              {

1635:                 k1 = P_offd_pass[1][j];

1636:                 tmp_marker_offd[C_array_offd[k1]] = i1;

1637:              }

1638:              cnt_offd = P_offd_i[i1];

1639:              for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1640:              {

1641:                 if (col_offd_S_to_A)

1642:                     j1 = map_A_to_S[A_offd_j[j]];

1643:                 else

1644:                     j1 = A_offd_j[j];

1645:                 if (CF_marker_offd[j1] != -3 &&

1646:                   (num_functions == 1 || dof_func[i1] == dof_func_offd[j1]))

1647:                     sum_N += A_offd_data[j];

1648:                 if (j1 != -1 && tmp_marker_offd[j1] == i1)

1649:                 {

1650:                    P_offd_data[cnt_offd] = A_offd_data[j];

1651:                    P_offd_j[cnt_offd++] = map_S_to_new[j1];

1652:                    sum_C += A_offd_data[j];

1653:                 }

1654:              }

1655:              diagonal = A_diag_data[A_diag_i[i1]];

1656:              if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1657:              for (j=P_diag_i[i1]; j < cnt; j++)

1658:                 P_diag_data[j] *= alfa;

1659:              for (j=P_offd_i[i1]; j < cnt_offd; j++)

1660:                 P_offd_data[j] *= alfa;

1661:           }

1662:           hypre_TFree(tmp_marker);

1663:           hypre_TFree(tmp_marker_offd);

0x4374c0 SUB	SP, SP, #304

0x4374c4 STP	X29, X30, [SP, #208]

0x4374c8 STP	X28, X27, [SP, #224]

0x4374cc STP	X26, X25, [SP, #240]

0x4374d0 STP	X24, X23, [SP, #256]

0x4374d4 STP	X22, X21, [SP, #272]

0x4374d8 STP	X20, X19, [SP, #288]

0x4374dc ADD	X29, SP, #208

0x4374e0 LDR	X8, [X29, #296]

0x4374e4 STP	X7, X6, [X29, #984]

0x4374e8 STUR	X4, [X29, #464]

0x4374ec LDR	X0, [X2]

0x4374f0 ORR	X24, XZR, X5

0x4374f4 ORR	X25, XZR, X3

0x4374f8 ORR	X26, XZR, X2

0x4374fc STR	X8, [SP, #88]

0x437500 LDR	X8, [X29, #288]

0x437504 STR	X8, [SP, #80]

0x437508 LDP	X8, X9, [X29, #272]

0x43750c STUR	X9, [X29, #416]

0x437510 STR	X8, [SP, #72]

0x437514 LDR	X8, [X29, #264]

0x437518 STR	X8, [SP, #64]

0x43751c LDP	X8, X22, [X29, #248]

0x437520 STR	X8, [SP, #56]

0x437524 LDR	X8, [X29, #240]

0x437528 STR	X8, [SP, #48]

0x43752c LDP	X8, X28, [X29, #224]

0x437530 STUR	X8, [X29, #496]

0x437534 LDP	X8, X9, [X29, #208]

0x437538 STP	X8, X9, [X29, #952]

0x43753c LDP	X8, X9, [X29, #192]

0x437540 STUR	X8, [X29, #456]

0x437544 LDR	X8, [X29, #184]

0x437548 STUR	X9, [X29, #432]

0x43754c STR	X8, [SP, #40]

0x437550 LDR	X8, [X29, #176]

0x437554 STR	X8, [SP, #32]

0x437558 LDR	X8, [X29, #168]

0x43755c STR	X8, [SP, #104]

0x437560 LDR	X8, [X29, #160]

0x437564 STR	X8, [SP, #96]

0x437568 LDP	X23, X8, [X29, #144]

0x43756c STUR	X8, [X29, #488]

0x437570 LDP	X8, X9, [X29, #128]

0x437574 STUR	X9, [X29, #424]

0x437578 STR	X8, [SP, #16]

0x43757c LDR	X8, [X29, #120]

0x437580 STR	X8, [SP, #8]

0x437584 LDR	X8, [X29, #112]

0x437588 STR	X8, [SP]

0x43758c LDP	X21, X27, [X29, #96]

0x437590 CBZ	X0, 4375c4

0x437594 MOVZ	W1, #8

0x437598 BL	4aaf00

0x43759c ORR	X19, XZR, X0

0x4375a0 LDR	X0, [X25]

0x4375a4 CBZ	X0, 4375d0

0x4375a8 MOVZ	W1, #8

0x4375ac BL	4aaf00

0x4375b0 ORR	X20, XZR, X0

0x4375b4 LDR	X8, [X26]

0x4375b8 CMP	X8, #1

0x4375bc B.GE	4375e0

0x4375c0 B	4375fc

0x4375c4 ORR	X19, XZR, XZR

0x4375c8 LDR	X0, [X25]

0x4375cc CBNZ	X0, 4375a8

0x4375d0 ORR	X20, XZR, XZR

0x4375d4 LDR	X8, [X26]

0x4375d8 CMP	X8, #1

0x4375dc B.LT	4375fc

0x4375e0 MOVN	X9, #0

0x4375e4 ORR	X8, XZR, XZR

(750) 0x4375e8 STR	X9, [X19, X8,LSL #3]

(750) 0x4375ec ADD	X8, X8, #1

(750) 0x4375f0 LDR	X10, [X26]

(750) 0x4375f4 CMP	X8, X10

(750) 0x4375f8 B.LT	4375e8

0x4375fc LDR	X8, [X25]

0x437600 CMP	X8, #1

0x437604 B.LT	437634

0x437608 MOVN	X9, #0

0x43760c ORR	X8, XZR, XZR

0x437610 HINT	#0

0x437614 HINT	#0

0x437618 HINT	#0

0x43761c HINT	#0

(751) 0x437620 STR	X9, [X20, X8,LSL #3]

(751) 0x437624 ADD	X8, X8, #1

(751) 0x437628 LDR	X10, [X25]

(751) 0x43762c CMP	X8, X10

(751) 0x437630 B.LT	437620

0x437634 BL	4acc50

0x437638 ORR	X25, XZR, X0

0x43763c BL	4acc30

0x437640 LDR	X9, [X24]

0x437644 SUB	X11, X0, #1

0x437648 SDIV	X10, X9, X0

0x43764c MUL	X8, X10, X25

0x437650 ADD	X10, X10, X8

0x437654 CMP	X25, X11

0x437658 CSEL	X9, X9, X10, #0

0x43765c CMP	X8, X9

0x437660 B.GE	437bf8

0x437664 LDUR	X10, [X29, #464]

0x437668 LDR	X17, [X21]

0x43766c LDR	X2, [X28]

0x437670 CNTW	X25, ALL

0x437674 PTRUE	P0.D, ALL

0x437678 LDR	X3, [X22]

0x43767c LDR	X11, [X10]

0x437680 LDUR	X10, [X29, #480]

0x437684 LDR	X10, [X10]

0x437688 LDR	X11, [X11, #8]

0x43768c STUR	X10, [X29, #480]

0x437690 LDUR	X10, [X29, #472]

0x437694 ADD	X9, X9, X11

0x437698 ADD	X6, X8, X11

0x43769c LDR	X10, [X10]

0x4376a0 STUR	X10, [X29, #472]

0x4376a4 LDR	X10, [X27]

0x4376a8 STR	X10, [SP, #24]

0x4376ac LDP	X8, X10, [SP]

0x4376b0 LDR	X12, [X8]

0x4376b4 LDR	X13, [X10]

0x4376b8 LDR	X10, [SP, #16]

0x4376bc LDR	X14, [X10]

0x4376c0 LDUR	X10, [X29, #424]

0x4376c4 LDR	X15, [X10]

0x4376c8 LDUR	X10, [X29, #456]

0x4376cc LDR	X10, [X10]

0x4376d0 STUR	X10, [X29, #456]

0x4376d4 LDP	X8, X10, [X29, #944]

0x4376d8 LDR	X1, [X8]

0x4376dc LDR	X10, [X10]

0x4376e0 STR	X10, [SP, #16]

0x4376e4 LDUR	X10, [X29, #448]

0x4376e8 LDR	X0, [X10]

0x4376ec LDUR	X10, [X29, #496]

0x4376f0 LDR	X10, [X10]

0x4376f4 STUR	X10, [X29, #496]

0x4376f8 LDR	X10, [SP, #96]

0x4376fc LDR	X10, [X10]

0x437700 STP	X9, X10, [X29, #952]

0x437704 LDR	X8, [SP, #104]

0x437708 LDR	X9, [X8]

0x43770c LDUR	X8, [X29, #416]

0x437710 LDR	X10, [X8]

0x437714 RDVL	X8, #1

0x437718 STUR	X9, [X29, #432]

0x43771c ADD	X9, X9, X8

0x437720 STR	X9, [SP, #8]

0x437724 ADD	X8, X10, X8

0x437728 STUR	X10, [X29, #424]

0x43772c STR	X8, [SP]

0x437730 STUR	X17, [X29, #464]

0x437734 B	437750

0x437738 HINT	#0

0x43773c HINT	#0

  (739) 0x437740 LDUR	X8, [X29, #440]

  (739) 0x437744 ADD	X6, X6, #1

  (739) 0x437748 CMP	X6, X8

  (739) 0x43774c B.GE	437bf8

  (739) 0x437750 LDP	X8, X9, [X29, #984]

  (739) 0x437754 LDR	X30, [X9, X6,LSL #3]

  (739) 0x437758 ADD	X21, X30, #1

  (739) 0x43775c LDR	X8, [X8, X30,LSL #3]

  (739) 0x437760 LDR	X26, [X17, X30,LSL #3]

  (739) 0x437764 LDR	X9, [X17, X21,LSL #3]

  (739) 0x437768 ADD	X11, X9, X8

  (739) 0x43776c SUB	X11, X11, X26

  (739) 0x437770 CMP	X8, X11

  (739) 0x437774 B.GE	43782c

  (739) 0x437778 LDR	X10, [SP, #24]

  (739) 0x43777c SUB	W16, W9, W26

  (739) 0x437780 ANDS	X18, X16, #0x3

  (739) 0x437784 LDR	X11, [X10, #8]

  (739) 0x437788 B.EQ	4377c8

  (739) 0x43778c ORR	X16, XZR, X8

  (739) 0x437790 HINT	#0

  (739) 0x437794 HINT	#0

  (739) 0x437798 HINT	#0

  (739) 0x43779c HINT	#0

    (745) 0x4377a0 LDR	X4, [X11, X16,LSL #3]

    (745) 0x4377a4 ADD	X16, X16, #1

    (745) 0x4377a8 SUBS	X18, X18, #1

    (745) 0x4377ac LDR	X4, [X12, X4,LSL #3]

    (745) 0x4377b0 STR	X30, [X19, X4,LSL #3]

    (745) 0x4377b4 B.NE	4377a0

  (739) 0x4377b8 SUB	X18, X26, X9

  (739) 0x4377bc CMN	X18, #4

  (739) 0x4377c0 B.LS	4377d8

  (739) 0x4377c4 B	437828

  (739) 0x4377c8 ORR	X16, XZR, X8

  (739) 0x4377cc SUB	X18, X26, X9

  (739) 0x4377d0 CMN	X18, #4

  (739) 0x4377d4 B.HI	437828

  (739) 0x4377d8 ADD	X8, X9, X8

  (739) 0x4377dc ADD	X9, X11, X16,LSL #3

  (739) 0x4377e0 SUB	X8, X8, X16

  (739) 0x4377e4 ADD	X9, X9, #16

  (739) 0x4377e8 SUB	X8, X8, X26

    (744) 0x4377ec LDUR	X11, [X9, #496]

    (744) 0x4377f0 SUBS	X8, X8, #4

    (744) 0x4377f4 LDR	X11, [X12, X11,LSL #3]

    (744) 0x4377f8 STR	X30, [X19, X11,LSL #3]

    (744) 0x4377fc LDUR	X11, [X9, #504]

    (744) 0x437800 LDR	X11, [X12, X11,LSL #3]

    (744) 0x437804 STR	X30, [X19, X11,LSL #3]

    (744) 0x437808 LDR	X11, [X9]

    (744) 0x43780c LDR	X11, [X12, X11,LSL #3]

    (744) 0x437810 STR	X30, [X19, X11,LSL #3]

    (744) 0x437814 LDR	X11, [X9, #8]

    (744) 0x437818 ADD	X9, X9, #32

    (744) 0x43781c LDR	X11, [X12, X11,LSL #3]

    (744) 0x437820 STR	X30, [X19, X11,LSL #3]

    (744) 0x437824 B.NE	4377ec

  (739) 0x437828 LDR	X26, [X17, X30,LSL #3]

  (739) 0x43782c LDR	X8, [X13, X30,LSL #3]

  (739) 0x437830 LDR	X16, [X13, X21,LSL #3]

  (739) 0x437834 MOVI	D2, #0

  (739) 0x437838 ADD	X8, X8, #1

  (739) 0x43783c CMP	X8, X16

  (739) 0x437840 B.GE	437900

  (739) 0x437844 LDR	X10, [SP, #96]

  (739) 0x437848 LDUR	X9, [X29, #488]

  (739) 0x43784c MOVI	D1, #0

  (739) 0x437850 LDR	X11, [X10]

  (739) 0x437854 LDR	X10, [SP, #104]

  (739) 0x437858 LDR	X9, [X9]

  (739) 0x43785c LDR	X18, [X10]

  (739) 0x437860 LDR	X10, [SP, #40]

  (739) 0x437864 LDR	X4, [X10]

  (739) 0x437868 LDR	X10, [SP, #32]

  (739) 0x43786c LDR	X7, [X10]

  (739) 0x437870 B	43788c

0x437874 HINT	#0

0x437878 HINT	#0

0x43787c HINT	#0

    (743) 0x437880 ADD	X8, X8, #1

    (743) 0x437884 CMP	X8, X16

    (743) 0x437888 B.GE	437904

    (743) 0x43788c LDR	X22, [X14, X8,LSL #3]

    (743) 0x437890 LDR	X5, [X15, X22,LSL #3]

    (743) 0x437894 CMN	X5, #3

    (743) 0x437898 B.EQ	4378c0

    (743) 0x43789c LDR	X5, [X23]

    (743) 0x4378a0 CMP	X5, #1

    (743) 0x4378a4 B.EQ	4378b8

    (743) 0x4378a8 LDR	X5, [X9, X30,LSL #3]

    (743) 0x4378ac LDR	X24, [X9, X22,LSL #3]

    (743) 0x4378b0 CMP	X5, X24

    (743) 0x4378b4 B.NE	4378c0

    (743) 0x4378b8 LDR	D3, [X11, X8,LSL #3]

    (743) 0x4378bc FADD	D1, D1, D3

    (743) 0x4378c0 CMN	X22, #1

    (743) 0x4378c4 B.EQ	437880

    (743) 0x4378c8 LDR	X5, [X19, X22,LSL #3]

    (743) 0x4378cc CMP	X5, X30

    (743) 0x4378d0 B.NE	437880

    (743) 0x4378d4 LDR	X16, [X4, X22,LSL #3]

    (743) 0x4378d8 LDR	D3, [X11, X8,LSL #3]

    (743) 0x4378dc STR	X16, [X7, X26,LSL #3]

    (743) 0x4378e0 LDR	X16, [X13, X21,LSL #3]

    (743) 0x4378e4 FADD	D2, D2, D3

    (743) 0x4378e8 STR	D3, [X18, X26,LSL #3]

    (743) 0x4378ec ADD	X26, X26, #1

    (743) 0x4378f0 B	437880

0x4378f4 HINT	#0

0x4378f8 HINT	#0

0x4378fc HINT	#0

  (739) 0x437900 MOVI	D1, #0

  (739) 0x437904 LDUR	X8, [X29, #456]

  (739) 0x437908 LDR	X9, [X1, X21,LSL #3]

  (739) 0x43790c LDR	X27, [X1, X30,LSL #3]

  (739) 0x437910 LDR	X8, [X8, X30,LSL #3]

  (739) 0x437914 ADD	X11, X9, X8

  (739) 0x437918 SUB	X11, X11, X27

  (739) 0x43791c CMP	X8, X11

  (739) 0x437920 B.GE	4379cc

  (739) 0x437924 LDR	X10, [SP, #16]

  (739) 0x437928 SUB	W16, W9, W27

  (739) 0x43792c ANDS	X18, X16, #0x3

  (739) 0x437930 LDR	X11, [X10, #8]

  (739) 0x437934 B.EQ	437968

  (739) 0x437938 ORR	X16, XZR, X8

  (739) 0x43793c HINT	#0

    (742) 0x437940 LDR	X4, [X11, X16,LSL #3]

    (742) 0x437944 ADD	X16, X16, #1

    (742) 0x437948 SUBS	X18, X18, #1

    (742) 0x43794c LDR	X4, [X0, X4,LSL #3]

    (742) 0x437950 STR	X30, [X20, X4,LSL #3]

    (742) 0x437954 B.NE	437940

  (739) 0x437958 SUB	X18, X27, X9

  (739) 0x43795c CMN	X18, #4

  (739) 0x437960 B.LS	437978

  (739) 0x437964 B	4379c8

  (739) 0x437968 ORR	X16, XZR, X8

  (739) 0x43796c SUB	X18, X27, X9

  (739) 0x437970 CMN	X18, #4

  (739) 0x437974 B.HI	4379c8

  (739) 0x437978 ADD	X8, X9, X8

  (739) 0x43797c ADD	X9, X11, X16,LSL #3

  (739) 0x437980 SUB	X8, X8, X16

  (739) 0x437984 ADD	X9, X9, #16

  (739) 0x437988 SUB	X8, X8, X27

    (741) 0x43798c LDUR	X11, [X9, #496]

    (741) 0x437990 SUBS	X8, X8, #4

    (741) 0x437994 LDR	X11, [X0, X11,LSL #3]

    (741) 0x437998 STR	X30, [X20, X11,LSL #3]

    (741) 0x43799c LDUR	X11, [X9, #504]

    (741) 0x4379a0 LDR	X11, [X0, X11,LSL #3]

    (741) 0x4379a4 STR	X30, [X20, X11,LSL #3]

    (741) 0x4379a8 LDR	X11, [X9]

    (741) 0x4379ac LDR	X11, [X0, X11,LSL #3]

    (741) 0x4379b0 STR	X30, [X20, X11,LSL #3]

    (741) 0x4379b4 LDR	X11, [X9, #8]

    (741) 0x4379b8 ADD	X9, X9, #32

    (741) 0x4379bc LDR	X11, [X0, X11,LSL #3]

    (741) 0x4379c0 STR	X30, [X20, X11,LSL #3]

    (741) 0x4379c4 B.NE	43798c

  (739) 0x4379c8 LDR	X27, [X1, X30,LSL #3]

  (739) 0x4379cc LDUR	X8, [X29, #496]

  (739) 0x4379d0 LDR	X28, [X8, X30,LSL #3]

  (739) 0x4379d4 LDR	X7, [X8, X21,LSL #3]

  (739) 0x4379d8 CMP	X28, X7

  (739) 0x4379dc B.GE	437aac

(740) 0x4379e0 LDP	X9, X8, [SP, #48]

(740) 0x4379e4 LDR	X4, [X8]

(740) 0x4379e8 LDUR	X8, [X29, #488]

(740) 0x4379ec LDR	X11, [X9]

(740) 0x4379f0 LDR	X18, [X8]

(740) 0x4379f4 LDP	X9, X8, [SP, #64]

(740) 0x4379f8 ADD	X4, X4, X28,LSL #3

(740) 0x4379fc LDR	X24, [X9]

(740) 0x437a00 LDR	X22, [X8]

(740) 0x437a04 LDUR	X8, [X29, #416]

(740) 0x437a08 LDP	X10, X9, [SP, #80]

(740) 0x437a0c LDR	X8, [X8]

(740) 0x437a10 LDR	X9, [X9]

(740) 0x437a14 LDR	X16, [X10]

(740) 0x437a18 B	437a30

0x437a1c HINT	#0

(740) 0x437a20 ADD	X28, X28, #1

(740) 0x437a24 ADD	X4, X4, #8

(740) 0x437a28 CMP	X28, X7

(740) 0x437a2c B.GE	437aac

(740) 0x437a30 ORR	X5, XZR, X4

(740) 0x437a34 CBZ	X2, 437a40

(740) 0x437a38 LDR	X5, [X4]

(740) 0x437a3c ADD	X5, X11, X5,LSL #3

(740) 0x437a40 LDR	X5, [X5]

(740) 0x437a44 LDR	X10, [X3, X5,LSL #3]

(740) 0x437a48 CMN	X10, #3

(740) 0x437a4c B.EQ	437a74

(740) 0x437a50 LDR	X10, [X23]

(740) 0x437a54 CMP	X10, #1

(740) 0x437a58 B.EQ	437a6c

(740) 0x437a5c LDR	X10, [X18, X30,LSL #3]

(740) 0x437a60 LDR	X17, [X24, X5,LSL #3]

(740) 0x437a64 CMP	X10, X17

(740) 0x437a68 B.NE	437a74

(740) 0x437a6c LDR	D3, [X22, X28,LSL #3]

(740) 0x437a70 FADD	D1, D1, D3

(740) 0x437a74 CMN	X5, #1

(740) 0x437a78 B.EQ	437a20

(740) 0x437a7c LDR	X10, [X20, X5,LSL #3]

(740) 0x437a80 CMP	X10, X30

(740) 0x437a84 B.NE	437a20

(740) 0x437a88 LDR	X10, [X9, X5,LSL #3]

(740) 0x437a8c LDR	D3, [X22, X28,LSL #3]

(740) 0x437a90 STR	X10, [X16, X27,LSL #3]

(740) 0x437a94 LDUR	X10, [X29, #496]

(740) 0x437a98 FADD	D2, D2, D3

(740) 0x437a9c STR	D3, [X8, X27,LSL #3]

(740) 0x437aa0 ADD	X27, X27, #1

(740) 0x437aa4 LDR	X7, [X10, X21,LSL #3]

(740) 0x437aa8 B	437a20

  (739) 0x437aac LDR	X8, [X13, X30,LSL #3]

  (739) 0x437ab0 LDUR	X9, [X29, #448]

  (739) 0x437ab4 LDR	D3, [X9, X8,LSL #3]

  (739) 0x437ab8 FMUL	D2, D2, D3

  (739) 0x437abc FCMP	D2, #0

  (739) 0x437ac0 B.EQ	437acc

  (739) 0x437ac4 FNEG	D0, D1

  (739) 0x437ac8 FDIV	D0, D0, D2

  (739) 0x437acc LDUR	X17, [X29, #464]

  (739) 0x437ad0 LDR	X4, [X17, X30,LSL #3]

  (739) 0x437ad4 SUBS	X8, X26, X4

  (739) 0x437ad8 B.LE	437b58

  (739) 0x437adc CMP	X8, X25

  (739) 0x437ae0 ORR	X9, XZR, X4

  (739) 0x437ae4 B.CC	437b38

  (739) 0x437ae8 LDUR	X10, [X29, #432]

  (739) 0x437aec SUB	X9, XZR, X25

  (739) 0x437af0 DUP	Z1.D, Z0.D[0]

  (739) 0x437af4 ORR	X16, XZR, XZR

  (739) 0x437af8 AND	X11, X8, X9

  (739) 0x437afc ADD	X9, X4, X11

  (739) 0x437b00 ADD	X18, X10, X4,LSL #3

  (739) 0x437b04 LDR	X10, [SP, #8]

  (739) 0x437b08 ADD	X4, X10, X4,LSL #3

    (749) 0x437b0c LD1D	{Z2.D}, P0/Z, [X18, X16,LSL #3]

    (749) 0x437b10 LD1D	{Z3.D}, P0/Z, [X4, X16,LSL #3]

    (749) 0x437b14 FMUL	Z2.D, Z1.D, Z2.D

    (749) 0x437b18 FMUL	Z3.D, Z1.D, Z3.D

    (749) 0x437b1c ST1D	{Z2.D}, P0, [X18, X16,LSL #3]

    (749) 0x437b20 ST1D	{Z3.D}, P0, [X4, X16,LSL #3]

    (749) 0x437b24 ADD	X16, X16, X25

    (749) 0x437b28 CMP	X11, X16

    (749) 0x437b2c B.NE	437b0c

  (739) 0x437b30 CMP	X8, X11

  (739) 0x437b34 B.EQ	437b58

  (739) 0x437b38 LDUR	X8, [X29, #432]

  (739) 0x437b3c ADD	X8, X8, X9,LSL #3

  (739) 0x437b40 SUB	X9, X26, X9

    (748) 0x437b44 LDR	D1, [X8]

    (748) 0x437b48 SUBS	X9, X9, #1

    (748) 0x437b4c FMUL	D1, D0, D1

    (748) 0x437b50 STR	D1, [X8], #8

    (748) 0x437b54 B.NE	437b44

  (739) 0x437b58 LDR	X4, [X1, X30,LSL #3]

  (739) 0x437b5c SUBS	X8, X27, X4

  (739) 0x437b60 B.LE	437740

  (739) 0x437b64 CMP	X8, X25

  (739) 0x437b68 ORR	X9, XZR, X4

  (739) 0x437b6c B.CC	437bcc

  (739) 0x437b70 LDUR	X10, [X29, #424]

  (739) 0x437b74 SUB	X9, XZR, X25

  (739) 0x437b78 DUP	Z1.D, Z0.D[0]

  (739) 0x437b7c ORR	X16, XZR, XZR

  (739) 0x437b80 AND	X11, X8, X9

  (739) 0x437b84 ADD	X9, X4, X11

  (739) 0x437b88 ADD	X18, X10, X4,LSL #3

  (739) 0x437b8c LDR	X10, [SP]

  (739) 0x437b90 ADD	X4, X10, X4,LSL #3

  (739) 0x437b94 HINT	#0

  (739) 0x437b98 HINT	#0

  (739) 0x437b9c HINT	#0

    (747) 0x437ba0 LD1D	{Z2.D}, P0/Z, [X18, X16,LSL #3]

    (747) 0x437ba4 LD1D	{Z3.D}, P0/Z, [X4, X16,LSL #3]

    (747) 0x437ba8 FMUL	Z2.D, Z1.D, Z2.D

    (747) 0x437bac FMUL	Z3.D, Z1.D, Z3.D

    (747) 0x437bb0 ST1D	{Z2.D}, P0, [X18, X16,LSL #3]

    (747) 0x437bb4 ST1D	{Z3.D}, P0, [X4, X16,LSL #3]

    (747) 0x437bb8 ADD	X16, X16, X25

    (747) 0x437bbc CMP	X11, X16

    (747) 0x437bc0 B.NE	437ba0

  (739) 0x437bc4 CMP	X8, X11

  (739) 0x437bc8 B.EQ	437740

  (739) 0x437bcc LDUR	X8, [X29, #424]

  (739) 0x437bd0 ADD	X8, X8, X9,LSL #3

  (739) 0x437bd4 SUB	X9, X27, X9

  (739) 0x437bd8 HINT	#0

  (739) 0x437bdc HINT	#0

    (746) 0x437be0 LDR	D1, [X8]

    (746) 0x437be4 SUBS	X9, X9, #1

    (746) 0x437be8 FMUL	D1, D0, D1

    (746) 0x437bec STR	D1, [X8], #8

    (746) 0x437bf0 B.NE	437be0

  (739) 0x437bf4 B	437740

0x437bf8 ORR	X0, XZR, X19

0x437bfc BL	4ab000

0x437c00 ORR	X0, XZR, X20

0x437c04 LDP	X20, X19, [SP, #288]

0x437c08 LDP	X22, X21, [SP, #272]

0x437c0c LDP	X24, X23, [SP, #256]

0x437c10 LDP	X26, X25, [SP, #240]

0x437c14 LDP	X28, X27, [SP, #224]

0x437c18 LDP	X29, X30, [SP, #208]

0x437c1c ADD	SP, SP, #304

0x437c20 B	4ab000

0x437c24 HINT	#0

0x437c28 HINT	#0

0x437c2c HINT	#0

Coverage (%)	Name	Module
►99.13+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_multi_interp.c:1575-1663
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1575,1585-1599,1605-1663.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 34.67 to 1.50 cycles (23.11x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 29% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 34.67 to 22.04 cycles (1.57x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_CAlloc: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1586
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1589
hypre_Free: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1662
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1596
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1597

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	171
nb uops	155
loop length	684
used w registers	1
used x registers	30
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.38 cycles
front end	19.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	7.50	7.50	10.25	10.25	10.25	10.25	0.00	0.00	0.00	0.00	34.67	34.67	34.67	20.00	20.00
cycles	7.50	7.50	10.25	10.25	10.25	10.25	0.00	0.00	0.00	0.00	34.67	34.67	34.67	20.00	20.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	19.38
Dispatch	34.67
DIV/SQRT	5.00-20.00
Overall L1	34.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	29%
load	26%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 34.67 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4374c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X7, X6, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X4, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X24, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X22, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X28, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X9, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X23, X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X21, X27, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CBZ X0, 4375c4 <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBZ X0, 4375d0 <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4375e0 <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4375fc <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBNZ X0, 4375a8 <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4375fc <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 437634 <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
BL 4acc50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4acc30 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X11, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV X10, X9, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MUL X8, X10, X25	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X25, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X9, X9, X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 437bf8 <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x738>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X2, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTW X25, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X3, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X10, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X10, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X10, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X10, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X10, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X10, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X9, X10, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
RDVL X8, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
STUR X9, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X8, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X17, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 437750 <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x290>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ab000 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4ab000 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_multi_interp.c:1575-1663
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1575,1585-1599,1605-1663.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_CAlloc: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1586
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1589
hypre_Free: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1662
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1596
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1597

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	171
nb uops	155
loop length	684
used w registers	1
used x registers	30
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.38 cycles
front end	19.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	7.50	7.50	10.25	10.25	10.25	10.25	0.00	0.00	0.00	0.00	34.67	34.67	34.67	20.00	20.00
cycles	7.50	7.50	10.25	10.25	10.25	10.25	0.00	0.00	0.00	0.00	34.67	34.67	34.67	20.00	20.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	19.38
Dispatch	34.67
DIV/SQRT	5.00-20.00
Overall L1	34.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	29%
load	26%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 34.67 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4374c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X7, X6, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X4, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X24, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X22, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X28, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X9, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X23, X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X21, X27, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CBZ X0, 4375c4 <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBZ X0, 4375d0 <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4375e0 <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4375fc <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBNZ X0, 4375a8 <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4375fc <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 437634 <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
BL 4acc50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4acc30 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X11, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV X10, X9, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MUL X8, X10, X25	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X25, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X9, X9, X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 437bf8 <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x738>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X2, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTW X25, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X3, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X10, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X10, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X10, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X10, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X10, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X10, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X9, X10, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
RDVL X8, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
STUR X9, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X8, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X17, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 437750 <hypre_BoomerAMGBuildMultipass.omp_outlined.17+0x290>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ab000 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4ab000 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass.omp_outlined.17–	0.26	0.12
○Loop 750 - par_multi_interp.c:1590-1591 - exec	0.08	0.03
▼Loop 740 - par_multi_interp.c:1605-1660 - exec–	0.00	0.00
▼Loop 739 - par_multi_interp.c:1605-1660 - exec–	0.04	0.01
○Loop 743 - par_multi_interp.c:1618-1628 - exec	0.14	0.05
○Loop 745 - par_multi_interp.c:1612-1615 - exec	0.00	0.01
○Loop 744 - par_multi_interp.c:1612-1615 - exec	0.00	0.00
○Loop 741 - par_multi_interp.c:1633-1636 - exec	0.00	0.00
○Loop 742 - par_multi_interp.c:1633-1636 - exec	0.00	0.00
○Loop 747 - par_multi_interp.c:1659-1660 - exec	0.00	0.00
○Loop 746 - par_multi_interp.c:1659-1660 - exec	0.00	0.00
○Loop 749 - par_multi_interp.c:1657-1658 - exec	0.00	0.00
○Loop 748 - par_multi_interp.c:1657-1658 - exec	0.00	0.00
○Loop 751 - par_multi_interp.c:1592-1593 - exec	0.00	0.00

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Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

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Cycles summary

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Vector efficiency ratios

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Front-end bottlenecks

ASM code