OV - exec - Function hypre_BoomerAMGBuildMultipass.omp

	Function: hypre_BoomerAMGBuildMultipass.omp_outlined.19	Module: exec	Source: par_multi_interp.c:1737-1881 [...]	Coverage (incl. loops): 1.01% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1737 - 1881

--------------------------------------------------------------------------------

1737: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa,tmp_array,tmp_array_offd)

[...]

1747:              if (n_fine)

1748:              {    tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); }

1749:              tmp_marker_offd = NULL;

1750:              if (num_cols_offd)

1751:              {    tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); }

1752:              tmp_array = NULL;

1753:              if (n_coarse)

1754:              {    tmp_array = hypre_CTAlloc(HYPRE_Int,n_coarse); }

1755:              tmp_array_offd = NULL;

1756:              if (new_num_cols_offd > n_coarse_offd)

1757:              {    tmp_array_offd = hypre_CTAlloc(HYPRE_Int,new_num_cols_offd); }

1758:              else

1759:              {    tmp_array_offd = hypre_CTAlloc(HYPRE_Int,n_coarse_offd);}

1760:              for (i=0; i < n_fine; i++)

1761:              {    tmp_marker[i] = -1; }

1762:              for (i=0; i < num_cols_offd; i++)

1763:              {    tmp_marker_offd[i] = -1; }

1764:

1765:              /* Compute this thread's range of pass_length */

1766:              my_thread_num = hypre_GetThreadNum();

1767:              num_threads = hypre_NumActiveThreads();

1768:              thread_start = pass_pointer[pass] + (pass_length/num_threads)*my_thread_num;

1769:              if (my_thread_num == num_threads-1)

1770:              {  thread_stop = pass_pointer[pass] + pass_length; }

1771:              else

1772:              {  thread_stop = pass_pointer[pass] + (pass_length/num_threads)*(my_thread_num+1); }

1773:

1774:              for (i=thread_start; i < thread_stop; i++)

1775:              {

1776:                 i1 = pass_array[i];

1777:                 sum_C = 0;

1778:                 sum_N = 0;

1779:                 j_start = P_diag_start[i1];

1780:                 j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1781:                 cnt = P_diag_i[i1];

1782:                 for (j=j_start; j < j_end; j++)

1783:                 {

1784:                    k1 = P_diag_pass[pass][j];

1785:                tmp_array[k1] = cnt;

1786:                P_diag_data[cnt] = 0;

1787:                P_diag_j[cnt++] = k1;

1788:                 }

1789:                 j_start = P_offd_start[i1];

1790:                 j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1791:                 cnt_offd = P_offd_i[i1];

1792:                 for (j=j_start; j < j_end; j++)

1793:                 {

1794:                    k1 = P_offd_pass[pass][j];

1795:                tmp_array_offd[k1] = cnt_offd;

1796:                P_offd_data[cnt_offd] = 0;

1797:                P_offd_j[cnt_offd++] = k1;

1798:                 }

1799:                 for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1800:                 {

1801:                j1 = S_diag_j[j];

1802:                if (assigned[j1] == pass-1)

1803:                   tmp_marker[j1] = i1;

1804:                 }

1805:                 for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1806:                 {

1807:                j1 = S_offd_j[j];

1808:                if (assigned_offd[j1] == pass-1)

1809:                   tmp_marker_offd[j1] = i1;

1810:                 }

1811:                 for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1812:                 {

1813:                j1 = A_diag_j[j];

1814:                if (tmp_marker[j1] == i1)

1815:                {

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

1823:                       }

1824:                   for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++)

1825:                   {

1826:                  k1 = P_offd_j[k];

1827:                      alfa = A_diag_data[j]*P_offd_data[k];

1828:                      P_offd_data[tmp_array_offd[k1]] += alfa;

1829:                      sum_C += alfa;

1830:                      sum_N += alfa;

1831:                       }

1832:                    }

1833:                    else

1834:                    {

1835:                       if (CF_marker[j1] != -3 &&

1836:                 (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1837:                  sum_N += A_diag_data[j];

1838:                    }

1839:                 }

1840:                 for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1841:                 {

1842:                if (col_offd_S_to_A)

1843:                   j1 = map_A_to_S[A_offd_j[j]];

1844:                else

1845:                   j1 = A_offd_j[j];

1846:

1847:                if (j1 > -1 && tmp_marker_offd[j1] == i1)

1848:                {

1849:                   j_start = Pext_start[j1];

1850:                   j_end = j_start+Pext_i[j1+1];

1851:                   for (k=j_start; k < j_end; k++)

1852:                   {

1853:                  k1 = Pext_pass[pass][k];

1854:                      alfa = A_offd_data[j]*Pext_data[k];

1855:                  if (k1 < 0)

1856:                         P_diag_data[tmp_array[-k1-1]] += alfa;

1857:                  else

1858:                         P_offd_data[tmp_array_offd[k1]] += alfa;

1859:                      sum_C += alfa;

1860:                      sum_N += alfa;

1861:                       }

1862:                    }

1863:                    else

1864:                    {

1865:                       if (CF_marker_offd[j1] != -3 &&

1866:                 (num_functions == 1 || dof_func_offd[j1] == dof_func[i1]))

1867:                  sum_N += A_offd_data[j];

1868:                    }

1869:                 }

1870:                 diagonal = A_diag_data[A_diag_i[i1]];

1871:                 if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1872:

1873:                 for (j=P_diag_i[i1]; j < P_diag_i[i1+1]; j++)

1874:                P_diag_data[j] *= alfa;

1875:                 for (j=P_offd_i[i1]; j < P_offd_i[i1+1]; j++)

1876:                P_offd_data[j] *= alfa;

1877:              }

1878:              hypre_TFree(tmp_marker);

1879:              hypre_TFree(tmp_marker_offd);

1880:              hypre_TFree(tmp_array);

1881:              hypre_TFree(tmp_array_offd);

0x437c30 SUB	SP, SP, #480

0x437c34 STP	X29, X30, [SP, #384]

0x437c38 STP	X28, X27, [SP, #400]

0x437c3c STP	X26, X25, [SP, #416]

0x437c40 STP	X24, X23, [SP, #432]

0x437c44 STP	X22, X21, [SP, #448]

0x437c48 STP	X20, X19, [SP, #464]

0x437c4c ADD	X29, SP, #384

0x437c50 LDR	X8, [X29, #376]

0x437c54 STUR	X7, [X29, #440]

0x437c58 LDR	X0, [X2]

0x437c5c ORR	X22, XZR, X6

0x437c60 ORR	X26, XZR, X5

0x437c64 ORR	X21, XZR, X4

0x437c68 ORR	X24, XZR, X3

0x437c6c ORR	X25, XZR, X2

0x437c70 STR	X8, [SP, #152]

0x437c74 LDR	X8, [X29, #368]

0x437c78 STR	X8, [SP, #144]

0x437c7c LDR	X8, [X29, #360]

0x437c80 STR	X8, [SP, #136]

0x437c84 LDR	X8, [X29, #352]

0x437c88 STR	X8, [SP, #128]

0x437c8c LDR	X8, [X29, #344]

0x437c90 STR	X8, [SP, #120]

0x437c94 LDR	X8, [X29, #336]

0x437c98 STR	X8, [SP, #112]

0x437c9c LDR	X8, [X29, #328]

0x437ca0 STR	X8, [SP, #104]

0x437ca4 LDR	X8, [X29, #320]

0x437ca8 STR	X8, [SP, #96]

0x437cac LDR	X8, [X29, #312]

0x437cb0 STR	X8, [SP, #88]

0x437cb4 LDP	X8, X9, [X29, #296]

0x437cb8 STP	X8, X9, [X29, #976]

0x437cbc LDP	X8, X9, [X29, #280]

0x437cc0 STP	X8, X9, [X29, #960]

0x437cc4 LDR	X8, [X29, #272]

0x437cc8 STR	X8, [SP, #80]

0x437ccc LDR	X8, [X29, #264]

0x437cd0 STR	X8, [SP, #176]

0x437cd4 LDP	X10, X9, [X29, #248]

0x437cd8 STUR	X9, [X29, #496]

0x437cdc LDP	X11, X9, [X29, #232]

0x437ce0 STP	X10, X9, [X29, #864]

0x437ce4 LDP	X10, X9, [X29, #216]

0x437ce8 STP	X11, X9, [X29, #880]

0x437cec LDP	X8, X9, [X29, #200]

0x437cf0 STUR	X8, [X29, #400]

0x437cf4 LDR	X8, [X29, #192]

0x437cf8 STP	X10, X9, [X29, #896]

0x437cfc STR	X8, [SP, #168]

0x437d00 LDP	X10, X9, [X29, #176]

0x437d04 STUR	X9, [X29, #488]

0x437d08 LDP	X8, X9, [X29, #160]

0x437d0c STP	X10, X8, [X29, #920]

0x437d10 LDR	X8, [X29, #152]

0x437d14 STUR	X9, [X29, #344]

0x437d18 STR	X8, [SP, #160]

0x437d1c LDP	X10, X9, [X29, #136]

0x437d20 LDP	X27, X23, [X29, #104]

0x437d24 LDR	X28, [X29, #96]

0x437d28 STUR	X9, [X29, #480]

0x437d2c LDP	X8, X9, [X29, #120]

0x437d30 STUR	X9, [X29, #336]

0x437d34 STP	X10, X8, [X29, #936]

0x437d38 CBZ	X0, 437d74

0x437d3c MOVZ	W1, #8

0x437d40 BL	4aaf00

0x437d44 ORR	X19, XZR, X0

0x437d48 LDR	X0, [X24]

0x437d4c CBZ	X0, 437d80

0x437d50 MOVZ	W1, #8

0x437d54 BL	4aaf00

0x437d58 ORR	X20, XZR, X0

0x437d5c LDR	X0, [X21]

0x437d60 CBZ	X0, 437d8c

0x437d64 MOVZ	W1, #8

0x437d68 BL	4aaf00

0x437d6c ORR	X21, XZR, X0

0x437d70 B	437d90

0x437d74 ORR	X19, XZR, XZR

0x437d78 LDR	X0, [X24]

0x437d7c CBNZ	X0, 437d50

0x437d80 ORR	X20, XZR, XZR

0x437d84 LDR	X0, [X21]

0x437d88 CBNZ	X0, 437d64

0x437d8c ORR	X21, XZR, XZR

0x437d90 LDR	X8, [X26]

0x437d94 LDR	X9, [X22]

0x437d98 MOVZ	W1, #8

0x437d9c CMP	X8, X9

0x437da0 CSEL	X0, X8, X9, #12

0x437da4 BL	4aaf00

0x437da8 LDR	X8, [X25]

0x437dac ORR	X22, XZR, X0

0x437db0 CMP	X8, #1

0x437db4 B.LT	437dd4

0x437db8 MOVN	X9, #0

0x437dbc ORR	X8, XZR, XZR

(767) 0x437dc0 STR	X9, [X19, X8,LSL #3]

(767) 0x437dc4 ADD	X8, X8, #1

(767) 0x437dc8 LDR	X10, [X25]

(767) 0x437dcc CMP	X8, X10

(767) 0x437dd0 B.LT	437dc0

0x437dd4 LDR	X8, [X24]

0x437dd8 CMP	X8, #1

0x437ddc B.LT	437dfc

0x437de0 MOVN	X9, #0

0x437de4 ORR	X8, XZR, XZR

(766) 0x437de8 STR	X9, [X20, X8,LSL #3]

(766) 0x437dec ADD	X8, X8, #1

(766) 0x437df0 LDR	X10, [X24]

(766) 0x437df4 CMP	X8, X10

(766) 0x437df8 B.LT	437de8

0x437dfc BL	4acc50

0x437e00 ORR	X24, XZR, X0

0x437e04 BL	4acc30

0x437e08 LDR	X9, [X27]

0x437e0c SUB	X11, X0, #1

0x437e10 SDIV	X10, X9, X0

0x437e14 MUL	X8, X10, X24

0x437e18 ADD	X10, X10, X8

0x437e1c CMP	X24, X11

0x437e20 CSEL	X9, X9, X10, #0

0x437e24 CMP	X8, X9

0x437e28 B.GE	4386f8

0x437e2c LDUR	X10, [X29, #440]

0x437e30 LDUR	X12, [X29, #480]

0x437e34 LDR	X11, [X28]

0x437e38 PTRUE	P0.D, ALL

0x437e3c LDR	X10, [X10]

0x437e40 LDR	X13, [X12]

0x437e44 LDR	X12, [SP, #160]

0x437e48 LDR	X15, [X12]

0x437e4c LDUR	X12, [X29, #488]

0x437e50 LDR	X10, [X10, X11,LSL #3]

0x437e54 LDR	X11, [X23]

0x437e58 LDR	X16, [X12]

0x437e5c LDR	X12, [SP, #168]

0x437e60 STUR	X11, [X29, #440]

0x437e64 LDUR	X11, [X29, #432]

0x437e68 ADD	X9, X9, X10

0x437e6c LDR	X11, [X11]

0x437e70 LDR	X12, [X12]

0x437e74 STUR	X11, [X29, #432]

0x437e78 LDUR	X11, [X29, #336]

0x437e7c LDR	X14, [X11]

0x437e80 LDUR	X11, [X29, #424]

0x437e84 LDR	X0, [X11]

0x437e88 LDUR	X11, [X29, #416]

0x437e8c LDR	X11, [X11]

0x437e90 STUR	X11, [X29, #416]

0x437e94 LDUR	X11, [X29, #344]

0x437e98 LDR	X17, [X11]

0x437e9c LDUR	X11, [X29, #408]

0x437ea0 LDR	X1, [X11]

0x437ea4 LDUR	X11, [X29, #400]

0x437ea8 LDR	X2, [X11]

0x437eac LDUR	X11, [X29, #392]

0x437eb0 LDR	X3, [X11]

0x437eb4 LDUR	X11, [X29, #384]

0x437eb8 LDR	X4, [X11]

0x437ebc LDUR	X11, [X29, #376]

0x437ec0 LDR	X5, [X11]

0x437ec4 LDUR	X11, [X29, #368]

0x437ec8 LDR	X6, [X11]

0x437ecc LDUR	X11, [X29, #360]

0x437ed0 LDR	X7, [X11]

0x437ed4 LDUR	X11, [X29, #352]

0x437ed8 LDR	X11, [X11]

0x437edc STUR	X11, [X29, #352]

0x437ee0 LDUR	X11, [X29, #496]

0x437ee4 LDR	X11, [X11]

0x437ee8 STUR	X11, [X29, #496]

0x437eec LDUR	X11, [X29, #464]

0x437ef0 LDR	X11, [X11]

0x437ef4 STUR	X11, [X29, #344]

0x437ef8 LDUR	X11, [X29, #472]

0x437efc LDR	X25, [X11]

0x437f00 LDR	X11, [SP, #176]

0x437f04 LDR	X11, [X11]

0x437f08 STUR	X11, [X29, #336]

0x437f0c CNTW	X11, ALL

0x437f10 SUB	X11, XZR, X11

0x437f14 STR	X11, [SP, #72]

0x437f18 STUR	X9, [X29, #328]

0x437f1c ADD	X9, X8, X10

0x437f20 RDVL	X8, #1

0x437f24 ADD	X11, X13, #8

0x437f28 ADD	X10, X15, #8

0x437f2c STP	X12, X15, [SP, #56]

0x437f30 STP	X16, X13, [SP, #184]

0x437f34 STP	X10, X11, [SP, #40]

0x437f38 ADD	X11, X16, #8

0x437f3c ADD	X10, X12, #8

0x437f40 STP	X10, X11, [SP, #24]

0x437f44 ADD	X10, X13, X8

0x437f48 ADD	X8, X16, X8

0x437f4c STP	X8, X10, [SP, #8]

0x437f50 STUR	X0, [X29, #424]

0x437f54 STP	X2, X1, [X29, #912]

0x437f58 STP	X4, X3, [X29, #896]

0x437f5c STP	X6, X5, [X29, #880]

0x437f60 STUR	X7, [X29, #360]

0x437f64 B	437f7c

(752) 0x437f68 LDUR	X9, [X29, #472]

(752) 0x437f6c LDUR	X8, [X29, #328]

(752) 0x437f70 ADD	X9, X9, #1

(752) 0x437f74 CMP	X9, X8

(752) 0x437f78 B.GE	4386f8

(752) 0x437f7c LDUR	X8, [X29, #440]

(752) 0x437f80 STUR	X9, [X29, #472]

(752) 0x437f84 LDR	X8, [X8, X9,LSL #3]

(752) 0x437f88 LDUR	X9, [X29, #432]

(752) 0x437f8c ADD	X10, X8, #1

(752) 0x437f90 LDR	X9, [X9, X8,LSL #3]

(752) 0x437f94 LDR	X12, [X14, X8,LSL #3]

(752) 0x437f98 LDR	X13, [X14, X10,LSL #3]

(752) 0x437f9c ADD	X11, X13, X9

(752) 0x437fa0 SUB	X11, X11, X12

(752) 0x437fa4 CMP	X9, X11

(752) 0x437fa8 B.GE	438048

(752) 0x437fac SUB	W16, W13, W12

(752) 0x437fb0 ADD	X15, X12, #1

(752) 0x437fb4 TBZ	W16, #0, 437fe0

(752) 0x437fb8 LDR	X16, [X28]

(752) 0x437fbc LDR	X18, [SP, #192]

(752) 0x437fc0 LDR	X16, [X0, X16,LSL #3]

(752) 0x437fc4 STR	XZR, [X18, X12,LSL #3]

(752) 0x437fc8 LDR	X18, [SP, #64]

(752) 0x437fcc LDR	X16, [X16, X9,LSL #3]

(752) 0x437fd0 ADD	X9, X9, #1

(752) 0x437fd4 STR	X12, [X21, X16,LSL #3]

(752) 0x437fd8 STR	X16, [X18, X12,LSL #3]

(752) 0x437fdc ORR	X12, XZR, X15

(752) 0x437fe0 CMP	X13, X15

(752) 0x437fe4 B.EQ	438048

(752) 0x437fe8 LDP	X15, X13, [SP, #40]

(752) 0x437fec ADD	X13, X13, X12,LSL #3

(752) 0x437ff0 ADD	X15, X15, X12,LSL #3

(752) 0x437ff4 HINT	#0

(752) 0x437ff8 HINT	#0

(752) 0x437ffc HINT	#0

  (761) 0x438000 LDR	X16, [X28]

  (761) 0x438004 ADD	X18, X12, #1

  (761) 0x438008 LDR	X16, [X0, X16,LSL #3]

  (761) 0x43800c LDR	X16, [X16, X9,LSL #3]

  (761) 0x438010 STR	X12, [X21, X16,LSL #3]

  (761) 0x438014 STP	XZR, XZR, [X13, #1016]

  (761) 0x438018 STUR	X16, [X15, #504]

  (761) 0x43801c ADD	X13, X13, #16

  (761) 0x438020 ADD	X12, X12, #2

  (761) 0x438024 LDR	X16, [X28]

  (761) 0x438028 LDR	X16, [X0, X16,LSL #3]

  (761) 0x43802c ADD	X16, X16, X9,LSL #3

  (761) 0x438030 ADD	X9, X9, #2

  (761) 0x438034 LDR	X16, [X16, #8]

  (761) 0x438038 CMP	X11, X9

  (761) 0x43803c STR	X18, [X21, X16,LSL #3]

  (761) 0x438040 STR	X16, [X15], #16

  (761) 0x438044 B.NE	438000

(752) 0x438048 LDUR	X9, [X29, #416]

(752) 0x43804c LDR	X13, [X17, X10,LSL #3]

(752) 0x438050 LDR	X12, [X17, X8,LSL #3]

(752) 0x438054 LDR	X9, [X9, X8,LSL #3]

(752) 0x438058 ADD	X11, X13, X9

(752) 0x43805c SUB	X11, X11, X12

(752) 0x438060 CMP	X9, X11

(752) 0x438064 B.GE	438108

(752) 0x438068 SUB	W16, W13, W12

(752) 0x43806c ADD	X15, X12, #1

(752) 0x438070 TBZ	W16, #0, 43809c

(752) 0x438074 LDR	X16, [X28]

(752) 0x438078 LDR	X18, [SP, #184]

(752) 0x43807c LDR	X16, [X1, X16,LSL #3]

(752) 0x438080 STR	XZR, [X18, X12,LSL #3]

(752) 0x438084 LDR	X18, [SP, #56]

(752) 0x438088 LDR	X16, [X16, X9,LSL #3]

(752) 0x43808c ADD	X9, X9, #1

(752) 0x438090 STR	X12, [X22, X16,LSL #3]

(752) 0x438094 STR	X16, [X18, X12,LSL #3]

(752) 0x438098 ORR	X12, XZR, X15

(752) 0x43809c CMP	X13, X15

(752) 0x4380a0 B.EQ	438108

(752) 0x4380a4 LDP	X15, X13, [SP, #24]

(752) 0x4380a8 ADD	X13, X13, X12,LSL #3

(752) 0x4380ac ADD	X15, X15, X12,LSL #3

(752) 0x4380b0 HINT	#0

(752) 0x4380b4 HINT	#0

(752) 0x4380b8 HINT	#0

(752) 0x4380bc HINT	#0

  (760) 0x4380c0 LDR	X16, [X28]

  (760) 0x4380c4 ADD	X18, X12, #1

  (760) 0x4380c8 LDR	X16, [X1, X16,LSL #3]

  (760) 0x4380cc LDR	X16, [X16, X9,LSL #3]

  (760) 0x4380d0 STR	X12, [X22, X16,LSL #3]

  (760) 0x4380d4 STP	XZR, XZR, [X13, #1016]

  (760) 0x4380d8 STUR	X16, [X15, #504]

  (760) 0x4380dc ADD	X13, X13, #16

  (760) 0x4380e0 ADD	X12, X12, #2

  (760) 0x4380e4 LDR	X16, [X28]

  (760) 0x4380e8 LDR	X16, [X1, X16,LSL #3]

  (760) 0x4380ec ADD	X16, X16, X9,LSL #3

  (760) 0x4380f0 ADD	X9, X9, #2

  (760) 0x4380f4 LDR	X16, [X16, #8]

  (760) 0x4380f8 CMP	X11, X9

  (760) 0x4380fc STR	X18, [X22, X16,LSL #3]

  (760) 0x438100 STR	X16, [X15], #16

  (760) 0x438104 B.NE	4380c0

(752) 0x438108 LDR	X9, [X2, X8,LSL #3]

(752) 0x43810c LDR	X11, [X2, X10,LSL #3]

(752) 0x438110 B	438124

0x438114 HINT	#0

0x438118 HINT	#0

0x43811c HINT	#0

  (759) 0x438120 ADD	X9, X9, #1

  (759) 0x438124 CMP	X9, X11

  (759) 0x438128 B.GE	438160

  (759) 0x43812c LDR	X12, [X3, X9,LSL #3]

  (759) 0x438130 LDR	X15, [X28]

  (759) 0x438134 LDR	X13, [X4, X12,LSL #3]

  (759) 0x438138 SUB	X15, X15, #1

  (759) 0x43813c CMP	X13, X15

  (759) 0x438140 B.NE	438120

  (759) 0x438144 STR	X8, [X19, X12,LSL #3]

  (759) 0x438148 LDR	X11, [X2, X10,LSL #3]

  (759) 0x43814c B	438120

0x438150 HINT	#0

0x438154 HINT	#0

0x438158 HINT	#0

0x43815c HINT	#0

(752) 0x438160 LDR	X9, [X5, X8,LSL #3]

(752) 0x438164 LDR	X11, [X5, X10,LSL #3]

(752) 0x438168 B	438170

  (758) 0x43816c ADD	X9, X9, #1

  (758) 0x438170 CMP	X9, X11

  (758) 0x438174 B.GE	4381a0

  (758) 0x438178 LDR	X12, [X6, X9,LSL #3]

  (758) 0x43817c LDR	X15, [X28]

  (758) 0x438180 LDR	X13, [X7, X12,LSL #3]

  (758) 0x438184 SUB	X15, X15, #1

  (758) 0x438188 CMP	X13, X15

  (758) 0x43818c B.NE	43816c

  (758) 0x438190 STR	X8, [X20, X12,LSL #3]

  (758) 0x438194 LDR	X11, [X5, X10,LSL #3]

  (758) 0x438198 B	43816c

0x43819c HINT	#0

(752) 0x4381a0 LDUR	X9, [X29, #352]

(752) 0x4381a4 MOVI	D2, #0

(752) 0x4381a8 LDR	X11, [X9, X8,LSL #3]

(752) 0x4381ac LDR	X13, [X9, X10,LSL #3]

(752) 0x4381b0 ADD	X16, X11, #1

(752) 0x4381b4 STUR	X11, [X29, #464]

(752) 0x4381b8 CMP	X16, X13

(752) 0x4381bc B.GE	438404

(752) 0x4381c0 LDR	X9, [SP, #80]

(752) 0x4381c4 MOVI	D1, #0

(752) 0x4381c8 LDR	X26, [X9]

(752) 0x4381cc LDP	X9, X11, [X29, #960]

(752) 0x4381d0 LDR	X6, [X11]

(752) 0x4381d4 LDR	X11, [SP, #176]

(752) 0x4381d8 LDR	X9, [X9]

(752) 0x4381dc LDR	X24, [X11]

(752) 0x4381e0 LDR	X11, [SP, #160]

(752) 0x4381e4 LDR	X4, [X11]

(752) 0x4381e8 LDUR	X11, [X29, #480]

(752) 0x4381ec LDR	X27, [X11]

(752) 0x4381f0 LDR	X11, [SP, #168]

(752) 0x4381f4 ADD	X5, X4, #8

(752) 0x4381f8 LDR	X12, [X11]

(752) 0x4381fc LDUR	X11, [X29, #488]

(752) 0x438200 ADD	X7, X27, #8

(752) 0x438204 LDR	X11, [X11]

(752) 0x438208 B	43822c

  (755) 0x43820c LDR	D3, [X24, X16,LSL #3]

  (755) 0x438210 FADD	D1, D1, D3

  (755) 0x438214 HINT	#0

  (755) 0x438218 HINT	#0

  (755) 0x43821c HINT	#0

  (755) 0x438220 ADD	X16, X16, #1

  (755) 0x438224 CMP	X16, X13

  (755) 0x438228 B.EQ	438408

  (755) 0x43822c LDUR	X15, [X29, #496]

  (755) 0x438230 LDR	X0, [X15, X16,LSL #3]

  (755) 0x438234 LDR	X15, [X19, X0,LSL #3]

  (755) 0x438238 CMP	X15, X8

  (755) 0x43823c B.NE	43826c

  (755) 0x438240 ADD	X1, X0, #1

  (755) 0x438244 LDR	X15, [X14, X0,LSL #3]

  (755) 0x438248 LDR	X3, [X14, X1,LSL #3]

  (755) 0x43824c CMP	X3, X15

  (755) 0x438250 B.LE	438338

  (755) 0x438254 SUB	W2, W3, W15

  (755) 0x438258 ADD	X18, X15, #1

  (755) 0x43825c TBNZ	W2, #0, 438294

  (755) 0x438260 CMP	X3, X18

  (755) 0x438264 B.NE	4382c8

  (755) 0x438268 B	438338

  (755) 0x43826c LDR	X15, [X26, X0,LSL #3]

  (755) 0x438270 CMN	X15, #3

  (755) 0x438274 B.EQ	438220

  (755) 0x438278 CMP	X9, #1

  (755) 0x43827c B.EQ	43820c

  (755) 0x438280 LDR	X15, [X6, X8,LSL #3]

  (755) 0x438284 LDR	X18, [X6, X0,LSL #3]

  (755) 0x438288 CMP	X15, X18

  (755) 0x43828c B.EQ	43820c

  (755) 0x438290 B	438220

  (755) 0x438294 LDR	X2, [X4, X15,LSL #3]

  (755) 0x438298 LDR	D0, [X24, X16,LSL #3]

  (755) 0x43829c LDR	D3, [X27, X15,LSL #3]

  (755) 0x4382a0 FMUL	D0, D0, D3

  (755) 0x4382a4 LDR	X15, [X21, X2,LSL #3]

  (755) 0x4382a8 LDR	D3, [X27, X15,LSL #3]

  (755) 0x4382ac FADD	D2, D2, D0

  (755) 0x4382b0 FADD	D1, D1, D0

  (755) 0x4382b4 FADD	D3, D0, D3

  (755) 0x4382b8 STR	D3, [X27, X15,LSL #3]

  (755) 0x4382bc ORR	X15, XZR, X18

  (755) 0x4382c0 CMP	X3, X18

  (755) 0x4382c4 B.EQ	438338

  (755) 0x4382c8 SUB	X3, X3, X15

  (755) 0x4382cc ADD	X30, X5, X15,LSL #3

  (755) 0x4382d0 ADD	X23, X7, X15,LSL #3

  (755) 0x4382d4 HINT	#0

  (755) 0x4382d8 HINT	#0

  (755) 0x4382dc HINT	#0

    (757) 0x4382e0 LDP	X15, X18, [X30, #1016]

    (757) 0x4382e4 LDR	D0, [X24, X16,LSL #3]

    (757) 0x4382e8 SUBS	X3, X3, #2

    (757) 0x4382ec ADD	X30, X30, #16

    (757) 0x4382f0 LDUR	D3, [X23, #504]

    (757) 0x4382f4 FMUL	D0, D0, D3

    (757) 0x4382f8 LDR	X15, [X21, X15,LSL #3]

    (757) 0x4382fc LDR	D3, [X27, X15,LSL #3]

    (757) 0x438300 FADD	D2, D2, D0

    (757) 0x438304 FADD	D1, D1, D0

    (757) 0x438308 FADD	D3, D0, D3

    (757) 0x43830c STR	D3, [X27, X15,LSL #3]

    (757) 0x438310 LDR	X15, [X21, X18,LSL #3]

    (757) 0x438314 LDR	D0, [X24, X16,LSL #3]

    (757) 0x438318 LDR	D3, [X23], #16

    (757) 0x43831c FMUL	D0, D0, D3

    (757) 0x438320 LDR	D3, [X27, X15,LSL #3]

    (757) 0x438324 FADD	D2, D2, D0

    (757) 0x438328 FADD	D1, D1, D0

    (757) 0x43832c FADD	D3, D0, D3

    (757) 0x438330 STR	D3, [X27, X15,LSL #3]

    (757) 0x438334 B.NE	4382e0

  (755) 0x438338 LDR	X15, [X17, X0,LSL #3]

  (755) 0x43833c LDR	X0, [X17, X1,LSL #3]

  (755) 0x438340 CMP	X0, X15

  (755) 0x438344 B.LE	438220

  (755) 0x438348 SUB	W1, W0, W15

  (755) 0x43834c ADD	X18, X15, #1

  (755) 0x438350 TBNZ	W1, #0, 438360

  (755) 0x438354 CMP	X0, X18

  (755) 0x438358 B.EQ	438220

  (755) 0x43835c B	438394

  (755) 0x438360 LDR	X1, [X12, X15,LSL #3]

  (755) 0x438364 LDR	D0, [X24, X16,LSL #3]

  (755) 0x438368 LDR	D3, [X11, X15,LSL #3]

  (755) 0x43836c FMUL	D0, D0, D3

  (755) 0x438370 LDR	X15, [X22, X1,LSL #3]

  (755) 0x438374 LDR	D3, [X11, X15,LSL #3]

  (755) 0x438378 FADD	D2, D2, D0

  (755) 0x43837c FADD	D1, D1, D0

  (755) 0x438380 FADD	D3, D0, D3

  (755) 0x438384 STR	D3, [X11, X15,LSL #3]

  (755) 0x438388 ORR	X15, XZR, X18

  (755) 0x43838c CMP	X0, X18

  (755) 0x438390 B.EQ	438220

  (755) 0x438394 ADD	X18, X12, #8

  (755) 0x438398 SUB	X0, X0, X15

  (755) 0x43839c ADD	X1, X18, X15,LSL #3

  (755) 0x4383a0 ADD	X18, X11, #8

  (755) 0x4383a4 ADD	X3, X18, X15,LSL #3

    (756) 0x4383a8 LDP	X15, X18, [X1, #1016]

    (756) 0x4383ac LDR	D0, [X24, X16,LSL #3]

    (756) 0x4383b0 SUBS	X0, X0, #2

    (756) 0x4383b4 ADD	X1, X1, #16

    (756) 0x4383b8 LDUR	D3, [X3, #504]

    (756) 0x4383bc FMUL	D0, D0, D3

    (756) 0x4383c0 LDR	X15, [X22, X15,LSL #3]

    (756) 0x4383c4 LDR	D3, [X11, X15,LSL #3]

    (756) 0x4383c8 FADD	D2, D2, D0

    (756) 0x4383cc FADD	D1, D1, D0

    (756) 0x4383d0 FADD	D3, D0, D3

    (756) 0x4383d4 STR	D3, [X11, X15,LSL #3]

    (756) 0x4383d8 LDR	X15, [X22, X18,LSL #3]

    (756) 0x4383dc LDR	D0, [X24, X16,LSL #3]

    (756) 0x4383e0 LDR	D3, [X3], #16

    (756) 0x4383e4 FMUL	D0, D0, D3

    (756) 0x4383e8 LDR	D3, [X11, X15,LSL #3]

    (756) 0x4383ec FADD	D2, D2, D0

    (756) 0x4383f0 FADD	D1, D1, D0

    (756) 0x4383f4 FADD	D3, D0, D3

    (756) 0x4383f8 STR	D3, [X11, X15,LSL #3]

    (756) 0x4383fc B.NE	4383a8

  (755) 0x438400 B	438220

(752) 0x438404 MOVI	D1, #0

(752) 0x438408 LDUR	X11, [X29, #344]

(752) 0x43840c LDR	X9, [X11, X8,LSL #3]

(752) 0x438410 LDR	X11, [X11, X10,LSL #3]

(752) 0x438414 CMP	X9, X11

(752) 0x438418 B.GE	438580

(752) 0x43841c LDR	X15, [SP, #144]

(752) 0x438420 LDP	X12, X13, [SP, #88]

(752) 0x438424 LDR	X3, [X28]

(752) 0x438428 LDR	X16, [X15]

(752) 0x43842c LDUR	X15, [X29, #448]

(752) 0x438430 LDR	X12, [X12]

(752) 0x438434 LDR	X13, [X13]

(752) 0x438438 LDR	X6, [X15]

(752) 0x43843c LDR	X15, [SP, #152]

(752) 0x438440 LDR	X23, [X15]

(752) 0x438444 LDUR	X15, [X29, #456]

(752) 0x438448 LDR	X24, [X15]

(752) 0x43844c LDR	X15, [SP, #128]

(752) 0x438450 LDR	X26, [X15]

(752) 0x438454 LDR	X15, [SP, #104]

(752) 0x438458 LDR	X27, [X15]

(752) 0x43845c LDR	X15, [SP, #112]

(752) 0x438460 LDR	X30, [X15]

(752) 0x438464 LDR	X15, [SP, #120]

(752) 0x438468 LDR	X0, [X15]

(752) 0x43846c LDR	X15, [SP, #136]

(752) 0x438470 LDR	X1, [X15]

(752) 0x438474 B	438494

0x438478 HINT	#0

0x43847c HINT	#0

  (753) 0x438480 LDR	D3, [X26, X9,LSL #3]

  (753) 0x438484 FADD	D1, D1, D3

  (753) 0x438488 ADD	X9, X9, #1

  (753) 0x43848c CMP	X9, X11

  (753) 0x438490 B.EQ	438580

  (753) 0x438494 ADD	X15, X13, X9,LSL #3

  (753) 0x438498 CBZ	X25, 4384a4

  (753) 0x43849c LDR	X15, [X15]

  (753) 0x4384a0 ADD	X15, X12, X15,LSL #3

  (753) 0x4384a4 LDR	X15, [X15]

  (753) 0x4384a8 TBNZ	X15, #63, 43854c

  (753) 0x4384ac LDR	X18, [X20, X15,LSL #3]

  (753) 0x4384b0 CMP	X18, X8

  (753) 0x4384b4 B.NE	43854c

  (753) 0x4384b8 ADD	X18, X30, X15,LSL #3

  (753) 0x4384bc LDR	X18, [X18, #8]

  (753) 0x4384c0 CMP	X18, #1

  (753) 0x4384c4 B.LT	438488

  (753) 0x4384c8 UBFM	X15, X15, #61, #60

  (753) 0x4384cc LDR	X5, [X0, X3,LSL #3]

  (753) 0x4384d0 LDR	X2, [X27, X15]

  (753) 0x4384d4 ADD	X4, X18, X2

  (753) 0x4384d8 LDP	X18, X15, [X29, #992]

  (753) 0x4384dc LDR	X15, [X15]

  (753) 0x4384e0 LDR	X18, [X18]

  (753) 0x4384e4 B	438510

    (754) 0x4384e8 ORN	X7, XZR, X7

    (754) 0x4384ec LDR	X7, [X21, X7,LSL #3]

    (754) 0x4384f0 LDR	D3, [X18, X7,LSL #3]

    (754) 0x4384f4 FADD	D3, D0, D3

    (754) 0x4384f8 STR	D3, [X18, X7,LSL #3]

    (754) 0x4384fc FADD	D2, D2, D0

    (754) 0x438500 FADD	D1, D1, D0

    (754) 0x438504 ADD	X2, X2, #1

    (754) 0x438508 CMP	X2, X4

    (754) 0x43850c B.GE	438488

    (754) 0x438510 LDR	D0, [X26, X9,LSL #3]

    (754) 0x438514 LDR	D3, [X1, X2,LSL #3]

    (754) 0x438518 LDR	X7, [X5, X2,LSL #3]

    (754) 0x43851c FMUL	D0, D0, D3

    (754) 0x438520 TBNZ	X7, #63, 4384e8

    (754) 0x438524 LDR	X7, [X22, X7,LSL #3]

    (754) 0x438528 LDR	D3, [X15, X7,LSL #3]

    (754) 0x43852c FADD	D3, D0, D3

    (754) 0x438530 STR	D3, [X15, X7,LSL #3]

    (754) 0x438534 FADD	D2, D2, D0

    (754) 0x438538 FADD	D1, D1, D0

    (754) 0x43853c ADD	X2, X2, #1

    (754) 0x438540 CMP	X2, X4

    (754) 0x438544 B.LT	438510

  (753) 0x438548 B	438488

  (753) 0x43854c LDR	X18, [X16, X15,LSL #3]

  (753) 0x438550 CMN	X18, #3

  (753) 0x438554 B.EQ	438488

  (753) 0x438558 CMP	X6, #1

  (753) 0x43855c B.EQ	438480

  (753) 0x438560 LDR	X15, [X23, X15,LSL #3]

  (753) 0x438564 LDR	X18, [X24, X8,LSL #3]

  (753) 0x438568 CMP	X15, X18

  (753) 0x43856c B.EQ	438480

  (753) 0x438570 B	438488

0x438574 HINT	#0

0x438578 HINT	#0

0x43857c HINT	#0

(752) 0x438580 LDUR	X9, [X29, #336]

(752) 0x438584 LDUR	X11, [X29, #464]

(752) 0x438588 LDR	D3, [X9, X11,LSL #3]

(752) 0x43858c FMUL	D2, D2, D3

(752) 0x438590 FCMP	D2, #0

(752) 0x438594 B.EQ	4385a0

(752) 0x438598 FNEG	D0, D1

(752) 0x43859c FDIV	D0, D0, D2

(752) 0x4385a0 LDR	X18, [X14, X8,LSL #3]

(752) 0x4385a4 LDR	X9, [X14, X10,LSL #3]

(752) 0x4385a8 LDUR	X0, [X29, #424]

(752) 0x4385ac CNTW	X23, ALL

(752) 0x4385b0 SUBS	X11, X9, X18

(752) 0x4385b4 LDP	X2, X1, [X29, #912]

(752) 0x4385b8 LDUR	X7, [X29, #360]

(752) 0x4385bc LDP	X4, X3, [X29, #896]

(752) 0x4385c0 LDP	X6, X5, [X29, #880]

(752) 0x4385c4 B.LE	438654

(752) 0x4385c8 CMP	X11, X23

(752) 0x4385cc ORR	X12, XZR, X18

(752) 0x4385d0 B.CC	43862c

(752) 0x4385d4 LDR	X12, [SP, #72]

(752) 0x4385d8 LDR	X16, [SP, #192]

(752) 0x4385dc LDR	X24, [SP, #16]

(752) 0x4385e0 DUP	Z1.D, Z0.D[0]

(752) 0x4385e4 ORR	X15, XZR, XZR

(752) 0x4385e8 AND	X13, X11, X12

(752) 0x4385ec ADD	X16, X16, X18,LSL #3

(752) 0x4385f0 ADD	X12, X18, X13

(752) 0x4385f4 ADD	X18, X24, X18,LSL #3

(752) 0x4385f8 HINT	#0

(752) 0x4385fc HINT	#0

  (765) 0x438600 LD1D	{Z2.D}, P0/Z, [X16, X15,LSL #3]

  (765) 0x438604 LD1D	{Z3.D}, P0/Z, [X18, X15,LSL #3]

  (765) 0x438608 FMUL	Z2.D, Z1.D, Z2.D

  (765) 0x43860c FMUL	Z3.D, Z1.D, Z3.D

  (765) 0x438610 ST1D	{Z2.D}, P0, [X16, X15,LSL #3]

  (765) 0x438614 ST1D	{Z3.D}, P0, [X18, X15,LSL #3]

  (765) 0x438618 ADD	X15, X15, X23

  (765) 0x43861c CMP	X13, X15

  (765) 0x438620 B.NE	438600

(752) 0x438624 CMP	X11, X13

(752) 0x438628 B.EQ	438654

(752) 0x43862c LDR	X11, [SP, #192]

(752) 0x438630 SUB	X9, X9, X12

(752) 0x438634 ADD	X11, X11, X12,LSL #3

(752) 0x438638 HINT	#0

(752) 0x43863c HINT	#0

  (764) 0x438640 LDR	D1, [X11]

  (764) 0x438644 SUBS	X9, X9, #1

  (764) 0x438648 FMUL	D1, D0, D1

  (764) 0x43864c STR	D1, [X11], #8

  (764) 0x438650 B.NE	438640

(752) 0x438654 LDR	X15, [X17, X8,LSL #3]

(752) 0x438658 LDR	X8, [X17, X10,LSL #3]

(752) 0x43865c SUBS	X9, X8, X15

(752) 0x438660 B.LE	437f68

(752) 0x438664 CMP	X9, X23

(752) 0x438668 ORR	X10, XZR, X15

(752) 0x43866c B.CC	4386cc

(752) 0x438670 LDR	X10, [SP, #72]

(752) 0x438674 LDR	X13, [SP, #184]

(752) 0x438678 LDR	X16, [SP, #8]

(752) 0x43867c DUP	Z1.D, Z0.D[0]

(752) 0x438680 ORR	X12, XZR, XZR

(752) 0x438684 AND	X11, X9, X10

(752) 0x438688 ADD	X13, X13, X15,LSL #3

(752) 0x43868c ADD	X10, X15, X11

(752) 0x438690 ADD	X15, X16, X15,LSL #3

(752) 0x438694 HINT	#0

(752) 0x438698 HINT	#0

(752) 0x43869c HINT	#0

  (763) 0x4386a0 LD1D	{Z2.D}, P0/Z, [X13, X12,LSL #3]

  (763) 0x4386a4 LD1D	{Z3.D}, P0/Z, [X15, X12,LSL #3]

  (763) 0x4386a8 FMUL	Z2.D, Z1.D, Z2.D

  (763) 0x4386ac FMUL	Z3.D, Z1.D, Z3.D

  (763) 0x4386b0 ST1D	{Z2.D}, P0, [X13, X12,LSL #3]

  (763) 0x4386b4 ST1D	{Z3.D}, P0, [X15, X12,LSL #3]

  (763) 0x4386b8 ADD	X12, X12, X23

  (763) 0x4386bc CMP	X11, X12

  (763) 0x4386c0 B.NE	4386a0

(752) 0x4386c4 CMP	X9, X11

(752) 0x4386c8 B.EQ	437f68

(752) 0x4386cc LDR	X9, [SP, #184]

(752) 0x4386d0 SUB	X8, X8, X10

(752) 0x4386d4 ADD	X9, X9, X10,LSL #3

(752) 0x4386d8 HINT	#0

(752) 0x4386dc HINT	#0

  (762) 0x4386e0 LDR	D1, [X9]

  (762) 0x4386e4 SUBS	X8, X8, #1

  (762) 0x4386e8 FMUL	D1, D0, D1

  (762) 0x4386ec STR	D1, [X9], #8

  (762) 0x4386f0 B.NE	4386e0

(752) 0x4386f4 B	437f68

0x4386f8 ORR	X0, XZR, X19

0x4386fc BL	4ab000

0x438700 ORR	X0, XZR, X20

0x438704 BL	4ab000

0x438708 ORR	X0, XZR, X21

0x43870c BL	4ab000

0x438710 ORR	X0, XZR, X22

0x438714 LDP	X20, X19, [SP, #464]

0x438718 LDP	X22, X21, [SP, #448]

0x43871c LDP	X24, X23, [SP, #432]

0x438720 LDP	X26, X25, [SP, #416]

0x438724 LDP	X28, X27, [SP, #400]

0x438728 LDP	X29, X30, [SP, #384]

0x43872c ADD	SP, SP, #480

0x438730 B	4ab000

0x438734 HINT	#0

0x438738 HINT	#0

0x43873c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.48+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.52+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:1884	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:785	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_multi_interp.c:1737-1881
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1737,1747-1881.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 46.67 to 2.50 cycles (18.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 30% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 46.67 to 25.71 cycles (1.82x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_CAlloc: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1748
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1751
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1754
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1756
hypre_Free: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1878
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1879
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1880
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1766
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1767

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	227
nb uops	211
loop length	908
used w registers	1
used x registers	31
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	34

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	26.38 cycles
front end	26.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	10.00	10.00	15.00	15.00	15.00	15.00	0.00	0.00	0.00	0.00	46.67	46.67	46.67	26.00	26.00
cycles	10.00	10.00	15.00	15.00	15.00	15.00	0.00	0.00	0.00	0.00	46.67	46.67	46.67	26.00	26.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	26.38
Dispatch	46.67
DIV/SQRT	5.00-20.00
Overall L1	46.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	30%
load	28%
store	35%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	26%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 46.67 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 437c30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #480	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STUR X7, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X22, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X25, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X8, X9, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X8, X9, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X9, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X11, X9, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X10, X9, [X29, #864]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X9, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X11, X9, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X10, X9, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X9, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X10, X8, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STUR X9, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X23, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X28, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STUR X9, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X10, X8, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X0, 437d74 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBZ X0, 437d80 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBZ X0, 437d8c <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 437d90 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBNZ X0, 437d50 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBNZ X0, 437d64 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X0, X8, X9, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 437dd4 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 437dfc <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4acc50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4acc30 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X11, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV X10, X9, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MUL X8, X10, X24	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X24, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X9, X9, X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4386f8 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0xac8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X12, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X12, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X11, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X11, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X11, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X11, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X11, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X11, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X11, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CNTW X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB X11, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X11, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X9, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
RDVL X8, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X11, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X12, X15, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X16, X13, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X11, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X11, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X10, X11, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X10, X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X16, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X8, X10, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X0, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X2, X1, [X29, #912]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X4, X3, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X6, X5, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X7, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 437f7c <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x34c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ab000 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ab000 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ab000 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X20, X19, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #480	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4ab000 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_multi_interp.c:1737-1881
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1737,1747-1881.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_CAlloc: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1748
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1751
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1754
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1756
hypre_Free: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1878
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1879
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1880
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1766
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1767

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	227
nb uops	211
loop length	908
used w registers	1
used x registers	31
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	34

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	26.38 cycles
front end	26.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	10.00	10.00	15.00	15.00	15.00	15.00	0.00	0.00	0.00	0.00	46.67	46.67	46.67	26.00	26.00
cycles	10.00	10.00	15.00	15.00	15.00	15.00	0.00	0.00	0.00	0.00	46.67	46.67	46.67	26.00	26.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	26.38
Dispatch	46.67
DIV/SQRT	5.00-20.00
Overall L1	46.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	30%
load	28%
store	35%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	26%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 46.67 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 437c30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #480	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STUR X7, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X22, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X25, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X8, X9, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X8, X9, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X9, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X11, X9, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X10, X9, [X29, #864]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X9, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X11, X9, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X10, X9, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X9, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X10, X8, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STUR X9, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X23, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X28, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STUR X9, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X10, X8, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X0, 437d74 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBZ X0, 437d80 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBZ X0, 437d8c <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 437d90 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBNZ X0, 437d50 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBNZ X0, 437d64 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X0, X8, X9, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 437dd4 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 437dfc <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4acc50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4acc30 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X11, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SDIV X10, X9, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MUL X8, X10, X24	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X24, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X9, X9, X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4386f8 <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0xac8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X12, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X12, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X11, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X11, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X11, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X11, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X11, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X11, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X11, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CNTW X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB X11, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X11, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X9, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X9, X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
RDVL X8, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X11, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X12, X15, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X16, X13, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X11, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X11, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X10, X11, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X10, X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X8, X16, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X8, X10, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X0, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X2, X1, [X29, #912]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X4, X3, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X6, X5, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X7, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 437f7c <hypre_BoomerAMGBuildMultipass.omp_outlined.19+0x34c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ab000 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ab000 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ab000 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X20, X19, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #480	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4ab000 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass.omp_outlined.19–	1.01	0.48
○Loop 767 - par_multi_interp.c:1760-1761 - exec	0.16	0.06
▼Loop 752 - par_multi_interp.c:1774-1876 - exec–	0.10	0.04
▼Loop 755 - par_multi_interp.c:1811-1837 - exec–	0.47	0.16
○Loop 757 - par_multi_interp.c:1816-1822 - exec	0.03	0.01
○Loop 756 - par_multi_interp.c:1824-1830 - exec	0.00	0.00
○Loop 759 - par_multi_interp.c:1799-1803 - exec	0.23	0.08
○Loop 761 - par_multi_interp.c:1782-1787 - exec	0.02	0.01
○Loop 764 - par_multi_interp.c:1873-1874 - exec	0.00	0.00
○Loop 758 - par_multi_interp.c:1805-1809 - exec	0.00	0.00
○Loop 765 - par_multi_interp.c:1873-1874 - exec	0.00	0.00
○Loop 763 - par_multi_interp.c:1875-1876 - exec	0.00	0.00
○Loop 762 - par_multi_interp.c:1875-1876 - exec	0.00	0.00
▼Loop 753 - par_multi_interp.c:1840-1867 - exec–	0.00	0.00
○Loop 754 - par_multi_interp.c:1851-1860 - exec	0.00	0.00
○Loop 760 - par_multi_interp.c:1792-1797 - exec	0.00	0.00
○Loop 766 - par_multi_interp.c:1762-1763 - exec	0.00	0.00

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