OV - exec - Function hypre_BoomerAMGBuildExtPIInterp.omp

	Function: hypre_BoomerAMGBuildExtPIInterp.omp_outlined	Module: exec	Source: par_lr_interp.c:1196-1757 [...]	Coverage (incl. loops): 0.20% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1196 - 1757

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1196: #pragma omp parallel private(i,my_thread_num,num_threads,start,stop,coarse_counter,jj_counter,jj_counter_offd, P_marker, P_marker_offd,jj,kk,i1,k1,loc_col,jj_begin_row,jj_begin_row_offd,jj_end_row,jj_end_row_offd,diagonal,sum,sgn,jj1,i2,distribute,strong_f_marker)

[...]

1219:        jj_counter = start_indexing;

1220:        jj_counter_offd = start_indexing;

1221:        if (n_fine)

1222:        {

1223:            P_marker = hypre_CTAlloc(HYPRE_Int, n_fine);

1224:            for (i = 0; i < n_fine; i++)

1225:            {  P_marker[i] = -1; }

1226:        }

1227:        if (full_off_procNodes)

1228:        {

1229:          P_marker_offd = hypre_CTAlloc(HYPRE_Int, full_off_procNodes);

1230:          for (i = 0; i < full_off_procNodes; i++)

1231:          {  P_marker_offd[i] = -1;}

1232:        }

1233:

1234:        /* this thread's row range */

1235:        my_thread_num = hypre_GetThreadNum();

1236:        num_threads = hypre_NumActiveThreads();

1237:        start = (n_fine/num_threads)*my_thread_num;

1238:        if (my_thread_num == num_threads-1)

[...]

1244:        for (i = start; i < stop; i++)

1245:        {

1246:          P_diag_i[i] = jj_counter;

1247:          if (num_procs > 1)

1248:            P_offd_i[i] = jj_counter_offd;

1249:

1250:          if (CF_marker[i] >= 0)

1251:          {

1252:            jj_counter++;

1253:            fine_to_coarse[i] = coarse_counter;

1254:            coarse_counter++;

[...]

1262:          else if (CF_marker[i] != -3)

1263:          {

1264:            for (jj = S_diag_i[i]; jj < S_diag_i[i+1]; jj++)

1265:            {

1266:              i1 = S_diag_j[jj];

1267:              if (CF_marker[i1] >= 0)

1268:              { /* i1 is a C point */

1269:                if (P_marker[i1] < P_diag_i[i])

1270:                {

1271:                  P_marker[i1] = jj_counter;

1272:                  jj_counter++;

1273:                }

1274:              }

1275:              else if (CF_marker[i1] != -3)

1276:              { /* i1 is a F point, loop through it's strong neighbors */

1277:                for (kk = S_diag_i[i1]; kk < S_diag_i[i1+1]; kk++)

1278:                {

1279:                  k1 = S_diag_j[kk];

1280:                  if (CF_marker[k1] >= 0)

1281:                  {

1282:                    if(P_marker[k1] < P_diag_i[i])

1283:                    {

1284:                      P_marker[k1] = jj_counter;

1285:                      jj_counter++;

1286:                    }

1287:                  }

1288:                }

1289:                if(num_procs > 1)

1290:                {

1291:                  for (kk = S_offd_i[i1]; kk < S_offd_i[i1+1]; kk++)

1292:                  {

1293:                    if(col_offd_S_to_A)

1294:                      k1 = col_offd_S_to_A[S_offd_j[kk]];

1295:                    else

1296:                      k1 = S_offd_j[kk];

1297:                    if (CF_marker_offd[k1] >= 0)

1298:                    {

1299:                      if(P_marker_offd[k1] < P_offd_i[i])

1300:                      {

1301:                        tmp_CF_marker_offd[k1] = 1;

1302:                        P_marker_offd[k1] = jj_counter_offd;

1303:                        jj_counter_offd++;

[...]

1311:            if (num_procs > 1)

1312:            {

1313:              for (jj = S_offd_i[i]; jj < S_offd_i[i+1]; jj++)

1314:              {

1315:                i1 = S_offd_j[jj];

1316:                if(col_offd_S_to_A)

1317:                  i1 = col_offd_S_to_A[i1];

1318:                if (CF_marker_offd[i1] >= 0)

1319:                {

1320:                  if(P_marker_offd[i1] < P_offd_i[i])

1321:                  {

1322:                    tmp_CF_marker_offd[i1] = 1;

1323:                    P_marker_offd[i1] = jj_counter_offd;

1324:                    jj_counter_offd++;

1325:                  }

1326:                }

1327:                else if (CF_marker_offd[i1] != -3)

1328:                { /* F point; look at neighbors of i1. Sop contains global col

1329:                   * numbers and entries that could be in S_diag or S_offd or

1330:                   * neither. */

1331:                  for(kk = Sop_i[i1]; kk < Sop_i[i1+1]; kk++)

1332:                  {

1333:                    k1 = Sop_j[kk];

1334:                    if(k1 >= col_1 && k1 < col_n)

1335:                    { /* In S_diag */

1336:                      loc_col = k1-col_1;

1337:                      if(P_marker[loc_col] < P_diag_i[i])

1338:                      {

1339:                        P_marker[loc_col] = jj_counter;

1340:                        jj_counter++;

1341:                      }

1342:                    }

1343:                    else

1344:                    {

1345:                      loc_col = -k1 - 1;

1346:                      if(P_marker_offd[loc_col] < P_offd_i[i])

1347:                      {

1348:                        P_marker_offd[loc_col] = jj_counter_offd;

1349:                        tmp_CF_marker_offd[loc_col] = 1;

1350:                        jj_counter_offd++;

[...]

1363: #pragma omp barrier

1364: #endif

1365:        P_diag_i[stop] = jj_counter;

1366:        P_offd_i[stop] = jj_counter_offd;

1367:        fine_to_coarse_offset[my_thread_num] = coarse_counter;

1368:        diag_offset[my_thread_num] = jj_counter;

1369:        offd_offset[my_thread_num] = jj_counter_offd;

1370:

1371:        /* Stitch P_diag_i, P_offd_i and fine_to_coarse together */

1372: #ifdef HYPRE_USING_OPENMP

1373: #pragma omp barrier

1374: #endif

1375:        if(my_thread_num == 0)

1376:        {

1377:          /* Calculate the offset for P_diag_i and P_offd_i for each thread */

1378:          for (i = 1; i < num_threads; i++)

1379:          {

1380:            diag_offset[i] = diag_offset[i-1] + diag_offset[i];

1381:            fine_to_coarse_offset[i] = fine_to_coarse_offset[i-1] + fine_to_coarse_offset[i];

1382:            offd_offset[i] = offd_offset[i-1] + offd_offset[i];

1383:          }

1384:        }

1385: #ifdef HYPRE_USING_OPENMP

1386: #pragma omp barrier

1387: #endif

1388:

1389:        if(my_thread_num > 0)

1390:        {

1391:          /* update row pointer array with offset,

1392:           * making sure to update the row stop index */

1393:          for (i = start+1; i <= stop; i++)

1394:          {

1395:             P_diag_i[i] += diag_offset[my_thread_num-1];

1396:             P_offd_i[i] += offd_offset[my_thread_num-1];

1397:          }

1398:          /* update fine_to_coarse by offsetting with the offset

1399:           * from the preceding thread */

1400:          for (i = start; i < stop; i++)

1401:          {

1402:            if(fine_to_coarse[i] >= 0)

1403:            { fine_to_coarse[i] += fine_to_coarse_offset[my_thread_num-1]; }

1404:          }

1405:        }

1406: #ifdef HYPRE_USING_OPENMP

1407: #pragma omp barrier

1408: #endif

1409:

1410:        if(my_thread_num == 0)

1411:        {

1412:          if (debug_flag==4)

1413:          {

1414:             wall_time = time_getWallclockSeconds() - wall_time;

1415:             hypre_printf("Proc = %d     determine structure    %f\n",

1416:                           my_id, wall_time);

1417:             fflush(NULL);

[...]

1423:          if (debug_flag== 4) wall_time = time_getWallclockSeconds();

1424:

1425:          P_diag_size =  P_diag_i[n_fine];

1426:          P_offd_size = P_offd_i[n_fine];

1427:

1428:          if (P_diag_size)

1429:          {

1430:             P_diag_j    = hypre_CTAlloc(HYPRE_Int, P_diag_size);

1431:             P_diag_data = hypre_CTAlloc(HYPRE_Real, P_diag_size);

1432:          }

1433:

1434:          if (P_offd_size)

1435:          {

1436:             P_offd_j    = hypre_CTAlloc(HYPRE_Int, P_offd_size);

1437:             P_offd_data = hypre_CTAlloc(HYPRE_Real, P_offd_size);

1438:          }

1439:        }

1440:

1441:        /* Fine to coarse mapping */

1442:        if(num_procs > 1   &&   my_thread_num == 0)

1443:        {

1444:          for (i = 0; i < n_fine; i++)

1445:            fine_to_coarse[i] += my_first_cpt;

1446:

1447:          hypre_alt_insert_new_nodes(comm_pkg, extend_comm_pkg, fine_to_coarse,

1448:                   full_off_procNodes,

1449:                   fine_to_coarse_offd);

1450:

1451:          for (i = 0; i < n_fine; i++)

1452:            fine_to_coarse[i] -= my_first_cpt;

1453:        }

1454:

1455:        for (i = 0; i < n_fine; i++)

1456:          P_marker[i] = -1;

1457:

1458:        for (i = 0; i < full_off_procNodes; i++)

1459:          P_marker_offd[i] = -1;

[...]

1467: #pragma omp barrier

1468: #endif

1469:        for (i = start; i < stop; i++)

1470:        {

1471:          jj_begin_row = P_diag_i[i];

[...]

1480:          if (CF_marker[i] >= 0)

1481:          {

1482:            P_diag_j[jj_counter]    = fine_to_coarse[i];

1483:            P_diag_data[jj_counter] = one;

[...]

1491:          else if (CF_marker[i] != -3)

1492:          {

1493:            strong_f_marker--;

1494:            for (jj = S_diag_i[i]; jj < S_diag_i[i+1]; jj++)

1495:            {

1496:              i1 = S_diag_j[jj];

[...]

1503:              if (CF_marker[i1] >= 0)

1504:              {

1505:                if (P_marker[i1] < jj_begin_row)

1506:                {

1507:                  P_marker[i1] = jj_counter;

1508:                  P_diag_j[jj_counter]    = fine_to_coarse[i1];

1509:                  P_diag_data[jj_counter] = zero;

1510:                  jj_counter++;

1511:                }

1512:              }

1513:              else  if (CF_marker[i1] != -3)

1514:              {

1515:                P_marker[i1] = strong_f_marker;

1516:                for (kk = S_diag_i[i1]; kk < S_diag_i[i1+1]; kk++)

1517:                {

1518:                  k1 = S_diag_j[kk];

1519:                  if (CF_marker[k1] >= 0)

1520:                  {

1521:                    if(P_marker[k1] < jj_begin_row)

1522:                    {

1523:                      P_marker[k1] = jj_counter;

1524:                      P_diag_j[jj_counter] = fine_to_coarse[k1];

1525:                      P_diag_data[jj_counter] = zero;

1526:                      jj_counter++;

1527:                    }

1528:                  }

1529:                }

1530:                if(num_procs > 1)

1531:                {

1532:                  for (kk = S_offd_i[i1]; kk < S_offd_i[i1+1]; kk++)

1533:                  {

1534:                    if(col_offd_S_to_A)

1535:                     k1 = col_offd_S_to_A[S_offd_j[kk]];

1536:                    else

1537:                     k1 = S_offd_j[kk];

1538:                    if(CF_marker_offd[k1] >= 0)

1539:                    {

1540:                      if(P_marker_offd[k1] < jj_begin_row_offd)

1541:                      {

1542:                        P_marker_offd[k1] = jj_counter_offd;

1543:                        P_offd_j[jj_counter_offd] = k1;

1544:                        P_offd_data[jj_counter_offd] = zero;

1545:                        jj_counter_offd++;

[...]

1553:            if ( num_procs > 1)

1554:            {

1555:              for (jj=S_offd_i[i]; jj < S_offd_i[i+1]; jj++)

1556:              {

1557:                i1 = S_offd_j[jj];

1558:                if(col_offd_S_to_A)

1559:                  i1 = col_offd_S_to_A[i1];

1560:                if ( CF_marker_offd[i1] >= 0)

1561:                {

1562:                  if(P_marker_offd[i1] < jj_begin_row_offd)

1563:                  {

1564:                    P_marker_offd[i1] = jj_counter_offd;

1565:                    P_offd_j[jj_counter_offd] = i1;

1566:                    P_offd_data[jj_counter_offd] = zero;

1567:                    jj_counter_offd++;

1568:                  }

1569:                }

1570:                else if (CF_marker_offd[i1] != -3)

1571:                {

1572:                  P_marker_offd[i1] = strong_f_marker;

1573:                  for(kk = Sop_i[i1]; kk < Sop_i[i1+1]; kk++)

1574:                  {

1575:                    k1 = Sop_j[kk];

1576:                    /* Find local col number */

1577:                    if(k1 >= col_1 && k1 < col_n)

1578:                    {

1579:                      loc_col = k1-col_1;

1580:                      if(P_marker[loc_col] < jj_begin_row)

1581:                      {

1582:                        P_marker[loc_col] = jj_counter;

1583:                        P_diag_j[jj_counter] = fine_to_coarse[loc_col];

1584:                        P_diag_data[jj_counter] = zero;

1585:                        jj_counter++;

1586:                      }

1587:                    }

1588:                    else

1589:                    {

1590:                      loc_col = -k1 - 1;

1591:                      if(P_marker_offd[loc_col] < jj_begin_row_offd)

1592:                      {

1593:                        P_marker_offd[loc_col] = jj_counter_offd;

1594:                        P_offd_j[jj_counter_offd]=loc_col;

1595:                        P_offd_data[jj_counter_offd] = zero;

1596:                        jj_counter_offd++;

[...]

1607:            diagonal = A_diag_data[A_diag_i[i]];

1608:

1609:            for (jj = A_diag_i[i]+1; jj < A_diag_i[i+1]; jj++)

1610:            { /* i1 is a c-point and strongly influences i, accumulate

1611:               * a_(i,i1) into interpolation weight */

1612:              i1 = A_diag_j[jj];

1613:              if (P_marker[i1] >= jj_begin_row)

1614:              {

1615:                P_diag_data[P_marker[i1]] += A_diag_data[jj];

1616:              }

1617:              else if(P_marker[i1] == strong_f_marker)

1618:              {

1619:                sum = zero;

1620:                sgn = 1;

1621:                if(A_diag_data[A_diag_i[i1]] < 0) sgn = -1;

1622:                /* Loop over row of A for point i1 and calculate the sum

1623:                 * of the connections to c-points that strongly influence i. */

1624:                for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1625:                {

1626:                  i2 = A_diag_j[jj1];

1627:                  if((P_marker[i2] >= jj_begin_row || i2 == i) && (sgn*A_diag_data[jj1]) < 0)

1628:                    sum += A_diag_data[jj1];

1629:                }

1630:                if(num_procs > 1)

1631:                {

1632:                  for(jj1 = A_offd_i[i1]; jj1< A_offd_i[i1+1]; jj1++)

1633:                  {

1634:                    i2 = A_offd_j[jj1];

1635:                    if(P_marker_offd[i2] >= jj_begin_row_offd &&

1636:                       (sgn*A_offd_data[jj1]) < 0)

1637:                       sum += A_offd_data[jj1];

1638:                  }

1639:                }

1640:                if(sum != 0)

1641:                {

1642:                  distribute = A_diag_data[jj]/sum;

1643:                  /* Loop over row of A for point i1 and do the distribution */

1644:                  for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1645:                  {

1646:                    i2 = A_diag_j[jj1];

1647:                    if(P_marker[i2] >= jj_begin_row && (sgn*A_diag_data[jj1]) < 0)

1648:                       P_diag_data[P_marker[i2]] +=

1649:                       distribute*A_diag_data[jj1];

1650:                        if(i2 == i && (sgn*A_diag_data[jj1]) < 0)

1651:                          diagonal += distribute*A_diag_data[jj1];

1652:                  }

1653:                  if(num_procs > 1)

1654:                  {

1655:                    for(jj1 = A_offd_i[i1]; jj1 < A_offd_i[i1+1]; jj1++)

1656:                    {

1657:                      i2 = A_offd_j[jj1];

1658:                      if(P_marker_offd[i2] >= jj_begin_row_offd &&

1659:                                 (sgn*A_offd_data[jj1]) < 0)

1660:                        P_offd_data[P_marker_offd[i2]] +=

[...]

1667:                  diagonal += A_diag_data[jj];

1668:                }

1669:              }

1670:              /* neighbor i1 weakly influences i, accumulate a_(i,i1) into

1671:               * diagonal */

1672:              else if (CF_marker[i1] != -3)

1673:              {

1674:                if(num_functions == 1 || dof_func[i] == dof_func[i1])

1675:                  diagonal += A_diag_data[jj];

1676:              }

1677:            }

1678:            if(num_procs > 1)

1679:            {

1680:              for(jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++)

1681:              {

1682:                i1 = A_offd_j[jj];

1683:                if(P_marker_offd[i1] >= jj_begin_row_offd)

1684:                  P_offd_data[P_marker_offd[i1]] += A_offd_data[jj];

1685:                else if(P_marker_offd[i1] == strong_f_marker)

1686:                {

1687:                  sum = zero;

1688:                  for(jj1 = A_ext_i[i1]; jj1 < A_ext_i[i1+1]; jj1++)

1689:                  {

1690:                    k1 = A_ext_j[jj1];

1691:                    if(k1 >= col_1 && k1 < col_n)

1692:                    { /* diag */

1693:                      loc_col = k1 - col_1;

1694:                      if(P_marker[loc_col] >= jj_begin_row || loc_col == i)

1695:                        sum += A_ext_data[jj1];

1696:                    }

1697:                    else

1698:                    {

1699:                      loc_col = -k1 - 1;

1700:                      if(P_marker_offd[loc_col] >= jj_begin_row_offd)

1701:                        sum += A_ext_data[jj1];

1702:                    }

1703:                  }

1704:                  if(sum != 0)

1705:                  {

1706:                    distribute = A_offd_data[jj] / sum;

1707:                    for(jj1 = A_ext_i[i1]; jj1 < A_ext_i[i1+1]; jj1++)

1708:                    {

1709:                      k1 = A_ext_j[jj1];

1710:                      if(k1 >= col_1 && k1 < col_n)

1711:                      { /* diag */

1712:                        loc_col = k1 - col_1;

1713:                        if(P_marker[loc_col] >= jj_begin_row)

1714:                          P_diag_data[P_marker[loc_col]] += distribute*

1715:                           A_ext_data[jj1];

1716:                                if(loc_col == i)

1717:                                  diagonal += distribute*A_ext_data[jj1];

1718:                      }

1719:                      else

1720:                      {

1721:                        loc_col = -k1 - 1;

1722:                        if(P_marker_offd[loc_col] >= jj_begin_row_offd)

1723:                          P_offd_data[P_marker_offd[loc_col]] += distribute*

1724:                            A_ext_data[jj1];

[...]

1733:                else if (CF_marker_offd[i1] != -3)

1734:                {

1735:                  if(num_functions == 1 || dof_func[i] == dof_func_offd[i1])

1736:                    diagonal += A_offd_data[jj];

1737:                }

1738:              }

1739:            }

1740:            if (diagonal)

1741:            {

1742:              for(jj = jj_begin_row; jj < jj_end_row; jj++)

1743:                 P_diag_data[jj] /= -diagonal;

1744:              for(jj = jj_begin_row_offd; jj < jj_end_row_offd; jj++)

1745:                 P_offd_data[jj] /= -diagonal;

1746:            }

1747:          }

1748:          strong_f_marker--;

[...]

1754:        if (n_fine)

1755:        {  hypre_TFree(P_marker); }

1756:        if (full_off_procNodes)

1757:        {  hypre_TFree(P_marker_offd); }

0x43b220 STP	X29, X30, [SP, #928]!

0x43b224 STP	X28, X27, [SP, #16]

0x43b228 STP	X26, X25, [SP, #32]

0x43b22c STP	X24, X23, [SP, #48]

0x43b230 STP	X22, X21, [SP, #64]

0x43b234 STP	X20, X19, [SP, #80]

0x43b238 ADD	X29, SP, #0

0x43b23c SUB	SP, SP, #448

0x43b240 STUR	X7, [X29, #472]

0x43b244 STUR	X6, [X29, #488]

0x43b248 LDR	X20, [X2]

0x43b24c STUR	X5, [X29, #456]

0x43b250 STUR	X3, [X29, #384]

0x43b254 STR	X0, [SP, #192]

0x43b258 LDR	X8, [X29, #432]

0x43b25c LDR	X0, [X3]

0x43b260 STR	X8, [SP, #88]

0x43b264 LDP	X8, X9, [X29, #416]

0x43b268 STUR	X9, [X29, #328]

0x43b26c STR	X8, [SP, #80]

0x43b270 LDR	X8, [X29, #408]

0x43b274 STR	X8, [SP, #72]

0x43b278 LDR	X8, [X29, #400]

0x43b27c STR	X8, [SP, #152]

0x43b280 LDR	X8, [X29, #392]

0x43b284 STR	X8, [SP, #144]

0x43b288 LDP	X8, X9, [X29, #376]

0x43b28c STUR	X9, [X29, #352]

0x43b290 STR	X8, [SP, #136]

0x43b294 LDR	X8, [X29, #368]

0x43b298 STR	X8, [SP, #128]

0x43b29c LDP	X8, X26, [X29, #336]

0x43b2a0 LDP	X19, X21, [X29, #352]

0x43b2a4 STR	X8, [SP, #96]

0x43b2a8 LDP	X27, X8, [X29, #320]

0x43b2ac STUR	X8, [X29, #312]

0x43b2b0 LDR	X8, [X29, #312]

0x43b2b4 STR	X8, [SP, #24]

0x43b2b8 LDR	X8, [X29, #304]

0x43b2bc STR	X8, [SP, #16]

0x43b2c0 LDR	X8, [X29, #296]

0x43b2c4 STR	X8, [SP, #48]

0x43b2c8 LDP	X8, X9, [X29, #280]

0x43b2cc STUR	X9, [X29, #416]

0x43b2d0 STUR	X8, [X29, #336]

0x43b2d4 LDP	X8, X9, [X29, #264]

0x43b2d8 STUR	X8, [X29, #400]

0x43b2dc LDR	X8, [X29, #256]

0x43b2e0 STUR	X9, [X29, #432]

0x43b2e4 STR	X8, [SP, #216]

0x43b2e8 LDR	X8, [X29, #248]

0x43b2ec STR	X8, [SP, #64]

0x43b2f0 LDR	X8, [X29, #240]

0x43b2f4 STR	X8, [SP, #8]

0x43b2f8 LDR	X8, [X29, #232]

0x43b2fc STR	X8, [SP, #40]

0x43b300 LDR	X8, [X29, #224]

0x43b304 STR	X8, [SP, #56]

0x43b308 LDR	X8, [X29, #216]

0x43b30c STR	X8, [SP, #200]

0x43b310 LDP	X8, X9, [X29, #200]

0x43b314 LDP	X28, X24, [X29, #184]

0x43b318 STUR	X8, [X29, #440]

0x43b31c LDR	X8, [X29, #176]

0x43b320 STUR	X9, [X29, #424]

0x43b324 STR	X8, [SP, #120]

0x43b328 LDR	X8, [X29, #168]

0x43b32c STR	X8, [SP, #112]

0x43b330 LDP	X8, X9, [X29, #152]

0x43b334 STUR	X9, [X29, #464]

0x43b338 LDP	X10, X9, [X29, #136]

0x43b33c STUR	X8, [X29, #320]

0x43b340 STUR	X9, [X29, #344]

0x43b344 LDP	X11, X9, [X29, #120]

0x43b348 STP	X9, X10, [X29, #808]

0x43b34c LDP	X8, X9, [X29, #104]

0x43b350 STUR	X8, [X29, #408]

0x43b354 LDR	X8, [X29, #96]

0x43b358 STP	X9, X11, [X29, #880]

0x43b35c STUR	X8, [X29, #360]

0x43b360 STR	X4, [SP, #224]

0x43b364 CBZ	X0, 43b3f8

0x43b368 MOVZ	W1, #8

0x43b36c BL	4aaf00

0x43b370 LDUR	X11, [X29, #384]

0x43b374 ORR	X22, XZR, X0

0x43b378 LDR	X8, [X11]

0x43b37c CMP	X8, #1

0x43b380 B.LT	43b3a0

0x43b384 MOVN	X9, #0

0x43b388 ORR	X8, XZR, XZR

(872) 0x43b38c STR	X9, [X22, X8,LSL #3]

(872) 0x43b390 ADD	X8, X8, #1

(872) 0x43b394 LDR	X10, [X11]

(872) 0x43b398 CMP	X8, X10

(872) 0x43b39c B.LT	43b38c

0x43b3a0 LDR	X4, [SP, #224]

0x43b3a4 LDR	X0, [X4]

0x43b3a8 STP	X21, X19, [SP, #160]

0x43b3ac STR	X26, [SP, #104]

0x43b3b0 STR	X27, [SP, #32]

0x43b3b4 CBZ	X0, 43b40c

0x43b3b8 MOVZ	W1, #8

0x43b3bc BL	4aaf00

0x43b3c0 LDR	X11, [SP, #224]

0x43b3c4 ORR	X23, XZR, X0

0x43b3c8 LDR	X8, [X11]

0x43b3cc CMP	X8, #1

0x43b3d0 B.LT	43b40c

0x43b3d4 MOVN	X9, #0

0x43b3d8 ORR	X8, XZR, XZR

0x43b3dc HINT	#0

(871) 0x43b3e0 STR	X9, [X23, X8,LSL #3]

(871) 0x43b3e4 ADD	X8, X8, #1

(871) 0x43b3e8 LDR	X10, [X11]

(871) 0x43b3ec CMP	X8, X10

(871) 0x43b3f0 B.LT	43b3e0

0x43b3f4 B	43b40c

0x43b3f8 LDR	X0, [X4]

0x43b3fc STP	X21, X19, [SP, #160]

0x43b400 STR	X26, [SP, #104]

0x43b404 STR	X27, [SP, #32]

0x43b408 CBNZ	X0, 43b3b8

0x43b40c BL	4acc50

0x43b410 ORR	X19, XZR, X0

0x43b414 BL	4acc30

0x43b418 LDUR	X8, [X29, #384]

0x43b41c SUB	X9, X0, #1

0x43b420 ORR	X26, XZR, XZR

0x43b424 LDR	X8, [X8]

0x43b428 SDIV	X10, X8, X0

0x43b42c MUL	X27, X10, X19

0x43b430 STR	X10, [SP, #176]

0x43b434 ADD	X10, X10, X27

0x43b438 CMP	X19, X9

0x43b43c CSEL	X14, X8, X10, #0

0x43b440 CMP	X14, X27

0x43b444 STUR	X14, [X29, #392]

0x43b448 STR	X19, [SP, #208]

0x43b44c STR	X0, [SP, #184]

0x43b450 B.GT	43b570

0x43b454 ORR	X19, XZR, X20

0x43b458 LDR	X8, [SP, #192]

0x43b45c ADRP	X0,

0x43b460 ADD	X0, X0, #1456

0x43b464 ORR	X21, XZR, X14

0x43b468 LDR	W25, [X8]

0x43b46c ORR	W1, WZR, W25

0x43b470 BL	4104c0

0x43b474 LDUR	X8, [X29, #456]

0x43b478 LDUR	X9, [X29, #472]

0x43b47c LDUR	X10, [X29, #440]

0x43b480 ADRP	X0,

0x43b484 ADD	X0, X0, #1480

0x43b488 ORR	W1, WZR, W25

0x43b48c LDR	X8, [X8]

0x43b490 LDR	X9, [X9]

0x43b494 LDR	X10, [X10]

0x43b498 STR	X19, [X8, X21,LSL #3]

0x43b49c STR	X20, [X9, X21,LSL #3]

0x43b4a0 LDR	X21, [SP, #208]

0x43b4a4 LDUR	X8, [X29, #424]

0x43b4a8 LDR	X8, [X8]

0x43b4ac STR	X26, [X10, X21,LSL #3]

0x43b4b0 LDR	X26, [SP, #200]

0x43b4b4 STR	X19, [X8, X21,LSL #3]

0x43b4b8 LDR	X8, [X26]

0x43b4bc STR	X20, [X8, X21,LSL #3]

0x43b4c0 ORR	W20, WZR, W25

0x43b4c4 BL	4104c0

0x43b4c8 LDR	X19, [SP, #216]

0x43b4cc LDR	X12, [SP, #184]

0x43b4d0 CBNZ	X21, 43b94c

0x43b4d4 SUBS	X8, X12, #1

0x43b4d8 B.LE	43b94c

0x43b4dc LDUR	X9, [X29, #424]

0x43b4e0 LDUR	X10, [X29, #440]

0x43b4e4 LDR	X11, [X26]

0x43b4e8 ADD	X13, X11, X12,LSL #3

0x43b4ec LDR	X9, [X9]

0x43b4f0 LDR	X10, [X10]

0x43b4f4 ADD	X14, X9, X12,LSL #3

0x43b4f8 CMP	X9, X13

0x43b4fc ADD	X15, X10, X12,LSL #3

0x43b500 CCMP	X11, X14, #2, #3

0x43b504 CSINC	W12, WZR, WZR, #2

0x43b508 CMP	X10, X13

0x43b50c CCMP	X11, X15, #2, #3

0x43b510 CSINC	W13, WZR, WZR, #2

0x43b514 CMP	X10, X14

0x43b518 CCMP	X9, X15, #2, #3

0x43b51c B.CC	43b908

0x43b520 TBNZ	W12, #0, 43b908

0x43b524 CBNZ	W13, 43b908

0x43b528 LDR	X12, [X9], #8

0x43b52c LDR	X13, [X11], #8

0x43b530 LDR	X14, [X10], #8

0x43b534 HINT	#0

0x43b538 HINT	#0

0x43b53c HINT	#0

(861) 0x43b540 LDR	X15, [X9]

(861) 0x43b544 SUBS	X8, X8, #1

(861) 0x43b548 ADD	X12, X15, X12

(861) 0x43b54c STR	X12, [X9], #8

(861) 0x43b550 LDR	X15, [X10]

(861) 0x43b554 ADD	X14, X15, X14

(861) 0x43b558 STR	X14, [X10], #8

(861) 0x43b55c LDR	X15, [X11]

(861) 0x43b560 ADD	X13, X15, X13

(861) 0x43b564 STR	X13, [X11], #8

(861) 0x43b568 B.NE	43b540

0x43b56c B	43b94c

0x43b570 LDUR	X9, [X29, #472]

0x43b574 LDUR	X8, [X29, #456]

0x43b578 ORR	X18, XZR, X27

0x43b57c ORR	X19, XZR, X20

0x43b580 LDR	X25, [X9]

0x43b584 LDP	X11, X9, [X29, #872]

0x43b588 LDR	X8, [X8]

0x43b58c LDR	X10, [X11]

0x43b590 LDR	X11, [X9]

0x43b594 LDUR	X9, [X29, #376]

0x43b598 LDR	X12, [X9]

0x43b59c LDUR	X9, [X29, #296]

0x43b5a0 LDR	X13, [X9]

0x43b5a4 LDUR	X9, [X29, #344]

0x43b5a8 LDR	X9, [X9]

0x43b5ac STUR	X9, [X29, #496]

0x43b5b0 LDUR	X9, [X29, #304]

0x43b5b4 LDR	X15, [X9]

0x43b5b8 LDUR	X9, [X29, #320]

0x43b5bc LDR	X9, [X9]

0x43b5c0 STUR	X9, [X29, #480]

0x43b5c4 LDUR	X9, [X29, #408]

0x43b5c8 LDR	X16, [X9]

0x43b5cc STUR	X16, [X29, #448]

0x43b5d0 B	43b600

0x43b5d4 HINT	#0

0x43b5d8 HINT	#0

0x43b5dc HINT	#0

        (862) 0x43b5e0 LDR	X9, [X10, X18,LSL #3]

        (862) 0x43b5e4 TBNZ	X9, #63, 43b620

        (862) 0x43b5e8 ADD	X19, X19, #1

        (862) 0x43b5ec STR	X26, [X16, X18,LSL #3]

        (862) 0x43b5f0 ADD	X26, X26, #1

        (862) 0x43b5f4 ADD	X18, X18, #1

        (862) 0x43b5f8 CMP	X18, X14

        (862) 0x43b5fc B.EQ	43b458

        (862) 0x43b600 LDUR	X9, [X29, #488]

        (862) 0x43b604 STR	X19, [X8, X18,LSL #3]

        (862) 0x43b608 LDR	X9, [X9]

        (862) 0x43b60c CMP	X9, #2

        (862) 0x43b610 B.LT	43b5e0

        (862) 0x43b614 STR	X20, [X25, X18,LSL #3]

        (862) 0x43b618 B	43b5e0

0x43b61c HINT	#0

        (862) 0x43b620 CMN	X9, #3

        (862) 0x43b624 B.EQ	43b5f4

      (863) 0x43b628 ADD	X1, X18, #1

      (863) 0x43b62c LDR	X2, [X11, X18,LSL #3]

      (863) 0x43b630 LDR	X9, [X11, X1,LSL #3]

      (863) 0x43b634 CMP	X2, X9

      (863) 0x43b638 B.GE	43b7c4

      (863) 0x43b63c LDUR	X9, [X29, #296]

      (863) 0x43b640 LDR	X3, [X9]

      (863) 0x43b644 LDUR	X9, [X29, #304]

      (863) 0x43b648 LDR	X4, [X9]

      (863) 0x43b64c LDUR	X9, [X29, #320]

      (863) 0x43b650 LDR	X5, [X9]

      (863) 0x43b654 B	43b670

0x43b658 HINT	#0

0x43b65c HINT	#0

        (867) 0x43b660 LDR	X9, [X11, X1,LSL #3]

        (867) 0x43b664 ADD	X2, X2, #1

        (867) 0x43b668 CMP	X2, X9

        (867) 0x43b66c B.GE	43b7c4

        (867) 0x43b670 LDR	X9, [X12, X2,LSL #3]

        (867) 0x43b674 LDR	X14, [X10, X9,LSL #3]

        (867) 0x43b678 TBNZ	X14, #63, 43b6a0

        (867) 0x43b67c LDR	X14, [X22, X9,LSL #3]

        (867) 0x43b680 LDR	X0, [X8, X18,LSL #3]

        (867) 0x43b684 CMP	X14, X0

        (867) 0x43b688 B.GE	43b660

        (867) 0x43b68c STR	X19, [X22, X9,LSL #3]

        (867) 0x43b690 ADD	X19, X19, #1

        (867) 0x43b694 B	43b660

0x43b698 HINT	#0

0x43b69c HINT	#0

        (867) 0x43b6a0 CMN	X14, #3

        (867) 0x43b6a4 B.EQ	43b660

        (867) 0x43b6a8 ADD	X6, X9, #1

        (867) 0x43b6ac LDR	X0, [X11, X9,LSL #3]

        (867) 0x43b6b0 LDR	X7, [X11, X6,LSL #3]

        (867) 0x43b6b4 B	43b6c4

0x43b6b8 HINT	#0

0x43b6bc HINT	#0

          (870) 0x43b6c0 ADD	X0, X0, #1

          (870) 0x43b6c4 CMP	X0, X7

          (870) 0x43b6c8 B.GE	43b6f8

          (870) 0x43b6cc LDR	X14, [X12, X0,LSL #3]

          (870) 0x43b6d0 LDR	X21, [X10, X14,LSL #3]

          (870) 0x43b6d4 TBNZ	X21, #63, 43b6c0

          (870) 0x43b6d8 LDR	X21, [X22, X14,LSL #3]

          (870) 0x43b6dc LDR	X30, [X8, X18,LSL #3]

          (870) 0x43b6e0 CMP	X21, X30

          (870) 0x43b6e4 B.GE	43b6c0

          (870) 0x43b6e8 STR	X19, [X22, X14,LSL #3]

          (870) 0x43b6ec ADD	X19, X19, #1

          (870) 0x43b6f0 LDR	X7, [X11, X6,LSL #3]

          (870) 0x43b6f4 B	43b6c0

        (867) 0x43b6f8 LDUR	X14, [X29, #488]

        (867) 0x43b6fc LDR	X14, [X14]

        (867) 0x43b700 CMP	X14, #2

        (867) 0x43b704 B.LT	43b660

        (867) 0x43b708 LDR	X7, [X3, X9,LSL #3]

        (867) 0x43b70c LDR	X0, [X3, X6,LSL #3]

        (867) 0x43b710 CMP	X7, X0

        (867) 0x43b714 B.GE	43b660

        (867) 0x43b718 LDUR	X9, [X29, #344]

        (867) 0x43b71c LDR	X21, [X9]

        (867) 0x43b720 LDUR	X9, [X29, #472]

        (867) 0x43b724 LDR	X30, [X9]

        (867) 0x43b728 LDUR	X9, [X29, #464]

        (867) 0x43b72c LDR	X9, [X9]

        (867) 0x43b730 CBNZ	X4, 43b74c

        (867) 0x43b734 B	43b790

0x43b738 HINT	#0

0x43b73c HINT	#0

          (868) 0x43b740 ADD	X7, X7, #1

          (868) 0x43b744 CMP	X7, X0

          (868) 0x43b748 B.GE	43b660

          (868) 0x43b74c LDR	X14, [X21, X7,LSL #3]

          (868) 0x43b750 LDR	X14, [X4, X14,LSL #3]

          (868) 0x43b754 LDR	X16, [X5, X14,LSL #3]

          (868) 0x43b758 TBNZ	X16, #63, 43b740

          (868) 0x43b75c LDR	X16, [X23, X14,LSL #3]

          (868) 0x43b760 LDR	X17, [X30, X18,LSL #3]

          (868) 0x43b764 CMP	X16, X17

          (868) 0x43b768 B.GE	43b740

          (868) 0x43b76c MOVZ	W16, #1

          (868) 0x43b770 STR	X16, [X9, X14,LSL #3]

          (868) 0x43b774 STR	X20, [X23, X14,LSL #3]

          (868) 0x43b778 ADD	X20, X20, #1

          (868) 0x43b77c LDR	X0, [X3, X6,LSL #3]

          (868) 0x43b780 B	43b740

          (869) 0x43b784 ADD	X7, X7, #1

          (869) 0x43b788 CMP	X7, X0

          (869) 0x43b78c B.GE	43b660

          (869) 0x43b790 LDR	X14, [X21, X7,LSL #3]

          (869) 0x43b794 LDR	X16, [X5, X14,LSL #3]

          (869) 0x43b798 TBNZ	X16, #63, 43b784

          (869) 0x43b79c LDR	X16, [X23, X14,LSL #3]

          (869) 0x43b7a0 LDR	X17, [X30, X18,LSL #3]

          (869) 0x43b7a4 CMP	X16, X17

          (869) 0x43b7a8 B.GE	43b784

          (869) 0x43b7ac MOVZ	W16, #1

          (869) 0x43b7b0 STR	X16, [X9, X14,LSL #3]

          (869) 0x43b7b4 STR	X20, [X23, X14,LSL #3]

          (869) 0x43b7b8 ADD	X20, X20, #1

          (869) 0x43b7bc LDR	X0, [X3, X6,LSL #3]

          (869) 0x43b7c0 B	43b784

      (863) 0x43b7c4 LDUR	X9, [X29, #488]

      (863) 0x43b7c8 LDR	X9, [X9]

      (863) 0x43b7cc CMP	X9, #2

      (863) 0x43b7d0 B.LT	43b8fc

      (863) 0x43b7d4 LDR	X2, [X13, X18,LSL #3]

      (863) 0x43b7d8 LDR	X9, [X13, X1,LSL #3]

      (863) 0x43b7dc CMP	X2, X9

      (863) 0x43b7e0 B.GE	43b8fc

    (864) 0x43b7e4 LDR	X9, [SP, #112]

    (864) 0x43b7e8 LDR	X3, [X9]

    (864) 0x43b7ec LDR	X9, [SP, #120]

    (864) 0x43b7f0 LDR	X4, [X9]

    (864) 0x43b7f4 LDUR	X9, [X29, #472]

    (864) 0x43b7f8 LDR	X5, [X9]

    (864) 0x43b7fc LDUR	X9, [X29, #464]

    (864) 0x43b800 LDR	X6, [X9]

    (864) 0x43b804 B	43b818

    (864) 0x43b808 LDR	X9, [X13, X1,LSL #3]

    (864) 0x43b80c ADD	X2, X2, #1

    (864) 0x43b810 CMP	X2, X9

    (864) 0x43b814 B.GE	43b8fc

    (864) 0x43b818 LDUR	X9, [X29, #496]

    (864) 0x43b81c LDR	X9, [X9, X2,LSL #3]

    (864) 0x43b820 CBZ	X15, 43b828

    (864) 0x43b824 LDR	X9, [X15, X9,LSL #3]

    (864) 0x43b828 LDUR	X14, [X29, #480]

    (864) 0x43b82c LDR	X14, [X14, X9,LSL #3]

    (864) 0x43b830 TBNZ	X14, #63, 43b860

    (864) 0x43b834 LDR	X14, [X23, X9,LSL #3]

    (864) 0x43b838 LDR	X16, [X5, X18,LSL #3]

    (864) 0x43b83c CMP	X14, X16

    (864) 0x43b840 B.GE	43b808

    (864) 0x43b844 MOVZ	W14, #1

    (864) 0x43b848 STR	X14, [X6, X9,LSL #3]

    (864) 0x43b84c STR	X20, [X23, X9,LSL #3]

    (864) 0x43b850 ADD	X20, X20, #1

    (864) 0x43b854 B	43b808

0x43b858 HINT	#0

0x43b85c HINT	#0

    (864) 0x43b860 CMN	X14, #3

    (864) 0x43b864 B.EQ	43b808

    (864) 0x43b868 ADD	X9, X3, X9,LSL #3

    (864) 0x43b86c LDP	X0, X14, [X9]

    (864) 0x43b870 CMP	X0, X14

    (864) 0x43b874 B.GE	43b808

  (866) 0x43b878 LDUR	X14, [X29, #472]

  (866) 0x43b87c LDR	X7, [X14]

  (866) 0x43b880 LDUR	X14, [X29, #464]

  (866) 0x43b884 LDR	X21, [X14]

  (866) 0x43b888 B	43b89c

  (866) 0x43b88c LDR	X14, [X9, #8]

  (866) 0x43b890 ADD	X0, X0, #1

  (866) 0x43b894 CMP	X0, X14

  (866) 0x43b898 B.GE	43b808

  (866) 0x43b89c LDR	X30, [X4, X0,LSL #3]

  (866) 0x43b8a0 LDR	X14, [X28]

  (866) 0x43b8a4 LDR	X16, [X24]

  (866) 0x43b8a8 SUBS	X14, X30, X14

  (866) 0x43b8ac CCMP	X30, X16, #0, #10

  (866) 0x43b8b0 B.LT	43b8e0

  (866) 0x43b8b4 ORN	X14, XZR, X30

  (866) 0x43b8b8 LDR	X17, [X7, X18,LSL #3]

  (866) 0x43b8bc LDR	X16, [X23, X14,LSL #3]

  (866) 0x43b8c0 CMP	X16, X17

  (866) 0x43b8c4 B.GE	43b88c

  (866) 0x43b8c8 STR	X20, [X23, X14,LSL #3]

  (866) 0x43b8cc MOVZ	W16, #1

  (866) 0x43b8d0 ADD	X20, X20, #1

  (866) 0x43b8d4 STR	X16, [X21, X14,LSL #3]

  (866) 0x43b8d8 B	43b88c

0x43b8dc HINT	#0

(865) 0x43b8e0 LDR	X16, [X22, X14,LSL #3]

(865) 0x43b8e4 LDR	X17, [X8, X18,LSL #3]

(865) 0x43b8e8 CMP	X16, X17

(865) 0x43b8ec B.GE	43b88c

(865) 0x43b8f0 STR	X19, [X22, X14,LSL #3]

(865) 0x43b8f4 ADD	X19, X19, #1

(865) 0x43b8f8 B	43b88c

      (863) 0x43b8fc LDUR	X14, [X29, #392]

      (863) 0x43b900 LDUR	X16, [X29, #448]

      (863) 0x43b904 B	43b5f4

0x43b908 ADD	X11, X11, #8

0x43b90c ADD	X10, X10, #8

0x43b910 ADD	X9, X9, #8

0x43b914 HINT	#0

0x43b918 HINT	#0

0x43b91c HINT	#0

(860) 0x43b920 LDP	X12, X13, [X9, #1016]

(860) 0x43b924 SUBS	X8, X8, #1

(860) 0x43b928 ADD	X12, X13, X12

(860) 0x43b92c STR	X12, [X9], #8

(860) 0x43b930 LDP	X12, X13, [X10, #1016]

(860) 0x43b934 ADD	X12, X13, X12

(860) 0x43b938 STR	X12, [X10], #8

(860) 0x43b93c LDP	X12, X13, [X11, #1016]

(860) 0x43b940 ADD	X12, X13, X12

(860) 0x43b944 STR	X12, [X11], #8

(860) 0x43b948 B.NE	43b920

0x43b94c ADRP	X0,

0x43b950 ADD	X0, X0, #1504

0x43b954 ORR	W1, WZR, W20

0x43b958 BL	4104c0

0x43b95c LDUR	X2, [X29, #392]

0x43b960 LDR	X25, [SP, #96]

0x43b964 CMP	X21, #1

0x43b968 B.LT	43ba50

0x43b96c SUBS	X8, X2, X27

0x43b970 B.LE	43ba50

0x43b974 LDUR	X9, [X29, #424]

0x43b978 LDUR	X10, [X29, #456]

0x43b97c LDUR	X12, [X29, #472]

0x43b980 CNTW	X13, ALL

0x43b984 MOVZ	W14, #16

0x43b988 CMP	X13, #16

0x43b98c CSEL	X14, X13, X14, #8

0x43b990 LDR	X17, [X26]

0x43b994 CMP	X8, X14

0x43b998 ORR	X14, XZR, X27

0x43b99c LDR	X16, [X9]

0x43b9a0 LDR	X11, [X10]

0x43b9a4 LDR	X12, [X12]

0x43b9a8 UBFM	X9, X21, #61, #60

0x43b9ac SUB	X10, X9, #8

0x43b9b0 ADD	X9, X16, X10

0x43b9b4 ADD	X10, X17, X10

0x43b9b8 B.CS	43ca04

0x43b9bc SUB	X13, X2, X14

0x43b9c0 UBFM	X14, X14, #61, #60

0x43b9c4 ADD	X14, X14, #8

0x43b9c8 ADD	X12, X12, X14

0x43b9cc ADD	X11, X11, X14

0x43b9d0 HINT	#0

0x43b9d4 HINT	#0

0x43b9d8 HINT	#0

0x43b9dc HINT	#0

(857) 0x43b9e0 LDR	X14, [X9]

(857) 0x43b9e4 LDR	X15, [X11]

(857) 0x43b9e8 SUBS	X13, X13, #1

(857) 0x43b9ec ADD	X14, X15, X14

(857) 0x43b9f0 STR	X14, [X11], #8

(857) 0x43b9f4 LDR	X14, [X10]

(857) 0x43b9f8 LDR	X15, [X12]

(857) 0x43b9fc ADD	X14, X15, X14

(857) 0x43ba00 STR	X14, [X12], #8

(857) 0x43ba04 B.NE	43b9e0

0x43ba08 LDUR	X9, [X29, #408]

0x43ba0c LDR	X11, [SP, #176]

0x43ba10 LDR	X10, [X9]

0x43ba14 LDUR	X9, [X29, #440]

0x43ba18 MUL	X11, X21, X11

0x43ba1c LDR	X9, [X9]

0x43ba20 ADD	X10, X10, X11,LSL #3

0x43ba24 ADD	X9, X9, X21,LSL #3

0x43ba28 B	43ba38

(858) 0x43ba2c ADD	X10, X10, #8

(858) 0x43ba30 SUBS	X8, X8, #1

(858) 0x43ba34 B.EQ	43ba50

(858) 0x43ba38 LDR	X11, [X10]

(858) 0x43ba3c TBNZ	X11, #63, 43ba2c

(858) 0x43ba40 LDUR	X12, [X9, #504]

(858) 0x43ba44 ADD	X11, X12, X11

(858) 0x43ba48 STR	X11, [X10]

(858) 0x43ba4c B	43ba2c

0x43ba50 ADRP	X0,

0x43ba54 ADD	X0, X0, #1528

0x43ba58 ORR	W1, WZR, W20

0x43ba5c BL	4104c0

0x43ba60 CBZ	X21, 43ba74

0x43ba64 LDUR	X13, [X29, #384]

0x43ba68 LDR	X12, [SP, #224]

0x43ba6c LDR	X8, [X13]

0x43ba70 B	43bc40

0x43ba74 LDR	X9, [SP, #56]

0x43ba78 LDR	X8, [X9]

0x43ba7c CMP	X8, #4

0x43ba80 B.NE	43bad8

0x43ba84 ORR	W21, WZR, W20

0x43ba88 ORR	X20, XZR, X9

0x43ba8c BL	4acce0

0x43ba90 LDR	X8, [SP, #40]

0x43ba94 ADRP	X0,

0x43ba98 ADD	X0, X0, #3787

0x43ba9c LDR	D1, [X8]

0x43baa0 FSUB	D0, D0, S1

0x43baa4 STR	D0, [X8]

0x43baa8 LDR	X8, [SP, #8]

0x43baac LDR	X1, [X8]

0x43bab0 BL	4ab120

0x43bab4 ORR	X0, XZR, XZR

0x43bab8 BL	4102b0

0x43babc LDR	X8, [X20]

0x43bac0 ORR	W20, WZR, W21

0x43bac4 CMP	X8, #4

0x43bac8 B.NE	43bad8

0x43bacc BL	4acce0

0x43bad0 LDR	X8, [SP, #40]

0x43bad4 STR	D0, [X8]

0x43bad8 LDUR	X8, [X29, #456]

0x43badc LDUR	X13, [X29, #384]

0x43bae0 LDR	X10, [SP, #64]

0x43bae4 LDR	X8, [X8]

0x43bae8 LDR	X9, [X13]

0x43baec LDR	X8, [X8, X9,LSL #3]

0x43baf0 STR	X8, [X10]

0x43baf4 LDUR	X8, [X29, #472]

0x43baf8 LDR	X9, [X13]

0x43bafc LDR	X8, [X8]

0x43bb00 LDR	X0, [X8, X9,LSL #3]

0x43bb04 STR	X0, [X19]

0x43bb08 LDR	X8, [X10]

0x43bb0c CBZ	X8, 43bb4c

0x43bb10 MOVZ	W1, #8

0x43bb14 ORR	X0, XZR, X8

0x43bb18 ORR	W21, WZR, W20

0x43bb1c ORR	X20, XZR, X10

0x43bb20 BL	4aaf00

0x43bb24 LDUR	X8, [X29, #400]

0x43bb28 MOVZ	W1, #8

0x43bb2c STR	X0, [X8]

0x43bb30 LDR	X0, [X20]

0x43bb34 ORR	W20, WZR, W21

0x43bb38 BL	4aaf00

0x43bb3c LDUR	X8, [X29, #432]

0x43bb40 LDUR	X13, [X29, #384]

0x43bb44 STR	X0, [X8]

0x43bb48 LDR	X0, [X19]

0x43bb4c LDR	X12, [SP, #224]

0x43bb50 CBZ	X0, 43bb80

0x43bb54 MOVZ	W1, #8

0x43bb58 BL	4aaf00

0x43bb5c LDUR	X8, [X29, #336]

0x43bb60 MOVZ	W1, #8

0x43bb64 STR	X0, [X8]

0x43bb68 LDR	X0, [X19]

0x43bb6c BL	4aaf00

0x43bb70 LDUR	X13, [X29, #384]

0x43bb74 LDR	X12, [SP, #224]

0x43bb78 LDUR	X8, [X29, #416]

0x43bb7c STR	X0, [X8]

0x43bb80 LDUR	X8, [X29, #488]

0x43bb84 LDR	X9, [X8]

0x43bb88 LDR	X8, [X13]

0x43bb8c CMP	X9, #1

0x43bb90 B.LE	43bc40

0x43bb94 LDR	X14, [SP, #48]

0x43bb98 CMP	X8, #1

0x43bb9c B.LT	43bbcc

0x43bba0 LDUR	X9, [X29, #408]

0x43bba4 ORR	X8, XZR, XZR

0x43bba8 LDR	X9, [X9]

(856) 0x43bbac LDR	X10, [X14]

(856) 0x43bbb0 LDR	X11, [X9, X8,LSL #3]

(856) 0x43bbb4 ADD	X10, X11, X10

(856) 0x43bbb8 STR	X10, [X9, X8,LSL #3]

(856) 0x43bbbc ADD	X8, X8, #1

(856) 0x43bbc0 LDR	X10, [X13]

(856) 0x43bbc4 CMP	X8, X10

(856) 0x43bbc8 B.LT	43bbac

0x43bbcc LDP	X9, X8, [SP, #16]

0x43bbd0 LDR	X3, [X12]

0x43bbd4 LDR	X1, [X8]

0x43bbd8 LDUR	X8, [X29, #408]

0x43bbdc LDR	X0, [X9]

0x43bbe0 LDR	X2, [X8]

0x43bbe4 LDR	X8, [SP, #32]

0x43bbe8 LDR	X4, [X8]

0x43bbec BL	47c4c0

0x43bbf0 LDUR	X13, [X29, #384]

0x43bbf4 LDR	X12, [SP, #224]

0x43bbf8 LDR	X8, [X13]

0x43bbfc CMP	X8, #1

0x43bc00 B.LT	43bc74

0x43bc04 LDUR	X8, [X29, #408]

0x43bc08 LDR	X14, [SP, #48]

0x43bc0c ORR	X9, XZR, XZR

0x43bc10 LDR	X10, [X8]

0x43bc14 HINT	#0

0x43bc18 HINT	#0

0x43bc1c HINT	#0

(855) 0x43bc20 LDR	X8, [X14]

(855) 0x43bc24 LDR	X11, [X10, X9,LSL #3]

(855) 0x43bc28 SUB	X8, X11, X8

(855) 0x43bc2c STR	X8, [X10, X9,LSL #3]

(855) 0x43bc30 ADD	X9, X9, #1

(855) 0x43bc34 LDR	X8, [X13]

(855) 0x43bc38 CMP	X9, X8

(855) 0x43bc3c B.LT	43bc20

0x43bc40 CMP	X8, #1

0x43bc44 B.LT	43bc74

0x43bc48 MOVN	X9, #0

0x43bc4c ORR	X8, XZR, XZR

0x43bc50 HINT	#0

0x43bc54 HINT	#0

0x43bc58 HINT	#0

0x43bc5c HINT	#0

(854) 0x43bc60 STR	X9, [X22, X8,LSL #3]

(854) 0x43bc64 ADD	X8, X8, #1

(854) 0x43bc68 LDR	X10, [X13]

(854) 0x43bc6c CMP	X8, X10

(854) 0x43bc70 B.LT	43bc60

0x43bc74 LDR	X8, [X12]

0x43bc78 CMP	X8, #1

0x43bc7c B.LT	43bc9c

0x43bc80 MOVN	X9, #0

0x43bc84 ORR	X8, XZR, XZR

(853) 0x43bc88 STR	X9, [X23, X8,LSL #3]

(853) 0x43bc8c ADD	X8, X8, #1

(853) 0x43bc90 LDR	X10, [X12]

(853) 0x43bc94 CMP	X8, X10

(853) 0x43bc98 B.LT	43bc88

0x43bc9c ADRP	X0,

0x43bca0 ADD	X0, X0, #1552

0x43bca4 ORR	W1, WZR, W20

0x43bca8 BL	4104c0

0x43bcac LDP	X13, X14, [X29, #896]

0x43bcb0 LDUR	X9, [X29, #312]

0x43bcb4 CMP	X14, X27

0x43bcb8 B.GT	43bcfc

0x43bcbc LDR	X8, [X13]

0x43bcc0 CBZ	X8, 43bccc

0x43bcc4 ORR	X0, XZR, X22

0x43bcc8 BL	4ab000

0x43bccc LDR	X8, [SP, #224]

0x43bcd0 LDR	X8, [X8]

0x43bcd4 CBZ	X8, 43c9e4

0x43bcd8 ORR	X0, XZR, X23

0x43bcdc ADD	SP, SP, #448

0x43bce0 LDP	X20, X19, [SP, #80]

0x43bce4 LDP	X22, X21, [SP, #64]

0x43bce8 LDP	X24, X23, [SP, #48]

0x43bcec LDP	X26, X25, [SP, #32]

0x43bcf0 LDP	X28, X27, [SP, #16]

0x43bcf4 LDP	X29, X30, [SP], #96

0x43bcf8 B	4ab000

0x43bcfc LDUR	X8, [X29, #456]

0x43bd00 CNTW	X1, ALL

0x43bd04 FMOV	D0, #1.0000000

0x43bd08 FMOV	D1, #-1.0000000

0x43bd0c MOVN	X30, #1

0x43bd10 SUB	X1, XZR, X1

0x43bd14 PTRUE	P0.D, ALL

0x43bd18 LDR	X15, [X8]

0x43bd1c LDUR	X8, [X29, #472]

0x43bd20 LDR	X8, [X8]

0x43bd24 STR	X8, [SP, #184]

0x43bd28 LDP	X11, X8, [X29, #872]

0x43bd2c LDR	X10, [X11]

0x43bd30 LDR	X11, [X8]

0x43bd34 LDUR	X8, [X29, #376]

0x43bd38 LDR	X12, [X8]

0x43bd3c LDUR	X8, [X29, #296]

0x43bd40 LDR	X8, [X8]

0x43bd44 STUR	X8, [X29, #480]

0x43bd48 LDUR	X8, [X29, #344]

0x43bd4c LDR	X8, [X8]

0x43bd50 STUR	X8, [X29, #472]

0x43bd54 LDUR	X8, [X29, #304]

0x43bd58 LDR	X8, [X8]

0x43bd5c STUR	X8, [X29, #464]

0x43bd60 LDUR	X8, [X29, #320]

0x43bd64 LDR	X8, [X8]

0x43bd68 STUR	X8, [X29, #456]

0x43bd6c LDR	X8, [SP, #104]

0x43bd70 LDR	X16, [X8]

0x43bd74 LDR	X8, [SP, #160]

0x43bd78 LDR	X17, [X8]

0x43bd7c LDUR	X8, [X29, #432]

0x43bd80 LDR	X18, [X8]

0x43bd84 LDUR	X8, [X29, #416]

0x43bd88 LDR	X0, [X8]

0x43bd8c LDR	X8, [SP, #168]

0x43bd90 LDR	X8, [X8]

0x43bd94 STUR	X8, [X29, #424]

0x43bd98 STR	X1, [SP, #56]

0x43bd9c LDR	X8, [SP, #128]

0x43bda0 LDR	X8, [X8]

0x43bda4 STR	X8, [SP, #104]

0x43bda8 RDVL	X8, #1

0x43bdac STUR	X16, [X29, #496]

0x43bdb0 ADD	X16, X16, #8

0x43bdb4 STUR	X17, [X29, #440]

0x43bdb8 STUR	X16, [X29, #368]

0x43bdbc ADD	X16, X17, #8

0x43bdc0 STUR	X16, [X29, #360]

0x43bdc4 ADD	X16, X18, X8

0x43bdc8 ADD	X8, X0, X8

0x43bdcc STR	X0, [SP, #64]

0x43bdd0 STP	X8, X16, [SP, #40]

0x43bdd4 LDR	X8, [SP, #136]

0x43bdd8 LDR	X8, [X8]

0x43bddc STUR	X8, [X29, #448]

0x43bde0 LDUR	X8, [X29, #408]

0x43bde4 LDR	X16, [X8]

0x43bde8 LDUR	X8, [X29, #400]

0x43bdec STR	X15, [SP, #192]

0x43bdf0 LDR	X17, [X8]

0x43bdf4 STP	X16, X18, [SP, #168]

0x43bdf8 STR	X17, [SP, #160]

0x43bdfc B	43be20

      (833) 0x43be00 LDR	D2, [X9]

      (833) 0x43be04 LDR	X8, [X16, X27,LSL #3]

      (833) 0x43be08 STR	X8, [X17, X7,LSL #3]

      (833) 0x43be0c STR	D2, [X18, X7,LSL #3]

      (833) 0x43be10 ADD	X27, X27, #1

      (833) 0x43be14 SUB	X30, X30, #1

      (833) 0x43be18 CMP	X27, X14

      (833) 0x43be1c B.EQ	43bcbc

      (833) 0x43be20 LDR	X7, [X15, X27,LSL #3]

      (833) 0x43be24 LDR	X8, [X10, X27,LSL #3]

      (833) 0x43be28 TBZ	X8, #63, 43be00

      (833) 0x43be2c CMN	X8, #3

      (833) 0x43be30 B.EQ	43be10

    (834) 0x43be34 LDR	X8, [SP, #184]

    (834) 0x43be38 ADD	X9, X27, #1

    (834) 0x43be3c SUB	X30, X30, #1

    (834) 0x43be40 ORR	X1, XZR, X7

    (834) 0x43be44 LDR	X13, [X11, X9,LSL #3]

    (834) 0x43be48 LDR	X3, [X8, X27,LSL #3]

    (834) 0x43be4c LDR	X8, [X11, X27,LSL #3]

    (834) 0x43be50 CMP	X8, X13

    (834) 0x43be54 ORR	X6, XZR, X3

    (834) 0x43be58 B.GE	43c02c

    (834) 0x43be5c LDUR	X9, [X29, #296]

    (834) 0x43be60 ORR	X1, XZR, X7

    (834) 0x43be64 ORR	X6, XZR, X3

    (834) 0x43be68 LDR	X14, [X9]

    (834) 0x43be6c LDUR	X9, [X29, #304]

    (834) 0x43be70 LDR	X16, [X9]

    (834) 0x43be74 LDUR	X9, [X29, #320]

    (834) 0x43be78 LDR	X0, [X9]

    (834) 0x43be7c LDUR	X9, [X29, #408]

    (834) 0x43be80 LDR	X4, [X9]

    (834) 0x43be84 LDUR	X9, [X29, #400]

    (834) 0x43be88 LDR	X5, [X9]

    (834) 0x43be8c LDUR	X9, [X29, #432]

    (834) 0x43be90 LDR	X19, [X9]

    (834) 0x43be94 B	43beb4

0x43be98 HINT	#0

0x43be9c HINT	#0

      (845) 0x43bea0 ADD	X9, X27, #1

      (845) 0x43bea4 ADD	X8, X8, #1

      (845) 0x43bea8 LDR	X9, [X11, X9,LSL #3]

      (845) 0x43beac CMP	X8, X9

      (845) 0x43beb0 B.GE	43c02c

      (845) 0x43beb4 LDR	X13, [X12, X8,LSL #3]

      (845) 0x43beb8 LDR	X15, [X10, X13,LSL #3]

      (845) 0x43bebc TBNZ	X15, #63, 43bee8

      (845) 0x43bec0 LDR	X15, [X22, X13,LSL #3]

      (845) 0x43bec4 CMP	X15, X7

      (845) 0x43bec8 B.GE	43bea0

      (845) 0x43becc LDR	D2, [X25]

      (845) 0x43bed0 STR	X1, [X22, X13,LSL #3]

      (845) 0x43bed4 LDR	X13, [X4, X13,LSL #3]

      (845) 0x43bed8 STR	X13, [X5, X1,LSL #3]

      (845) 0x43bedc STR	D2, [X19, X1,LSL #3]

      (845) 0x43bee0 ADD	X1, X1, #1

      (845) 0x43bee4 B	43bea0

      (845) 0x43bee8 CMN	X15, #3

      (845) 0x43beec B.EQ	43bea0

      (845) 0x43bef0 STR	X30, [X22, X13,LSL #3]

      (845) 0x43bef4 ADD	X20, X13, #1

      (845) 0x43bef8 LDR	X15, [X11, X13,LSL #3]

      (845) 0x43befc LDR	X26, [X11, X20,LSL #3]

      (845) 0x43bf00 CMP	X15, X26

      (845) 0x43bf04 B.GE	43bf68

      (845) 0x43bf08 LDUR	X9, [X29, #408]

      (845) 0x43bf0c LDR	X2, [X9]

      (845) 0x43bf10 LDUR	X9, [X29, #400]

      (845) 0x43bf14 LDR	X21, [X9]

      (845) 0x43bf18 LDUR	X9, [X29, #432]

      (845) 0x43bf1c LDR	X18, [X9]

      (845) 0x43bf20 B	43bf30

        (848) 0x43bf24 ADD	X15, X15, #1

        (848) 0x43bf28 CMP	X15, X26

        (848) 0x43bf2c B.GE	43bf68

        (848) 0x43bf30 LDR	X17, [X12, X15,LSL #3]

        (848) 0x43bf34 LDR	X9, [X10, X17,LSL #3]

        (848) 0x43bf38 TBNZ	X9, #63, 43bf24

        (848) 0x43bf3c LDR	X9, [X22, X17,LSL #3]

        (848) 0x43bf40 CMP	X9, X7

        (848) 0x43bf44 B.GE	43bf24

        (848) 0x43bf48 STR	X1, [X22, X17,LSL #3]

        (848) 0x43bf4c LDR	D2, [X25]

        (848) 0x43bf50 LDR	X9, [X2, X17,LSL #3]

        (848) 0x43bf54 STR	X9, [X21, X1,LSL #3]

        (848) 0x43bf58 LDR	X26, [X11, X20,LSL #3]

        (848) 0x43bf5c STR	D2, [X18, X1,LSL #3]

        (848) 0x43bf60 ADD	X1, X1, #1

        (848) 0x43bf64 B	43bf24

      (845) 0x43bf68 LDUR	X9, [X29, #488]

      (845) 0x43bf6c LDR	X9, [X9]

      (845) 0x43bf70 CMP	X9, #2

      (845) 0x43bf74 B.LT	43bea0

      (845) 0x43bf78 LDR	X21, [X14, X13,LSL #3]

      (845) 0x43bf7c LDR	X15, [X14, X20,LSL #3]

      (845) 0x43bf80 CMP	X21, X15

      (845) 0x43bf84 B.GE	43bea0

      (845) 0x43bf88 LDUR	X9, [X29, #344]

      (845) 0x43bf8c LDR	X26, [X9]

      (845) 0x43bf90 LDUR	X9, [X29, #336]

      (845) 0x43bf94 LDR	X13, [X9]

      (845) 0x43bf98 LDUR	X9, [X29, #416]

      (845) 0x43bf9c LDR	X2, [X9]

      (845) 0x43bfa0 CBNZ	X16, 43bfb4

      (845) 0x43bfa4 B	43bff8

        (846) 0x43bfa8 ADD	X21, X21, #1

        (846) 0x43bfac CMP	X21, X15

        (846) 0x43bfb0 B.GE	43bea0

        (846) 0x43bfb4 LDR	X9, [X26, X21,LSL #3]

        (846) 0x43bfb8 LDR	X17, [X16, X9,LSL #3]

        (846) 0x43bfbc LDR	X9, [X0, X17,LSL #3]

        (846) 0x43bfc0 TBNZ	X9, #63, 43bfa8

        (846) 0x43bfc4 LDR	X9, [X23, X17,LSL #3]

        (846) 0x43bfc8 CMP	X9, X3

        (846) 0x43bfcc B.GE	43bfa8

        (846) 0x43bfd0 LDR	D2, [X25]

        (846) 0x43bfd4 STR	X6, [X23, X17,LSL #3]

        (846) 0x43bfd8 STR	X17, [X13, X6,LSL #3]

        (846) 0x43bfdc LDR	X15, [X14, X20,LSL #3]

        (846) 0x43bfe0 STR	D2, [X2, X6,LSL #3]

        (846) 0x43bfe4 ADD	X6, X6, #1

        (846) 0x43bfe8 B	43bfa8

        (847) 0x43bfec ADD	X21, X21, #1

        (847) 0x43bff0 CMP	X21, X15

        (847) 0x43bff4 B.GE	43bea0

        (847) 0x43bff8 LDR	X17, [X26, X21,LSL #3]

        (847) 0x43bffc LDR	X9, [X0, X17,LSL #3]

        (847) 0x43c000 TBNZ	X9, #63, 43bfec

        (847) 0x43c004 LDR	X9, [X23, X17,LSL #3]

        (847) 0x43c008 CMP	X9, X3

        (847) 0x43c00c B.GE	43bfec

        (847) 0x43c010 LDR	D2, [X25]

        (847) 0x43c014 STR	X6, [X23, X17,LSL #3]

        (847) 0x43c018 STR	X17, [X13, X6,LSL #3]

        (847) 0x43c01c LDR	X15, [X14, X20,LSL #3]

        (847) 0x43c020 STR	D2, [X2, X6,LSL #3]

        (847) 0x43c024 ADD	X6, X6, #1

        (847) 0x43c028 B	43bfec

    (834) 0x43c02c LDUR	X8, [X29, #488]

    (834) 0x43c030 LDR	X8, [X8]

    (834) 0x43c034 CMP	X8, #2

    (834) 0x43c038 B.LT	43c1a8

    (834) 0x43c03c LDUR	X9, [X29, #480]

    (834) 0x43c040 ADD	X13, X27, #1

    (834) 0x43c044 LDR	X8, [X9, X27,LSL #3]

    (834) 0x43c048 LDR	X9, [X9, X13,LSL #3]

    (834) 0x43c04c CMP	X8, X9

    (834) 0x43c050 B.GE	43c1b0

    (834) 0x43c054 LDR	X9, [SP, #112]

    (834) 0x43c058 LDR	X14, [X9]

    (834) 0x43c05c LDR	X9, [SP, #120]

    (834) 0x43c060 LDR	X16, [X9]

    (834) 0x43c064 LDUR	X9, [X29, #336]

    (834) 0x43c068 LDR	X0, [X9]

    (834) 0x43c06c LDUR	X9, [X29, #416]

    (834) 0x43c070 LDR	X4, [X9]

    (834) 0x43c074 B	43c098

0x43c078 HINT	#0

0x43c07c HINT	#0

      (843) 0x43c080 LDUR	X9, [X29, #480]

      (843) 0x43c084 ADD	X13, X27, #1

      (843) 0x43c088 ADD	X8, X8, #1

      (843) 0x43c08c LDR	X9, [X9, X13,LSL #3]

      (843) 0x43c090 CMP	X8, X9

      (843) 0x43c094 B.GE	43c1b8

      (843) 0x43c098 LDUR	X9, [X29, #472]

      (843) 0x43c09c LDR	X13, [X9, X8,LSL #3]

      (843) 0x43c0a0 LDUR	X9, [X29, #464]

      (843) 0x43c0a4 CBZ	X9, 43c0ac

      (843) 0x43c0a8 LDR	X13, [X9, X13,LSL #3]

      (843) 0x43c0ac LDUR	X9, [X29, #456]

      (843) 0x43c0b0 LDR	X15, [X9, X13,LSL #3]

      (843) 0x43c0b4 TBNZ	X15, #63, 43c0e0

      (843) 0x43c0b8 LDR	X9, [X23, X13,LSL #3]

      (843) 0x43c0bc CMP	X9, X3

      (843) 0x43c0c0 B.GE	43c080

      (843) 0x43c0c4 LDR	D2, [X25]

      (843) 0x43c0c8 STR	X6, [X23, X13,LSL #3]

      (843) 0x43c0cc STR	X13, [X0, X6,LSL #3]

      (843) 0x43c0d0 STR	D2, [X4, X6,LSL #3]

      (843) 0x43c0d4 ADD	X6, X6, #1

      (843) 0x43c0d8 B	43c080

0x43c0dc HINT	#0

      (843) 0x43c0e0 CMN	X15, #3

      (843) 0x43c0e4 B.EQ	43c080

      (843) 0x43c0e8 UBFM	X9, X13, #61, #60

      (843) 0x43c0ec ADD	X13, X14, X13,LSL #3

      (843) 0x43c0f0 STR	X30, [X23, X9]

      (843) 0x43c0f4 LDP	X15, X9, [X13]

      (843) 0x43c0f8 CMP	X15, X9

      (843) 0x43c0fc B.GE	43c080

      (843) 0x43c100 LDUR	X9, [X29, #336]

      (843) 0x43c104 LDR	X2, [X9]

      (843) 0x43c108 LDUR	X9, [X29, #416]

      (843) 0x43c10c LDR	X5, [X9]

      (843) 0x43c110 LDUR	X9, [X29, #408]

      (843) 0x43c114 LDR	X19, [X9]

      (843) 0x43c118 LDUR	X9, [X29, #400]

      (843) 0x43c11c LDR	X20, [X9]

      (843) 0x43c120 LDUR	X9, [X29, #432]

      (843) 0x43c124 LDR	X21, [X9]

      (843) 0x43c128 B	43c13c

        (844) 0x43c12c LDR	X9, [X13, #8]

        (844) 0x43c130 ADD	X15, X15, #1

        (844) 0x43c134 CMP	X15, X9

        (844) 0x43c138 B.GE	43c080

        (844) 0x43c13c LDR	X17, [X16, X15,LSL #3]

        (844) 0x43c140 LDR	X9, [X28]

        (844) 0x43c144 LDR	X26, [X24]

        (844) 0x43c148 SUBS	X18, X17, X9

        (844) 0x43c14c CCMP	X17, X26, #0, #10

        (844) 0x43c150 B.LT	43c180

        (844) 0x43c154 ORN	X17, XZR, X17

        (844) 0x43c158 LDR	X9, [X23, X17,LSL #3]

        (844) 0x43c15c CMP	X9, X3

        (844) 0x43c160 B.GE	43c12c

        (844) 0x43c164 LDR	D2, [X25]

        (844) 0x43c168 STR	X6, [X23, X17,LSL #3]

        (844) 0x43c16c STR	X17, [X2, X6,LSL #3]

        (844) 0x43c170 STR	D2, [X5, X6,LSL #3]

        (844) 0x43c174 ADD	X6, X6, #1

        (844) 0x43c178 B	43c12c

0x43c17c HINT	#0

        (844) 0x43c180 LDR	X9, [X22, X18,LSL #3]

        (844) 0x43c184 CMP	X9, X7

        (844) 0x43c188 B.GE	43c12c

        (844) 0x43c18c LDR	D2, [X25]

        (844) 0x43c190 STR	X1, [X22, X18,LSL #3]

        (844) 0x43c194 LDR	X9, [X19, X18,LSL #3]

        (844) 0x43c198 STR	X9, [X20, X1,LSL #3]

        (844) 0x43c19c STR	D2, [X21, X1,LSL #3]

        (844) 0x43c1a0 ADD	X1, X1, #1

        (844) 0x43c1a4 B	43c12c

    (834) 0x43c1a8 ORR	W19, WZR, WZR

    (834) 0x43c1ac B	43c1c8

    (834) 0x43c1b0 MOVZ	W19, #1

    (834) 0x43c1b4 B	43c1c8

    (834) 0x43c1b8 LDUR	X8, [X29, #488]

    (834) 0x43c1bc LDR	X8, [X8]

    (834) 0x43c1c0 CMP	X8, #1

    (834) 0x43c1c4 CSINC	W19, WZR, WZR, #13

    (834) 0x43c1c8 LDUR	X13, [X29, #424]

    (834) 0x43c1cc LDUR	X9, [X29, #496]

    (834) 0x43c1d0 LDUR	X14, [X29, #440]

    (834) 0x43c1d4 LDR	X8, [X13, X27,LSL #3]

    (834) 0x43c1d8 LDR	D2, [X9, X8,LSL #3]

    (834) 0x43c1dc ADD	X9, X27, #1

    (834) 0x43c1e0 ADD	X8, X8, #1

    (834) 0x43c1e4 LDR	X0, [X13, X9,LSL #3]

    (834) 0x43c1e8 CMP	X8, X0

    (834) 0x43c1ec B.GE	43c668

    (834) 0x43c1f0 LDUR	X9, [X29, #432]

    (834) 0x43c1f4 LDR	X4, [X9]

    (834) 0x43c1f8 LDR	X9, [SP, #144]

    (834) 0x43c1fc LDR	X9, [X9]

    (834) 0x43c200 STUR	X9, [X29, #376]

    (834) 0x43c204 LDR	X9, [SP, #152]

    (834) 0x43c208 LDR	X9, [X9]

    (834) 0x43c20c STR	X9, [SP, #216]

    (834) 0x43c210 LDR	X9, [SP, #128]

    (834) 0x43c214 LDR	X26, [X9]

    (834) 0x43c218 LDR	X9, [SP, #136]

    (834) 0x43c21c LDR	X9, [X9]

    (834) 0x43c220 STR	X9, [SP, #208]

    (834) 0x43c224 ADD	X9, X9, #8

    (834) 0x43c228 STR	X9, [SP, #200]

    (834) 0x43c22c B	43c260

0x43c230 HINT	#0

0x43c234 HINT	#0

0x43c238 HINT	#0

0x43c23c HINT	#0

      (838) 0x43c240 LDUR	X9, [X29, #496]

      (838) 0x43c244 LDR	D4, [X4, X13,LSL #3]

      (838) 0x43c248 LDR	D3, [X9, X8,LSL #3]

      (838) 0x43c24c FADD	D3, D3, D4

      (838) 0x43c250 STR	D3, [X4, X13,LSL #3]

      (838) 0x43c254 ADD	X8, X8, #1

      (838) 0x43c258 CMP	X8, X0

      (838) 0x43c25c B.EQ	43c668

      (838) 0x43c260 LDR	X20, [X14, X8,LSL #3]

      (838) 0x43c264 LDR	X13, [X22, X20,LSL #3]

      (838) 0x43c268 CMP	X13, X7

      (838) 0x43c26c B.GE	43c240

      (838) 0x43c270 CMP	X13, X30

      (838) 0x43c274 B.NE	43c300

      (838) 0x43c278 LDUR	X13, [X29, #424]

      (838) 0x43c27c LDUR	X9, [X29, #496]

      (838) 0x43c280 LDR	D4, [X25]

      (838) 0x43c284 ADD	X21, X20, #1

      (838) 0x43c288 LDR	X14, [X13, X20,LSL #3]

      (838) 0x43c28c LDR	X16, [X13, X21,LSL #3]

      (838) 0x43c290 LDR	D3, [X9, X14,LSL #3]

      (838) 0x43c294 ADD	X5, X14, #1

      (838) 0x43c298 FCMP	D3, #0

      (838) 0x43c29c FCSEL	D3, D1, D0, #4

      (838) 0x43c2a0 CMP	X5, X16

      (838) 0x43c2a4 B.GE	43c34c

      (838) 0x43c2a8 SUB	W9, W14, W16

      (838) 0x43c2ac TBNZ	W9, #0, 43c33c

      (838) 0x43c2b0 LDUR	X9, [X29, #440]

      (838) 0x43c2b4 LDR	X9, [X9, X5,LSL #3]

      (838) 0x43c2b8 LDR	X13, [X22, X9,LSL #3]

      (838) 0x43c2bc CMP	X9, X27

      (838) 0x43c2c0 CCMP	X13, X7, #0, #1

      (838) 0x43c2c4 B.LT	43c2e0

      (838) 0x43c2c8 LDUR	X9, [X29, #496]

      (838) 0x43c2cc LDR	D5, [X9, X5,LSL #3]

      (838) 0x43c2d0 FMUL	D6, D3, D5

      (838) 0x43c2d4 FCMP	D6, #0

      (838) 0x43c2d8 B.PL	43c2e0

      (838) 0x43c2dc FADD	D4, D4, D5

      (838) 0x43c2e0 ADD	X18, X14, #2

      (838) 0x43c2e4 SUB	X9, X16, #2

      (838) 0x43c2e8 CMP	X9, X14

      (838) 0x43c2ec B.EQ	43c34c

      (838) 0x43c2f0 B	43c384

0x43c2f4 HINT	#0

0x43c2f8 HINT	#0

0x43c2fc HINT	#0

      (838) 0x43c300 LDR	X9, [X10, X20,LSL #3]

      (838) 0x43c304 CMN	X9, #3

      (838) 0x43c308 B.EQ	43c254

      (838) 0x43c30c LDUR	X9, [X29, #376]

      (838) 0x43c310 CMP	X9, #1

      (838) 0x43c314 B.EQ	43c32c

      (838) 0x43c318 LDR	X13, [SP, #216]

      (838) 0x43c31c LDR	X9, [X13, X27,LSL #3]

      (838) 0x43c320 LDR	X13, [X13, X20,LSL #3]

      (838) 0x43c324 CMP	X9, X13

      (838) 0x43c328 B.NE	43c254

      (838) 0x43c32c LDUR	X9, [X29, #496]

      (838) 0x43c330 LDR	D3, [X9, X8,LSL #3]

      (838) 0x43c334 FADD	D2, D2, D3

      (838) 0x43c338 B	43c254

      (838) 0x43c33c ADD	X18, X14, #1

      (838) 0x43c340 SUB	X9, X16, #2

      (838) 0x43c344 CMP	X9, X14

      (838) 0x43c348 B.NE	43c384

      (838) 0x43c34c CBZ	W19, 43c440

      (838) 0x43c350 LDR	X15, [X26, X20,LSL #3]

      (838) 0x43c354 LDR	X13, [X26, X21,LSL #3]

      (838) 0x43c358 CMP	X13, X15

      (838) 0x43c35c B.LE	43c440

      (838) 0x43c360 LDUR	X9, [X29, #352]

      (838) 0x43c364 LDR	X2, [X9]

      (838) 0x43c368 SUB	W9, W13, W15

      (838) 0x43c36c TBNZ	W9, #0, 43c404

      (838) 0x43c370 ORR	X18, XZR, X15

      (838) 0x43c374 ADD	X9, X15, #1

      (838) 0x43c378 CMP	X13, X9

      (838) 0x43c37c B.EQ	43c440

      (838) 0x43c380 B	43c524

      (838) 0x43c384 LDUR	X9, [X29, #368]

      (838) 0x43c388 SUB	X13, X16, X18

      (838) 0x43c38c ADD	X15, X9, X18,LSL #3

      (838) 0x43c390 LDUR	X9, [X29, #360]

      (838) 0x43c394 ADD	X2, X9, X18,LSL #3

      (838) 0x43c398 B	43c3b0

0x43c39c HINT	#0

        (842) 0x43c3a0 ADD	X2, X2, #16

        (842) 0x43c3a4 SUBS	X13, X13, #2

        (842) 0x43c3a8 ADD	X15, X15, #16

        (842) 0x43c3ac B.EQ	43c34c

        (842) 0x43c3b0 LDUR	X9, [X2, #504]

        (842) 0x43c3b4 LDR	X17, [X22, X9,LSL #3]

        (842) 0x43c3b8 CMP	X9, X27

        (842) 0x43c3bc CCMP	X17, X7, #0, #1

        (842) 0x43c3c0 B.LT	43c3d8

        (842) 0x43c3c4 LDUR	D5, [X15, #504]

        (842) 0x43c3c8 FMUL	D6, D3, D5

        (842) 0x43c3cc FCMP	D6, #0

        (842) 0x43c3d0 B.PL	43c3d8

        (842) 0x43c3d4 FADD	D4, D4, D5

        (842) 0x43c3d8 LDR	X9, [X2]

        (842) 0x43c3dc LDR	X17, [X22, X9,LSL #3]

        (842) 0x43c3e0 CMP	X9, X27

        (842) 0x43c3e4 CCMP	X17, X7, #0, #1

        (842) 0x43c3e8 B.LT	43c3a0

        (842) 0x43c3ec LDR	D5, [X15]

        (842) 0x43c3f0 FMUL	D6, D3, D5

        (842) 0x43c3f4 FCMP	D6, #0

        (842) 0x43c3f8 B.PL	43c3a0

        (842) 0x43c3fc FADD	D4, D4, D5

        (842) 0x43c400 B	43c3a0

      (838) 0x43c404 LDR	X9, [SP, #208]

      (838) 0x43c408 LDR	X9, [X9, X15,LSL #3]

      (838) 0x43c40c LDR	X9, [X23, X9,LSL #3]

      (838) 0x43c410 CMP	X9, X3

      (838) 0x43c414 B.LT	43c42c

      (838) 0x43c418 LDR	D5, [X2, X15,LSL #3]

      (838) 0x43c41c FMUL	D6, D3, D5

      (838) 0x43c420 FCMP	D6, #0

      (838) 0x43c424 B.PL	43c42c

      (838) 0x43c428 FADD	D4, D4, D5

      (838) 0x43c42c ADD	X18, X15, #1

      (838) 0x43c430 ADD	X9, X15, #1

      (838) 0x43c434 CMP	X13, X9

      (838) 0x43c438 B.NE	43c524

      (838) 0x43c43c HINT	#0

      (838) 0x43c440 LDUR	X9, [X29, #496]

      (838) 0x43c444 FCMP	D4, #0

      (838) 0x43c448 LDR	D5, [X9, X8,LSL #3]

      (838) 0x43c44c B.EQ	43c518

      (838) 0x43c450 FDIV	D4, D5, D4

      (838) 0x43c454 CMP	X5, X16

      (838) 0x43c458 B.GE	43c4d8

      (838) 0x43c45c LDUR	X9, [X29, #432]

      (838) 0x43c460 LDR	X13, [X9]

      (838) 0x43c464 ORN	X9, XZR, X14

      (838) 0x43c468 ADD	X15, X9, X16

      (838) 0x43c46c LDUR	X9, [X29, #360]

      (838) 0x43c470 ADD	X16, X9, X14,LSL #3

      (838) 0x43c474 LDUR	X9, [X29, #368]

      (838) 0x43c478 ADD	X14, X9, X14,LSL #3

      (838) 0x43c47c B	43c48c

        (840) 0x43c480 SUBS	X15, X15, #1

        (840) 0x43c484 ADD	X14, X14, #8

        (840) 0x43c488 B.EQ	43c4d8

        (840) 0x43c48c LDR	X18, [X16], #8

        (840) 0x43c490 LDR	X2, [X22, X18,LSL #3]

        (840) 0x43c494 CMP	X2, X7

        (840) 0x43c498 B.LT	43c4b8

        (840) 0x43c49c LDR	D5, [X14]

        (840) 0x43c4a0 FMUL	D6, D3, D5

        (840) 0x43c4a4 FCMP	D6, #0

        (840) 0x43c4a8 B.PL	43c4b8

        (840) 0x43c4ac LDR	D6, [X13, X2,LSL #3]

        (840) 0x43c4b0 FMADD	D5, D4, D5, D6

        (840) 0x43c4b4 STR	D5, [X13, X2,LSL #3]

        (840) 0x43c4b8 CMP	X18, X27

        (840) 0x43c4bc B.NE	43c480

        (840) 0x43c4c0 LDR	D5, [X14]

        (840) 0x43c4c4 FMUL	D6, D3, D5

        (840) 0x43c4c8 FCMP	D6, #0

        (840) 0x43c4cc B.PL	43c480

        (840) 0x43c4d0 FMADD	D2, D4, D5, D2

        (840) 0x43c4d4 B	43c480

      (838) 0x43c4d8 CBZ	W19, 43c5d8

      (838) 0x43c4dc LDR	X15, [X26, X20,LSL #3]

      (838) 0x43c4e0 LDR	X14, [X26, X21,LSL #3]

      (838) 0x43c4e4 CMP	X14, X15

      (838) 0x43c4e8 B.LE	43c5d8

      (838) 0x43c4ec LDUR	X9, [X29, #352]

      (838) 0x43c4f0 LDR	X16, [X9]

      (838) 0x43c4f4 LDUR	X9, [X29, #416]

      (838) 0x43c4f8 LDR	X13, [X9]

      (838) 0x43c4fc SUB	W9, W14, W15

      (838) 0x43c500 TBNZ	W9, #0, 43c598

      (838) 0x43c504 ORR	X18, XZR, X15

      (838) 0x43c508 ADD	X9, X15, #1

      (838) 0x43c50c CMP	X14, X9

      (838) 0x43c510 B.EQ	43c5d8

      (838) 0x43c514 B	43c5e0

      (838) 0x43c518 LDUR	X14, [X29, #440]

      (838) 0x43c51c FADD	D2, D2, D5

      (838) 0x43c520 B	43c254

      (838) 0x43c524 LDR	X9, [SP, #200]

      (838) 0x43c528 SUB	X13, X13, X18

      (838) 0x43c52c ADD	X15, X9, X18,LSL #3

      (838) 0x43c530 ADD	X9, X2, X18,LSL #3

      (838) 0x43c534 ADD	X2, X9, #8

      (838) 0x43c538 B	43c54c

0x43c53c HINT	#0

        (841) 0x43c540 SUBS	X13, X13, #2

        (841) 0x43c544 ADD	X2, X2, #16

        (841) 0x43c548 B.EQ	43c440

        (841) 0x43c54c LDUR	X9, [X15, #504]

        (841) 0x43c550 LDR	X9, [X23, X9,LSL #3]

        (841) 0x43c554 CMP	X9, X3

        (841) 0x43c558 B.LT	43c570

        (841) 0x43c55c LDUR	D5, [X2, #504]

        (841) 0x43c560 FMUL	D6, D3, D5

        (841) 0x43c564 FCMP	D6, #0

        (841) 0x43c568 B.PL	43c570

        (841) 0x43c56c FADD	D4, D4, D5

        (841) 0x43c570 LDR	X9, [X15], #16

        (841) 0x43c574 LDR	X9, [X23, X9,LSL #3]

        (841) 0x43c578 CMP	X9, X3

        (841) 0x43c57c B.LT	43c540

        (841) 0x43c580 LDR	D5, [X2]

        (841) 0x43c584 FMUL	D6, D3, D5

        (841) 0x43c588 FCMP	D6, #0

        (841) 0x43c58c B.PL	43c540

        (841) 0x43c590 FADD	D4, D4, D5

        (841) 0x43c594 B	43c540

      (838) 0x43c598 LDR	X9, [SP, #208]

      (838) 0x43c59c LDR	X9, [X9, X15,LSL #3]

      (838) 0x43c5a0 LDR	X18, [X23, X9,LSL #3]

      (838) 0x43c5a4 CMP	X18, X3

      (838) 0x43c5a8 B.LT	43c5c8

      (838) 0x43c5ac LDR	D5, [X16, X15,LSL #3]

      (838) 0x43c5b0 FMUL	D6, D3, D5

      (838) 0x43c5b4 FCMP	D6, #0

      (838) 0x43c5b8 B.PL	43c5c8

      (838) 0x43c5bc LDR	D6, [X13, X18,LSL #3]

      (838) 0x43c5c0 FMADD	D5, D4, D5, D6

      (838) 0x43c5c4 STR	D5, [X13, X18,LSL #3]

      (838) 0x43c5c8 ADD	X18, X15, #1

      (838) 0x43c5cc ADD	X9, X15, #1

      (838) 0x43c5d0 CMP	X14, X9

      (838) 0x43c5d4 B.NE	43c5e0

      (838) 0x43c5d8 LDUR	X14, [X29, #440]

      (838) 0x43c5dc B	43c254

      (838) 0x43c5e0 LDR	X9, [SP, #200]

      (838) 0x43c5e4 SUB	X14, X14, X18

      (838) 0x43c5e8 ADD	X15, X9, X18,LSL #3

      (838) 0x43c5ec ADD	X9, X16, X18,LSL #3

      (838) 0x43c5f0 ADD	X16, X9, #8

      (838) 0x43c5f4 B	43c60c

0x43c5f8 HINT	#0

0x43c5fc HINT	#0

        (839) 0x43c600 SUBS	X14, X14, #2

        (839) 0x43c604 ADD	X16, X16, #16

        (839) 0x43c608 B.EQ	43c5d8

        (839) 0x43c60c LDUR	X9, [X15, #504]

        (839) 0x43c610 LDR	X18, [X23, X9,LSL #3]

        (839) 0x43c614 CMP	X18, X3

        (839) 0x43c618 B.LT	43c638

        (839) 0x43c61c LDUR	D5, [X16, #504]

        (839) 0x43c620 FMUL	D6, D3, D5

        (839) 0x43c624 FCMP	D6, #0

        (839) 0x43c628 B.PL	43c638

        (839) 0x43c62c LDR	D6, [X13, X18,LSL #3]

        (839) 0x43c630 FMADD	D5, D4, D5, D6

        (839) 0x43c634 STR	D5, [X13, X18,LSL #3]

        (839) 0x43c638 LDR	X9, [X15], #16

        (839) 0x43c63c LDR	X18, [X23, X9,LSL #3]

        (839) 0x43c640 CMP	X18, X3

        (839) 0x43c644 B.LT	43c600

        (839) 0x43c648 LDR	D5, [X16]

        (839) 0x43c64c FMUL	D6, D3, D5

        (839) 0x43c650 FCMP	D6, #0

        (839) 0x43c654 B.PL	43c600

        (839) 0x43c658 LDR	D6, [X13, X18,LSL #3]

        (839) 0x43c65c FMADD	D5, D4, D5, D6

        (839) 0x43c660 STR	D5, [X13, X18,LSL #3]

        (839) 0x43c664 B	43c600

    (834) 0x43c668 CBZ	W19, 43c8a0

    (834) 0x43c66c LDR	X9, [SP, #104]

    (834) 0x43c670 ADD	X13, X27, #1

    (834) 0x43c674 LDR	X8, [X9, X27,LSL #3]

    (834) 0x43c678 LDR	X9, [X9, X13,LSL #3]

    (834) 0x43c67c CMP	X8, X9

    (834) 0x43c680 B.GE	43c8a0

  (835) 0x43c684 LDUR	X13, [X29, #352]

  (835) 0x43c688 LDR	X26, [X28]

  (835) 0x43c68c LDR	X14, [X13]

  (835) 0x43c690 LDUR	X13, [X29, #416]

  (835) 0x43c694 LDR	X16, [X13]

  (835) 0x43c698 LDUR	X13, [X29, #320]

  (835) 0x43c69c LDR	X0, [X13]

  (835) 0x43c6a0 LDR	X13, [SP, #144]

  (835) 0x43c6a4 LDR	X13, [X13]

  (835) 0x43c6a8 STUR	X13, [X29, #376]

  (835) 0x43c6ac LDR	X13, [SP, #152]

  (835) 0x43c6b0 LDR	X15, [X13]

  (835) 0x43c6b4 LDR	X13, [SP, #88]

  (835) 0x43c6b8 LDR	X13, [X13]

  (835) 0x43c6bc STP	X13, X15, [SP, #208]

  (835) 0x43c6c0 LDP	X15, X13, [SP, #72]

  (835) 0x43c6c4 LDR	X20, [X15]

  (835) 0x43c6c8 LDR	X21, [X13]

  (835) 0x43c6cc B	43c6fc

0x43c6d0 HINT	#0

0x43c6d4 HINT	#0

0x43c6d8 HINT	#0

0x43c6dc HINT	#0

  (835) 0x43c6e0 LDR	D3, [X14, X8,LSL #3]

  (835) 0x43c6e4 LDR	D4, [X16, X15,LSL #3]

  (835) 0x43c6e8 FADD	D3, D3, D4

  (835) 0x43c6ec STR	D3, [X16, X15,LSL #3]

  (835) 0x43c6f0 ADD	X8, X8, #1

  (835) 0x43c6f4 CMP	X8, X9

  (835) 0x43c6f8 B.EQ	43c8a0

  (835) 0x43c6fc LDUR	X13, [X29, #448]

  (835) 0x43c700 LDR	X13, [X13, X8,LSL #3]

  (835) 0x43c704 LDR	X15, [X23, X13,LSL #3]

  (835) 0x43c708 CMP	X15, X3

  (835) 0x43c70c B.GE	43c6e0

  (835) 0x43c710 CMP	X15, X30

  (835) 0x43c714 B.NE	43c7a0

  (835) 0x43c718 LDR	D3, [X25]

  (835) 0x43c71c ADD	X13, X20, X13,LSL #3

  (835) 0x43c720 LDP	X19, X13, [X13]

  (835) 0x43c724 SUBS	X5, X13, X19

  (835) 0x43c728 B.LE	43c7d0

  (835) 0x43c72c LDUR	X17, [X29, #328]

  (835) 0x43c730 LDR	X15, [X24]

  (835) 0x43c734 ORR	X2, XZR, X19

  (835) 0x43c738 LDR	X18, [X17]

  (835) 0x43c73c B	43c754

    (837) 0x43c740 LDR	D4, [X18, X2,LSL #3]

    (837) 0x43c744 FADD	D3, D3, D4

    (837) 0x43c748 ADD	X2, X2, #1

    (837) 0x43c74c CMP	X13, X2

    (837) 0x43c750 B.EQ	43c7dc

    (837) 0x43c754 LDR	X17, [X21, X2,LSL #3]

    (837) 0x43c758 SUBS	X4, X17, X26

    (837) 0x43c75c CCMP	X17, X15, #0, #10

    (837) 0x43c760 B.LT	43c780

    (837) 0x43c764 ORN	X17, XZR, X17

    (837) 0x43c768 LDR	X17, [X23, X17,LSL #3]

    (837) 0x43c76c CMP	X17, X3

    (837) 0x43c770 B.GE	43c740

    (837) 0x43c774 B	43c748

0x43c778 HINT	#0

0x43c77c HINT	#0

    (837) 0x43c780 LDR	X17, [X22, X4,LSL #3]

    (837) 0x43c784 CMP	X4, X27

    (837) 0x43c788 CCMP	X17, X7, #0, #1

    (837) 0x43c78c B.LT	43c748

    (837) 0x43c790 B	43c740

0x43c794 HINT	#0

0x43c798 HINT	#0

0x43c79c HINT	#0

  (835) 0x43c7a0 LDR	X15, [X0, X13,LSL #3]

  (835) 0x43c7a4 CMN	X15, #3

  (835) 0x43c7a8 B.EQ	43c6f0

  (835) 0x43c7ac LDUR	X15, [X29, #376]

  (835) 0x43c7b0 CMP	X15, #1

  (835) 0x43c7b4 B.EQ	43c894

  (835) 0x43c7b8 LDP	X17, X15, [SP, #208]

  (835) 0x43c7bc LDR	X15, [X15, X27,LSL #3]

  (835) 0x43c7c0 LDR	X13, [X17, X13,LSL #3]

  (835) 0x43c7c4 CMP	X15, X13

  (835) 0x43c7c8 B.NE	43c6f0

  (835) 0x43c7cc B	43c894

  (835) 0x43c7d0 FCMP	D3, #0

  (835) 0x43c7d4 B.NE	43c6f0

  (835) 0x43c7d8 B	43c894

  (835) 0x43c7dc FCMP	D3, #0

  (835) 0x43c7e0 B.EQ	43c894

(836) 0x43c7e4 LDR	D4, [X14, X8,LSL #3]

(836) 0x43c7e8 LDUR	X13, [X29, #328]

(836) 0x43c7ec LDUR	X15, [X29, #432]

(836) 0x43c7f0 ADD	X2, X21, X19,LSL #3

(836) 0x43c7f4 FDIV	D3, D4, D3

(836) 0x43c7f8 LDR	X17, [X13]

(836) 0x43c7fc LDUR	X13, [X29, #416]

(836) 0x43c800 LDR	X15, [X15]

(836) 0x43c804 LDR	X13, [X13]

(836) 0x43c808 ADD	X19, X17, X19,LSL #3

(836) 0x43c80c B	43c82c

0x43c810 HINT	#0

0x43c814 HINT	#0

0x43c818 HINT	#0

0x43c81c HINT	#0

(836) 0x43c820 ADD	X19, X19, #8

(836) 0x43c824 SUBS	X5, X5, #1

(836) 0x43c828 B.EQ	43c6f0

(836) 0x43c82c LDR	X17, [X2], #8

(836) 0x43c830 LDR	X4, [X24]

(836) 0x43c834 SUBS	X18, X17, X26

(836) 0x43c838 CCMP	X17, X4, #0, #10

(836) 0x43c83c B.LT	43c864

(836) 0x43c840 ORN	X17, XZR, X17

(836) 0x43c844 LDR	X17, [X23, X17,LSL #3]

(836) 0x43c848 CMP	X17, X3

(836) 0x43c84c B.LT	43c820

(836) 0x43c850 LDR	D4, [X19]

(836) 0x43c854 LDR	D5, [X13, X17,LSL #3]

(836) 0x43c858 FMADD	D4, D3, D4, D5

(836) 0x43c85c STR	D4, [X13, X17,LSL #3]

(836) 0x43c860 B	43c820

(836) 0x43c864 LDR	X17, [X22, X18,LSL #3]

(836) 0x43c868 CMP	X17, X7

(836) 0x43c86c B.LT	43c880

(836) 0x43c870 LDR	D4, [X19]

(836) 0x43c874 LDR	D5, [X15, X17,LSL #3]

(836) 0x43c878 FMADD	D4, D3, D4, D5

(836) 0x43c87c STR	D4, [X15, X17,LSL #3]

(836) 0x43c880 CMP	X18, X27

(836) 0x43c884 B.NE	43c820

(836) 0x43c888 LDR	D4, [X19]

(836) 0x43c88c FMADD	D2, D3, D4, D2

(836) 0x43c890 B	43c820

  (835) 0x43c894 LDR	D3, [X14, X8,LSL #3]

  (835) 0x43c898 FADD	D2, D2, D3

  (835) 0x43c89c B	43c6f0

    (834) 0x43c8a0 FCMP	D2, #0

    (834) 0x43c8a4 B.EQ	43c9cc

    (834) 0x43c8a8 LDUR	X13, [X29, #384]

    (834) 0x43c8ac LDR	X18, [SP, #176]

    (834) 0x43c8b0 CNTW	X17, ALL

    (834) 0x43c8b4 SUBS	X8, X1, X7

    (834) 0x43c8b8 B.LE	43c934

    (834) 0x43c8bc FNEG	D3, D2

    (834) 0x43c8c0 CMP	X8, X17

    (834) 0x43c8c4 B.CC	43c918

    (834) 0x43c8c8 LDP	X16, X9, [SP, #48]

    (834) 0x43c8cc DUP	Z4.D, Z3.D[0]

    (834) 0x43c8d0 ADD	X15, X18, X7,LSL #3

    (834) 0x43c8d4 ORR	X14, XZR, XZR

    (834) 0x43c8d8 AND	X13, X8, X9

    (834) 0x43c8dc ADD	X16, X16, X7,LSL #3

    (834) 0x43c8e0 ADD	X9, X7, X13

      (852) 0x43c8e4 LD1D	{Z5.D}, P0/Z, [X15, X14,LSL #3]

      (852) 0x43c8e8 LD1D	{Z6.D}, P0/Z, [X16, X14,LSL #3]

      (852) 0x43c8ec FDIV	Z5.D, P0/M, Z5.D, Z4.D

      (852) 0x43c8f0 ST1D	{Z5.D}, P0, [X15, X14,LSL #3]

      (852) 0x43c8f4 FDIV	Z6.D, P0/M, Z6.D, Z4.D

      (852) 0x43c8f8 ST1D	{Z6.D}, P0, [X16, X14,LSL #3]

      (852) 0x43c8fc ADD	X14, X14, X17

      (852) 0x43c900 CMP	X13, X14

      (852) 0x43c904 B.NE	43c8e4

    (834) 0x43c908 CMP	X8, X13

    (834) 0x43c90c LDUR	X13, [X29, #384]

    (834) 0x43c910 ORR	X7, XZR, X9

    (834) 0x43c914 B.EQ	43c934

    (834) 0x43c918 ADD	X8, X18, X7,LSL #3

    (834) 0x43c91c SUB	X9, X1, X7

      (851) 0x43c920 LDR	D4, [X8]

      (851) 0x43c924 SUBS	X9, X9, #1

      (851) 0x43c928 FDIV	D4, D4, D3

      (851) 0x43c92c STR	D4, [X8], #8

      (851) 0x43c930 B.NE	43c920

    (834) 0x43c934 SUBS	X8, X6, X3

    (834) 0x43c938 B.LE	43c9bc

    (834) 0x43c93c FNEG	D2, D2

    (834) 0x43c940 CMP	X8, X17

    (834) 0x43c944 B.CC	43c99c

    (834) 0x43c948 LDP	X9, X15, [SP, #56]

    (834) 0x43c94c LDR	X16, [SP, #40]

    (834) 0x43c950 DUP	Z3.D, Z2.D[0]

    (834) 0x43c954 ORR	X14, XZR, XZR

    (834) 0x43c958 AND	X13, X8, X9

    (834) 0x43c95c ADD	X15, X15, X3,LSL #3

    (834) 0x43c960 ADD	X16, X16, X3,LSL #3

    (834) 0x43c964 ADD	X9, X3, X13

      (850) 0x43c968 LD1D	{Z4.D}, P0/Z, [X15, X14,LSL #3]

      (850) 0x43c96c LD1D	{Z5.D}, P0/Z, [X16, X14,LSL #3]

      (850) 0x43c970 FDIV	Z4.D, P0/M, Z4.D, Z3.D

      (850) 0x43c974 ST1D	{Z4.D}, P0, [X15, X14,LSL #3]

      (850) 0x43c978 FDIV	Z5.D, P0/M, Z5.D, Z3.D

      (850) 0x43c97c ST1D	{Z5.D}, P0, [X16, X14,LSL #3]

      (850) 0x43c980 ADD	X14, X14, X17

      (850) 0x43c984 CMP	X13, X14

      (850) 0x43c988 B.NE	43c968

    (834) 0x43c98c CMP	X8, X13

    (834) 0x43c990 LDUR	X13, [X29, #384]

    (834) 0x43c994 ORR	X3, XZR, X9

    (834) 0x43c998 B.EQ	43c9bc

    (834) 0x43c99c LDR	X8, [SP, #64]

    (834) 0x43c9a0 SUB	X9, X6, X3

    (834) 0x43c9a4 ADD	X8, X8, X3,LSL #3

      (849) 0x43c9a8 LDR	D3, [X8]

      (849) 0x43c9ac SUBS	X9, X9, #1

      (849) 0x43c9b0 FDIV	D3, D3, D2

      (849) 0x43c9b4 STR	D3, [X8], #8

      (849) 0x43c9b8 B.NE	43c9a8

    (834) 0x43c9bc LDUR	X9, [X29, #312]

    (834) 0x43c9c0 LDUR	X14, [X29, #392]

    (834) 0x43c9c4 LDR	X15, [SP, #192]

    (834) 0x43c9c8 B	43c9dc

    (834) 0x43c9cc LDP	X13, X14, [X29, #896]

    (834) 0x43c9d0 LDUR	X9, [X29, #312]

    (834) 0x43c9d4 LDR	X15, [SP, #192]

    (834) 0x43c9d8 LDR	X18, [SP, #176]

    (834) 0x43c9dc LDP	X17, X16, [SP, #160]

    (834) 0x43c9e0 B	43be10

0x43c9e4 ADD	SP, SP, #448

0x43c9e8 LDP	X20, X19, [SP, #80]

0x43c9ec LDP	X22, X21, [SP, #64]

0x43c9f0 LDP	X24, X23, [SP, #48]

0x43c9f4 LDP	X26, X25, [SP, #32]

0x43c9f8 LDP	X28, X27, [SP, #16]

0x43c9fc LDP	X29, X30, [SP], #96

0x43ca00 RET

0x43ca04 LDR	X14, [SP, #176]

0x43ca08 UBFM	X18, X2, #61, #60

0x43ca0c ADD	X16, X16, X21,LSL #3

0x43ca10 ADD	X4, X17, X21,LSL #3

0x43ca14 ADD	X18, X18, #8

0x43ca18 ADD	X2, X11, X18

0x43ca1c ADD	X3, X12, X18

0x43ca20 MUL	X14, X21, X14

0x43ca24 UBFM	X15, X14, #61, #60

0x43ca28 ADD	X14, X15, #8

0x43ca2c ADD	X1, X11, X14

0x43ca30 ADD	X14, X12, X14

0x43ca34 CMP	X1, X16

0x43ca38 CCMP	X9, X2, #2, #3

0x43ca3c CSINC	W0, WZR, WZR, #2

0x43ca40 CMP	X1, X4

0x43ca44 CCMP	X10, X2, #2, #3

0x43ca48 CSINC	W18, WZR, WZR, #2

0x43ca4c CMP	X14, X16

0x43ca50 CCMP	X9, X3, #2, #3

0x43ca54 CSINC	W17, WZR, WZR, #2

0x43ca58 CMP	X14, X4

0x43ca5c CCMP	X10, X3, #2, #3

0x43ca60 CSINC	W16, WZR, WZR, #2

0x43ca64 CMP	X14, X2

0x43ca68 LDUR	X2, [X29, #392]

0x43ca6c ORR	X14, XZR, X27

0x43ca70 CCMP	X1, X3, #2, #3

0x43ca74 B.CC	43b9bc

0x43ca78 ORR	X14, XZR, X27

0x43ca7c TBNZ	W0, #0, 43b9bc

0x43ca80 ORR	X14, XZR, X27

0x43ca84 TBNZ	W18, #0, 43b9bc

0x43ca88 ORR	X14, XZR, X27

0x43ca8c TBNZ	W17, #0, 43b9bc

0x43ca90 ORR	X14, XZR, X27

0x43ca94 TBNZ	W16, #0, 43b9bc

0x43ca98 PTRUE	P0.D, ALL

0x43ca9c SUB	X14, XZR, X13

0x43caa0 ADD	X0, X15, #8

0x43caa4 ORR	X16, XZR, XZR

0x43caa8 AND	X17, X8, X14

0x43caac RDVL	X18, #1

0x43cab0 ADD	X15, X11, X0

0x43cab4 LD1RD	{Z0.D}, P0/Z, [X10]

0x43cab8 LD1RD	{Z1.D}, P0/Z, [X9]

0x43cabc ADD	X1, X0, X18

0x43cac0 ADD	X14, X27, X17

0x43cac4 ADD	X0, X12, X0

0x43cac8 ADD	X18, X11, X1

0x43cacc ADD	X1, X12, X1

0x43cad0 HINT	#0

0x43cad4 HINT	#0

0x43cad8 HINT	#0

0x43cadc HINT	#0

(859) 0x43cae0 LD1D	{Z2.D}, P0/Z, [X15, X16,LSL #3]

(859) 0x43cae4 LD1D	{Z3.D}, P0/Z, [X18, X16,LSL #3]

(859) 0x43cae8 ADD	Z2.D, Z2.D, Z1.D

(859) 0x43caec ADD	Z3.D, Z3.D, Z1.D

(859) 0x43caf0 ST1D	{Z2.D}, P0, [X15, X16,LSL #3]

(859) 0x43caf4 ST1D	{Z3.D}, P0, [X18, X16,LSL #3]

(859) 0x43caf8 LD1D	{Z2.D}, P0/Z, [X0, X16,LSL #3]

(859) 0x43cafc LD1D	{Z3.D}, P0/Z, [X1, X16,LSL #3]

(859) 0x43cb00 ADD	Z2.D, Z2.D, Z0.D

(859) 0x43cb04 ADD	Z3.D, Z3.D, Z0.D

(859) 0x43cb08 ST1D	{Z2.D}, P0, [X0, X16,LSL #3]

(859) 0x43cb0c ST1D	{Z3.D}, P0, [X1, X16,LSL #3]

(859) 0x43cb10 ADD	X16, X16, X13

(859) 0x43cb14 CMP	X17, X16

(859) 0x43cb18 B.NE	43cae0

0x43cb1c CMP	X8, X17

0x43cb20 B.NE	43b9bc

0x43cb24 B	43ba08

0x43cb28 HINT	#0

0x43cb2c HINT	#0

Coverage (%)	Name	Module
►99.22+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_lr_interp.c:1196-1757
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1196,1219-1238,1244-1254,1262-1303,1311-1350,1363-1417,1423-1459,1467-1471,1480-1483,1491-1496,1503-1545,1553-1596,1607-1660,1667-1724,1733-1748,1754-1757.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 99.50 to 32.67 cycles (3.05x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 26% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 99.50 to 69.71 cycles (1.43x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_CAlloc: 6 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1223
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1229
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1430
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1431
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1436
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1437
hypre_Free: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1755
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1235
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1236
hypre_alt_insert_new_nodes: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1447
hypre_printf: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1415
time_getWallclockSeconds: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1414
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1423
unknown: 6 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1363
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1373
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1386
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1407
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1417
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1467

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function is loading 3 bytes.

Arithmetic intensity

Arithmetic intensity is 0.33 FP operations per loaded or stored byte.

General properties

nb instructions	591
nb uops	522
loop length	2364
used w registers	12
used x registers	32
used b registers	0
used h registers	0
used s registers	2
used d registers	2
used q registers	0
used v registers	0
used z registers	2
nb stack references	85

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	65.25 cycles
front end	65.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	30.50	30.50	45.75	45.75	45.75	45.75	1.25	1.25	1.25	1.25	99.50	99.17	99.33	44.50	44.50
cycles	30.50	30.50	45.75	45.75	45.75	45.75	1.25	1.25	1.25	1.25	99.50	99.17	99.33	44.50	44.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	65.25
Dispatch	99.50
DIV/SQRT	5.00-20.00
Overall L1	99.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	26%
load	28%
store	28%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	24%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	26%
load	28%
store	28%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	24%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 99.50 cycles. At this rate:

0% of peak load performance is reached (0.03 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 43b220

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB SP, SP, #448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR X7, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X6, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X5, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X3, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X26, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X19, X21, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X27, X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X24, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X9, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X11, X9, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X9, X10, [X29, #808]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X9, X11, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X8, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBZ X0, 43b3f8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X11, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 43b3a0 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X4, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X21, X19, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X26, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBZ X0, 43b40c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 43b40c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
B 43b40c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X21, X19, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X26, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBNZ X0, 43b3b8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4acc50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4acc30 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X9, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SDIV X10, X8, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MUL X27, X10, X19	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR X10, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X10, X10, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X19, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X14, X8, X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X14, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STUR X14, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X19, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GT 43b570 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x350>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4ec45c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #1456	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X21, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W25, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4ec480>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #1480	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X19, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X20, [X9, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X26, [X10, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X26, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X19, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W20, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X21, 43b94c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x72c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUBS X8, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 43b94c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x72c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X11, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X9, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X9, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X15, X10, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CCMP X11, X14, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC W12, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X10, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X11, X15, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC W13, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X10, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X9, X15, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.CC 43b908 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x6e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
TBNZ W12, #0, 43b908 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x6e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ W13, 43b908 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x6e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [X9], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X11], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X10], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
B 43b94c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x72c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X18, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X19, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X11, X9, [X29, #872]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X9, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X9, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STUR X16, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 43b600 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x3e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADD X11, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADRP X0, <4ec94c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #1504	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X2, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 43ba50 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x830>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUBS X8, X2, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 43ba50 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x830>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X12, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MOVZ W14, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP X13, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X14, X13, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X17, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ORR X14, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X16, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X9, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X10, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X17, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.CS 43ca04 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x17e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X13, X2, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X14, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X12, X12, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X11, X21, X11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X10, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X9, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 43ba38 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x818>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4eca50>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #1528	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X21, 43ba74 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x854>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 43bc40 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xa20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 43bad8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x8b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4acce0 <time_getWallclockSeconds>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4b0a94>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3787	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR D1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FSUB D0, D0, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4ab120 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4102b0 <@plt_start@+0x290>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W20, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 43bad8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x8b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4acce0 <time_getWallclockSeconds>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D0, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X13, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 43bb4c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x92c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X0, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W21, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR W20, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X13, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X0, 43bb80 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x960>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 43bc40 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xa20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 43bbcc <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x9ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X3, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X2, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 47c4c0 <hypre_alt_insert_new_nodes>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 43bc74 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xa54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 43bc74 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xa54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR X8, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 43bc9c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xa7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <4ecc9c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #1552	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X14, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDUR X9, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X14, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 43bcfc <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xadc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 43bccc <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xaac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ab000 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 43c9e4 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x17c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD SP, SP, #448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
B 4ab000 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTW X1, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FMOV D0, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVN X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X1, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X15, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X11, X8, [X29, #872]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X8, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X1, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
RDVL X8, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
STUR X16, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X16, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STUR X17, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X16, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X16, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STUR X16, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X16, X18, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X8, X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X0, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X8, X16, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X15, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X16, X18, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X17, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 43be20 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xc00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADD SP, SP, #448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X18, X2, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X16, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X17, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X2, X11, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X12, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MUL X14, X21, X14	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
UBFM X15, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X12, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X1, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X9, X2, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC W0, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP X1, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X10, X2, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC W18, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP X14, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X9, X3, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC W17, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X14, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X10, X3, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC W16, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP X14, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDUR X2, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X14, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CCMP X1, X3, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.CC 43b9bc <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x79c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X14, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
TBNZ W0, #0, 43b9bc <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x79c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X14, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
TBNZ W18, #0, 43b9bc <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x79c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X14, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
TBNZ W17, #0, 43b9bc <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x79c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X14, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
TBNZ W16, #0, 43b9bc <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x79c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
SUB X14, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X16, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X17, X8, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RDVL X18, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X15, X11, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LD1RD {Z0.D}, P0/Z, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LD1RD {Z1.D}, P0/Z, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
ADD X1, X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X27, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X12, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X18, X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
CMP X8, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 43b9bc <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x79c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 43ba08 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x7e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_lr_interp.c:1196-1757
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_CAlloc: 6 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1223
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1229
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1430
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1431
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1436
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1437
hypre_Free: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1755
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1235
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1236
hypre_alt_insert_new_nodes: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1447
hypre_printf: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1415
time_getWallclockSeconds: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1414
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1423
unknown: 6 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1363
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1373
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1386
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1407
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1417
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1467

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function is loading 3 bytes.

Arithmetic intensity

Arithmetic intensity is 0.33 FP operations per loaded or stored byte.

General properties

nb instructions	591
nb uops	522
loop length	2364
used w registers	12
used x registers	32
used b registers	0
used h registers	0
used s registers	2
used d registers	2
used q registers	0
used v registers	0
used z registers	2
nb stack references	85

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	65.25 cycles
front end	65.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	30.50	30.50	45.75	45.75	45.75	45.75	1.25	1.25	1.25	1.25	99.50	99.17	99.33	44.50	44.50
cycles	30.50	30.50	45.75	45.75	45.75	45.75	1.25	1.25	1.25	1.25	99.50	99.17	99.33	44.50	44.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	65.25
Dispatch	99.50
DIV/SQRT	5.00-20.00
Overall L1	99.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	26%
load	28%
store	28%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	24%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	26%
load	28%
store	28%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	24%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 99.50 cycles. At this rate:

0% of peak load performance is reached (0.03 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 43b220

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB SP, SP, #448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR X7, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X6, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X5, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X3, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X26, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X19, X21, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X27, X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X24, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X9, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X11, X9, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X9, X10, [X29, #808]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X9, X11, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X8, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBZ X0, 43b3f8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X11, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 43b3a0 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X4, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X21, X19, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X26, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBZ X0, 43b40c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 43b40c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
B 43b40c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X21, X19, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X26, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBNZ X0, 43b3b8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4acc50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4acc30 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X9, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SDIV X10, X8, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MUL X27, X10, X19	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR X10, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X10, X10, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X19, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X14, X8, X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X14, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STUR X14, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X19, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GT 43b570 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x350>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4ec45c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #1456	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X21, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W25, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4ec480>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #1480	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X19, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X20, [X9, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X26, [X10, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X26, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X19, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W20, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X21, 43b94c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x72c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUBS X8, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 43b94c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x72c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X11, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X9, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X9, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X15, X10, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CCMP X11, X14, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC W12, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X10, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X11, X15, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC W13, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X10, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X9, X15, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.CC 43b908 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x6e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
TBNZ W12, #0, 43b908 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x6e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ W13, 43b908 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x6e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [X9], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X11], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X10], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
B 43b94c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x72c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X18, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X19, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X11, X9, [X29, #872]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X9, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X9, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STUR X16, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 43b600 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x3e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADD X11, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADRP X0, <4ec94c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #1504	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X2, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 43ba50 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x830>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUBS X8, X2, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 43ba50 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x830>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X12, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MOVZ W14, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP X13, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X14, X13, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X17, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ORR X14, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X16, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X9, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X10, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X17, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.CS 43ca04 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x17e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X13, X2, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X14, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X12, X12, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X11, X21, X11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X10, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X9, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 43ba38 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x818>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4eca50>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #1528	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X21, 43ba74 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x854>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 43bc40 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xa20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 43bad8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x8b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4acce0 <time_getWallclockSeconds>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4b0a94>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3787	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR D1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FSUB D0, D0, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4ab120 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4102b0 <@plt_start@+0x290>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W20, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 43bad8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x8b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4acce0 <time_getWallclockSeconds>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D0, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X13, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 43bb4c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x92c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X0, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W21, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR W20, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X13, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X0, 43bb80 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x960>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 43bc40 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xa20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 43bbcc <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x9ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X3, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X2, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 47c4c0 <hypre_alt_insert_new_nodes>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 43bc74 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xa54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 43bc74 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xa54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR X8, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 43bc9c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xa7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <4ecc9c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #1552	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X14, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDUR X9, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X14, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 43bcfc <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xadc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 43bccc <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xaac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ab000 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 43c9e4 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x17c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD SP, SP, #448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
B 4ab000 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTW X1, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FMOV D0, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVN X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X1, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X15, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X11, X8, [X29, #872]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X8, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X1, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
RDVL X8, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
STUR X16, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X16, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STUR X17, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X16, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X16, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STUR X16, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X16, X18, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X8, X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X0, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X8, X16, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X15, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X16, X18, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X17, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 43be20 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0xc00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADD SP, SP, #448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X18, X2, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X16, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X17, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X2, X11, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X12, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MUL X14, X21, X14	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
UBFM X15, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X12, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X1, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X9, X2, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC W0, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP X1, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X10, X2, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC W18, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP X14, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X9, X3, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC W17, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X14, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X10, X3, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC W16, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP X14, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDUR X2, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X14, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CCMP X1, X3, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.CC 43b9bc <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x79c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X14, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
TBNZ W0, #0, 43b9bc <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x79c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X14, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
TBNZ W18, #0, 43b9bc <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x79c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X14, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
TBNZ W17, #0, 43b9bc <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x79c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X14, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
TBNZ W16, #0, 43b9bc <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x79c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
SUB X14, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X16, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X17, X8, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RDVL X18, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X15, X11, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LD1RD {Z0.D}, P0/Z, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LD1RD {Z1.D}, P0/Z, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
ADD X1, X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X27, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X12, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X18, X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
CMP X8, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 43b9bc <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x79c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 43ba08 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x7e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildExtPIInterp.omp_outlined–	0.20	0.10
○Loop 854 - par_lr_interp.c:1455-1456 - exec	0.01	0.01
○Loop 872 - par_lr_interp.c:1224-1225 - exec	0.00	0.00
○Loop 858 - par_lr_interp.c:1400-1403 - exec	0.00	0.01
○Loop 859 - par_lr_interp.c:1393-1396 - exec	0.00	0.00
▼Loop 865 - par_lr_interp.c:1244-1350 - exec–	0.00	0.00
▼Loop 866 - par_lr_interp.c:1244-1350 - exec–	0.00	0.00
▼Loop 864 - par_lr_interp.c:1244-1341 - exec–	0.00	0.00
▼Loop 863 - par_lr_interp.c:1244-1341 - exec–	0.00	0.00
▼Loop 867 - par_lr_interp.c:1264-1303 - exec–	0.00	0.01
○Loop 870 - par_lr_interp.c:1277-1285 - exec	0.02	0.01
○Loop 868 - par_lr_interp.c:1291-1303 - exec	0.00	0.00
○Loop 869 - par_lr_interp.c:1291-1303 - exec	0.00	0.00
○Loop 862 - par_lr_interp.c:1244-1262 - exec	0.00	0.00
○Loop 855 - par_lr_interp.c:1451-1452 - exec	0.00	0.00
○Loop 857 - par_lr_interp.c:1393-1396 - exec	0.00	0.00
▼Loop 836 - par_lr_interp.c:1469-1748 - exec–	0.00	0.00
▼Loop 835 - par_lr_interp.c:1469-1748 - exec–	0.00	0.00
▼Loop 834 - par_lr_interp.c:1469-1748 - exec–	0.00	0.01
▼Loop 838 - par_lr_interp.c:1609-1675 - exec–	0.04	0.02
○Loop 842 - par_lr_interp.c:1624-1628 - exec	0.05	0.02
○Loop 840 - par_lr_interp.c:1644-1651 - exec	0.03	0.01
○Loop 839 - par_lr_interp.c:1655-1660 - exec	0.00	0.00
○Loop 841 - par_lr_interp.c:1632-1637 - exec	0.00	0.00
▼Loop 845 - par_lr_interp.c:1494-1545 - exec–	0.00	0.01
○Loop 848 - par_lr_interp.c:1516-1526 - exec	0.03	0.01
○Loop 846 - par_lr_interp.c:1532-1545 - exec	0.00	0.00
○Loop 847 - par_lr_interp.c:1532-1545 - exec	0.00	0.00
○Loop 852 - par_lr_interp.c:1742-1743 - exec	0.00	0.00
○Loop 851 - par_lr_interp.c:1742-1743 - exec	0.00	0.00
○Loop 850 - par_lr_interp.c:1744-1745 - exec	0.00	0.00
○Loop 849 - par_lr_interp.c:1744-1745 - exec	0.00	0.00
○Loop 833 - par_lr_interp.c:1469-1748 - exec	0.00	0.00
▼Loop 843 - par_lr_interp.c:1555-1596 - exec–	0.00	0.00
○Loop 844 - par_lr_interp.c:1573-1596 - exec	0.00	0.00
○Loop 837 - par_lr_interp.c:1688-1700 - exec	0.00	0.00
○Loop 853 - par_lr_interp.c:1458-1459 - exec	0.00	0.00
○Loop 861 - par_lr_interp.c:1378-1382 - exec	0.00	0.00
○Loop 856 - par_lr_interp.c:1444-1445 - exec	0.00	0.00
○Loop 871 - par_lr_interp.c:1230-1231 - exec	0.00	0.00
○Loop 860 - par_lr_interp.c:1378-1382 - exec	0.00	0.00

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Matching between your function (in the source code) and the binary function

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Cycles summary

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Vector efficiency ratios

Cycles and memory resources usage

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ASM code

Code clean check

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Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code