OV - exec - Function hypre_BoomerAMGCreateS.omp

	Function: hypre_BoomerAMGCreateS.omp_outlined.1	Module: exec	Source: par_strength.c:246-513 [...]	Coverage (incl. loops): 0.26% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 246 - 513

--------------------------------------------------------------------------------

246: #pragma omp parallel private(i,diag,row_scale,row_sum,jA,jS)

247: #endif

248:    {

249:    HYPRE_Int start, stop;

250:    hypre_GetSimpleThreadPartition(&start, &stop, num_variables);

251:    HYPRE_Int jS_diag = 0, jS_offd = 0;

252:

253:    for (i = start; i < stop; i++)

254:    {

255:       S_diag_i[i] = jS_diag;

256:       if (num_cols_offd)

257:       {

258:          S_offd_i[i] = jS_offd;

259:       }

260:

261:       diag = A_diag_data[A_diag_i[i]];

262:

263:       /* compute scaling factor and row sum */

264:       row_scale = 0.0;

265:       row_sum = diag;

266:       if (num_functions > 1)

267:       {

268:          if (diag < 0)

269:          {

270:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

271:             {

272:                if (dof_func[i] == dof_func[A_diag_j[jA]])

273:                {

274:                   row_scale = hypre_max(row_scale, A_diag_data[jA]);

275:                   row_sum += A_diag_data[jA];

276:                }

277:             }

278:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

279:             {

280:                if (dof_func[i] == dof_func_offd[A_offd_j[jA]])

281:                {

282:                   row_scale = hypre_max(row_scale, A_offd_data[jA]);

283:                   row_sum += A_offd_data[jA];

[...]

289:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

290:             {

291:                if (dof_func[i] == dof_func[A_diag_j[jA]])

292:                {

293:                   row_scale = hypre_min(row_scale, A_diag_data[jA]);

294:                   row_sum += A_diag_data[jA];

295:                }

296:             }

297:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

298:             {

299:                if (dof_func[i] == dof_func_offd[A_offd_j[jA]])

300:                {

301:                   row_scale = hypre_min(row_scale, A_offd_data[jA]);

302:                   row_sum += A_offd_data[jA];

[...]

309:          if (diag < 0)

310:          {

311:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

312:             {

313:                row_scale = hypre_max(row_scale, A_diag_data[jA]);

314:                row_sum += A_diag_data[jA];

315:             }

316:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

317:             {

318:                row_scale = hypre_max(row_scale, A_offd_data[jA]);

319:                row_sum += A_offd_data[jA];

320:             }

321:          }

322:          else

323:          {

324:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

325:             {

326:                row_scale = hypre_min(row_scale, A_diag_data[jA]);

327:                row_sum += A_diag_data[jA];

328:             }

329:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

330:             {

331:                row_scale = hypre_min(row_scale, A_offd_data[jA]);

332:                row_sum += A_offd_data[jA];

333:             }

334:          } /* diag >= 0*/

335:       } /* num_functions <= 1 */

336:

337:       jS_diag += A_diag_i[i + 1] - A_diag_i[i] - 1;

338:       jS_offd += A_offd_i[i + 1] - A_offd_i[i];

339:

340:       /* compute row entries of S */

341:       S_temp_diag_j[A_diag_i[i]] = -1;

342:       if ((fabs(row_sum) > fabs(diag)*max_row_sum) && (max_row_sum < 1.0))

343:       {

344:          /* make all dependencies weak */

345:          for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

346:          {

347:             S_temp_diag_j[jA] = -1;

348:          }

349:          jS_diag -= A_diag_i[i + 1] - (A_diag_i[i] + 1);

350:

351:          for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

352:          {

353:             S_temp_offd_j[jA] = -1;

354:          }

355:          jS_offd -= A_offd_i[i + 1] - A_offd_i[i];

356:       }

357:       else

358:       {

359:          if (num_functions > 1)

360:          {

361:             if (diag < 0)

362:             {

363:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

364:                {

365:                   if (A_diag_data[jA] <= strength_threshold * row_scale

366:                       || dof_func[i] != dof_func[A_diag_j[jA]])

367:                   {

368:                      S_temp_diag_j[jA] = -1;

369:                      --jS_diag;

370:                   }

371:                   else

372:                   {

373:                      S_temp_diag_j[jA] = A_diag_j[jA];

374:                   }

375:                }

376:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

377:                {

378:                   if (A_offd_data[jA] <= strength_threshold * row_scale

379:                       || dof_func[i] != dof_func_offd[A_offd_j[jA]])

380:                   {

381:                      S_temp_offd_j[jA] = -1;

382:                      --jS_offd;

383:                   }

384:                   else

385:                   {

386:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

392:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

393:                {

394:                   if (A_diag_data[jA] >= strength_threshold * row_scale

395:                       || dof_func[i] != dof_func[A_diag_j[jA]])

396:                   {

397:                      S_temp_diag_j[jA] = -1;

398:                      --jS_diag;

399:                   }

400:                   else

401:                   {

402:                      S_temp_diag_j[jA] = A_diag_j[jA];

403:                   }

404:                }

405:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

406:                {

407:                   if (A_offd_data[jA] >= strength_threshold * row_scale

408:                       || dof_func[i] != dof_func_offd[A_offd_j[jA]])

409:                   {

410:                      S_temp_offd_j[jA] = -1;

411:                      --jS_offd;

412:                   }

413:                   else

414:                   {

415:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

422:             if (diag < 0)

423:             {

424:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

425:                {

426:                   if (A_diag_data[jA] <= strength_threshold * row_scale)

427:                   {

428:                      S_temp_diag_j[jA] = -1;

429:                      --jS_diag;

430:                   }

431:                   else

432:                   {

433:                      S_temp_diag_j[jA] = A_diag_j[jA];

434:                   }

435:                }

436:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

437:                {

438:                   if (A_offd_data[jA] <= strength_threshold * row_scale)

439:                   {

440:                      S_temp_offd_j[jA] = -1;

441:                      --jS_offd;

442:                   }

443:                   else

444:                   {

445:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

451:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

452:                {

453:                   if (A_diag_data[jA] >= strength_threshold * row_scale)

454:                   {

455:                      S_temp_diag_j[jA] = -1;

456:                      --jS_diag;

457:                   }

458:                   else

459:                   {

460:                      S_temp_diag_j[jA] = A_diag_j[jA];

461:                   }

462:                }

463:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

464:                {

465:                   if (A_offd_data[jA] >= strength_threshold * row_scale)

466:                   {

467:                      S_temp_offd_j[jA] = -1;

468:                      --jS_offd;

469:                   }

470:                   else

471:                   {

472:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

480:    hypre_prefix_sum_pair(&jS_diag, S_diag_i + num_variables, &jS_offd, S_offd_i + num_variables, prefix_sum_workspace);

[...]

492:    for (i = start; i < stop; i++)

493:    {

494:       S_diag_i[i] += jS_diag;

495:       S_offd_i[i] += jS_offd;

496:

497:       jS = S_diag_i[i];

498:       for (jA = A_diag_i[i]; jA < A_diag_i[i+1]; jA++)

499:       {

500:          if (S_temp_diag_j[jA] > -1)

501:          {

502:             S_diag_j[jS]    = S_temp_diag_j[jA];

503:             jS++;

504:          }

505:       }

506:

507:       jS = S_offd_i[i];

508:       for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

509:       {

510:          if (S_temp_offd_j[jA] > -1)

511:          {

512:             S_offd_j[jS]    = S_temp_offd_j[jA];

513:             jS++;

0x465900 SUB	SP, SP, #240

0x465904 STP	X29, X30, [SP, #144]

0x465908 STP	X28, X27, [SP, #160]

0x46590c STP	X26, X25, [SP, #176]

0x465910 STP	X24, X23, [SP, #192]

0x465914 STP	X22, X21, [SP, #208]

0x465918 STP	X20, X19, [SP, #224]

0x46591c ADD	X29, SP, #144

0x465920 LDR	X8, [X29, #184]

0x465924 STR	X2, [SP, #8]

0x465928 LDR	X2, [X2]

0x46592c SUB	X0, X29, #16

0x465930 SUB	X1, X29, #24

0x465934 ORR	X24, XZR, X6

0x465938 ORR	X22, XZR, X4

0x46593c LDR	X25, [X29, #168]

0x465940 STR	X7, [SP, #40]

0x465944 STUR	X5, [X29, #456]

0x465948 ORR	X19, XZR, X3

0x46594c STR	X8, [SP, #16]

0x465950 LDR	X8, [X29, #152]

0x465954 STR	X8, [SP, #24]

0x465958 LDR	X8, [X29, #120]

0x46595c STR	X8, [SP, #32]

0x465960 BL	4acc70

0x465964 LDP	X9, X12, [X29, #1000]

0x465968 LDR	X8, [X19]

0x46596c CMP	X12, X9

0x465970 STP	XZR, XZR, [X29, #984]

0x465974 STR	X19, [SP]

0x465978 B.GE	4664f4

0x46597c LDUR	X11, [X29, #456]

0x465980 LDR	X14, [X29, #176]

0x465984 LDR	X5, [X29, #160]

0x465988 MOVI	D2, #0

0x46598c FMOV	D3, #1.0000000

0x465990 MOVN	X26, #0

0x465994 ORR	X9, XZR, XZR

0x465998 ORR	X10, XZR, XZR

0x46599c LDP	X16, X15, [X29, #104]

0x4659a0 LDP	X13, X3, [X29, #136]

0x4659a4 LDR	X6, [X29, #128]

0x4659a8 LDR	X17, [X29, #96]

0x4659ac LDR	X0, [X24]

0x4659b0 LDR	X30, [X25]

0x4659b4 LDR	X18, [X11]

0x4659b8 LDR	X11, [SP, #40]

0x4659bc LDR	X7, [X15]

0x4659c0 LDR	D0, [X5]

0x4659c4 LDR	D1, [X14]

0x4659c8 LDR	X19, [X13]

0x4659cc STUR	X3, [X29, #464]

0x4659d0 LDR	X3, [X3]

0x4659d4 LDR	X4, [X16]

0x4659d8 STUR	X6, [X29, #448]

0x4659dc LDR	X6, [X6]

0x4659e0 LDR	X1, [X11]

0x4659e4 LDR	X11, [SP, #32]

0x4659e8 LDR	X2, [X11]

0x4659ec LDR	X11, [SP, #24]

0x4659f0 STP	X19, X7, [SP, #64]

0x4659f4 LDR	X24, [X11]

0x4659f8 ADD	X11, X7, #8

0x4659fc STR	X11, [SP, #56]

0x465a00 ADD	X11, X19, #8

0x465a04 STR	X11, [SP, #48]

0x465a08 B	465a24

    (2008) 0x465a0c SUB	X11, X14, X5

    (2008) 0x465a10 ADD	X9, X11, X9

    (2008) 0x465a14 STUR	X9, [X29, #472]

    (2008) 0x465a18 LDUR	X11, [X29, #488]

    (2008) 0x465a1c CMP	X12, X11

    (2008) 0x465a20 B.GE	4664f4

    (2008) 0x465a24 STR	X10, [X8, X12,LSL #3]

    (2008) 0x465a28 ORR	X27, XZR, X12

    (2008) 0x465a2c LDR	X12, [X22]

    (2008) 0x465a30 CBZ	X12, 465a38

    (2008) 0x465a34 STR	X9, [X18, X27,LSL #3]

    (2008) 0x465a38 LDR	X19, [X1, X27,LSL #3]

    (2008) 0x465a3c LDR	X14, [X17]

    (2008) 0x465a40 ADD	X12, X27, #1

    (2008) 0x465a44 MOVI	D4, #0

    (2008) 0x465a48 LDR	X28, [X1, X12,LSL #3]

    (2008) 0x465a4c LDR	D5, [X0, X19,LSL #3]

    (2008) 0x465a50 ADD	X20, X19, #1

    (2008) 0x465a54 CMP	X14, #2

    (2008) 0x465a58 B.LT	465ac0

    (2008) 0x465a5c FCMP	D5, #0

    (2008) 0x465a60 B.PL	465c00

    (2008) 0x465a64 FMOV	D6, D5

    (2008) 0x465a68 CMP	X20, X28

    (2008) 0x465a6c B.GE	465da4

    (2008) 0x465a70 LDR	X21, [X4, X27,LSL #3]

    (2008) 0x465a74 SUB	W14, W19, W28

    (2008) 0x465a78 TBNZ	W14, #0, 465d94

    (2008) 0x465a7c LDR	X11, [SP, #72]

    (2008) 0x465a80 FMOV	D6, D5

    (2008) 0x465a84 LDR	X14, [X11, X20,LSL #3]

    (2008) 0x465a88 LDR	X14, [X4, X14,LSL #3]

    (2008) 0x465a8c CMP	X21, X14

    (2008) 0x465a90 B.NE	465aa0

    (2008) 0x465a94 LDR	D6, [X0, X20,LSL #3]

    (2008) 0x465a98 FMAXNM	D4, D6, D2

    (2008) 0x465a9c FADD	D6, D5, D6

    (2008) 0x465aa0 ADD	X20, X19, #2

    (2008) 0x465aa4 SUB	X14, X28, #2

    (2008) 0x465aa8 CMP	X14, X19

    (2008) 0x465aac B.EQ	465da4

    (2008) 0x465ab0 B	465e24

0x465ab4 HINT	#0

0x465ab8 HINT	#0

0x465abc HINT	#0

    (2008) 0x465ac0 FCMP	D5, #0

    (2008) 0x465ac4 B.PL	465c60

    (2008) 0x465ac8 FMOV	D6, D5

    (2008) 0x465acc CMP	X20, X28

    (2008) 0x465ad0 B.GE	465b60

    (2008) 0x465ad4 SUB	W11, W19, W28

    (2008) 0x465ad8 FMOV	D6, D5

    (2008) 0x465adc ORN	W11, WZR, W11

    (2008) 0x465ae0 ANDS	X14, X11, #0x3

    (2008) 0x465ae4 B.EQ	465b04

      (2016) 0x465ae8 LDR	D7, [X0, X20,LSL #3]

      (2016) 0x465aec ADD	X20, X20, #1

      (2016) 0x465af0 FCMP	D4, D7

      (2016) 0x465af4 FADD	D6, D6, D7

      (2016) 0x465af8 FCSEL	D4, D7, D4, #4

      (2016) 0x465afc SUBS	X14, X14, #1

      (2016) 0x465b00 B.NE	465ae8

    (2008) 0x465b04 SUB	X11, X28, X19

    (2008) 0x465b08 SUB	X11, X11, #2

    (2008) 0x465b0c CMP	X11, #3

    (2008) 0x465b10 B.CC	465b60

    (2008) 0x465b14 ADD	X11, X0, #16

    (2008) 0x465b18 SUB	X14, X28, X20

    (2008) 0x465b1c ADD	X5, X11, X20,LSL #3

      (2015) 0x465b20 LDP	D7, D16, [X5, #1008]

      (2015) 0x465b24 FCMP	D4, D7

      (2015) 0x465b28 FADD	D6, D6, D7

      (2015) 0x465b2c FCSEL	D4, D7, D4, #4

      (2015) 0x465b30 FADD	D6, D6, D16

      (2015) 0x465b34 FCMP	D4, D16

      (2015) 0x465b38 FCSEL	D4, D16, D4, #4

      (2015) 0x465b3c LDP	D7, D16, [X5], #32

      (2015) 0x465b40 FCMP	D4, D7

      (2015) 0x465b44 FADD	D6, D6, D7

      (2015) 0x465b48 FCSEL	D4, D7, D4, #4

      (2015) 0x465b4c FADD	D6, D6, D16

      (2015) 0x465b50 FCMP	D4, D16

      (2015) 0x465b54 FCSEL	D4, D16, D4, #4

      (2015) 0x465b58 SUBS	X14, X14, #4

      (2015) 0x465b5c B.NE	465b20

    (2008) 0x465b60 LDR	X21, [X2, X27,LSL #3]

    (2008) 0x465b64 LDR	X20, [X2, X12,LSL #3]

    (2008) 0x465b68 SUBS	X14, X21, X20

    (2008) 0x465b6c B.GE	466028

    (2008) 0x465b70 SUB	W11, W20, W21

    (2008) 0x465b74 ORR	X23, XZR, X21

    (2008) 0x465b78 ANDS	X5, X11, #0x3

    (2008) 0x465b7c B.EQ	465b9c

      (2014) 0x465b80 LDR	D7, [X3, X23,LSL #3]

      (2014) 0x465b84 ADD	X23, X23, #1

      (2014) 0x465b88 FCMP	D4, D7

      (2014) 0x465b8c FADD	D6, D6, D7

      (2014) 0x465b90 FCSEL	D4, D7, D4, #4

      (2014) 0x465b94 SUBS	X5, X5, #1

      (2014) 0x465b98 B.NE	465b80

    (2008) 0x465b9c CMN	X14, #4

    (2008) 0x465ba0 B.HI	466028

    (2008) 0x465ba4 ADD	X11, X3, #16

    (2008) 0x465ba8 ADD	X14, X11, X23,LSL #3

      (2013) 0x465bac LDP	D7, D16, [X14, #1008]

      (2013) 0x465bb0 ADD	X23, X23, #4

      (2013) 0x465bb4 FCMP	D4, D7

      (2013) 0x465bb8 FADD	D6, D6, D7

      (2013) 0x465bbc FCSEL	D4, D7, D4, #4

      (2013) 0x465bc0 FADD	D6, D6, D16

      (2013) 0x465bc4 FCMP	D4, D16

      (2013) 0x465bc8 FCSEL	D4, D16, D4, #4

      (2013) 0x465bcc LDP	D7, D16, [X14], #32

      (2013) 0x465bd0 FCMP	D4, D7

      (2013) 0x465bd4 FADD	D6, D6, D7

      (2013) 0x465bd8 FCSEL	D4, D7, D4, #4

      (2013) 0x465bdc FADD	D6, D6, D16

      (2013) 0x465be0 FCMP	D4, D16

      (2013) 0x465be4 FCSEL	D4, D16, D4, #4

      (2013) 0x465be8 CMP	X20, X23

      (2013) 0x465bec B.NE	465bac

    (2008) 0x465bf0 B	466028

0x465bf4 HINT	#0

0x465bf8 HINT	#0

0x465bfc HINT	#0

    (2008) 0x465c00 FMOV	D6, D5

    (2008) 0x465c04 CMP	X20, X28

    (2008) 0x465c08 B.GE	465dec

    (2008) 0x465c0c LDR	X21, [X4, X27,LSL #3]

    (2008) 0x465c10 SUB	W14, W19, W28

    (2008) 0x465c14 TBNZ	W14, #0, 465ddc

    (2008) 0x465c18 LDR	X11, [SP, #72]

    (2008) 0x465c1c FMOV	D6, D5

    (2008) 0x465c20 LDR	X14, [X11, X20,LSL #3]

    (2008) 0x465c24 LDR	X14, [X4, X14,LSL #3]

    (2008) 0x465c28 CMP	X21, X14

    (2008) 0x465c2c B.NE	465c40

    (2008) 0x465c30 LDR	D6, [X0, X20,LSL #3]

    (2008) 0x465c34 FCMP	D6, #0

    (2008) 0x465c38 FCSEL	D4, D2, D6, #12

    (2008) 0x465c3c FADD	D6, D5, D6

    (2008) 0x465c40 ADD	X20, X19, #2

    (2008) 0x465c44 SUB	X14, X28, #2

    (2008) 0x465c48 CMP	X14, X19

    (2008) 0x465c4c B.EQ	465dec

    (2008) 0x465c50 B	465f74

0x465c54 HINT	#0

0x465c58 HINT	#0

0x465c5c HINT	#0

    (2008) 0x465c60 FMOV	D6, D5

    (2008) 0x465c64 CMP	X20, X28

    (2008) 0x465c68 B.GE	465d00

    (2008) 0x465c6c SUB	W11, W19, W28

    (2008) 0x465c70 FMOV	D6, D5

    (2008) 0x465c74 ORN	W11, WZR, W11

    (2008) 0x465c78 ANDS	X14, X11, #0x3

    (2008) 0x465c7c B.EQ	465c9c

      (2012) 0x465c80 LDR	D7, [X0, X20,LSL #3]

      (2012) 0x465c84 ADD	X20, X20, #1

      (2012) 0x465c88 FCMP	D4, D7

      (2012) 0x465c8c FADD	D6, D6, D7

      (2012) 0x465c90 FCSEL	D4, D4, D7, #4

      (2012) 0x465c94 SUBS	X14, X14, #1

      (2012) 0x465c98 B.NE	465c80

    (2008) 0x465c9c SUB	X11, X28, X19

    (2008) 0x465ca0 SUB	X11, X11, #2

    (2008) 0x465ca4 CMP	X11, #3

    (2008) 0x465ca8 B.CC	465d00

    (2008) 0x465cac ADD	X11, X0, #16

    (2008) 0x465cb0 SUB	X14, X28, X20

    (2008) 0x465cb4 ADD	X5, X11, X20,LSL #3

    (2008) 0x465cb8 HINT	#0

    (2008) 0x465cbc HINT	#0

      (2011) 0x465cc0 LDP	D7, D16, [X5, #1008]

      (2011) 0x465cc4 FCMP	D4, D7

      (2011) 0x465cc8 FADD	D6, D6, D7

      (2011) 0x465ccc FCSEL	D4, D4, D7, #4

      (2011) 0x465cd0 FADD	D6, D6, D16

      (2011) 0x465cd4 FCMP	D4, D16

      (2011) 0x465cd8 FCSEL	D4, D4, D16, #4

      (2011) 0x465cdc LDP	D7, D16, [X5], #32

      (2011) 0x465ce0 FCMP	D4, D7

      (2011) 0x465ce4 FADD	D6, D6, D7

      (2011) 0x465ce8 FCSEL	D4, D4, D7, #4

      (2011) 0x465cec FADD	D6, D6, D16

      (2011) 0x465cf0 FCMP	D4, D16

      (2011) 0x465cf4 FCSEL	D4, D4, D16, #4

      (2011) 0x465cf8 SUBS	X14, X14, #4

      (2011) 0x465cfc B.NE	465cc0

    (2008) 0x465d00 LDR	X21, [X2, X27,LSL #3]

    (2008) 0x465d04 LDR	X20, [X2, X12,LSL #3]

    (2008) 0x465d08 SUBS	X14, X21, X20

    (2008) 0x465d0c B.GE	466028

    (2008) 0x465d10 SUB	W11, W20, W21

    (2008) 0x465d14 ORR	X23, XZR, X21

    (2008) 0x465d18 ANDS	X5, X11, #0x3

    (2008) 0x465d1c B.EQ	465d3c

      (2010) 0x465d20 LDR	D7, [X3, X23,LSL #3]

      (2010) 0x465d24 ADD	X23, X23, #1

      (2010) 0x465d28 FCMP	D4, D7

      (2010) 0x465d2c FADD	D6, D6, D7

      (2010) 0x465d30 FCSEL	D4, D4, D7, #4

      (2010) 0x465d34 SUBS	X5, X5, #1

      (2010) 0x465d38 B.NE	465d20

    (2008) 0x465d3c CMN	X14, #4

    (2008) 0x465d40 B.HI	466028

    (2008) 0x465d44 ADD	X11, X3, #16

    (2008) 0x465d48 ADD	X14, X11, X23,LSL #3

      (2009) 0x465d4c LDP	D7, D16, [X14, #1008]

      (2009) 0x465d50 ADD	X23, X23, #4

      (2009) 0x465d54 FCMP	D4, D7

      (2009) 0x465d58 FADD	D6, D6, D7

      (2009) 0x465d5c FCSEL	D4, D4, D7, #4

      (2009) 0x465d60 FADD	D6, D6, D16

      (2009) 0x465d64 FCMP	D4, D16

      (2009) 0x465d68 FCSEL	D4, D4, D16, #4

      (2009) 0x465d6c LDP	D7, D16, [X14], #32

      (2009) 0x465d70 FCMP	D4, D7

      (2009) 0x465d74 FADD	D6, D6, D7

      (2009) 0x465d78 FCSEL	D4, D4, D7, #4

      (2009) 0x465d7c FADD	D6, D6, D16

      (2009) 0x465d80 FCMP	D4, D16

      (2009) 0x465d84 FCSEL	D4, D4, D16, #4

      (2009) 0x465d88 CMP	X20, X23

      (2009) 0x465d8c B.NE	465d4c

    (2008) 0x465d90 B	466028

    (2008) 0x465d94 FMOV	D6, D5

    (2008) 0x465d98 SUB	X14, X28, #2

    (2008) 0x465d9c CMP	X14, X19

    (2008) 0x465da0 B.NE	465e24

    (2008) 0x465da4 LDR	X21, [X2, X27,LSL #3]

    (2008) 0x465da8 LDR	X20, [X2, X12,LSL #3]

    (2008) 0x465dac CMP	X20, X21

    (2008) 0x465db0 B.LE	466028

    (2008) 0x465db4 LDUR	X11, [X29, #464]

    (2008) 0x465db8 LDR	X23, [X4, X27,LSL #3]

    (2008) 0x465dbc SUB	W14, W20, W21

    (2008) 0x465dc0 LDR	X5, [X11]

    (2008) 0x465dc4 TBNZ	W14, #0, 465eb4

    (2008) 0x465dc8 ORR	X7, XZR, X21

    (2008) 0x465dcc ADD	X14, X21, #1

    (2008) 0x465dd0 CMP	X20, X14

    (2008) 0x465dd4 B.NE	465ee8

    (2008) 0x465dd8 B	466028

    (2008) 0x465ddc FMOV	D6, D5

    (2008) 0x465de0 SUB	X14, X28, #2

    (2008) 0x465de4 CMP	X14, X19

    (2008) 0x465de8 B.NE	465f74

    (2008) 0x465dec LDR	X21, [X2, X27,LSL #3]

    (2008) 0x465df0 LDR	X20, [X2, X12,LSL #3]

    (2008) 0x465df4 CMP	X20, X21

    (2008) 0x465df8 B.LE	466028

    (2008) 0x465dfc LDUR	X11, [X29, #464]

    (2008) 0x465e00 LDR	X23, [X4, X27,LSL #3]

    (2008) 0x465e04 LDR	X5, [X11]

    (2008) 0x465e08 SUB	W11, W20, W21

    (2008) 0x465e0c TBNZ	W11, #0, 465ff4

    (2008) 0x465e10 ORR	X7, XZR, X21

    (2008) 0x465e14 ADD	X11, X21, #1

    (2008) 0x465e18 CMP	X20, X11

    (2008) 0x465e1c B.EQ	466028

  (2018) 0x465e20 B	466468

    (2008) 0x465e24 ADD	X11, X0, #8

    (2008) 0x465e28 SUB	X23, X28, X20

    (2008) 0x465e2c ADD	X14, X11, X20,LSL #3

    (2008) 0x465e30 LDR	X11, [SP, #56]

    (2008) 0x465e34 ADD	X20, X11, X20,LSL #3

    (2008) 0x465e38 B	465e50

0x465e3c HINT	#0

      (2021) 0x465e40 ADD	X20, X20, #16

      (2021) 0x465e44 SUBS	X23, X23, #2

      (2021) 0x465e48 ADD	X14, X14, #16

      (2021) 0x465e4c B.EQ	465da4

      (2021) 0x465e50 LDUR	X5, [X20, #504]

      (2021) 0x465e54 LDR	X5, [X4, X5,LSL #3]

      (2021) 0x465e58 CMP	X21, X5

      (2021) 0x465e5c B.EQ	465e80

      (2021) 0x465e60 LDR	X5, [X20]

      (2021) 0x465e64 LDR	X5, [X4, X5,LSL #3]

      (2021) 0x465e68 CMP	X21, X5

      (2021) 0x465e6c B.NE	465e40

      (2021) 0x465e70 B	465ea0

0x465e74 HINT	#0

0x465e78 HINT	#0

0x465e7c HINT	#0

      (2021) 0x465e80 LDUR	D7, [X14, #504]

      (2021) 0x465e84 FCMP	D4, D7

      (2021) 0x465e88 FADD	D6, D6, D7

      (2021) 0x465e8c FCSEL	D4, D7, D4, #4

      (2021) 0x465e90 LDR	X5, [X20]

      (2021) 0x465e94 LDR	X5, [X4, X5,LSL #3]

      (2021) 0x465e98 CMP	X21, X5

      (2021) 0x465e9c B.NE	465e40

      (2021) 0x465ea0 LDR	D7, [X14]

      (2021) 0x465ea4 FCMP	D4, D7

      (2021) 0x465ea8 FADD	D6, D6, D7

      (2021) 0x465eac FCSEL	D4, D7, D4, #4

      (2021) 0x465eb0 B	465e40

    (2008) 0x465eb4 LDR	X11, [SP, #64]

    (2008) 0x465eb8 LDR	X14, [X11, X21,LSL #3]

    (2008) 0x465ebc LDR	X14, [X6, X14,LSL #3]

    (2008) 0x465ec0 CMP	X23, X14

    (2008) 0x465ec4 B.NE	465ed8

    (2008) 0x465ec8 LDR	D7, [X5, X21,LSL #3]

    (2008) 0x465ecc FCMP	D4, D7

    (2008) 0x465ed0 FADD	D6, D6, D7

    (2008) 0x465ed4 FCSEL	D4, D7, D4, #4

    (2008) 0x465ed8 ADD	X7, X21, #1

    (2008) 0x465edc ADD	X14, X21, #1

    (2008) 0x465ee0 CMP	X20, X14

    (2008) 0x465ee4 B.EQ	466028

    (2008) 0x465ee8 LDR	X11, [SP, #48]

    (2008) 0x465eec ADD	X5, X5, X7,LSL #3

    (2008) 0x465ef0 SUB	X14, X20, X7

    (2008) 0x465ef4 ADD	X5, X5, #8

    (2008) 0x465ef8 ADD	X7, X11, X7,LSL #3

    (2008) 0x465efc B	465f0c

      (2020) 0x465f00 SUBS	X14, X14, #2

      (2020) 0x465f04 ADD	X5, X5, #16

      (2020) 0x465f08 B.EQ	466028

      (2020) 0x465f0c LDUR	X11, [X7, #504]

      (2020) 0x465f10 LDR	X11, [X6, X11,LSL #3]

      (2020) 0x465f14 CMP	X23, X11

      (2020) 0x465f18 B.EQ	465f40

      (2020) 0x465f1c LDR	X11, [X7], #16

      (2020) 0x465f20 LDR	X11, [X6, X11,LSL #3]

      (2020) 0x465f24 CMP	X23, X11

      (2020) 0x465f28 B.NE	465f00

      (2020) 0x465f2c B	465f60

0x465f30 HINT	#0

0x465f34 HINT	#0

0x465f38 HINT	#0

0x465f3c HINT	#0

      (2020) 0x465f40 LDUR	D7, [X5, #504]

      (2020) 0x465f44 FCMP	D4, D7

      (2020) 0x465f48 FADD	D6, D6, D7

      (2020) 0x465f4c FCSEL	D4, D7, D4, #4

      (2020) 0x465f50 LDR	X11, [X7], #16

      (2020) 0x465f54 LDR	X11, [X6, X11,LSL #3]

      (2020) 0x465f58 CMP	X23, X11

      (2020) 0x465f5c B.NE	465f00

      (2020) 0x465f60 LDR	D7, [X5]

      (2020) 0x465f64 FCMP	D4, D7

      (2020) 0x465f68 FADD	D6, D6, D7

      (2020) 0x465f6c FCSEL	D4, D7, D4, #4

      (2020) 0x465f70 B	465f00

    (2008) 0x465f74 ADD	X11, X0, #8

    (2008) 0x465f78 SUB	X23, X28, X20

    (2008) 0x465f7c ADD	X14, X11, X20,LSL #3

    (2008) 0x465f80 LDR	X11, [SP, #56]

    (2008) 0x465f84 ADD	X20, X11, X20,LSL #3

    (2008) 0x465f88 B	465f9c

      (2019) 0x465f8c ADD	X20, X20, #16

      (2019) 0x465f90 SUBS	X23, X23, #2

      (2019) 0x465f94 ADD	X14, X14, #16

      (2019) 0x465f98 B.EQ	465dec

      (2019) 0x465f9c LDUR	X11, [X20, #504]

      (2019) 0x465fa0 LDR	X11, [X4, X11,LSL #3]

      (2019) 0x465fa4 CMP	X21, X11

      (2019) 0x465fa8 B.EQ	465fc0

      (2019) 0x465fac LDR	X11, [X20]

      (2019) 0x465fb0 LDR	X11, [X4, X11,LSL #3]

      (2019) 0x465fb4 CMP	X21, X11

      (2019) 0x465fb8 B.NE	465f8c

      (2019) 0x465fbc B	465fe0

      (2019) 0x465fc0 LDUR	D7, [X14, #504]

      (2019) 0x465fc4 FCMP	D4, D7

      (2019) 0x465fc8 FADD	D6, D6, D7

      (2019) 0x465fcc FCSEL	D4, D4, D7, #4

      (2019) 0x465fd0 LDR	X11, [X20]

      (2019) 0x465fd4 LDR	X11, [X4, X11,LSL #3]

      (2019) 0x465fd8 CMP	X21, X11

      (2019) 0x465fdc B.NE	465f8c

      (2019) 0x465fe0 LDR	D7, [X14]

      (2019) 0x465fe4 FCMP	D4, D7

      (2019) 0x465fe8 FADD	D6, D6, D7

      (2019) 0x465fec FCSEL	D4, D4, D7, #4

      (2019) 0x465ff0 B	465f8c

    (2008) 0x465ff4 LDR	X11, [SP, #64]

    (2008) 0x465ff8 LDR	X11, [X11, X21,LSL #3]

    (2008) 0x465ffc LDR	X11, [X6, X11,LSL #3]

    (2008) 0x466000 CMP	X23, X11

    (2008) 0x466004 B.NE	466018

    (2008) 0x466008 LDR	D7, [X5, X21,LSL #3]

    (2008) 0x46600c FCMP	D4, D7

    (2008) 0x466010 FADD	D6, D6, D7

    (2008) 0x466014 FCSEL	D4, D4, D7, #4

    (2008) 0x466018 ADD	X7, X21, #1

    (2008) 0x46601c ADD	X11, X21, #1

    (2008) 0x466020 CMP	X20, X11

    (2008) 0x466024 B.NE	466468

    (2008) 0x466028 ORN	X11, XZR, X19

    (2008) 0x46602c ADD	X10, X28, X10

    (2008) 0x466030 FCMP	D0, D3

    (2008) 0x466034 ADD	X10, X10, X11

    (2008) 0x466038 SUB	X11, X20, X21

    (2008) 0x46603c ADD	X9, X11, X9

    (2008) 0x466040 STP	X9, X10, [X29, #984]

    (2008) 0x466044 STR	X26, [X24, X19,LSL #3]

    (2008) 0x466048 B.PL	4660e0

    (2008) 0x46604c FABS	D7, D5

    (2008) 0x466050 FABS	D6, D6

    (2008) 0x466054 FMUL	D7, D7, D0

    (2008) 0x466058 FCMP	D6, D7

    (2008) 0x46605c B.LE	4660e0

    (2008) 0x466060 LDR	X11, [X1, X27,LSL #3]

    (2008) 0x466064 LDR	X5, [X1, X12,LSL #3]

    (2008) 0x466068 ADD	X14, X11, #1

    (2008) 0x46606c CMP	X14, X5

    (2008) 0x466070 B.GE	46609c

    (2008) 0x466074 HINT	#0

    (2008) 0x466078 HINT	#0

    (2008) 0x46607c HINT	#0

      (2031) 0x466080 STR	X26, [X24, X14,LSL #3]

      (2031) 0x466084 ADD	X14, X14, #1

      (2031) 0x466088 LDR	X5, [X1, X12,LSL #3]

      (2031) 0x46608c CMP	X14, X5

      (2031) 0x466090 B.LT	466080

    (2008) 0x466094 LDR	X11, [X1, X27,LSL #3]

    (2008) 0x466098 ADD	X14, X11, #1

    (2008) 0x46609c SUB	X11, X14, X5

    (2008) 0x4660a0 ADD	X10, X11, X10

    (2008) 0x4660a4 STUR	X10, [X29, #480]

    (2008) 0x4660a8 LDR	X14, [X2, X27,LSL #3]

    (2008) 0x4660ac LDR	X5, [X2, X12,LSL #3]

    (2008) 0x4660b0 CMP	X14, X5

    (2008) 0x4660b4 B.GE	465a0c

    (2008) 0x4660b8 HINT	#0

    (2008) 0x4660bc HINT	#0

      (2030) 0x4660c0 STR	X26, [X30, X14,LSL #3]

      (2030) 0x4660c4 ADD	X14, X14, #1

      (2030) 0x4660c8 LDR	X5, [X2, X12,LSL #3]

      (2030) 0x4660cc CMP	X14, X5

      (2030) 0x4660d0 B.LT	4660c0

    (2008) 0x4660d4 LDR	X14, [X2, X27,LSL #3]

    (2008) 0x4660d8 B	465a0c

0x4660dc HINT	#0

    (2008) 0x4660e0 LDR	X14, [X1, X27,LSL #3]

    (2008) 0x4660e4 LDR	X11, [X17]

    (2008) 0x4660e8 ADD	X19, X14, #1

    (2008) 0x4660ec LDR	X14, [X1, X12,LSL #3]

    (2008) 0x4660f0 CMP	X11, #2

    (2008) 0x4660f4 B.LT	466200

    (2008) 0x4660f8 FCMP	D5, #0

    (2008) 0x4660fc B.PL	4662c4

    (2008) 0x466100 CMP	X19, X14

    (2008) 0x466104 B.GE	466170

    (2008) 0x466108 LDR	X14, [X16]

    (2008) 0x46610c LDR	X5, [X15]

    (2008) 0x466110 FMUL	D5, D4, D1

    (2008) 0x466114 B	46613c

0x466118 HINT	#0

0x46611c HINT	#0

      (2029) 0x466120 SUB	X10, X10, #1

      (2029) 0x466124 STR	X26, [X24, X19,LSL #3]

      (2029) 0x466128 STUR	X10, [X29, #480]

      (2029) 0x46612c LDR	X11, [X1, X12,LSL #3]

      (2029) 0x466130 ADD	X19, X19, #1

      (2029) 0x466134 CMP	X19, X11

      (2029) 0x466138 B.GE	466170

      (2029) 0x46613c LDR	D6, [X0, X19,LSL #3]

      (2029) 0x466140 FCMP	D6, D5

      (2029) 0x466144 B.LS	466120

      (2029) 0x466148 LDR	X7, [X5, X19,LSL #3]

      (2029) 0x46614c LDR	X11, [X14, X27,LSL #3]

      (2029) 0x466150 LDR	X20, [X14, X7,LSL #3]

      (2029) 0x466154 CMP	X11, X20

      (2029) 0x466158 B.NE	466120

      (2029) 0x46615c STR	X7, [X24, X19,LSL #3]

      (2029) 0x466160 LDR	X11, [X1, X12,LSL #3]

      (2029) 0x466164 ADD	X19, X19, #1

      (2029) 0x466168 CMP	X19, X11

      (2029) 0x46616c B.LT	46613c

    (2008) 0x466170 LDR	X14, [X2, X27,LSL #3]

    (2008) 0x466174 LDR	X11, [X2, X12,LSL #3]

    (2008) 0x466178 CMP	X14, X11

    (2008) 0x46617c B.GE	465a18

    (2008) 0x466180 LDUR	X11, [X29, #448]

    (2008) 0x466184 LDR	X5, [X16]

    (2008) 0x466188 LDR	X19, [X13]

    (2008) 0x46618c FMUL	D4, D4, D1

    (2008) 0x466190 LDR	X20, [X25]

    (2008) 0x466194 LDR	X7, [X11]

    (2008) 0x466198 B	4661bc

0x46619c HINT	#0

      (2028) 0x4661a0 SUB	X9, X9, #1

      (2028) 0x4661a4 STR	X26, [X20, X14,LSL #3]

      (2028) 0x4661a8 STUR	X9, [X29, #472]

      (2028) 0x4661ac LDR	X11, [X2, X12,LSL #3]

      (2028) 0x4661b0 ADD	X14, X14, #1

      (2028) 0x4661b4 CMP	X14, X11

      (2028) 0x4661b8 B.GE	465a18

      (2028) 0x4661bc LDR	D5, [X3, X14,LSL #3]

      (2028) 0x4661c0 FCMP	D5, D4

      (2028) 0x4661c4 B.LS	4661a0

      (2028) 0x4661c8 LDR	X21, [X19, X14,LSL #3]

      (2028) 0x4661cc LDR	X11, [X5, X27,LSL #3]

      (2028) 0x4661d0 LDR	X23, [X7, X21,LSL #3]

      (2028) 0x4661d4 CMP	X11, X23

      (2028) 0x4661d8 B.NE	4661a0

      (2028) 0x4661dc STR	X21, [X20, X14,LSL #3]

      (2028) 0x4661e0 LDR	X11, [X2, X12,LSL #3]

      (2028) 0x4661e4 ADD	X14, X14, #1

      (2028) 0x4661e8 CMP	X14, X11

      (2028) 0x4661ec B.LT	4661bc

    (2008) 0x4661f0 B	465a18

0x4661f4 HINT	#0

0x4661f8 HINT	#0

0x4661fc HINT	#0

    (2008) 0x466200 FCMP	D5, #0

    (2008) 0x466204 B.PL	4663b4

    (2008) 0x466208 CMP	X19, X14

    (2008) 0x46620c B.GE	466260

    (2008) 0x466210 LDR	X14, [X15]

    (2008) 0x466214 FMUL	D5, D4, D1

    (2008) 0x466218 B	466238

0x46621c HINT	#0

      (2025) 0x466220 LDR	X11, [X14, X19,LSL #3]

      (2025) 0x466224 STR	X11, [X24, X19,LSL #3]

      (2025) 0x466228 LDR	X11, [X1, X12,LSL #3]

      (2025) 0x46622c ADD	X19, X19, #1

      (2025) 0x466230 CMP	X19, X11

      (2025) 0x466234 B.GE	466260

      (2025) 0x466238 LDR	D6, [X0, X19,LSL #3]

      (2025) 0x46623c FCMP	D6, D5

      (2025) 0x466240 B.HI	466220

      (2025) 0x466244 SUB	X10, X10, #1

      (2025) 0x466248 STR	X26, [X24, X19,LSL #3]

      (2025) 0x46624c STUR	X10, [X29, #480]

      (2025) 0x466250 LDR	X11, [X1, X12,LSL #3]

      (2025) 0x466254 ADD	X19, X19, #1

      (2025) 0x466258 CMP	X19, X11

      (2025) 0x46625c B.LT	466238

    (2008) 0x466260 LDR	X14, [X2, X27,LSL #3]

    (2008) 0x466264 LDR	X11, [X2, X12,LSL #3]

    (2008) 0x466268 CMP	X14, X11

    (2008) 0x46626c B.GE	465a18

    (2008) 0x466270 LDR	X5, [X25]

    (2008) 0x466274 LDR	X7, [X13]

    (2008) 0x466278 FMUL	D4, D4, D1

    (2008) 0x46627c B	466298

      (2024) 0x466280 LDR	X11, [X7, X14,LSL #3]

      (2024) 0x466284 STR	X11, [X5, X14,LSL #3]

      (2024) 0x466288 LDR	X11, [X2, X12,LSL #3]

      (2024) 0x46628c ADD	X14, X14, #1

      (2024) 0x466290 CMP	X14, X11

      (2024) 0x466294 B.GE	465a18

      (2024) 0x466298 LDR	D5, [X3, X14,LSL #3]

      (2024) 0x46629c FCMP	D5, D4

      (2024) 0x4662a0 B.HI	466280

      (2024) 0x4662a4 SUB	X9, X9, #1

      (2024) 0x4662a8 STR	X26, [X5, X14,LSL #3]

      (2024) 0x4662ac STUR	X9, [X29, #472]

      (2024) 0x4662b0 LDR	X11, [X2, X12,LSL #3]

      (2024) 0x4662b4 ADD	X14, X14, #1

      (2024) 0x4662b8 CMP	X14, X11

      (2024) 0x4662bc B.LT	466298

    (2008) 0x4662c0 B	465a18

    (2008) 0x4662c4 CMP	X19, X14

    (2008) 0x4662c8 B.GE	466330

    (2008) 0x4662cc LDR	X14, [X16]

    (2008) 0x4662d0 LDR	X5, [X15]

    (2008) 0x4662d4 FMUL	D5, D4, D1

    (2008) 0x4662d8 B	4662fc

0x4662dc HINT	#0

      (2027) 0x4662e0 SUB	X10, X10, #1

      (2027) 0x4662e4 STR	X26, [X24, X19,LSL #3]

      (2027) 0x4662e8 STUR	X10, [X29, #480]

      (2027) 0x4662ec LDR	X11, [X1, X12,LSL #3]

      (2027) 0x4662f0 ADD	X19, X19, #1

      (2027) 0x4662f4 CMP	X19, X11

      (2027) 0x4662f8 B.GE	466330

      (2027) 0x4662fc LDR	D6, [X0, X19,LSL #3]

      (2027) 0x466300 FCMP	D6, D5

      (2027) 0x466304 B.GE	4662e0

      (2027) 0x466308 LDR	X7, [X5, X19,LSL #3]

      (2027) 0x46630c LDR	X11, [X14, X27,LSL #3]

      (2027) 0x466310 LDR	X20, [X14, X7,LSL #3]

      (2027) 0x466314 CMP	X11, X20

      (2027) 0x466318 B.NE	4662e0

      (2027) 0x46631c STR	X7, [X24, X19,LSL #3]

      (2027) 0x466320 LDR	X11, [X1, X12,LSL #3]

      (2027) 0x466324 ADD	X19, X19, #1

      (2027) 0x466328 CMP	X19, X11

      (2027) 0x46632c B.LT	4662fc

    (2008) 0x466330 LDR	X14, [X2, X27,LSL #3]

    (2008) 0x466334 LDR	X11, [X2, X12,LSL #3]

    (2008) 0x466338 CMP	X14, X11

    (2008) 0x46633c B.GE	465a18

    (2008) 0x466340 LDUR	X11, [X29, #448]

    (2008) 0x466344 LDR	X5, [X16]

    (2008) 0x466348 LDR	X19, [X13]

    (2008) 0x46634c FMUL	D4, D4, D1

    (2008) 0x466350 LDR	X20, [X25]

    (2008) 0x466354 LDR	X7, [X11]

    (2008) 0x466358 B	46637c

0x46635c HINT	#0

      (2026) 0x466360 SUB	X9, X9, #1

      (2026) 0x466364 STR	X26, [X20, X14,LSL #3]

      (2026) 0x466368 STUR	X9, [X29, #472]

      (2026) 0x46636c LDR	X11, [X2, X12,LSL #3]

      (2026) 0x466370 ADD	X14, X14, #1

      (2026) 0x466374 CMP	X14, X11

      (2026) 0x466378 B.GE	465a18

      (2026) 0x46637c LDR	D5, [X3, X14,LSL #3]

      (2026) 0x466380 FCMP	D5, D4

      (2026) 0x466384 B.GE	466360

      (2026) 0x466388 LDR	X21, [X19, X14,LSL #3]

      (2026) 0x46638c LDR	X11, [X5, X27,LSL #3]

      (2026) 0x466390 LDR	X23, [X7, X21,LSL #3]

      (2026) 0x466394 CMP	X11, X23

      (2026) 0x466398 B.NE	466360

      (2026) 0x46639c STR	X21, [X20, X14,LSL #3]

      (2026) 0x4663a0 LDR	X11, [X2, X12,LSL #3]

      (2026) 0x4663a4 ADD	X14, X14, #1

      (2026) 0x4663a8 CMP	X14, X11

      (2026) 0x4663ac B.LT	46637c

    (2008) 0x4663b0 B	465a18

    (2008) 0x4663b4 FMUL	D4, D4, D1

    (2008) 0x4663b8 CMP	X19, X14

    (2008) 0x4663bc B.GE	466408

    (2008) 0x4663c0 LDR	X14, [X15]

    (2008) 0x4663c4 B	4663e0

      (2023) 0x4663c8 LDR	X11, [X14, X19,LSL #3]

      (2023) 0x4663cc STR	X11, [X24, X19,LSL #3]

      (2023) 0x4663d0 LDR	X11, [X1, X12,LSL #3]

      (2023) 0x4663d4 ADD	X19, X19, #1

      (2023) 0x4663d8 CMP	X19, X11

      (2023) 0x4663dc B.GE	466408

      (2023) 0x4663e0 LDR	D5, [X0, X19,LSL #3]

      (2023) 0x4663e4 FCMP	D5, D4

      (2023) 0x4663e8 B.LT	4663c8

      (2023) 0x4663ec SUB	X10, X10, #1

      (2023) 0x4663f0 STR	X26, [X24, X19,LSL #3]

      (2023) 0x4663f4 STUR	X10, [X29, #480]

      (2023) 0x4663f8 LDR	X11, [X1, X12,LSL #3]

      (2023) 0x4663fc ADD	X19, X19, #1

      (2023) 0x466400 CMP	X19, X11

      (2023) 0x466404 B.LT	4663e0

    (2008) 0x466408 LDR	X14, [X2, X27,LSL #3]

    (2008) 0x46640c LDR	X11, [X2, X12,LSL #3]

    (2008) 0x466410 CMP	X14, X11

    (2008) 0x466414 B.GE	465a18

    (2008) 0x466418 LDR	X5, [X25]

    (2008) 0x46641c LDR	X7, [X13]

    (2008) 0x466420 B	46643c

      (2022) 0x466424 LDR	X11, [X7, X14,LSL #3]

      (2022) 0x466428 STR	X11, [X5, X14,LSL #3]

      (2022) 0x46642c LDR	X11, [X2, X12,LSL #3]

      (2022) 0x466430 ADD	X14, X14, #1

      (2022) 0x466434 CMP	X14, X11

      (2022) 0x466438 B.GE	465a18

      (2022) 0x46643c LDR	D5, [X3, X14,LSL #3]

      (2022) 0x466440 FCMP	D5, D4

      (2022) 0x466444 B.LT	466424

      (2022) 0x466448 SUB	X9, X9, #1

      (2022) 0x46644c STR	X26, [X5, X14,LSL #3]

      (2022) 0x466450 STUR	X9, [X29, #472]

      (2022) 0x466454 LDR	X11, [X2, X12,LSL #3]

      (2022) 0x466458 ADD	X14, X14, #1

      (2022) 0x46645c CMP	X14, X11

      (2022) 0x466460 B.LT	46643c

    (2008) 0x466464 B	465a18

  (2018) 0x466468 ADD	X11, X5, X7,LSL #3

  (2018) 0x46646c SUB	X14, X20, X7

  (2018) 0x466470 ADD	X5, X11, #8

  (2018) 0x466474 LDR	X11, [SP, #48]

  (2018) 0x466478 ADD	X7, X11, X7,LSL #3

  (2018) 0x46647c B	46648c

  (2018) 0x466480 SUBS	X14, X14, #2

  (2018) 0x466484 ADD	X5, X5, #16

  (2018) 0x466488 B.EQ	466028

  (2018) 0x46648c LDUR	X11, [X7, #504]

  (2018) 0x466490 LDR	X11, [X6, X11,LSL #3]

  (2018) 0x466494 CMP	X23, X11

  (2018) 0x466498 B.EQ	4664c0

  (2018) 0x46649c LDR	X11, [X7], #16

  (2018) 0x4664a0 LDR	X11, [X6, X11,LSL #3]

  (2018) 0x4664a4 CMP	X23, X11

  (2018) 0x4664a8 B.NE	466480

  (2018) 0x4664ac B	4664e0

0x4664b0 HINT	#0

0x4664b4 HINT	#0

0x4664b8 HINT	#0

0x4664bc HINT	#0

(2017) 0x4664c0 LDUR	D7, [X5, #504]

(2017) 0x4664c4 FCMP	D4, D7

(2017) 0x4664c8 FADD	D6, D6, D7

(2017) 0x4664cc FCSEL	D4, D4, D7, #4

(2017) 0x4664d0 LDR	X11, [X7], #16

(2017) 0x4664d4 LDR	X11, [X6, X11,LSL #3]

(2017) 0x4664d8 CMP	X23, X11

(2017) 0x4664dc B.NE	466480

  (2018) 0x4664e0 LDR	D7, [X5]

  (2018) 0x4664e4 FCMP	D4, D7

  (2018) 0x4664e8 FADD	D6, D6, D7

  (2018) 0x4664ec FCSEL	D4, D4, D7, #4

  (2018) 0x4664f0 B	466480

0x4664f4 LDP	X9, X11, [SP, #8]

0x4664f8 LDUR	X19, [X29, #456]

0x4664fc SUB	X0, X29, #32

0x466500 SUB	X2, X29, #40

0x466504 LDR	X9, [X9]

0x466508 LDR	X10, [X19]

0x46650c LDR	X4, [X11]

0x466510 ADD	X1, X8, X9,LSL #3

0x466514 ADD	X3, X10, X9,LSL #3

0x466518 BL	4ad890

0x46651c LDP	X8, X10, [X29, #1000]

0x466520 CMP	X10, X8

0x466524 B.GE	466624

0x466528 LDR	X11, [SP]

0x46652c LDP	X15, X13, [SP, #32]

0x466530 LDR	X14, [SP, #24]

0x466534 LDR	X12, [X19]

0x466538 LDR	X16, [X25]

0x46653c LDR	X11, [X11]

0x466540 LDR	X13, [X13]

0x466544 LDP	X9, X8, [X29, #192]

0x466548 LDR	X14, [X14]

0x46654c LDR	X15, [X15]

0x466550 B	46656c

0x466554 HINT	#0

0x466558 HINT	#0

0x46655c HINT	#0

  (2005) 0x466560 LDUR	X17, [X29, #488]

  (2005) 0x466564 CMP	X10, X17

  (2005) 0x466568 B.GE	466624

  (2005) 0x46656c ORR	X17, XZR, X10

  (2005) 0x466570 LDUR	X10, [X29, #480]

  (2005) 0x466574 LDR	X18, [X11, X17,LSL #3]

  (2005) 0x466578 ADD	X10, X18, X10

  (2005) 0x46657c STR	X10, [X11, X17,LSL #3]

  (2005) 0x466580 LDUR	X10, [X29, #472]

  (2005) 0x466584 LDR	X18, [X12, X17,LSL #3]

  (2005) 0x466588 ADD	X10, X18, X10

  (2005) 0x46658c STR	X10, [X12, X17,LSL #3]

  (2005) 0x466590 ADD	X10, X17, #1

  (2005) 0x466594 LDR	X18, [X13, X17,LSL #3]

  (2005) 0x466598 LDR	X0, [X13, X10,LSL #3]

  (2005) 0x46659c CMP	X18, X0

  (2005) 0x4665a0 B.GE	4665e4

(2006) 0x4665a4 LDR	X1, [X11, X17,LSL #3]

(2006) 0x4665a8 LDR	X2, [X9]

(2006) 0x4665ac B	4665cc

0x4665b0 HINT	#0

0x4665b4 HINT	#0

0x4665b8 HINT	#0

0x4665bc HINT	#0

(2006) 0x4665c0 ADD	X18, X18, #1

(2006) 0x4665c4 CMP	X18, X0

(2006) 0x4665c8 B.GE	4665e4

(2006) 0x4665cc LDR	X3, [X14, X18,LSL #3]

(2006) 0x4665d0 TBNZ	X3, #63, 4665c0

(2006) 0x4665d4 STR	X3, [X2, X1,LSL #3]

(2006) 0x4665d8 ADD	X1, X1, #1

(2006) 0x4665dc LDR	X0, [X13, X10,LSL #3]

(2006) 0x4665e0 B	4665c0

  (2005) 0x4665e4 LDR	X18, [X15, X17,LSL #3]

  (2005) 0x4665e8 LDR	X0, [X15, X10,LSL #3]

  (2005) 0x4665ec CMP	X18, X0

  (2005) 0x4665f0 B.GE	466560

  (2005) 0x4665f4 LDR	X17, [X12, X17,LSL #3]

  (2005) 0x4665f8 LDR	X1, [X8]

  (2005) 0x4665fc B	46660c

    (2007) 0x466600 ADD	X18, X18, #1

    (2007) 0x466604 CMP	X18, X0

    (2007) 0x466608 B.GE	466560

    (2007) 0x46660c LDR	X2, [X16, X18,LSL #3]

    (2007) 0x466610 TBNZ	X2, #63, 466600

    (2007) 0x466614 STR	X2, [X1, X17,LSL #3]

    (2007) 0x466618 ADD	X17, X17, #1

    (2007) 0x46661c LDR	X0, [X15, X10,LSL #3]

    (2007) 0x466620 B	466600

0x466624 LDP	X20, X19, [SP, #224]

0x466628 LDP	X22, X21, [SP, #208]

0x46662c LDP	X24, X23, [SP, #192]

0x466630 LDP	X26, X25, [SP, #176]

0x466634 LDP	X28, X27, [SP, #160]

0x466638 LDP	X29, X30, [SP, #144]

0x46663c ADD	SP, SP, #240

0x466640 RET

0x466644 HINT	#0

0x466648 HINT	#0

0x46664c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.59+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.41+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_BoomerAMGCreateS	par_strength.c:520	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:581	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_strength.c:246-513
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:246-283,289-302,309-386,392-415,422-445,451-472,480,492-513.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.83 to 0.67 cycles (35.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 30% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 23.83 to 6.87 cycles (3.47x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_GetSimpleThreadPartition: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:250
hypre_prefix_sum_pair: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:480

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	140
nb uops	99
loop length	560
used w registers	0
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	4
used q registers	0
used v registers	0
used z registers	0
nb stack references	28

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.38 cycles
front end	12.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	5.25	5.25	5.25	5.25	0.50	0.50	0.50	0.50	23.83	23.50	23.67	9.50	9.50
cycles	3.50	3.50	5.25	5.25	5.25	5.25	0.50	0.50	0.50	0.50	23.83	23.50	23.67	9.50	9.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.38
Dispatch	23.83
Overall L1	23.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	30%
load	28%
store	35%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	30%
load	28%
store	35%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.83 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 465900

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X0, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X1, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X24, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X25, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X5, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X19, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4acc70 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X12, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X12, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STP XZR, XZR, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X19, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GE 4664f4 <hypre_BoomerAMGCreateS.omp_outlined.1+0xbf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X11, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D3, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVN X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X16, X15, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X13, X3, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X6, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X30, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X11, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D0, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X19, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X3, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STUR X6, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X11, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X19, X7, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X24, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X11, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X11, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X11, X19, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X11, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 465a24 <hypre_BoomerAMGCreateS.omp_outlined.1+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X9, X11, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDUR X19, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X0, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X2, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X4, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X1, X8, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X10, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4ad890 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X10, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 466624 <hypre_BoomerAMGCreateS.omp_outlined.1+0xd24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X15, X13, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 46656c <hypre_BoomerAMGCreateS.omp_outlined.1+0xc6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_strength.c:246-513
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_GetSimpleThreadPartition: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:250
hypre_prefix_sum_pair: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:480

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	140
nb uops	99
loop length	560
used w registers	0
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	4
used q registers	0
used v registers	0
used z registers	0
nb stack references	28

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.38 cycles
front end	12.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	5.25	5.25	5.25	5.25	0.50	0.50	0.50	0.50	23.83	23.50	23.67	9.50	9.50
cycles	3.50	3.50	5.25	5.25	5.25	5.25	0.50	0.50	0.50	0.50	23.83	23.50	23.67	9.50	9.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.38
Dispatch	23.83
Overall L1	23.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	30%
load	28%
store	35%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	30%
load	28%
store	35%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.83 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 465900

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X0, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X1, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X24, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X25, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X5, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X19, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4acc70 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X12, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X12, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STP XZR, XZR, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X19, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GE 4664f4 <hypre_BoomerAMGCreateS.omp_outlined.1+0xbf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X11, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D3, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVN X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X16, X15, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X13, X3, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X6, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X30, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X11, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D0, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X19, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X3, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STUR X6, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X11, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X19, X7, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X24, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X11, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X11, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X11, X19, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X11, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 465a24 <hypre_BoomerAMGCreateS.omp_outlined.1+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X9, X11, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDUR X19, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X0, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X2, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X4, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X1, X8, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X10, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4ad890 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X10, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 466624 <hypre_BoomerAMGCreateS.omp_outlined.1+0xd24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X15, X13, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 46656c <hypre_BoomerAMGCreateS.omp_outlined.1+0xc6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X20, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCreateS.omp_outlined.1–	0.26	0.12
▼Loop 2006 - par_strength.c:492-513 - exec–	0.07	0.02
▼Loop 2005 - par_strength.c:492-513 - exec–	0.01	0.01
○Loop 2007 - par_strength.c:508-513 - exec	0.00	0.00
▼Loop 2017 - par_strength.c:253-472 - exec–	0.00	0.00
▼Loop 2018 - par_strength.c:253-472 - exec–	0.00	0.00
▼Loop 2008 - par_strength.c:253-472 - exec–	0.05	0.02
○Loop 2023 - par_strength.c:451-460 - exec	0.10	0.03
○Loop 2011 - par_strength.c:324-327 - exec	0.04	0.01
○Loop 2012 - par_strength.c:324-327 - exec	0.00	0.01
○Loop 2025 - par_strength.c:424-433 - exec	0.00	0.00
○Loop 2009 - par_strength.c:329-332 - exec	0.00	0.00
○Loop 2015 - par_strength.c:311-314 - exec	0.00	0.00
○Loop 2019 - par_strength.c:289-294 - exec	0.00	0.00
○Loop 2020 - par_strength.c:278-283 - exec	0.00	0.00
○Loop 2030 - par_strength.c:351-353 - exec	0.00	0.00
○Loop 2029 - par_strength.c:363-373 - exec	0.00	0.00
○Loop 2013 - par_strength.c:316-319 - exec	0.00	0.00
○Loop 2014 - par_strength.c:316-319 - exec	0.00	0.00
○Loop 2028 - par_strength.c:376-386 - exec	0.00	0.00
○Loop 2016 - par_strength.c:311-314 - exec	0.00	0.00
○Loop 2024 - par_strength.c:436-445 - exec	0.00	0.00
○Loop 2021 - par_strength.c:270-275 - exec	0.00	0.00
○Loop 2031 - par_strength.c:345-347 - exec	0.00	0.00
○Loop 2010 - par_strength.c:329-332 - exec	0.00	0.00
○Loop 2026 - par_strength.c:405-415 - exec	0.00	0.00
○Loop 2027 - par_strength.c:392-402 - exec	0.00	0.00
○Loop 2022 - par_strength.c:463-472 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code