OV - exec - Function hypre_BoomerAMGCreate2ndS.omp

	Function: hypre_BoomerAMGCreate2ndS.omp_outlined.15	Module: exec	Source: par_strength.c:1668-2230 [...]	Coverage (incl. loops): 1.39% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 1668 - 2230

--------------------------------------------------------------------------------

1668: #pragma omp parallel private(i1,i2,i3,jj1,jj2,index)

1669: #endif

1670:    {

1671:       HYPRE_Int my_thread_num = hypre_GetThreadNum();

1672:

1673:       HYPRE_Int i1_begin, i1_end;

1674:       hypre_GetSimpleThreadPartition(&i1_begin, &i1_end, num_cols_diag_S);

1675:

1676:       HYPRE_Int *C_temp_diag_j = NULL, *C_temp_offd_j = NULL;

1677:       HYPRE_Int *C_temp_diag_data = NULL, *C_temp_offd_data = NULL;

1678:

1679:       if (num_paths > 1)

1680:       {

1681:          C_temp_diag_j = C_temp_diag_j_array + num_coarse*my_thread_num;

1682:          C_temp_offd_j = C_temp_offd_j_array + num_cols_offd_C*my_thread_num;

1683:

1684:          C_temp_diag_data = C_temp_diag_data_array + num_coarse*my_thread_num;

1685:          C_temp_offd_data = C_temp_offd_data_array + num_cols_offd_C*my_thread_num;

1686:       }

1687:

1688:       HYPRE_Int *S_marker = NULL, *S_marker_offd = NULL;

1689:       if (num_coarse) S_marker = S_marker_array + num_coarse*my_thread_num;

1690:       if (num_cols_offd_C) S_marker_offd = S_marker_offd_array + num_cols_offd_C*my_thread_num;

1691:       for (i1 = 0; i1 < num_coarse; i1++)

1692:       {

1693:          S_marker[i1] = -1;

1694:       }

1695:       for (i1 = 0; i1 < num_cols_offd_C; i1++)

1696:       {

1697:          S_marker_offd[i1] = -1;

[...]

1705:       HYPRE_Int num_nonzeros_diag = 0;

1706:       HYPRE_Int num_nonzeros_offd = 0;

1707:

1708:       HYPRE_Int ic_begin = num_coarse_prefix_sum[my_thread_num];

1709:       HYPRE_Int ic_end = num_coarse_prefix_sum[my_thread_num + 1];

1710:       HYPRE_Int ic;

1711:

1712:       if (num_paths == 1)

1713:       {

1714:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

1720:              HYPRE_Int i1 = coarse_to_fine[ic];

1721:

1722:              HYPRE_Int jj_row_begin_diag = num_nonzeros_diag;

1723:              HYPRE_Int jj_row_begin_offd = num_nonzeros_offd;

1724:

1725:              C_diag_i[ic] = num_nonzeros_diag;

1726:              if (num_cols_offd_C)

1727:              {

1728:                 C_offd_i[ic] = num_nonzeros_offd;

1729:              }

1730:

1731:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

1732:              {

1733:                  i2 = S_diag_j[jj1];

1734:                  if (CF_marker[i2] > 0)

1735:                  {

1736:                     index = fine_to_coarse[i2];

1737:                     if (S_marker[index] < jj_row_begin_diag)

1738:                     {

1739:                        S_marker[index] = num_nonzeros_diag;

1740:                        num_nonzeros_diag++;

1741:                     }

1742:                  }

1743:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

1744:                  {

1745:                     i3 = S_diag_j[jj2];

1746:                     if (CF_marker[i3] > 0)

1747:                     {

1748:                        index = fine_to_coarse[i3];

1749:                        if (index != ic && S_marker[index] < jj_row_begin_diag)

1750:                        {

1751:                           S_marker[index] = num_nonzeros_diag;

1752:                           num_nonzeros_diag++;

1753:                        }

1754:                     }

1755:                  }

1756:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

1757:                  {

1758:                     i3 = S_offd_j[jj2];

1759:                     if (CF_marker_offd[i3] > 0)

1760:                     {

1761:                        index = map_S_to_C[i3];

1762:                        if (S_marker_offd[index] < jj_row_begin_offd)

1763:                        {

1764:                           S_marker_offd[index] = num_nonzeros_offd;

1765:                           num_nonzeros_offd++;

1766:                        }

1767:                     }

1768:                  }

1769:              }

1770:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

1771:              {

1772:                  i2 = S_offd_j[jj1];

1773:                  if (CF_marker_offd[i2] > 0)

1774:                  {

1775:                     index = map_S_to_C[i2];

1776:                     if (S_marker_offd[index] < jj_row_begin_offd)

1777:                     {

1778:                        S_marker_offd[index] = num_nonzeros_offd;

1779:                        num_nonzeros_offd++;

1780:                     }

1781:                  }

1782:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

1783:                  {

1784:                     i3 = S_ext_diag_j[jj2];

1785:                     if (i3 != ic && S_marker[i3] < jj_row_begin_diag)

1786:                     {

1787:                        S_marker[i3] = num_nonzeros_diag;

1788:                        num_nonzeros_diag++;

1789:                     }

1790:                  }

1791:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

1792:                  {

1793:                     i3 = S_ext_offd_j[jj2];

1794:                     if (S_marker_offd[i3] < jj_row_begin_offd)

1795:                     {

1796:                        S_marker_offd[i3] = num_nonzeros_offd;

1797:                        num_nonzeros_offd++;

[...]

1806:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

1812:              HYPRE_Int i1 = coarse_to_fine[ic];

1813:

1814:              HYPRE_Int jj_row_begin_diag = jj_count_diag;

1815:              HYPRE_Int jj_row_begin_offd = jj_count_offd;

1816:

1817:              C_diag_i[ic] = num_nonzeros_diag;

1818:              if (num_cols_offd_C)

1819:              {

1820:                 C_offd_i[ic] = num_nonzeros_offd;

1821:              }

1822:

1823:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

1824:              {

1825:                  i2 = S_diag_j[jj1];

1826:                  if (CF_marker[i2] > 0)

1827:                  {

1828:                     index = fine_to_coarse[i2];

1829:                     if (S_marker[index] < jj_row_begin_diag)

1830:                     {

1831:                        S_marker[index] = jj_count_diag;

1832:                        C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 2;

1833:                        jj_count_diag++;

1834:                     }

1835:                     else

1836:                     {

1837:                        C_temp_diag_data[S_marker[index] - jj_row_begin_diag] += 2;

1838:                     }

1839:                  }

1840:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

1841:                  {

1842:                     i3 = S_diag_j[jj2];

1843:                     if (CF_marker[i3] > 0 && fine_to_coarse[i3] != ic)

1844:                     {

1845:                        index = fine_to_coarse[i3];

1846:                        if (S_marker[index] < jj_row_begin_diag)

1847:                        {

1848:                           S_marker[index] = jj_count_diag;

1849:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

1850:                           jj_count_diag++;

1851:                        }

1852:                        else

1853:                        {

1854:                           C_temp_diag_data[S_marker[index] - jj_row_begin_diag]++;

1855:                        }

1856:                     }

1857:                  }

1858:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

1859:                  {

1860:                     i3 = S_offd_j[jj2];

1861:                     if (CF_marker_offd[i3] > 0)

1862:                     {

1863:                        index = map_S_to_C[i3];

1864:                        if (S_marker_offd[index] < jj_row_begin_offd)

1865:                        {

1866:                           S_marker_offd[index] = jj_count_offd;

1867:                           C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

1868:                           jj_count_offd++;

1869:                        }

1870:                        else

1871:                        {

1872:                           C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd]++;

1873:                        }

1874:                     }

1875:                  }

1876:              }

1877:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

1878:              {

1879:                  i2 = S_offd_j[jj1];

1880:                  if (CF_marker_offd[i2] > 0)

1881:                  {

1882:                     index = map_S_to_C[i2];

1883:                     if (S_marker_offd[index] < jj_row_begin_offd)

1884:                     {

1885:                        S_marker_offd[index] = jj_count_offd;

1886:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 2;

1887:                        jj_count_offd++;

1888:                     }

1889:                     else

1890:                     {

1891:                        C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd] += 2;

1892:                     }

1893:                  }

1894:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

1895:                  {

1896:                     i3 = S_ext_diag_j[jj2];

1897:                     if (i3 != ic)

1898:                     {

1899:                        if (S_marker[i3] < jj_row_begin_diag)

1900:                        {

1901:                           S_marker[i3] = jj_count_diag;

1902:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

1903:                           jj_count_diag++;

1904:                        }

1905:                        else

1906:                        {

1907:                           C_temp_diag_data[S_marker[i3] - jj_row_begin_diag]++;

1908:                        }

1909:                     }

1910:                  }

1911:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

1912:                  {

1913:                     i3 = S_ext_offd_j[jj2];

1914:                     if (S_marker_offd[i3] < jj_row_begin_offd)

1915:                     {

1916:                        S_marker_offd[i3] = jj_count_offd;

1917:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

1918:                        jj_count_offd++;

1919:                     }

1920:                     else

1921:                     {

1922:                        C_temp_offd_data[S_marker_offd[i3] - jj_row_begin_offd]++;

1923:                     }

1924:                  }

1925:              }

1926:

1927:              for (jj1 = jj_row_begin_diag; jj1 < jj_count_diag; jj1++)

1928:              {

1929:                  if (C_temp_diag_data[jj1 - jj_row_begin_diag] >= num_paths)

1930:                  {

1931:                     ++num_nonzeros_diag;

1932:                  }

1933:                  C_temp_diag_data[jj1 - jj_row_begin_diag] = 0;

1934:              }

1935:              for (jj1 = jj_row_begin_offd; jj1 < jj_count_offd; jj1++)

1936:              {

1937:                  if (C_temp_offd_data[jj1 - jj_row_begin_offd] >= num_paths)

1938:                  {

1939:                     ++num_nonzeros_offd;

1940:                  }

1941:                  C_temp_offd_data[jj1 - jj_row_begin_offd] = 0;

1942:              }

1943:          } /* for each row */

1944:       } /* num_paths > 1 */

1945:

1946:       hypre_prefix_sum_pair(

1947:          &num_nonzeros_diag, &C_diag_i[num_coarse],

1948:          &num_nonzeros_offd, &C_offd_i[num_coarse],

1949:          prefix_sum_workspace);

1950:

1951:       for (i1 = 0; i1 < num_coarse; i1++)

1952:       {

1953:          S_marker[i1] = -1;

1954:       }

1955:       for (i1 = 0; i1 < num_cols_offd_C; i1++)

1956:       {

1957:          S_marker_offd[i1] = -1;

1958:       }

1959:

1960: #ifdef HYPRE_USING_OPENMP

1961: #pragma omp barrier

1962: #pragma omp master

1963: #endif

1964:       {

1965:          if (C_diag_i[num_coarse])

1966:          {

1967:             C_diag_j = hypre_TAlloc(HYPRE_Int, C_diag_i[num_coarse]);

1968:          }

1969:          if (C_offd_i[num_coarse])

1970:          {

1971:             C_offd_j = hypre_TAlloc(HYPRE_Int, C_offd_i[num_coarse]);

1972:          }

1973:       }

1974: #ifdef HYPRE_USING_OPENMP

1975: #pragma omp barrier

1976: #endif

1977:

1978:       for (ic = ic_begin; ic < ic_end - 1; ic++)

1979:       {

1980:          if (C_diag_i[ic+1] == C_diag_i[ic] && C_offd_i[ic+1] == C_offd_i[ic])

1981:             CF_marker[coarse_to_fine[ic]] = 2;

1982:

1983:          C_diag_i[ic] += num_nonzeros_diag;

1984:          C_offd_i[ic] += num_nonzeros_offd;

1985:       }

1986:       if (ic_begin < ic_end)

1987:       {

1988:          C_diag_i[ic] += num_nonzeros_diag;

1989:          C_offd_i[ic] += num_nonzeros_offd;

1990:

1991:          HYPRE_Int next_C_diag_i = prefix_sum_workspace[2*(my_thread_num + 1)];

1992:          HYPRE_Int next_C_offd_i = prefix_sum_workspace[2*(my_thread_num + 1) + 1];

1993:

1994:          if (next_C_diag_i == C_diag_i[ic] && next_C_offd_i == C_offd_i[ic])

1995:             CF_marker[coarse_to_fine[ic]] = 2;

1996:       }

1997:

1998:       if (num_paths == 1)

1999:       {

2000:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

2006:              HYPRE_Int i1 = coarse_to_fine[ic];

2007:

2008:              HYPRE_Int jj_row_begin_diag = num_nonzeros_diag;

2009:              HYPRE_Int jj_row_begin_offd = num_nonzeros_offd;

2010:

2011:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

2012:              {

2013:                  i2 = S_diag_j[jj1];

2014:                  if (CF_marker[i2] > 0)

2015:                  {

2016:                     index = fine_to_coarse[i2];

2017:                     if (S_marker[index] < jj_row_begin_diag)

2018:                     {

2019:                        S_marker[index] = num_nonzeros_diag;

2020:                        C_diag_j[num_nonzeros_diag] = index;

2021:                        num_nonzeros_diag++;

2022:                     }

2023:                  }

2024:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

2025:                  {

2026:                     i3 = S_diag_j[jj2];

2027:                     if (CF_marker[i3] > 0)

2028:                     {

2029:                        index = fine_to_coarse[i3];

2030:                        if (index != ic && S_marker[index] < jj_row_begin_diag)

2031:                        {

2032:                           S_marker[index] = num_nonzeros_diag;

2033:                           C_diag_j[num_nonzeros_diag] = index;

2034:                           num_nonzeros_diag++;

2035:                        }

2036:                     }

2037:                  }

2038:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

2039:                  {

2040:                     i3 = S_offd_j[jj2];

2041:                     if (CF_marker_offd[i3] > 0)

2042:                     {

2043:                        index = map_S_to_C[i3];

2044:                        if (S_marker_offd[index] < jj_row_begin_offd)

2045:                        {

2046:                           S_marker_offd[index] = num_nonzeros_offd;

2047:                           C_offd_j[num_nonzeros_offd] = index;

2048:                           num_nonzeros_offd++;

2049:                        }

2050:                     }

2051:                  }

2052:              }

2053:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

2054:              {

2055:                  i2 = S_offd_j[jj1];

2056:                  if (CF_marker_offd[i2] > 0)

2057:                  {

2058:                     index = map_S_to_C[i2];

2059:                     if (S_marker_offd[index] < jj_row_begin_offd)

2060:                     {

2061:                        S_marker_offd[index] = num_nonzeros_offd;

2062:                        C_offd_j[num_nonzeros_offd] = index;

2063:                        num_nonzeros_offd++;

2064:                     }

2065:                  }

2066:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

2067:                  {

2068:                     i3 = S_ext_diag_j[jj2];

2069:                     if (i3 != ic && S_marker[i3] < jj_row_begin_diag)

2070:                     {

2071:                        S_marker[i3] = num_nonzeros_diag;

2072:                        C_diag_j[num_nonzeros_diag] = i3;

2073:                        num_nonzeros_diag++;

2074:                     }

2075:                  }

2076:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

2077:                  {

2078:                     i3 = S_ext_offd_j[jj2];

2079:                     if (S_marker_offd[i3] < jj_row_begin_offd)

2080:                     {

2081:                        S_marker_offd[i3] = num_nonzeros_offd;

2082:                        C_offd_j[num_nonzeros_offd] = i3;

2083:                        num_nonzeros_offd++;

[...]

2093:          jj_count_offd = num_nonzeros_offd;

2094:

2095:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

2101:              HYPRE_Int i1 = coarse_to_fine[ic];

2102:

2103:              HYPRE_Int jj_row_begin_diag = jj_count_diag;

2104:              HYPRE_Int jj_row_begin_offd = jj_count_offd;

2105:

2106:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

2107:              {

2108:                  i2 = S_diag_j[jj1];

2109:                  if (CF_marker[i2] > 0)

2110:                  {

2111:                     index = fine_to_coarse[i2];

2112:                     if (S_marker[index] < jj_row_begin_diag)

2113:                     {

2114:                        S_marker[index] = jj_count_diag;

2115:                        C_temp_diag_j[jj_count_diag - jj_row_begin_diag] = index;

2116:                        C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 2;

2117:                        jj_count_diag++;

2118:                     }

2119:                     else

2120:                     {

2121:                        C_temp_diag_data[S_marker[index] - jj_row_begin_diag] += 2;

2122:                     }

2123:                  }

2124:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

2125:                  {

2126:                     i3 = S_diag_j[jj2];

2127:                     if (CF_marker[i3] > 0 && fine_to_coarse[i3] != ic)

2128:                     {

2129:                        index = fine_to_coarse[i3];

2130:                        if (S_marker[index] < jj_row_begin_diag)

2131:                        {

2132:                           S_marker[index] = jj_count_diag;

2133:                           C_temp_diag_j[jj_count_diag - jj_row_begin_diag] = index;

2134:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

2135:                           jj_count_diag++;

2136:                        }

2137:                        else

2138:                        {

2139:                           C_temp_diag_data[S_marker[index] - jj_row_begin_diag]++;

2140:                        }

2141:                     }

2142:                  }

2143:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

2144:                  {

2145:                     i3 = S_offd_j[jj2];

2146:                     if (CF_marker_offd[i3] > 0)

2147:                     {

2148:                        index = map_S_to_C[i3];

2149:                        if (S_marker_offd[index] < jj_row_begin_offd)

2150:                        {

2151:                           S_marker_offd[index] = jj_count_offd;

2152:                           C_temp_offd_j[jj_count_offd - jj_row_begin_offd] = index;

2153:                           C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

2154:                           jj_count_offd++;

2155:                        }

2156:                        else

2157:                        {

2158:                           C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd]++;

2159:                        }

2160:                     }

2161:                  }

2162:              }

2163:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

2164:              {

2165:                  i2 = S_offd_j[jj1];

2166:                  if (CF_marker_offd[i2] > 0)

2167:                  {

2168:                     index = map_S_to_C[i2];

2169:                     if (S_marker_offd[index] < jj_row_begin_offd)

2170:                     {

2171:                        S_marker_offd[index] = jj_count_offd;

2172:                        C_temp_offd_j[jj_count_offd - jj_row_begin_offd] = index;

2173:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 2;

2174:                        jj_count_offd++;

2175:                     }

2176:                     else

2177:                     {

2178:                        C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd] += 2;

2179:                     }

2180:                  }

2181:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

2182:                  {

2183:                     i3 = S_ext_diag_j[jj2];

2184:                     if (i3 != ic)

2185:                     {

2186:                        if (S_marker[i3] < jj_row_begin_diag)

2187:                        {

2188:                           S_marker[i3] = jj_count_diag;

2189:                           C_temp_diag_j[jj_count_diag - jj_row_begin_diag] = i3;

2190:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

2191:                           jj_count_diag++;

2192:                        }

2193:                        else

2194:                        {

2195:                           C_temp_diag_data[S_marker[i3] - jj_row_begin_diag]++;

2196:                        }

2197:                     }

2198:                  }

2199:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

2200:                  {

2201:                     i3 = S_ext_offd_j[jj2];

2202:                     if (S_marker_offd[i3] < jj_row_begin_offd)

2203:                     {

2204:                        S_marker_offd[i3] = jj_count_offd;

2205:                        C_temp_offd_j[jj_count_offd - jj_row_begin_offd] = i3;

2206:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

2207:                        jj_count_offd++;

2208:                     }

2209:                     else

2210:                     {

2211:                        C_temp_offd_data[S_marker_offd[i3] - jj_row_begin_offd]++;

2212:                     }

2213:                  }

2214:              }

2215:

2216:              for (jj1 = jj_row_begin_diag; jj1 < jj_count_diag; jj1++)

2217:              {

2218:                  if (C_temp_diag_data[jj1 - jj_row_begin_diag] >= num_paths)

2219:                  {

2220:                     C_diag_j[num_nonzeros_diag++] = C_temp_diag_j[jj1 - jj_row_begin_diag];

2221:                  }

2222:                  C_temp_diag_data[jj1 - jj_row_begin_diag] = 0;

2223:              }

2224:              for (jj1 = jj_row_begin_offd; jj1 < jj_count_offd; jj1++)

2225:              {

2226:                  if (C_temp_offd_data[jj1 - jj_row_begin_offd] >= num_paths)

2227:                  {

2228:                     C_offd_j[num_nonzeros_offd++] = C_temp_offd_j[jj1 - jj_row_begin_offd];

2229:                  }

2230:                  C_temp_offd_data[jj1 - jj_row_begin_offd] = 0;

0x4699d0 SUB	SP, SP, #384

0x4699d4 STP	X29, X30, [SP, #288]

0x4699d8 STP	X28, X27, [SP, #304]

0x4699dc STP	X26, X25, [SP, #320]

0x4699e0 STP	X24, X23, [SP, #336]

0x4699e4 STP	X22, X21, [SP, #352]

0x4699e8 STP	X20, X19, [SP, #368]

0x4699ec ADD	X29, SP, #288

0x4699f0 LDP	X27, X22, [X29, #112]

0x4699f4 ORR	X21, XZR, X7

0x4699f8 ORR	X24, XZR, X6

0x4699fc ORR	X20, XZR, X5

0x469a00 ORR	X25, XZR, X4

0x469a04 ORR	X19, XZR, X3

0x469a08 ORR	X26, XZR, X2

0x469a0c STR	X0, [SP, #32]

0x469a10 BL	4acc50

0x469a14 LDR	X2, [X26]

0x469a18 ORR	X28, XZR, X0

0x469a1c SUB	X0, X29, #16

0x469a20 SUB	X1, X29, #24

0x469a24 BL	4acc70

0x469a28 LDR	X10, [X20]

0x469a2c LDR	X8, [X19]

0x469a30 LDR	X9, [X21]

0x469a34 ORR	X15, XZR, X20

0x469a38 MUL	X11, X10, X28

0x469a3c CMP	X8, #1

0x469a40 STUR	X21, [X29, #400]

0x469a44 B.LE	469a74

0x469a48 LDP	X13, X8, [X29, #96]

0x469a4c LDR	X12, [X25]

0x469a50 ADD	X26, X12, X11,LSL #3

0x469a54 LDR	X14, [X24]

0x469a58 LDR	X13, [X13]

0x469a5c LDR	X8, [X8]

0x469a60 MUL	X12, X9, X28

0x469a64 ADD	X23, X14, X12,LSL #3

0x469a68 ADD	X20, X13, X11,LSL #3

0x469a6c ADD	X21, X8, X12,LSL #3

0x469a70 B	469a88

0x469a74 ORR	X21, XZR, XZR

0x469a78 ORR	X20, XZR, XZR

0x469a7c ORR	X23, XZR, XZR

0x469a80 ORR	X26, XZR, XZR

0x469a84 MUL	X12, X9, X28

0x469a88 LDR	X13, [X27]

0x469a8c LDR	X14, [X29, #144]

0x469a90 LDR	X8, [X29, #128]

0x469a94 ADD	X13, X13, X11,LSL #3

0x469a98 LDR	X11, [X22]

0x469a9c CMP	X10, #0

0x469aa0 CSEL	X24, XZR, X13, #0

0x469aa4 ADD	X12, X11, X12,LSL #3

0x469aa8 CMP	X9, #0

0x469aac CSEL	X25, XZR, X12, #0

0x469ab0 CMP	X10, #1

0x469ab4 B.LT	469ae0

0x469ab8 LDUR	X27, [X29, #400]

0x469abc MOVN	X10, #0

0x469ac0 ORR	X9, XZR, XZR

(2137) 0x469ac4 STR	X10, [X13, X9,LSL #3]

(2137) 0x469ac8 ADD	X9, X9, #1

(2137) 0x469acc LDR	X11, [X15]

(2137) 0x469ad0 CMP	X9, X11

(2137) 0x469ad4 B.LT	469ac4

0x469ad8 LDR	X9, [X27]

0x469adc B	469ae4

0x469ae0 LDUR	X27, [X29, #400]

0x469ae4 LDR	X10, [X29, #256]

0x469ae8 CMP	X9, #1

0x469aec LDR	X9, [X29, #136]

0x469af0 STP	X10, X15, [SP, #80]

0x469af4 LDP	X10, X11, [X29, #240]

0x469af8 STR	X9, [SP, #96]

0x469afc STUR	X11, [X29, #384]

0x469b00 STR	X10, [SP, #72]

0x469b04 LDP	X10, X11, [X29, #224]

0x469b08 STUR	X11, [X29, #376]

0x469b0c STR	X10, [SP, #64]

0x469b10 LDP	X9, X11, [X29, #208]

0x469b14 STUR	X11, [X29, #464]

0x469b18 LDP	X10, X11, [X29, #192]

0x469b1c STP	X11, X9, [X29, #920]

0x469b20 STR	X10, [SP, #56]

0x469b24 LDP	X10, X11, [X29, #176]

0x469b28 STR	X10, [SP, #112]

0x469b2c LDR	X10, [X29, #168]

0x469b30 STUR	X11, [X29, #456]

0x469b34 STR	X10, [SP, #48]

0x469b38 LDR	X10, [X29, #160]

0x469b3c STR	X10, [SP, #40]

0x469b40 LDR	X10, [X29, #152]

0x469b44 STR	X10, [SP, #120]

0x469b48 B.LT	469b74

0x469b4c MOVN	X10, #0

0x469b50 ORR	X9, XZR, XZR

0x469b54 HINT	#0

0x469b58 HINT	#0

0x469b5c HINT	#0

(2136) 0x469b60 STR	X10, [X12, X9,LSL #3]

(2136) 0x469b64 ADD	X9, X9, #1

(2136) 0x469b68 LDR	X11, [X27]

(2136) 0x469b6c CMP	X9, X11

(2136) 0x469b70 B.LT	469b60

0x469b74 LDR	X8, [X8]

0x469b78 STP	XZR, XZR, [X29, #984]

0x469b7c ADD	X9, X28, #1

0x469b80 LDR	X10, [X14]

0x469b84 STR	X14, [SP, #104]

0x469b88 LDR	X22, [X8, X28,LSL #3]

0x469b8c STR	X9, [SP, #8]

0x469b90 LDR	X9, [X8, X9,LSL #3]

0x469b94 LDR	X8, [X19]

0x469b98 STUR	X10, [X29, #392]

0x469b9c STP	X13, X12, [SP, #16]

0x469ba0 CMP	X8, #1

0x469ba4 STP	X9, X19, [X29, #936]

0x469ba8 B.NE	469ea0

0x469bac CMP	X22, X9

0x469bb0 B.GE	46a410

0x469bb4 LDR	X8, [SP, #96]

0x469bb8 ORR	X18, XZR, X22

0x469bbc LDR	X8, [X8]

0x469bc0 STUR	X8, [X29, #440]

0x469bc4 LDR	X8, [SP, #120]

0x469bc8 LDR	X8, [X8]

0x469bcc STR	X8, [SP, #144]

0x469bd0 LDP	X9, X8, [SP, #40]

0x469bd4 LDR	X12, [X8]

0x469bd8 LDR	X8, [SP, #112]

0x469bdc LDR	X11, [X9]

0x469be0 LDR	X13, [X8]

0x469be4 LDR	X8, [SP, #56]

0x469be8 LDR	X14, [X8]

0x469bec LDP	X9, X8, [X29, #920]

0x469bf0 LDR	X15, [X9]

0x469bf4 LDR	X16, [X8]

0x469bf8 LDP	X9, X8, [SP, #64]

0x469bfc LDR	X17, [X9]

0x469c00 LDR	X0, [X8]

0x469c04 B	469c1c

  (2129) 0x469c08 LDUR	X8, [X29, #424]

  (2129) 0x469c0c LDUR	X27, [X29, #400]

  (2129) 0x469c10 ADD	X18, X18, #1

  (2129) 0x469c14 CMP	X18, X8

  (2129) 0x469c18 B.EQ	46a410

  (2129) 0x469c1c LDUR	X8, [X29, #440]

  (2129) 0x469c20 LDP	X2, X1, [X29, #984]

  (2129) 0x469c24 LDR	X10, [X8, X18,LSL #3]

  (2129) 0x469c28 LDUR	X8, [X29, #392]

  (2129) 0x469c2c STR	X1, [X8, X18,LSL #3]

  (2129) 0x469c30 LDR	X8, [X27]

  (2129) 0x469c34 CBZ	X8, 469c44

  (2129) 0x469c38 LDUR	X8, [X29, #472]

  (2129) 0x469c3c LDR	X9, [SP, #144]

  (2129) 0x469c40 STR	X8, [X9, X18,LSL #3]

  (2129) 0x469c44 ADD	X3, X10, #1

  (2129) 0x469c48 LDR	X4, [X11, X10,LSL #3]

  (2129) 0x469c4c STUR	X10, [X29, #448]

  (2129) 0x469c50 LDR	X8, [X11, X3,LSL #3]

  (2129) 0x469c54 CMP	X4, X8

  (2129) 0x469c58 B.GE	469d8c

  (2129) 0x469c5c LDUR	X8, [X29, #456]

  (2129) 0x469c60 LDR	X5, [X8]

  (2129) 0x469c64 LDP	X9, X8, [X29, #920]

  (2129) 0x469c68 LDR	X6, [X9]

  (2129) 0x469c6c LDR	X7, [X8]

  (2129) 0x469c70 B	469c90

0x469c74 HINT	#0

0x469c78 HINT	#0

0x469c7c HINT	#0

    (2132) 0x469c80 LDR	X8, [X11, X3,LSL #3]

    (2132) 0x469c84 ADD	X4, X4, #1

    (2132) 0x469c88 CMP	X4, X8

    (2132) 0x469c8c B.GE	469d8c

    (2132) 0x469c90 LDR	X27, [X12, X4,LSL #3]

    (2132) 0x469c94 LDR	X8, [X13, X27,LSL #3]

    (2132) 0x469c98 CMP	X8, #1

    (2132) 0x469c9c B.LT	469cc0

    (2132) 0x469ca0 LDR	X8, [X5, X27,LSL #3]

    (2132) 0x469ca4 LDR	X9, [X24, X8,LSL #3]

    (2132) 0x469ca8 CMP	X9, X1

    (2132) 0x469cac B.GE	469cc0

    (2132) 0x469cb0 LDUR	X9, [X29, #480]

    (2132) 0x469cb4 STR	X9, [X24, X8,LSL #3]

    (2132) 0x469cb8 ADD	X8, X9, #1

    (2132) 0x469cbc STUR	X8, [X29, #480]

    (2132) 0x469cc0 ADD	X28, X27, #1

    (2132) 0x469cc4 LDR	X30, [X11, X27,LSL #3]

    (2132) 0x469cc8 LDR	X10, [X11, X28,LSL #3]

    (2132) 0x469ccc CMP	X30, X10

    (2132) 0x469cd0 B.GE	469d2c

    (2132) 0x469cd4 LDUR	X8, [X29, #456]

    (2132) 0x469cd8 LDR	X9, [X8]

    (2132) 0x469cdc B	469cec

      (2134) 0x469ce0 ADD	X30, X30, #1

      (2134) 0x469ce4 CMP	X30, X10

      (2134) 0x469ce8 B.GE	469d2c

      (2134) 0x469cec LDR	X8, [X12, X30,LSL #3]

      (2134) 0x469cf0 LDR	X19, [X13, X8,LSL #3]

      (2134) 0x469cf4 CMP	X19, #1

      (2134) 0x469cf8 B.LT	469ce0

      (2134) 0x469cfc LDR	X8, [X9, X8,LSL #3]

      (2134) 0x469d00 CMP	X8, X18

      (2134) 0x469d04 B.EQ	469ce0

      (2134) 0x469d08 LDR	X19, [X24, X8,LSL #3]

      (2134) 0x469d0c CMP	X19, X1

      (2134) 0x469d10 B.GE	469ce0

      (2134) 0x469d14 LDUR	X10, [X29, #480]

      (2134) 0x469d18 STR	X10, [X24, X8,LSL #3]

      (2134) 0x469d1c ADD	X8, X10, #1

      (2134) 0x469d20 STUR	X8, [X29, #480]

      (2134) 0x469d24 LDR	X10, [X11, X28,LSL #3]

      (2134) 0x469d28 B	469ce0

    (2132) 0x469d2c LDR	X27, [X14, X27,LSL #3]

    (2132) 0x469d30 LDR	X9, [X14, X28,LSL #3]

    (2132) 0x469d34 CMP	X27, X9

    (2132) 0x469d38 B.GE	469c80

    (2132) 0x469d3c LDUR	X8, [X29, #464]

    (2132) 0x469d40 LDR	X10, [X8]

    (2132) 0x469d44 B	469d54

      (2133) 0x469d48 ADD	X27, X27, #1

      (2133) 0x469d4c CMP	X27, X9

      (2133) 0x469d50 B.GE	469c80

      (2133) 0x469d54 LDR	X8, [X6, X27,LSL #3]

      (2133) 0x469d58 LDR	X19, [X7, X8,LSL #3]

      (2133) 0x469d5c CMP	X19, #1

      (2133) 0x469d60 B.LT	469d48

      (2133) 0x469d64 LDR	X8, [X10, X8,LSL #3]

      (2133) 0x469d68 LDR	X19, [X25, X8,LSL #3]

      (2133) 0x469d6c CMP	X19, X2

      (2133) 0x469d70 B.GE	469d48

      (2133) 0x469d74 LDUR	X9, [X29, #472]

      (2133) 0x469d78 STR	X9, [X25, X8,LSL #3]

      (2133) 0x469d7c ADD	X8, X9, #1

      (2133) 0x469d80 STUR	X8, [X29, #472]

      (2133) 0x469d84 LDR	X9, [X14, X28,LSL #3]

      (2133) 0x469d88 B	469d48

  (2129) 0x469d8c LDUR	X8, [X29, #448]

  (2129) 0x469d90 LDR	X9, [X14, X3,LSL #3]

  (2129) 0x469d94 LDR	X8, [X14, X8,LSL #3]

  (2129) 0x469d98 CMP	X8, X9

  (2129) 0x469d9c B.GE	469c08

(2130) 0x469da0 LDUR	X9, [X29, #464]

(2130) 0x469da4 LDR	X4, [X9]

(2130) 0x469da8 LDP	X10, X9, [X29, #888]

(2130) 0x469dac LDR	X5, [X10]

(2130) 0x469db0 LDR	X6, [X9]

(2130) 0x469db4 B	469dd0

0x469db8 HINT	#0

0x469dbc HINT	#0

(2130) 0x469dc0 LDR	X9, [X14, X3,LSL #3]

(2130) 0x469dc4 ADD	X8, X8, #1

(2130) 0x469dc8 CMP	X8, X9

(2130) 0x469dcc B.GE	469c08

(2130) 0x469dd0 LDR	X27, [X15, X8,LSL #3]

(2130) 0x469dd4 LDR	X9, [X16, X27,LSL #3]

(2130) 0x469dd8 CMP	X9, #1

(2130) 0x469ddc B.LT	469e00

(2130) 0x469de0 LDR	X9, [X4, X27,LSL #3]

(2130) 0x469de4 LDR	X10, [X25, X9,LSL #3]

(2130) 0x469de8 CMP	X10, X2

(2130) 0x469dec B.GE	469e00

(2130) 0x469df0 LDUR	X10, [X29, #472]

(2130) 0x469df4 STR	X10, [X25, X9,LSL #3]

(2130) 0x469df8 ADD	X9, X10, #1

(2130) 0x469dfc STUR	X9, [X29, #472]

(2130) 0x469e00 ADD	X7, X27, #1

(2130) 0x469e04 LDR	X9, [X17, X27,LSL #3]

(2130) 0x469e08 LDR	X10, [X17, X7,LSL #3]

(2130) 0x469e0c B	469e24

0x469e10 HINT	#0

0x469e14 HINT	#0

0x469e18 HINT	#0

0x469e1c HINT	#0

  (2131) 0x469e20 ADD	X9, X9, #1

  (2131) 0x469e24 CMP	X9, X10

  (2131) 0x469e28 B.GE	469e60

  (2131) 0x469e2c LDR	X28, [X5, X9,LSL #3]

  (2131) 0x469e30 CMP	X28, X18

  (2131) 0x469e34 B.EQ	469e20

  (2131) 0x469e38 LDR	X19, [X24, X28,LSL #3]

  (2131) 0x469e3c CMP	X19, X1

  (2131) 0x469e40 B.GE	469e20

  (2131) 0x469e44 LDUR	X10, [X29, #480]

  (2131) 0x469e48 STR	X10, [X24, X28,LSL #3]

  (2131) 0x469e4c ADD	X10, X10, #1

  (2131) 0x469e50 STUR	X10, [X29, #480]

  (2131) 0x469e54 LDR	X10, [X17, X7,LSL #3]

  (2131) 0x469e58 B	469e20

0x469e5c HINT	#0

(2130) 0x469e60 LDR	X9, [X0, X27,LSL #3]

(2130) 0x469e64 LDR	X10, [X0, X7,LSL #3]

(2130) 0x469e68 B	469e70

  (2135) 0x469e6c ADD	X9, X9, #1

  (2135) 0x469e70 CMP	X9, X10

  (2135) 0x469e74 B.GE	469dc0

  (2135) 0x469e78 LDR	X27, [X6, X9,LSL #3]

  (2135) 0x469e7c LDR	X19, [X25, X27,LSL #3]

  (2135) 0x469e80 CMP	X19, X2

  (2135) 0x469e84 B.GE	469e6c

  (2135) 0x469e88 LDUR	X10, [X29, #472]

  (2135) 0x469e8c STR	X10, [X25, X27,LSL #3]

  (2135) 0x469e90 ADD	X10, X10, #1

  (2135) 0x469e94 STUR	X10, [X29, #472]

  (2135) 0x469e98 LDR	X10, [X0, X7,LSL #3]

  (2135) 0x469e9c B	469e6c

0x469ea0 CMP	X22, X9

0x469ea4 B.GE	46a410

0x469ea8 LDR	X8, [SP, #96]

0x469eac MOVZ	W4, #1

0x469eb0 ORR	X1, XZR, XZR

0x469eb4 ORR	X3, XZR, XZR

0x469eb8 ORR	X5, XZR, X22

0x469ebc LDR	X9, [X8]

0x469ec0 LDR	X8, [SP, #120]

0x469ec4 LDR	X8, [X8]

0x469ec8 STP	X8, X9, [SP, #128]

0x469ecc LDP	X9, X8, [SP, #40]

0x469ed0 LDR	X12, [X8]

0x469ed4 LDR	X8, [SP, #112]

0x469ed8 LDR	X11, [X9]

0x469edc LDR	X13, [X8]

0x469ee0 LDR	X8, [SP, #56]

0x469ee4 LDR	X14, [X8]

0x469ee8 LDP	X10, X8, [X29, #920]

0x469eec LDR	X9, [X10]

0x469ef0 LDR	X8, [X8]

0x469ef4 STP	X8, X9, [X29, #952]

0x469ef8 LDP	X9, X8, [SP, #64]

0x469efc LDR	X2, [X9]

0x469f00 LDR	X6, [X8]

0x469f04 B	469f14

    (2119) 0x469f08 ADD	X5, X5, #1

    (2119) 0x469f0c CMP	X5, X16

    (2119) 0x469f10 B.EQ	46a410

    (2119) 0x469f14 LDR	X8, [SP, #136]

    (2119) 0x469f18 LDUR	X9, [X29, #392]

    (2119) 0x469f1c ORR	X7, XZR, X3

    (2119) 0x469f20 ORR	X30, XZR, X1

    (2119) 0x469f24 LDR	X15, [X8, X5,LSL #3]

    (2119) 0x469f28 LDUR	X8, [X29, #480]

    (2119) 0x469f2c STR	X8, [X9, X5,LSL #3]

    (2119) 0x469f30 LDR	X8, [X27]

    (2119) 0x469f34 CBZ	X8, 469f44

    (2119) 0x469f38 LDUR	X8, [X29, #472]

    (2119) 0x469f3c LDR	X9, [SP, #128]

    (2119) 0x469f40 STR	X8, [X9, X5,LSL #3]

    (2119) 0x469f44 ADD	X16, X15, #1

    (2119) 0x469f48 LDR	X10, [X11, X15,LSL #3]

    (2119) 0x469f4c STR	X15, [SP, #144]

    (2119) 0x469f50 ORR	X3, XZR, X7

    (2119) 0x469f54 ORR	X1, XZR, X30

    (2119) 0x469f58 LDR	X8, [X11, X16,LSL #3]

    (2119) 0x469f5c CMP	X10, X8

    (2119) 0x469f60 B.GE	46a0e0

    (2119) 0x469f64 LDUR	X8, [X29, #456]

    (2119) 0x469f68 ORR	X1, XZR, X30

    (2119) 0x469f6c ORR	X3, XZR, X7

    (2119) 0x469f70 LDR	X9, [X8]

    (2119) 0x469f74 LDP	X8, X15, [X29, #920]

    (2119) 0x469f78 LDR	X8, [X8]

    (2119) 0x469f7c LDR	X0, [X15]

    (2119) 0x469f80 B	469f94

      (2125) 0x469f84 LDR	X15, [X11, X16,LSL #3]

      (2125) 0x469f88 ADD	X10, X10, #1

      (2125) 0x469f8c CMP	X10, X15

      (2125) 0x469f90 B.GE	46a0e0

      (2125) 0x469f94 LDR	X27, [X12, X10,LSL #3]

      (2125) 0x469f98 LDR	X15, [X13, X27,LSL #3]

      (2125) 0x469f9c CMP	X15, #1

      (2125) 0x469fa0 B.LT	469fc8

      (2125) 0x469fa4 LDR	X15, [X9, X27,LSL #3]

      (2125) 0x469fa8 LDR	X17, [X24, X15,LSL #3]

      (2125) 0x469fac SUBS	X17, X17, X30

      (2125) 0x469fb0 B.GE	469fe0

      (2125) 0x469fb4 STR	X1, [X24, X15,LSL #3]

      (2125) 0x469fb8 SUB	X15, X1, X30

      (2125) 0x469fbc MOVZ	W17, #2

      (2125) 0x469fc0 ADD	X1, X1, #1

      (2125) 0x469fc4 STR	X17, [X20, X15,LSL #3]

      (2125) 0x469fc8 ADD	X28, X27, #1

      (2125) 0x469fcc LDR	X17, [X11, X27,LSL #3]

      (2125) 0x469fd0 LDR	X15, [X11, X28,LSL #3]

      (2125) 0x469fd4 CMP	X17, X15

      (2125) 0x469fd8 B.LT	46a000

      (2125) 0x469fdc B	46a06c

      (2125) 0x469fe0 LDR	X15, [X20, X17,LSL #3]

      (2125) 0x469fe4 ADD	X15, X15, #2

      (2125) 0x469fe8 STR	X15, [X20, X17,LSL #3]

      (2125) 0x469fec ADD	X28, X27, #1

      (2125) 0x469ff0 LDR	X17, [X11, X27,LSL #3]

      (2125) 0x469ff4 LDR	X15, [X11, X28,LSL #3]

      (2125) 0x469ff8 CMP	X17, X15

      (2125) 0x469ffc B.GE	46a06c

      (2125) 0x46a000 LDUR	X15, [X29, #456]

      (2125) 0x46a004 LDR	X15, [X15]

      (2125) 0x46a008 B	46a030

        (2127) 0x46a00c LDR	X18, [X20, X19,LSL #3]

        (2127) 0x46a010 ADD	X18, X18, #1

        (2127) 0x46a014 STR	X18, [X20, X19,LSL #3]

        (2127) 0x46a018 HINT	#0

        (2127) 0x46a01c HINT	#0

        (2127) 0x46a020 LDR	X18, [X11, X28,LSL #3]

        (2127) 0x46a024 ADD	X17, X17, #1

        (2127) 0x46a028 CMP	X17, X18

        (2127) 0x46a02c B.GE	46a06c

        (2127) 0x46a030 LDR	X18, [X12, X17,LSL #3]

        (2127) 0x46a034 LDR	X19, [X13, X18,LSL #3]

        (2127) 0x46a038 CMP	X19, #1

        (2127) 0x46a03c B.LT	46a020

        (2127) 0x46a040 LDR	X18, [X15, X18,LSL #3]

        (2127) 0x46a044 CMP	X18, X5

        (2127) 0x46a048 B.EQ	46a020

        (2127) 0x46a04c LDR	X19, [X24, X18,LSL #3]

        (2127) 0x46a050 SUBS	X19, X19, X30

        (2127) 0x46a054 B.GE	46a00c

        (2127) 0x46a058 STR	X1, [X24, X18,LSL #3]

        (2127) 0x46a05c SUB	X18, X1, X30

        (2127) 0x46a060 ADD	X1, X1, #1

        (2127) 0x46a064 STR	X4, [X20, X18,LSL #3]

        (2127) 0x46a068 B	46a020

      (2125) 0x46a06c LDR	X17, [X14, X27,LSL #3]

      (2125) 0x46a070 LDR	X15, [X14, X28,LSL #3]

      (2125) 0x46a074 CMP	X17, X15

      (2125) 0x46a078 B.GE	469f84

      (2125) 0x46a07c LDUR	X15, [X29, #464]

      (2125) 0x46a080 LDR	X15, [X15]

      (2125) 0x46a084 B	46a0a4

        (2126) 0x46a088 LDR	X18, [X21, X19,LSL #3]

        (2126) 0x46a08c ADD	X18, X18, #1

        (2126) 0x46a090 STR	X18, [X21, X19,LSL #3]

        (2126) 0x46a094 LDR	X18, [X14, X28,LSL #3]

        (2126) 0x46a098 ADD	X17, X17, #1

        (2126) 0x46a09c CMP	X17, X18

        (2126) 0x46a0a0 B.GE	469f84

        (2126) 0x46a0a4 LDR	X18, [X8, X17,LSL #3]

        (2126) 0x46a0a8 LDR	X19, [X0, X18,LSL #3]

        (2126) 0x46a0ac CMP	X19, #1

        (2126) 0x46a0b0 B.LT	46a094

        (2126) 0x46a0b4 LDR	X18, [X15, X18,LSL #3]

        (2126) 0x46a0b8 LDR	X19, [X25, X18,LSL #3]

        (2126) 0x46a0bc SUBS	X19, X19, X7

        (2126) 0x46a0c0 B.GE	46a088

        (2126) 0x46a0c4 STR	X3, [X25, X18,LSL #3]

        (2126) 0x46a0c8 SUB	X18, X3, X7

        (2126) 0x46a0cc ADD	X3, X3, #1

        (2126) 0x46a0d0 STR	X4, [X21, X18,LSL #3]

        (2126) 0x46a0d4 B	46a094

0x46a0d8 HINT	#0

0x46a0dc HINT	#0

    (2119) 0x46a0e0 LDR	X8, [SP, #144]

    (2119) 0x46a0e4 LDR	X9, [X14, X16,LSL #3]

    (2119) 0x46a0e8 LDR	X8, [X14, X8,LSL #3]

    (2119) 0x46a0ec CMP	X8, X9

    (2119) 0x46a0f0 B.GE	46a260

    (2119) 0x46a0f4 LDUR	X9, [X29, #464]

    (2119) 0x46a0f8 LDP	X10, X15, [X29, #888]

    (2119) 0x46a0fc LDR	X9, [X9]

    (2119) 0x46a100 LDR	X10, [X10]

    (2119) 0x46a104 LDR	X17, [X15]

    (2119) 0x46a108 B	46a11c

      (2122) 0x46a10c LDR	X15, [X14, X16,LSL #3]

      (2122) 0x46a110 ADD	X8, X8, #1

      (2122) 0x46a114 CMP	X8, X15

      (2122) 0x46a118 B.GE	46a260

      (2122) 0x46a11c LDUR	X15, [X29, #448]

      (2122) 0x46a120 LDR	X27, [X15, X8,LSL #3]

      (2122) 0x46a124 LDUR	X15, [X29, #440]

      (2122) 0x46a128 LDR	X15, [X15, X27,LSL #3]

      (2122) 0x46a12c CMP	X15, #1

      (2122) 0x46a130 B.LT	46a158

      (2122) 0x46a134 LDR	X15, [X9, X27,LSL #3]

      (2122) 0x46a138 LDR	X18, [X25, X15,LSL #3]

      (2122) 0x46a13c SUBS	X18, X18, X7

      (2122) 0x46a140 B.GE	46a180

      (2122) 0x46a144 STR	X3, [X25, X15,LSL #3]

      (2122) 0x46a148 SUB	X15, X3, X7

      (2122) 0x46a14c MOVZ	W18, #2

      (2122) 0x46a150 ADD	X3, X3, #1

      (2122) 0x46a154 STR	X18, [X21, X15,LSL #3]

      (2122) 0x46a158 LDR	X15, [X2, X27,LSL #3]

      (2122) 0x46a15c ADD	X0, X27, #1

      (2122) 0x46a160 LDR	X18, [X2, X0,LSL #3]

      (2122) 0x46a164 CMP	X15, X18

      (2122) 0x46a168 B.LT	46a1c0

      (2122) 0x46a16c B	46a1f8

0x46a170 HINT	#0

0x46a174 HINT	#0

0x46a178 HINT	#0

0x46a17c HINT	#0

      (2122) 0x46a180 LDR	X15, [X21, X18,LSL #3]

      (2122) 0x46a184 ADD	X15, X15, #2

      (2122) 0x46a188 STR	X15, [X21, X18,LSL #3]

      (2122) 0x46a18c LDR	X15, [X2, X27,LSL #3]

      (2122) 0x46a190 ADD	X0, X27, #1

      (2122) 0x46a194 LDR	X18, [X2, X0,LSL #3]

      (2122) 0x46a198 CMP	X15, X18

      (2122) 0x46a19c B.LT	46a1c0

      (2122) 0x46a1a0 B	46a1f8

        (2124) 0x46a1a4 LDR	X18, [X20, X19,LSL #3]

        (2124) 0x46a1a8 ADD	X18, X18, #1

        (2124) 0x46a1ac STR	X18, [X20, X19,LSL #3]

        (2124) 0x46a1b0 ADD	X15, X15, #1

        (2124) 0x46a1b4 LDR	X18, [X2, X0,LSL #3]

        (2124) 0x46a1b8 CMP	X15, X18

        (2124) 0x46a1bc B.GE	46a1f8

        (2124) 0x46a1c0 LDR	X18, [X10, X15,LSL #3]

        (2124) 0x46a1c4 CMP	X18, X5

        (2124) 0x46a1c8 B.EQ	46a1b0

        (2124) 0x46a1cc LDR	X19, [X24, X18,LSL #3]

        (2124) 0x46a1d0 SUBS	X19, X19, X30

        (2124) 0x46a1d4 B.GE	46a1a4

        (2124) 0x46a1d8 STR	X1, [X24, X18,LSL #3]

        (2124) 0x46a1dc SUB	X18, X1, X30

        (2124) 0x46a1e0 ADD	X1, X1, #1

        (2124) 0x46a1e4 ADD	X15, X15, #1

        (2124) 0x46a1e8 STR	X4, [X20, X18,LSL #3]

        (2124) 0x46a1ec LDR	X18, [X2, X0,LSL #3]

        (2124) 0x46a1f0 CMP	X15, X18

        (2124) 0x46a1f4 B.LT	46a1c0

      (2122) 0x46a1f8 LDR	X15, [X6, X27,LSL #3]

      (2122) 0x46a1fc LDR	X18, [X6, X0,LSL #3]

      (2122) 0x46a200 CMP	X15, X18

      (2122) 0x46a204 B.LT	46a22c

      (2122) 0x46a208 B	46a10c

        (2123) 0x46a20c STR	X3, [X25, X18,LSL #3]

        (2123) 0x46a210 SUB	X18, X3, X7

        (2123) 0x46a214 ADD	X3, X3, #1

        (2123) 0x46a218 ADD	X15, X15, #1

        (2123) 0x46a21c STR	X4, [X21, X18,LSL #3]

        (2123) 0x46a220 LDR	X18, [X6, X0,LSL #3]

        (2123) 0x46a224 CMP	X15, X18

        (2123) 0x46a228 B.GE	46a10c

        (2123) 0x46a22c LDR	X18, [X17, X15,LSL #3]

        (2123) 0x46a230 LDR	X19, [X25, X18,LSL #3]

        (2123) 0x46a234 SUBS	X19, X19, X7

        (2123) 0x46a238 B.LT	46a20c

        (2123) 0x46a23c LDR	X18, [X21, X19,LSL #3]

        (2123) 0x46a240 ADD	X15, X15, #1

        (2123) 0x46a244 ADD	X18, X18, #1

        (2123) 0x46a248 STR	X18, [X21, X19,LSL #3]

        (2123) 0x46a24c LDR	X18, [X6, X0,LSL #3]

        (2123) 0x46a250 CMP	X15, X18

        (2123) 0x46a254 B.LT	46a22c

      (2122) 0x46a258 B	46a10c

0x46a25c HINT	#0

    (2119) 0x46a260 LDUR	X16, [X29, #424]

    (2119) 0x46a264 LDUR	X27, [X29, #400]

    (2119) 0x46a268 CMP	X1, X30

    (2119) 0x46a26c B.LE	46a2b0

    (2119) 0x46a270 SUB	W8, W1, W30

    (2119) 0x46a274 ORR	X9, XZR, X30

    (2119) 0x46a278 TBZ	W8, #0, 46a2a4

    (2119) 0x46a27c LDUR	X9, [X29, #432]

    (2119) 0x46a280 LDR	X8, [X20]

    (2119) 0x46a284 LDR	X9, [X9]

    (2119) 0x46a288 CMP	X8, X9

    (2119) 0x46a28c B.LT	46a29c

    (2119) 0x46a290 LDUR	X8, [X29, #480]

    (2119) 0x46a294 ADD	X8, X8, #1

    (2119) 0x46a298 STUR	X8, [X29, #480]

    (2119) 0x46a29c ADD	X9, X30, #1

    (2119) 0x46a2a0 STR	XZR, [X20]

    (2119) 0x46a2a4 ADD	X8, X30, #1

    (2119) 0x46a2a8 CMP	X1, X8

    (2119) 0x46a2ac B.NE	46a380

    (2119) 0x46a2b0 LDUR	X17, [X29, #432]

    (2119) 0x46a2b4 CMP	X3, X7

    (2119) 0x46a2b8 B.LE	469f08

    (2119) 0x46a2bc SUB	W8, W3, W7

    (2119) 0x46a2c0 ORR	X9, XZR, X7

    (2119) 0x46a2c4 TBZ	W8, #0, 46a2ec

    (2119) 0x46a2c8 LDR	X8, [X21]

    (2119) 0x46a2cc LDR	X9, [X17]

    (2119) 0x46a2d0 CMP	X8, X9

    (2119) 0x46a2d4 B.LT	46a2e4

    (2119) 0x46a2d8 LDUR	X8, [X29, #472]

    (2119) 0x46a2dc ADD	X8, X8, #1

    (2119) 0x46a2e0 STUR	X8, [X29, #472]

    (2119) 0x46a2e4 ADD	X9, X7, #1

    (2119) 0x46a2e8 STR	XZR, [X21]

    (2119) 0x46a2ec ADD	X8, X7, #1

    (2119) 0x46a2f0 CMP	X3, X8

    (2119) 0x46a2f4 B.EQ	469f08

    (2119) 0x46a2f8 ADD	X10, X21, #8

    (2119) 0x46a2fc SUB	X8, X3, X9

    (2119) 0x46a300 SUB	X10, X10, X7,LSL #3

    (2119) 0x46a304 ADD	X9, X10, X9,LSL #3

    (2119) 0x46a308 B	46a318

      (2128) 0x46a30c STR	XZR, [X9], #16

      (2128) 0x46a310 SUBS	X8, X8, #2

      (2128) 0x46a314 B.EQ	469f08

      (2128) 0x46a318 LDUR	X10, [X9, #504]

      (2128) 0x46a31c LDR	X15, [X17]

      (2128) 0x46a320 CMP	X10, X15

      (2128) 0x46a324 B.GE	46a340

      (2128) 0x46a328 STUR	XZR, [X9, #504]

      (2128) 0x46a32c LDR	X10, [X9]

      (2128) 0x46a330 LDR	X15, [X17]

      (2128) 0x46a334 CMP	X10, X15

      (2128) 0x46a338 B.LT	46a30c

      (2128) 0x46a33c B	46a360

      (2128) 0x46a340 LDUR	X10, [X29, #472]

      (2128) 0x46a344 ADD	X10, X10, #1

      (2128) 0x46a348 STUR	X10, [X29, #472]

      (2128) 0x46a34c STUR	XZR, [X9, #504]

      (2128) 0x46a350 LDR	X10, [X9]

      (2128) 0x46a354 LDR	X15, [X17]

      (2128) 0x46a358 CMP	X10, X15

      (2128) 0x46a35c B.LT	46a30c

      (2128) 0x46a360 LDUR	X10, [X29, #472]

      (2128) 0x46a364 ADD	X10, X10, #1

      (2128) 0x46a368 STUR	X10, [X29, #472]

      (2128) 0x46a36c B	46a30c

0x46a370 HINT	#0

0x46a374 HINT	#0

0x46a378 HINT	#0

0x46a37c HINT	#0

  (2121) 0x46a380 ADD	X10, X20, #8

  (2121) 0x46a384 SUB	X8, X1, X9

  (2121) 0x46a388 SUB	X10, X10, X30,LSL #3

  (2121) 0x46a38c ADD	X9, X10, X9,LSL #3

  (2121) 0x46a390 B	46a3ac

0x46a394 HINT	#0

0x46a398 HINT	#0

0x46a39c HINT	#0

  (2121) 0x46a3a0 STR	XZR, [X9], #16

  (2121) 0x46a3a4 SUBS	X8, X8, #2

  (2121) 0x46a3a8 B.EQ	46a2b0

  (2121) 0x46a3ac LDUR	X17, [X29, #432]

  (2121) 0x46a3b0 LDUR	X10, [X9, #504]

  (2121) 0x46a3b4 LDR	X15, [X17]

  (2121) 0x46a3b8 CMP	X10, X15

  (2121) 0x46a3bc B.GE	46a3e0

  (2121) 0x46a3c0 STUR	XZR, [X9, #504]

  (2121) 0x46a3c4 LDR	X10, [X9]

  (2121) 0x46a3c8 LDR	X15, [X17]

  (2121) 0x46a3cc CMP	X10, X15

  (2121) 0x46a3d0 B.LT	46a3a0

  (2121) 0x46a3d4 B	46a400

0x46a3d8 HINT	#0

0x46a3dc HINT	#0

(2120) 0x46a3e0 LDUR	X10, [X29, #480]

(2120) 0x46a3e4 ADD	X10, X10, #1

(2120) 0x46a3e8 STUR	X10, [X29, #480]

(2120) 0x46a3ec STUR	XZR, [X9, #504]

(2120) 0x46a3f0 LDR	X10, [X9]

(2120) 0x46a3f4 LDR	X15, [X17]

(2120) 0x46a3f8 CMP	X10, X15

(2120) 0x46a3fc B.LT	46a3a0

  (2121) 0x46a400 LDUR	X10, [X29, #480]

  (2121) 0x46a404 ADD	X10, X10, #1

  (2121) 0x46a408 STUR	X10, [X29, #480]

  (2121) 0x46a40c B	46a3a0

0x46a410 LDP	X10, X19, [SP, #80]

0x46a414 LDR	X9, [SP, #120]

0x46a418 SUB	X0, X29, #32

0x46a41c SUB	X2, X29, #40

0x46a420 LDR	X8, [X19]

0x46a424 LDR	X9, [X9]

0x46a428 LDR	X4, [X10]

0x46a42c LDUR	X10, [X29, #392]

0x46a430 ADD	X1, X10, X8,LSL #3

0x46a434 ADD	X3, X9, X8,LSL #3

0x46a438 BL	4ad890

0x46a43c LDR	X8, [X19]

0x46a440 LDR	X12, [SP, #16]

0x46a444 CMP	X8, #1

0x46a448 B.LT	46a474

0x46a44c MOVN	X9, #0

0x46a450 ORR	X11, XZR, X19

0x46a454 ORR	X8, XZR, XZR

0x46a458 HINT	#0

0x46a45c HINT	#0

(2118) 0x46a460 STR	X9, [X12, X8,LSL #3]

(2118) 0x46a464 ADD	X8, X8, #1

(2118) 0x46a468 LDR	X10, [X11]

(2118) 0x46a46c CMP	X8, X10

(2118) 0x46a470 B.LT	46a460

0x46a474 LDP	X8, X9, [X29, #264]

0x46a478 LDR	X11, [SP, #24]

0x46a47c STUR	X8, [X29, #448]

0x46a480 LDR	X8, [X27]

0x46a484 STUR	X9, [X29, #392]

0x46a488 CMP	X8, #1

0x46a48c B.LT	46a4b4

0x46a490 MOVN	X9, #0

0x46a494 ORR	X8, XZR, XZR

0x46a498 HINT	#0

0x46a49c HINT	#0

(2117) 0x46a4a0 STR	X9, [X11, X8,LSL #3]

(2117) 0x46a4a4 ADD	X8, X8, #1

(2117) 0x46a4a8 LDR	X10, [X27]

(2117) 0x46a4ac CMP	X8, X10

(2117) 0x46a4b0 B.LT	46a4a0

0x46a4b4 LDR	X8, [SP, #32]

0x46a4b8 ADRP	X0,

0x46a4bc ADD	X0, X0, #912

0x46a4c0 LDR	W27, [X8]

0x46a4c4 ORR	W1, WZR, W27

0x46a4c8 BL	4104c0

0x46a4cc ADRP	X0,

0x46a4d0 ADD	X0, X0, #936

0x46a4d4 ORR	W1, WZR, W27

0x46a4d8 BL	410280

0x46a4dc CBZ	W0, 46a540

0x46a4e0 LDR	X8, [SP, #104]

0x46a4e4 LDR	X10, [SP, #88]

0x46a4e8 LDR	X9, [X8]

0x46a4ec LDR	X8, [X10]

0x46a4f0 LDR	X9, [X9, X8,LSL #3]

0x46a4f4 CBZ	X9, 46a510

0x46a4f8 UBFM	X0, X9, #61, #60

0x46a4fc ORR	X19, XZR, X10

0x46a500 BL	4aae90

0x46a504 LDUR	X8, [X29, #448]

0x46a508 STR	X0, [X8]

0x46a50c LDR	X8, [X19]

0x46a510 LDR	X9, [SP, #120]

0x46a514 LDR	X9, [X9]

0x46a518 LDR	X8, [X9, X8,LSL #3]

0x46a51c CBZ	X8, 46a530

0x46a520 UBFM	X0, X8, #61, #60

0x46a524 BL	4aae90

0x46a528 LDUR	X8, [X29, #392]

0x46a52c STR	X0, [X8]

0x46a530 ADRP	X0,

0x46a534 ADD	X0, X0, #936

0x46a538 ORR	W1, WZR, W27

0x46a53c BL	410500

0x46a540 ADRP	X0,

0x46a544 ADD	X0, X0, #960

0x46a548 ORR	W1, WZR, W27

0x46a54c BL	4104c0

0x46a550 LDP	X17, X18, [X29, #936]

0x46a554 LDR	X0, [SP, #104]

0x46a558 SUB	X8, X17, #1

0x46a55c LDUR	X30, [X29, #392]

0x46a560 CMP	X22, X8

0x46a564 ORR	X8, XZR, X22

0x46a568 B.GE	46a5f8

0x46a56c LDP	X8, X9, [SP, #112]

0x46a570 LDR	X10, [SP, #96]

0x46a574 MOVZ	W13, #2

0x46a578 LDR	X12, [X0]

0x46a57c ADD	X12, X12, X22,LSL #3

0x46a580 LDR	X11, [X9]

0x46a584 LDR	X10, [X10]

0x46a588 LDR	X8, [X8]

0x46a58c ORN	X9, XZR, X22

0x46a590 ADD	X9, X9, X17

0x46a594 ADD	X10, X10, X22,LSL #3

0x46a598 ADD	X11, X11, X22,LSL #3

0x46a59c B	46a5c8

(2116) 0x46a5a0 LDUR	X15, [X29, #480]

(2116) 0x46a5a4 SUBS	X9, X9, #1

(2116) 0x46a5a8 ADD	X10, X10, #8

(2116) 0x46a5ac ADD	X14, X14, X15

(2116) 0x46a5b0 STR	X14, [X12], #8

(2116) 0x46a5b4 LDUR	X14, [X29, #472]

(2116) 0x46a5b8 LDR	X15, [X11]

(2116) 0x46a5bc ADD	X14, X15, X14

(2116) 0x46a5c0 STR	X14, [X11], #8

(2116) 0x46a5c4 B.EQ	46a5f4

(2116) 0x46a5c8 LDP	X14, X15, [X12]

(2116) 0x46a5cc CMP	X15, X14

(2116) 0x46a5d0 B.NE	46a5a0

(2116) 0x46a5d4 LDP	X16, X14, [X11]

(2116) 0x46a5d8 CMP	X14, X16

(2116) 0x46a5dc ORR	X14, XZR, X15

(2116) 0x46a5e0 B.NE	46a5a0

(2116) 0x46a5e4 LDR	X14, [X10]

(2116) 0x46a5e8 STR	X13, [X8, X14,LSL #3]

(2116) 0x46a5ec LDR	X14, [X12]

(2116) 0x46a5f0 B	46a5a0

0x46a5f4 SUB	X8, X17, #1

0x46a5f8 CMP	X22, X17

0x46a5fc B.GE	46af40

0x46a600 LDR	X11, [X0]

0x46a604 LDUR	X9, [X29, #480]

0x46a608 LDR	X10, [X11, X8,LSL #3]

0x46a60c ADD	X9, X10, X9

0x46a610 LDR	X10, [SP, #120]

0x46a614 STR	X9, [X11, X8,LSL #3]

0x46a618 LDUR	X9, [X29, #472]

0x46a61c LDR	X10, [X10]

0x46a620 LDR	X12, [X10, X8,LSL #3]

0x46a624 ADD	X9, X12, X9

0x46a628 LDR	X12, [SP, #8]

0x46a62c STR	X9, [X10, X8,LSL #3]

0x46a630 LDR	X10, [SP, #80]

0x46a634 LDR	X11, [X11, X8,LSL #3]

0x46a638 LDR	X10, [X10]

0x46a63c ADD	X10, X10, X12,LSL #4

0x46a640 LDR	X12, [X10]

0x46a644 CMP	X12, X11

0x46a648 B.NE	46a674

0x46a64c LDR	X10, [X10, #8]

0x46a650 CMP	X10, X9

0x46a654 B.NE	46a674

0x46a658 LDR	X10, [SP, #96]

0x46a65c LDR	X9, [SP, #112]

0x46a660 LDR	X10, [X10]

0x46a664 LDR	X9, [X9]

0x46a668 LDR	X8, [X10, X8,LSL #3]

0x46a66c MOVZ	W10, #2

0x46a670 STR	X10, [X9, X8,LSL #3]

0x46a674 LDR	X8, [X18]

0x46a678 CMP	X8, #1

0x46a67c B.NE	46a980

0x46a680 LDR	X8, [SP, #96]

0x46a684 LDP	X9, X10, [SP, #40]

0x46a688 LDR	X11, [SP, #112]

0x46a68c LDR	X16, [SP, #72]

0x46a690 LDR	X8, [X8]

0x46a694 LDP	X12, X15, [SP, #56]

0x46a698 LDP	X13, X14, [X29, #920]

0x46a69c LDR	X9, [X9]

0x46a6a0 LDR	X10, [X10]

0x46a6a4 LDR	X11, [X11]

0x46a6a8 LDR	X12, [X12]

0x46a6ac LDR	X13, [X13]

0x46a6b0 LDR	X14, [X14]

0x46a6b4 LDR	X15, [X15]

0x46a6b8 LDR	X16, [X16]

0x46a6bc B	46a6d0

  (2109) 0x46a6c0 LDUR	X17, [X29, #424]

  (2109) 0x46a6c4 ADD	X22, X22, #1

  (2109) 0x46a6c8 CMP	X22, X17

  (2109) 0x46a6cc B.EQ	46af40

  (2109) 0x46a6d0 LDR	X1, [X8, X22,LSL #3]

  (2109) 0x46a6d4 LDP	X18, X17, [X29, #984]

  (2109) 0x46a6d8 ADD	X0, X1, #1

  (2109) 0x46a6dc LDR	X2, [X9, X1,LSL #3]

  (2109) 0x46a6e0 LDR	X3, [X9, X0,LSL #3]

  (2109) 0x46a6e4 CMP	X2, X3

  (2109) 0x46a6e8 B.GE	46a84c

  (2109) 0x46a6ec LDP	X4, X3, [X29, #960]

  (2109) 0x46a6f0 LDP	X5, X6, [X29, #920]

  (2109) 0x46a6f4 LDR	X3, [X3]

  (2109) 0x46a6f8 LDR	X4, [X4]

  (2109) 0x46a6fc LDR	X5, [X5]

  (2109) 0x46a700 LDR	X6, [X6]

  (2109) 0x46a704 B	46a718

    (2113) 0x46a708 LDR	X7, [X9, X0,LSL #3]

    (2113) 0x46a70c ADD	X2, X2, #1

    (2113) 0x46a710 CMP	X2, X7

    (2113) 0x46a714 B.GE	46a84c

    (2113) 0x46a718 LDR	X19, [X10, X2,LSL #3]

    (2113) 0x46a71c LDR	X7, [X11, X19,LSL #3]

    (2113) 0x46a720 CMP	X7, #1

    (2113) 0x46a724 B.LT	46a750

    (2113) 0x46a728 LDR	X7, [X3, X19,LSL #3]

    (2113) 0x46a72c LDR	X20, [X24, X7,LSL #3]

    (2113) 0x46a730 CMP	X20, X17

    (2113) 0x46a734 B.GE	46a750

    (2113) 0x46a738 LDUR	X20, [X29, #480]

    (2113) 0x46a73c STR	X20, [X24, X7,LSL #3]

    (2113) 0x46a740 STR	X7, [X4, X20,LSL #3]

    (2113) 0x46a744 LDUR	X7, [X29, #480]

    (2113) 0x46a748 ADD	X7, X7, #1

    (2113) 0x46a74c STUR	X7, [X29, #480]

    (2113) 0x46a750 ADD	X7, X19, #1

    (2113) 0x46a754 LDR	X20, [X9, X19,LSL #3]

    (2113) 0x46a758 LDR	X23, [X9, X7,LSL #3]

    (2113) 0x46a75c CMP	X20, X23

    (2113) 0x46a760 B.GE	46a7e0

    (2113) 0x46a764 LDP	X26, X21, [X29, #960]

    (2113) 0x46a768 LDR	X21, [X21]

    (2113) 0x46a76c LDR	X26, [X26]

    (2113) 0x46a770 B	46a78c

0x46a774 HINT	#0

0x46a778 HINT	#0

0x46a77c HINT	#0

      (2115) 0x46a780 ADD	X20, X20, #1

      (2115) 0x46a784 CMP	X20, X23

      (2115) 0x46a788 B.GE	46a7e0

      (2115) 0x46a78c LDR	X27, [X10, X20,LSL #3]

      (2115) 0x46a790 LDR	X28, [X11, X27,LSL #3]

      (2115) 0x46a794 CMP	X28, #1

      (2115) 0x46a798 B.LT	46a780

      (2115) 0x46a79c LDR	X27, [X21, X27,LSL #3]

      (2115) 0x46a7a0 CMP	X27, X22

      (2115) 0x46a7a4 B.EQ	46a780

      (2115) 0x46a7a8 LDR	X28, [X24, X27,LSL #3]

      (2115) 0x46a7ac CMP	X28, X17

      (2115) 0x46a7b0 B.GE	46a780

      (2115) 0x46a7b4 LDUR	X23, [X29, #480]

      (2115) 0x46a7b8 STR	X23, [X24, X27,LSL #3]

      (2115) 0x46a7bc STR	X27, [X26, X23,LSL #3]

      (2115) 0x46a7c0 LDUR	X23, [X29, #480]

      (2115) 0x46a7c4 ADD	X23, X23, #1

      (2115) 0x46a7c8 STUR	X23, [X29, #480]

      (2115) 0x46a7cc LDR	X23, [X9, X7,LSL #3]

      (2115) 0x46a7d0 B	46a780

0x46a7d4 HINT	#0

0x46a7d8 HINT	#0

0x46a7dc HINT	#0

    (2113) 0x46a7e0 LDR	X19, [X12, X19,LSL #3]

    (2113) 0x46a7e4 LDR	X21, [X12, X7,LSL #3]

    (2113) 0x46a7e8 CMP	X19, X21

    (2113) 0x46a7ec B.GE	46a708

    (2113) 0x46a7f0 LDUR	X20, [X29, #464]

    (2113) 0x46a7f4 LDR	X23, [X30]

    (2113) 0x46a7f8 LDR	X20, [X20]

    (2113) 0x46a7fc B	46a80c

      (2114) 0x46a800 ADD	X19, X19, #1

      (2114) 0x46a804 CMP	X19, X21

      (2114) 0x46a808 B.GE	46a708

      (2114) 0x46a80c LDR	X26, [X5, X19,LSL #3]

      (2114) 0x46a810 LDR	X27, [X6, X26,LSL #3]

      (2114) 0x46a814 CMP	X27, #1

      (2114) 0x46a818 B.LT	46a800

      (2114) 0x46a81c LDR	X26, [X20, X26,LSL #3]

      (2114) 0x46a820 LDR	X27, [X25, X26,LSL #3]

      (2114) 0x46a824 CMP	X27, X18

      (2114) 0x46a828 B.GE	46a800

      (2114) 0x46a82c LDUR	X21, [X29, #472]

      (2114) 0x46a830 STR	X21, [X25, X26,LSL #3]

      (2114) 0x46a834 STR	X26, [X23, X21,LSL #3]

      (2114) 0x46a838 LDUR	X21, [X29, #472]

      (2114) 0x46a83c ADD	X21, X21, #1

      (2114) 0x46a840 STUR	X21, [X29, #472]

      (2114) 0x46a844 LDR	X21, [X12, X7,LSL #3]

      (2114) 0x46a848 B	46a800

  (2109) 0x46a84c LDR	X1, [X12, X1,LSL #3]

  (2109) 0x46a850 LDR	X2, [X12, X0,LSL #3]

  (2109) 0x46a854 CMP	X1, X2

  (2109) 0x46a858 B.GE	46a6c0

(2110) 0x46a85c LDUR	X2, [X29, #464]

(2110) 0x46a860 LDP	X4, X5, [X29, #888]

(2110) 0x46a864 LDR	X3, [X30]

(2110) 0x46a868 LDR	X2, [X2]

(2110) 0x46a86c LDR	X4, [X4]

(2110) 0x46a870 LDR	X5, [X5]

(2110) 0x46a874 B	46a890

0x46a878 HINT	#0

0x46a87c HINT	#0

(2110) 0x46a880 LDR	X6, [X12, X0,LSL #3]

(2110) 0x46a884 ADD	X1, X1, #1

(2110) 0x46a888 CMP	X1, X6

(2110) 0x46a88c B.GE	46a6c0

(2110) 0x46a890 LDR	X7, [X13, X1,LSL #3]

(2110) 0x46a894 LDR	X6, [X14, X7,LSL #3]

(2110) 0x46a898 CMP	X6, #1

(2110) 0x46a89c B.LT	46a8c8

(2110) 0x46a8a0 LDR	X6, [X2, X7,LSL #3]

(2110) 0x46a8a4 LDR	X19, [X25, X6,LSL #3]

(2110) 0x46a8a8 CMP	X19, X18

(2110) 0x46a8ac B.GE	46a8c8

(2110) 0x46a8b0 LDUR	X19, [X29, #472]

(2110) 0x46a8b4 STR	X19, [X25, X6,LSL #3]

(2110) 0x46a8b8 STR	X6, [X3, X19,LSL #3]

(2110) 0x46a8bc LDUR	X6, [X29, #472]

(2110) 0x46a8c0 ADD	X6, X6, #1

(2110) 0x46a8c4 STUR	X6, [X29, #472]

(2110) 0x46a8c8 ADD	X6, X7, #1

(2110) 0x46a8cc LDR	X19, [X15, X7,LSL #3]

(2110) 0x46a8d0 LDR	X21, [X15, X6,LSL #3]

(2110) 0x46a8d4 CMP	X19, X21

(2110) 0x46a8d8 B.GE	46a92c

(2110) 0x46a8dc LDUR	X20, [X29, #448]

(2110) 0x46a8e0 LDR	X20, [X20]

(2110) 0x46a8e4 B	46a8f4

  (2112) 0x46a8e8 ADD	X19, X19, #1

  (2112) 0x46a8ec CMP	X19, X21

  (2112) 0x46a8f0 B.GE	46a92c

  (2112) 0x46a8f4 LDR	X23, [X4, X19,LSL #3]

  (2112) 0x46a8f8 CMP	X23, X22

  (2112) 0x46a8fc B.EQ	46a8e8

  (2112) 0x46a900 LDR	X26, [X24, X23,LSL #3]

  (2112) 0x46a904 CMP	X26, X17

  (2112) 0x46a908 B.GE	46a8e8

  (2112) 0x46a90c LDUR	X21, [X29, #480]

  (2112) 0x46a910 STR	X21, [X24, X23,LSL #3]

  (2112) 0x46a914 STR	X23, [X20, X21,LSL #3]

  (2112) 0x46a918 LDUR	X21, [X29, #480]

  (2112) 0x46a91c ADD	X21, X21, #1

  (2112) 0x46a920 STUR	X21, [X29, #480]

  (2112) 0x46a924 LDR	X21, [X15, X6,LSL #3]

  (2112) 0x46a928 B	46a8e8

(2110) 0x46a92c LDR	X7, [X16, X7,LSL #3]

(2110) 0x46a930 LDR	X20, [X16, X6,LSL #3]

(2110) 0x46a934 CMP	X7, X20

(2110) 0x46a938 B.GE	46a880

(2110) 0x46a93c LDR	X19, [X30]

(2110) 0x46a940 B	46a950

  (2111) 0x46a944 ADD	X7, X7, #1

  (2111) 0x46a948 CMP	X7, X20

  (2111) 0x46a94c B.GE	46a880

  (2111) 0x46a950 LDR	X21, [X5, X7,LSL #3]

  (2111) 0x46a954 LDR	X23, [X25, X21,LSL #3]

  (2111) 0x46a958 CMP	X23, X18

  (2111) 0x46a95c B.GE	46a944

  (2111) 0x46a960 LDUR	X20, [X29, #472]

  (2111) 0x46a964 STR	X20, [X25, X21,LSL #3]

  (2111) 0x46a968 STR	X21, [X19, X20,LSL #3]

  (2111) 0x46a96c LDUR	X20, [X29, #472]

  (2111) 0x46a970 ADD	X20, X20, #1

  (2111) 0x46a974 STUR	X20, [X29, #472]

  (2111) 0x46a978 LDR	X20, [X16, X6,LSL #3]

  (2111) 0x46a97c B	46a944

0x46a980 LDR	X8, [SP, #96]

0x46a984 LDP	X12, X13, [X29, #984]

0x46a988 MOVZ	W4, #1

0x46a98c LDR	X8, [X8]

0x46a990 STR	X8, [SP, #144]

0x46a994 LDP	X10, X8, [SP, #40]

0x46a998 LDR	X9, [X10]

0x46a99c LDR	X10, [X8]

0x46a9a0 LDR	X8, [SP, #112]

0x46a9a4 LDR	X11, [X8]

0x46a9a8 LDR	X8, [SP, #56]

0x46a9ac LDR	X14, [X8]

0x46a9b0 LDUR	X8, [X29, #408]

0x46a9b4 LDR	X8, [X8]

0x46a9b8 STUR	X8, [X29, #440]

0x46a9bc LDUR	X8, [X29, #416]

0x46a9c0 LDR	X0, [X8]

0x46a9c4 LDR	X8, [SP, #64]

0x46a9c8 LDR	X2, [X8]

0x46a9cc LDR	X8, [SP, #72]

0x46a9d0 LDR	X5, [X8]

0x46a9d4 B	46a9f0

0x46a9d8 HINT	#0

0x46a9dc HINT	#0

    (2099) 0x46a9e0 LDUR	X8, [X29, #424]

    (2099) 0x46a9e4 ADD	X22, X22, #1

    (2099) 0x46a9e8 CMP	X22, X8

    (2099) 0x46a9ec B.EQ	46af40

    (2099) 0x46a9f0 LDR	X8, [SP, #144]

    (2099) 0x46a9f4 ORR	X6, XZR, X12

    (2099) 0x46a9f8 ORR	X7, XZR, X13

    (2099) 0x46a9fc LDR	X8, [X8, X22,LSL #3]

    (2099) 0x46aa00 ADD	X30, X8, #1

    (2099) 0x46aa04 LDR	X17, [X9, X8,LSL #3]

    (2099) 0x46aa08 STUR	X8, [X29, #400]

    (2099) 0x46aa0c LDR	X8, [X9, X30,LSL #3]

    (2099) 0x46aa10 CMP	X17, X8

    (2099) 0x46aa14 B.GE	46abc0

    (2099) 0x46aa18 LDUR	X8, [X29, #456]

    (2099) 0x46aa1c ORR	X13, XZR, X7

    (2099) 0x46aa20 ORR	X12, XZR, X6

    (2099) 0x46aa24 LDR	X18, [X8]

    (2099) 0x46aa28 LDUR	X8, [X29, #408]

    (2099) 0x46aa2c LDR	X1, [X8]

    (2099) 0x46aa30 LDUR	X8, [X29, #416]

    (2099) 0x46aa34 LDR	X8, [X8]

    (2099) 0x46aa38 B	46aa50

0x46aa3c HINT	#0

      (2105) 0x46aa40 LDR	X15, [X9, X30,LSL #3]

      (2105) 0x46aa44 ADD	X17, X17, #1

      (2105) 0x46aa48 CMP	X17, X15

      (2105) 0x46aa4c B.GE	46abc0

      (2105) 0x46aa50 LDR	X28, [X10, X17,LSL #3]

      (2105) 0x46aa54 LDR	X15, [X11, X28,LSL #3]

      (2105) 0x46aa58 CMP	X15, #1

      (2105) 0x46aa5c B.LT	46aa88

      (2105) 0x46aa60 LDR	X15, [X18, X28,LSL #3]

      (2105) 0x46aa64 LDR	X16, [X24, X15,LSL #3]

      (2105) 0x46aa68 SUBS	X16, X16, X7

      (2105) 0x46aa6c B.GE	46aaa0

      (2105) 0x46aa70 SUB	X16, X13, X7

      (2105) 0x46aa74 STR	X13, [X24, X15,LSL #3]

      (2105) 0x46aa78 ADD	X13, X13, #1

      (2105) 0x46aa7c STR	X15, [X26, X16,LSL #3]

      (2105) 0x46aa80 MOVZ	W15, #2

      (2105) 0x46aa84 STR	X15, [X20, X16,LSL #3]

      (2105) 0x46aa88 ADD	X3, X28, #1

      (2105) 0x46aa8c LDR	X27, [X9, X28,LSL #3]

      (2105) 0x46aa90 LDR	X15, [X9, X3,LSL #3]

      (2105) 0x46aa94 CMP	X27, X15

      (2105) 0x46aa98 B.LT	46aac0

      (2105) 0x46aa9c B	46ab40

      (2105) 0x46aaa0 LDR	X15, [X20, X16,LSL #3]

      (2105) 0x46aaa4 ADD	X15, X15, #2

      (2105) 0x46aaa8 STR	X15, [X20, X16,LSL #3]

      (2105) 0x46aaac ADD	X3, X28, #1

      (2105) 0x46aab0 LDR	X27, [X9, X28,LSL #3]

      (2105) 0x46aab4 LDR	X15, [X9, X3,LSL #3]

      (2105) 0x46aab8 CMP	X27, X15

      (2105) 0x46aabc B.GE	46ab40

      (2105) 0x46aac0 LDUR	X15, [X29, #456]

      (2105) 0x46aac4 LDR	X15, [X15]

      (2105) 0x46aac8 B	46aaf0

        (2107) 0x46aacc LDR	X16, [X20, X19,LSL #3]

        (2107) 0x46aad0 ADD	X16, X16, #1

        (2107) 0x46aad4 STR	X16, [X20, X19,LSL #3]

        (2107) 0x46aad8 HINT	#0

        (2107) 0x46aadc HINT	#0

        (2107) 0x46aae0 LDR	X16, [X9, X3,LSL #3]

        (2107) 0x46aae4 ADD	X27, X27, #1

        (2107) 0x46aae8 CMP	X27, X16

        (2107) 0x46aaec B.GE	46ab40

        (2107) 0x46aaf0 LDR	X16, [X10, X27,LSL #3]

        (2107) 0x46aaf4 LDR	X19, [X11, X16,LSL #3]

        (2107) 0x46aaf8 CMP	X19, #1

        (2107) 0x46aafc B.LT	46aae0

        (2107) 0x46ab00 LDR	X16, [X15, X16,LSL #3]

        (2107) 0x46ab04 CMP	X16, X22

        (2107) 0x46ab08 B.EQ	46aae0

        (2107) 0x46ab0c LDR	X19, [X24, X16,LSL #3]

        (2107) 0x46ab10 SUBS	X19, X19, X7

        (2107) 0x46ab14 B.GE	46aacc

        (2107) 0x46ab18 SUB	X19, X13, X7

        (2107) 0x46ab1c STR	X13, [X24, X16,LSL #3]

        (2107) 0x46ab20 ADD	X13, X13, #1

        (2107) 0x46ab24 STR	X16, [X26, X19,LSL #3]

        (2107) 0x46ab28 STR	X4, [X20, X19,LSL #3]

        (2107) 0x46ab2c B	46aae0

0x46ab30 HINT	#0

0x46ab34 HINT	#0

0x46ab38 HINT	#0

0x46ab3c HINT	#0

      (2105) 0x46ab40 LDR	X27, [X14, X28,LSL #3]

      (2105) 0x46ab44 LDR	X15, [X14, X3,LSL #3]

      (2105) 0x46ab48 CMP	X27, X15

      (2105) 0x46ab4c B.GE	46aa40

      (2105) 0x46ab50 LDUR	X15, [X29, #464]

      (2105) 0x46ab54 LDR	X15, [X15]

      (2105) 0x46ab58 B	46ab7c

0x46ab5c HINT	#0

        (2106) 0x46ab60 LDR	X16, [X21, X19,LSL #3]

        (2106) 0x46ab64 ADD	X16, X16, #1

        (2106) 0x46ab68 STR	X16, [X21, X19,LSL #3]

        (2106) 0x46ab6c LDR	X16, [X14, X3,LSL #3]

        (2106) 0x46ab70 ADD	X27, X27, #1

        (2106) 0x46ab74 CMP	X27, X16

        (2106) 0x46ab78 B.GE	46aa40

        (2106) 0x46ab7c LDR	X16, [X1, X27,LSL #3]

        (2106) 0x46ab80 LDR	X19, [X8, X16,LSL #3]

        (2106) 0x46ab84 CMP	X19, #1

        (2106) 0x46ab88 B.LT	46ab6c

        (2106) 0x46ab8c LDR	X16, [X15, X16,LSL #3]

        (2106) 0x46ab90 LDR	X19, [X25, X16,LSL #3]

        (2106) 0x46ab94 SUBS	X19, X19, X6

        (2106) 0x46ab98 B.GE	46ab60

        (2106) 0x46ab9c SUB	X19, X12, X6

        (2106) 0x46aba0 STR	X12, [X25, X16,LSL #3]

        (2106) 0x46aba4 ADD	X12, X12, #1

        (2106) 0x46aba8 STR	X16, [X23, X19,LSL #3]

        (2106) 0x46abac STR	X4, [X21, X19,LSL #3]

        (2106) 0x46abb0 B	46ab6c

0x46abb4 HINT	#0

0x46abb8 HINT	#0

0x46abbc HINT	#0

    (2099) 0x46abc0 LDUR	X8, [X29, #400]

    (2099) 0x46abc4 LDR	X15, [X14, X30,LSL #3]

    (2099) 0x46abc8 LDR	X8, [X14, X8,LSL #3]

    (2099) 0x46abcc CMP	X8, X15

    (2099) 0x46abd0 B.GE	46ad60

    (2099) 0x46abd4 LDUR	X16, [X29, #376]

    (2099) 0x46abd8 LDUR	X15, [X29, #464]

    (2099) 0x46abdc LDR	X17, [X16]

    (2099) 0x46abe0 LDUR	X16, [X29, #384]

    (2099) 0x46abe4 LDR	X15, [X15]

    (2099) 0x46abe8 LDR	X18, [X16]

    (2099) 0x46abec B	46ac10

0x46abf0 HINT	#0

0x46abf4 HINT	#0

0x46abf8 HINT	#0

0x46abfc HINT	#0

      (2102) 0x46ac00 LDR	X16, [X14, X30,LSL #3]

      (2102) 0x46ac04 ADD	X8, X8, #1

      (2102) 0x46ac08 CMP	X8, X16

      (2102) 0x46ac0c B.GE	46ad60

      (2102) 0x46ac10 LDUR	X16, [X29, #440]

      (2102) 0x46ac14 LDR	X3, [X16, X8,LSL #3]

      (2102) 0x46ac18 LDR	X16, [X0, X3,LSL #3]

      (2102) 0x46ac1c CMP	X16, #1

      (2102) 0x46ac20 B.LT	46ac4c

      (2102) 0x46ac24 LDR	X16, [X15, X3,LSL #3]

      (2102) 0x46ac28 LDR	X1, [X25, X16,LSL #3]

      (2102) 0x46ac2c SUBS	X1, X1, X6

      (2102) 0x46ac30 B.GE	46ac64

      (2102) 0x46ac34 SUB	X1, X12, X6

      (2102) 0x46ac38 STR	X12, [X25, X16,LSL #3]

      (2102) 0x46ac3c ADD	X12, X12, #1

      (2102) 0x46ac40 STR	X16, [X23, X1,LSL #3]

      (2102) 0x46ac44 MOVZ	W16, #2

      (2102) 0x46ac48 STR	X16, [X21, X1,LSL #3]

      (2102) 0x46ac4c LDR	X27, [X2, X3,LSL #3]

      (2102) 0x46ac50 ADD	X1, X3, #1

      (2102) 0x46ac54 LDR	X16, [X2, X1,LSL #3]

      (2102) 0x46ac58 CMP	X27, X16

      (2102) 0x46ac5c B.LT	46aca4

      (2102) 0x46ac60 B	46ace0

      (2102) 0x46ac64 LDR	X16, [X21, X1,LSL #3]

      (2102) 0x46ac68 ADD	X16, X16, #2

      (2102) 0x46ac6c STR	X16, [X21, X1,LSL #3]

      (2102) 0x46ac70 LDR	X27, [X2, X3,LSL #3]

      (2102) 0x46ac74 ADD	X1, X3, #1

      (2102) 0x46ac78 LDR	X16, [X2, X1,LSL #3]

      (2102) 0x46ac7c CMP	X27, X16

      (2102) 0x46ac80 B.LT	46aca4

      (2102) 0x46ac84 B	46ace0

        (2104) 0x46ac88 LDR	X16, [X20, X19,LSL #3]

        (2104) 0x46ac8c ADD	X16, X16, #1

        (2104) 0x46ac90 STR	X16, [X20, X19,LSL #3]

        (2104) 0x46ac94 ADD	X27, X27, #1

        (2104) 0x46ac98 LDR	X16, [X2, X1,LSL #3]

        (2104) 0x46ac9c CMP	X27, X16

        (2104) 0x46aca0 B.GE	46ace0

        (2104) 0x46aca4 LDR	X16, [X17, X27,LSL #3]

        (2104) 0x46aca8 CMP	X16, X22

        (2104) 0x46acac B.EQ	46ac94

        (2104) 0x46acb0 LDR	X19, [X24, X16,LSL #3]

        (2104) 0x46acb4 SUBS	X19, X19, X7

        (2104) 0x46acb8 B.GE	46ac88

        (2104) 0x46acbc SUB	X19, X13, X7

        (2104) 0x46acc0 STR	X13, [X24, X16,LSL #3]

        (2104) 0x46acc4 ADD	X13, X13, #1

        (2104) 0x46acc8 ADD	X27, X27, #1

        (2104) 0x46accc STR	X16, [X26, X19,LSL #3]

        (2104) 0x46acd0 STR	X4, [X20, X19,LSL #3]

        (2104) 0x46acd4 LDR	X16, [X2, X1,LSL #3]

        (2104) 0x46acd8 CMP	X27, X16

        (2104) 0x46acdc B.LT	46aca4

      (2102) 0x46ace0 LDR	X3, [X5, X3,LSL #3]

      (2102) 0x46ace4 LDR	X16, [X5, X1,LSL #3]

      (2102) 0x46ace8 CMP	X3, X16

      (2102) 0x46acec B.LT	46ad24

      (2102) 0x46acf0 B	46ac00

0x46acf4 HINT	#0

0x46acf8 HINT	#0

0x46acfc HINT	#0

        (2103) 0x46ad00 SUB	X19, X12, X6

        (2103) 0x46ad04 STR	X12, [X25, X16,LSL #3]

        (2103) 0x46ad08 ADD	X12, X12, #1

        (2103) 0x46ad0c ADD	X3, X3, #1

        (2103) 0x46ad10 STR	X16, [X23, X19,LSL #3]

        (2103) 0x46ad14 STR	X4, [X21, X19,LSL #3]

        (2103) 0x46ad18 LDR	X16, [X5, X1,LSL #3]

        (2103) 0x46ad1c CMP	X3, X16

        (2103) 0x46ad20 B.GE	46ac00

        (2103) 0x46ad24 LDR	X16, [X18, X3,LSL #3]

        (2103) 0x46ad28 LDR	X19, [X25, X16,LSL #3]

        (2103) 0x46ad2c SUBS	X19, X19, X6

        (2103) 0x46ad30 B.LT	46ad00

        (2103) 0x46ad34 LDR	X16, [X21, X19,LSL #3]

        (2103) 0x46ad38 ADD	X3, X3, #1

        (2103) 0x46ad3c ADD	X16, X16, #1

        (2103) 0x46ad40 STR	X16, [X21, X19,LSL #3]

        (2103) 0x46ad44 LDR	X16, [X5, X1,LSL #3]

        (2103) 0x46ad48 CMP	X3, X16

        (2103) 0x46ad4c B.LT	46ad24

      (2102) 0x46ad50 B	46ac00

0x46ad54 HINT	#0

0x46ad58 HINT	#0

0x46ad5c HINT	#0

    (2099) 0x46ad60 LDUR	X19, [X29, #432]

    (2099) 0x46ad64 LDUR	X27, [X29, #392]

    (2099) 0x46ad68 CMP	X13, X7

    (2099) 0x46ad6c B.LE	46adbc

    (2099) 0x46ad70 LDUR	X8, [X29, #448]

    (2099) 0x46ad74 SUB	W15, W13, W7

    (2099) 0x46ad78 ORR	X17, XZR, X7

    (2099) 0x46ad7c LDR	X8, [X8]

    (2099) 0x46ad80 TBZ	W15, #0, 46adb0

    (2099) 0x46ad84 LDR	X15, [X20]

    (2099) 0x46ad88 LDR	X16, [X19]

    (2099) 0x46ad8c CMP	X15, X16

    (2099) 0x46ad90 B.LT	46ada8

    (2099) 0x46ad94 LDUR	X16, [X29, #480]

    (2099) 0x46ad98 LDR	X15, [X26]

    (2099) 0x46ad9c ADD	X17, X16, #1

    (2099) 0x46ada0 STUR	X17, [X29, #480]

    (2099) 0x46ada4 STR	X15, [X8, X16,LSL #3]

    (2099) 0x46ada8 ADD	X17, X7, #1

    (2099) 0x46adac STR	XZR, [X20]

    (2099) 0x46adb0 ADD	X15, X7, #1

    (2099) 0x46adb4 CMP	X13, X15

    (2099) 0x46adb8 B.NE	46aea4

    (2099) 0x46adbc CMP	X12, X6

    (2099) 0x46adc0 B.LE	46a9e0

    (2099) 0x46adc4 LDR	X8, [X27]

    (2099) 0x46adc8 SUB	W15, W12, W6

    (2099) 0x46adcc ORR	X17, XZR, X6

    (2099) 0x46add0 TBZ	W15, #0, 46ae00

    (2099) 0x46add4 LDR	X15, [X21]

    (2099) 0x46add8 LDR	X16, [X19]

    (2099) 0x46addc CMP	X15, X16

    (2099) 0x46ade0 B.LT	46adf8

    (2099) 0x46ade4 LDUR	X16, [X29, #472]

    (2099) 0x46ade8 LDR	X15, [X23]

    (2099) 0x46adec ADD	X17, X16, #1

    (2099) 0x46adf0 STUR	X17, [X29, #472]

    (2099) 0x46adf4 STR	X15, [X8, X16,LSL #3]

    (2099) 0x46adf8 ADD	X17, X6, #1

    (2099) 0x46adfc STR	XZR, [X21]

    (2099) 0x46ae00 ADD	X15, X6, #1

    (2099) 0x46ae04 CMP	X12, X15

    (2099) 0x46ae08 B.EQ	46a9e0

    (2099) 0x46ae0c UBFM	X16, X17, #61, #60

    (2099) 0x46ae10 SUB	X15, X12, X17

    (2099) 0x46ae14 ADD	X17, X23, #8

    (2099) 0x46ae18 ADD	X18, X21, #8

    (2099) 0x46ae1c SUB	X16, X16, X6,LSL #3

    (2099) 0x46ae20 ADD	X17, X17, X16

    (2099) 0x46ae24 ADD	X18, X18, X16

    (2099) 0x46ae28 B	46ae3c

      (2108) 0x46ae2c STR	XZR, [X18], #16

      (2108) 0x46ae30 SUBS	X15, X15, #2

      (2108) 0x46ae34 ADD	X17, X17, #16

      (2108) 0x46ae38 B.EQ	46a9e0

      (2108) 0x46ae3c LDUR	X16, [X18, #504]

      (2108) 0x46ae40 LDR	X1, [X19]

      (2108) 0x46ae44 CMP	X16, X1

      (2108) 0x46ae48 B.GE	46ae64

      (2108) 0x46ae4c STUR	XZR, [X18, #504]

      (2108) 0x46ae50 LDR	X16, [X18]

      (2108) 0x46ae54 LDR	X1, [X19]

      (2108) 0x46ae58 CMP	X16, X1

      (2108) 0x46ae5c B.LT	46ae2c

      (2108) 0x46ae60 B	46ae8c

      (2108) 0x46ae64 LDUR	X1, [X29, #472]

      (2108) 0x46ae68 LDUR	X16, [X17, #504]

      (2108) 0x46ae6c ADD	X3, X1, #1

      (2108) 0x46ae70 STUR	X3, [X29, #472]

      (2108) 0x46ae74 STR	X16, [X8, X1,LSL #3]

      (2108) 0x46ae78 STUR	XZR, [X18, #504]

      (2108) 0x46ae7c LDR	X16, [X18]

      (2108) 0x46ae80 LDR	X1, [X19]

      (2108) 0x46ae84 CMP	X16, X1

      (2108) 0x46ae88 B.LT	46ae2c

      (2108) 0x46ae8c LDUR	X1, [X29, #472]

      (2108) 0x46ae90 LDR	X16, [X17]

      (2108) 0x46ae94 ADD	X3, X1, #1

      (2108) 0x46ae98 STUR	X3, [X29, #472]

      (2108) 0x46ae9c STR	X16, [X8, X1,LSL #3]

      (2108) 0x46aea0 B	46ae2c

  (2101) 0x46aea4 UBFM	X16, X17, #61, #60

  (2101) 0x46aea8 SUB	X15, X13, X17

  (2101) 0x46aeac ADD	X17, X26, #8

  (2101) 0x46aeb0 ADD	X18, X20, #8

  (2101) 0x46aeb4 SUB	X16, X16, X7,LSL #3

  (2101) 0x46aeb8 ADD	X17, X17, X16

  (2101) 0x46aebc ADD	X18, X18, X16

  (2101) 0x46aec0 B	46aed4

  (2101) 0x46aec4 STR	XZR, [X18], #16

  (2101) 0x46aec8 SUBS	X15, X15, #2

  (2101) 0x46aecc ADD	X17, X17, #16

  (2101) 0x46aed0 B.EQ	46adbc

  (2101) 0x46aed4 LDUR	X16, [X18, #504]

  (2101) 0x46aed8 LDR	X1, [X19]

  (2101) 0x46aedc CMP	X16, X1

  (2101) 0x46aee0 B.GE	46af00

  (2101) 0x46aee4 STUR	XZR, [X18, #504]

  (2101) 0x46aee8 LDR	X16, [X18]

  (2101) 0x46aeec LDR	X1, [X19]

  (2101) 0x46aef0 CMP	X16, X1

  (2101) 0x46aef4 B.LT	46aec4

  (2101) 0x46aef8 B	46af28

0x46aefc HINT	#0

(2100) 0x46af00 LDUR	X1, [X29, #480]

(2100) 0x46af04 LDUR	X16, [X17, #504]

(2100) 0x46af08 ADD	X3, X1, #1

(2100) 0x46af0c STUR	X3, [X29, #480]

(2100) 0x46af10 STR	X16, [X8, X1,LSL #3]

(2100) 0x46af14 STUR	XZR, [X18, #504]

(2100) 0x46af18 LDR	X16, [X18]

(2100) 0x46af1c LDR	X1, [X19]

(2100) 0x46af20 CMP	X16, X1

(2100) 0x46af24 B.LT	46aec4

  (2101) 0x46af28 LDUR	X1, [X29, #480]

  (2101) 0x46af2c LDR	X16, [X17]

  (2101) 0x46af30 ADD	X3, X1, #1

  (2101) 0x46af34 STUR	X3, [X29, #480]

  (2101) 0x46af38 STR	X16, [X8, X1,LSL #3]

  (2101) 0x46af3c B	46aec4

0x46af40 LDP	X20, X19, [SP, #368]

0x46af44 LDP	X22, X21, [SP, #352]

0x46af48 LDP	X24, X23, [SP, #336]

0x46af4c LDP	X26, X25, [SP, #320]

0x46af50 LDP	X28, X27, [SP, #304]

0x46af54 LDP	X29, X30, [SP, #288]

0x46af58 ADD	SP, SP, #384

0x46af5c RET

Coverage (%)	Name	Source Location	Module
►98.57+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.43+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_BoomerAMGCreate2ndS	par_strength.c:2238	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:617	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_strength.c:1668-2230
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1668-1697,1705-1714,1720-1797,1806,1812-2000,2006-2083,2093-2095,2101-2230.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 28% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 66.17 to 11.37 cycles (5.82x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_GetSimpleThreadPartition: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1674
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1671
hypre_MAlloc: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1967
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1971
hypre_prefix_sum_pair: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1946
unknown: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1961
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1962
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1973
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1975

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes.

General properties

nb instructions	385
nb uops	322
loop length	1540
used w registers	7
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	40.25 cycles
front end	40.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	16.50	16.50	25.00	25.00	25.00	25.00	0.00	0.00	0.00	0.00	66.17	65.83	66.00	20.50	20.50
cycles	16.50	16.50	25.00	25.00	25.00	25.00	0.00	0.00	0.00	0.00	66.17	65.83	66.00	20.50	20.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	40.25
Dispatch	66.17
Overall L1	66.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	28%
load	25%
store	32%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 66.17 cycles. At this rate:

0% of peak load performance is reached (0.05 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4699d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X27, X22, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X21, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X25, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X19, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X0, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4acc50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X28, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X0, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X1, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4acc70 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X15, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MUL X11, X10, X28	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STUR X21, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LE 469a74 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X12, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X26, X12, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X12, X9, X28	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X23, X14, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X20, X13, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X21, X8, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 469a88 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X23, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X26, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MUL X12, X9, X28	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X13, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X13, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X11, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X24, XZR, X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X11, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X25, XZR, X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 469ae0 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X27, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 469ae4 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X27, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X10, X15, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X11, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X11, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X11, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X11, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X9, X11, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X11, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X11, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X11, X9, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X11, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X10, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LT 469b74 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP XZR, XZR, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X9, X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X22, [X8, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X13, X12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STP X9, X19, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B.NE 469ea0 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x4d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X22, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 46a410 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xa40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X18, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X9, X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X17, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 469c1c <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
CMP X22, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 46a410 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xa40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X1, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X5, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X10, X8, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X2, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X6, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 469f14 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X10, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X0, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X2, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X10, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X10, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X9, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ad890 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 46a474 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xaa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X11, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X8, X9, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X11, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 46a4b4 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xae4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4ee4b8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #912	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W27, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4ee4cc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #936	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410280 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W0, 46a540 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xb70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X9, 46a510 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xb40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X0, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X19, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4aae90 <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 46a530 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xb60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X0, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4aae90 <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADRP X0, <4ee530>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #936	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410500 <@plt_start@+0x4e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4ee540>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #960	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X17, X18, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X0, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X8, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X30, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X22, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ORR X8, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.GE 46a5f8 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xc28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X9, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X10, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X12, X12, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORN X9, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X9, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X10, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X11, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 46a5c8 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xbf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X22, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 46af40 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x1570>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X11, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [X11, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X12, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [X10, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X10, X12,LSL #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 46a674 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xca4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 46a674 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xca4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X10, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X10, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 46a980 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xfb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X11, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X12, X15, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X13, X14, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 46a6d0 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xd00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X12, X13, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 46a9f0 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x1020>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_strength.c:1668-2230
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_GetSimpleThreadPartition: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1674
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1671
hypre_MAlloc: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1967
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1971
hypre_prefix_sum_pair: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1946
unknown: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1961
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1962
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1973
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1975

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes.

General properties

nb instructions	385
nb uops	322
loop length	1540
used w registers	7
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	40.25 cycles
front end	40.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	16.50	16.50	25.00	25.00	25.00	25.00	0.00	0.00	0.00	0.00	66.17	65.83	66.00	20.50	20.50
cycles	16.50	16.50	25.00	25.00	25.00	25.00	0.00	0.00	0.00	0.00	66.17	65.83	66.00	20.50	20.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	40.25
Dispatch	66.17
Overall L1	66.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	28%
load	25%
store	32%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 66.17 cycles. At this rate:

0% of peak load performance is reached (0.05 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4699d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X27, X22, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X21, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X25, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X19, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X0, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4acc50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X28, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X0, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X1, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4acc70 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X15, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MUL X11, X10, X28	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STUR X21, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LE 469a74 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X12, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X26, X12, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X12, X9, X28	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X23, X14, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X20, X13, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X21, X8, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 469a88 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X23, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X26, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MUL X12, X9, X28	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X13, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X13, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X11, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X24, XZR, X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X11, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X25, XZR, X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 469ae0 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X27, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 469ae4 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X27, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X10, X15, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X11, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X11, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X11, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X11, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X9, X11, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X11, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X11, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X11, X9, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X11, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X10, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LT 469b74 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP XZR, XZR, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X9, X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X22, [X8, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X13, X12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STP X9, X19, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B.NE 469ea0 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x4d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X22, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 46a410 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xa40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X18, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X9, X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X17, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 469c1c <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
CMP X22, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 46a410 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xa40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X1, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X5, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X10, X8, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X2, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X6, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 469f14 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X10, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X0, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X2, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X10, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X10, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X9, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4ad890 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 46a474 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xaa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X11, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X8, X9, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X11, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 46a4b4 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xae4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4ee4b8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #912	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W27, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4ee4cc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #936	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410280 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W0, 46a540 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xb70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X9, 46a510 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xb40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X0, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X19, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4aae90 <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 46a530 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xb60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X0, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4aae90 <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADRP X0, <4ee530>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #936	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410500 <@plt_start@+0x4e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4ee540>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #960	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X17, X18, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X0, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X8, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X30, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X22, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ORR X8, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.GE 46a5f8 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xc28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X9, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X10, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X12, X12, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORN X9, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X9, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X10, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X11, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 46a5c8 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xbf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X22, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 46af40 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x1570>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X11, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [X11, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X12, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [X10, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X10, X12,LSL #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 46a674 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xca4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 46a674 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xca4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X10, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X10, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 46a980 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xfb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X11, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X12, X15, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X13, X14, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 46a6d0 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0xd00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X12, X13, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 46a9f0 <hypre_BoomerAMGCreate2ndS.omp_outlined.15+0x1020>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCreate2ndS.omp_outlined.15–	1.39	0.66
○Loop 2118 - par_strength.c:1951-1953 - exec	0.03	0.01
○Loop 2137 - par_strength.c:1691-1693 - exec	0.01	0.01
○Loop 2116 - par_strength.c:1978-1984 - exec	0.00	0.00
○Loop 2117 - par_strength.c:1955-1957 - exec	0.00	0.00
▼Loop 2110 - par_strength.c:1998-2083 - exec–	0.00	0.00
▼Loop 2109 - par_strength.c:1998-2053 - exec–	0.00	0.01
▼Loop 2113 - par_strength.c:2011-2048 - exec–	0.09	0.03
○Loop 2115 - par_strength.c:2024-2034 - exec	0.59	0.20
○Loop 2114 - par_strength.c:2038-2048 - exec	0.00	0.00
○Loop 2112 - par_strength.c:2066-2073 - exec	0.00	0.00
○Loop 2111 - par_strength.c:2076-2083 - exec	0.00	0.00
○Loop 2136 - par_strength.c:1695-1697 - exec	0.00	0.00
▼Loop 2100 - par_strength.c:2093-2230 - exec–	0.00	0.00
▼Loop 2101 - par_strength.c:2093-2230 - exec–	0.00	0.00
▼Loop 2099 - par_strength.c:2093-2230 - exec–	0.00	0.00
○Loop 2108 - par_strength.c:2224-2230 - exec	0.00	0.00
▼Loop 2105 - par_strength.c:2106-2158 - exec–	0.00	0.00
○Loop 2106 - par_strength.c:2143-2158 - exec	0.00	0.00
○Loop 2107 - par_strength.c:2124-2139 - exec	0.00	0.00
▼Loop 2102 - par_strength.c:2163-2211 - exec–	0.00	0.00
○Loop 2104 - par_strength.c:2181-2195 - exec	0.00	0.00
○Loop 2103 - par_strength.c:2199-2211 - exec	0.00	0.00
▼Loop 2130 - par_strength.c:1714-1797 - exec–	0.00	0.00
▼Loop 2129 - par_strength.c:1714-1770 - exec–	0.00	0.01
▼Loop 2132 - par_strength.c:1731-1765 - exec–	0.09	0.03
○Loop 2134 - par_strength.c:1743-1752 - exec	0.58	0.20
○Loop 2133 - par_strength.c:1756-1765 - exec	0.00	0.00
○Loop 2135 - par_strength.c:1791-1797 - exec	0.00	0.00
○Loop 2131 - par_strength.c:1782-1788 - exec	0.00	0.00
▼Loop 2120 - par_strength.c:1806-1941 - exec–	0.00	0.00
▼Loop 2121 - par_strength.c:1806-1941 - exec–	0.00	0.00
▼Loop 2119 - par_strength.c:1806-1941 - exec–	0.00	0.00
▼Loop 2125 - par_strength.c:1823-1872 - exec–	0.00	0.00
○Loop 2127 - par_strength.c:1840-1854 - exec	0.00	0.00
○Loop 2126 - par_strength.c:1858-1872 - exec	0.00	0.00
▼Loop 2122 - par_strength.c:1877-1922 - exec–	0.00	0.00
○Loop 2123 - par_strength.c:1911-1922 - exec	0.00	0.00
○Loop 2124 - par_strength.c:1894-1907 - exec	0.00	0.00
○Loop 2128 - par_strength.c:1935-1941 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code