OV - exec - Function hypre_ParCSRComputeL1NormsThreads.omp

	Function: hypre_ParCSRComputeL1NormsThreads.omp_outlined	Module: exec	Source: ams.c:3363-3540 [...]	Coverage (incl. loops): 0.20% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3363 - 3540

--------------------------------------------------------------------------------

3363: #pragma omp parallel for private(i,ii,j,k,ns,ne,rest,size,diag,cf_diag) HYPRE_SMP_SCHEDULE

3364: #endif

3365:    for (k = 0; k < num_threads; k++)

3366:    {

3367:       size = num_rows/num_threads;

3368:       rest = num_rows - size*num_threads;

3369:       if (k < rest)

3370:       {

3371:          ns = k*size+k;

3372:          ne = (k+1)*size+k+1;

3373:       }

3374:       else

3375:       {

3376:          ns = k*size+rest;

3377:          ne = (k+1)*size+rest;

3378:       }

3379:

3380:       if (option == 1)

3381:       {

3382:          for (i = ns; i < ne; i++)

3383:          {

3384:             l1_norm[i] = 0.0;

3385:             if (cf_marker == NULL)

3386:             {

3387:                /* Add the l1 norm of the diag part of the ith row */

3388:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3389:                   l1_norm[i] += fabs(A_diag_data[j]);

3390:                /* Add the l1 norm of the offd part of the ith row */

3391:                if (num_cols_offd)

3392:                {

3393:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3394:                      l1_norm[i] += fabs(A_offd_data[j]);

3395:                }

3396:             }

3397:             else

3398:             {

3399:                cf_diag = cf_marker[i];

3400:                /* Add the CF l1 norm of the diag part of the ith row */

3401:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3402:                   if (cf_diag == cf_marker[A_diag_J[j]])

3403:                      l1_norm[i] += fabs(A_diag_data[j]);

3404:                /* Add the CF l1 norm of the offd part of the ith row */

3405:                if (num_cols_offd)

3406:                {

3407:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3408:                      if (cf_diag == cf_marker_offd[A_offd_J[j]])

3409:                         l1_norm[i] += fabs(A_offd_data[j]);

[...]

3416:          for (i = ns; i < ne; i++)

3417:          {

3418:             l1_norm[i] = 0.0;

3419:             if (cf_marker == NULL)

3420:             {

3421:                /* Add the diagonal and the local off-thread part of the ith row */

3422:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3423:                {

3424:                   ii = A_diag_J[j];

3425:                   if (ii == i || ii < ns || ii >= ne)

3426:                      l1_norm[i] += fabs(A_diag_data[j]);

3427:                }

3428:                /* Add the l1 norm of the offd part of the ith row */

3429:                if (num_cols_offd)

3430:                {

3431:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3432:                      l1_norm[i] += fabs(A_offd_data[j]);

3433:                }

3434:             }

3435:             else

3436:             {

3437:                cf_diag = cf_marker[i];

3438:                /* Add the diagonal and the local off-thread part of the ith row */

3439:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3440:                {

3441:                   ii = A_diag_J[j];

3442:                   if ((ii == i || ii < ns || ii >= ne) &&

3443:                       (cf_diag == cf_marker[A_diag_J[j]]))

3444:                      l1_norm[i] += fabs(A_diag_data[j]);

3445:                }

3446:                /* Add the CF l1 norm of the offd part of the ith row */

3447:                if (num_cols_offd)

3448:                {

3449:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3450:                      if (cf_diag == cf_marker_offd[A_offd_J[j]])

3451:                         l1_norm[i] += fabs(A_offd_data[j]);

[...]

3458:          for (i = ns; i < ne; i++)

3459:          {

3460:             l1_norm[i] = 0.0;

3461:             for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3462:                l1_norm[i] += A_diag_data[j] * A_diag_data[j];

3463:             if (num_cols_offd)

3464:                for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3465:                   l1_norm[i] += A_offd_data[j] * A_offd_data[j];

3466:          }

3467:       }

3468:       else if (option == 4)

3469:       {

3470:          for (i = ns; i < ne; i++)

3471:          {

3472:             l1_norm[i] = 0.0;

3473:             if (cf_marker == NULL)

3474:             {

3475:                /* Add the diagonal and the local off-thread part of the ith row */

3476:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3477:                {

3478:                   ii = A_diag_J[j];

3479:                   if (ii == i || ii < ns || ii >= ne)

3480:                   {

3481:                      if (ii == i)

[...]

3493:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3494:                      l1_norm[i] += 0.5*fabs(A_offd_data[j]);

3495:                }

3496:             }

3497:             else

3498:             {

3499:                cf_diag = cf_marker[i];

3500:                /* Add the diagonal and the local off-thread part of the ith row */

3501:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3502:                {

3503:                   ii = A_diag_J[j];

3504:                   if ((ii == i || ii < ns || ii >= ne) &&

3505:                       (cf_diag == cf_marker[A_diag_J[j]]))

3506:                   {

3507:                      if (ii == i)

[...]

3517:                if (num_cols_offd)

3518:                {

3519:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3520:                      if (cf_diag == cf_marker_offd[A_offd_J[j]])

3521:                         l1_norm[i] += 0.5*fabs(A_offd_data[j]);

3522:                }

3523:             }

3524:

3525:             /* Truncate according to Remark 6.2 */

3526:             if (l1_norm[i] <= 4.0/3.0*diag)

3527:                l1_norm[i] = diag;

3528:          }

3529:       }

3530:

3531:       /* Handle negative definite matrices */

3532:       for (i = ns; i < ne; i++)

3533:          if (A_diag_data[A_diag_I[i]] < 0)

3534:             l1_norm[i] = -l1_norm[i];

3535:

3536:       for (i = ns; i < ne; i++)

3537:          /* if (fabs(l1_norm[i]) < DBL_EPSILON) */

3538:          if (fabs(l1_norm[i]) == 0.0)

3539:          {

3540:             hypre_error_in_arg(1);

0x479d80 SUB	SP, SP, #272

0x479d84 STP	D9, D8, [SP, #160]

0x479d88 STP	X29, X30, [SP, #176]

0x479d8c STP	X28, X27, [SP, #192]

0x479d90 STP	X26, X25, [SP, #208]

0x479d94 STP	X24, X23, [SP, #224]

0x479d98 STP	X22, X21, [SP, #240]

0x479d9c STP	X20, X19, [SP, #256]

0x479da0 ADD	X29, SP, #176

0x479da4 LDR	X8, [X2]

0x479da8 STR	X7, [SP, #88]

0x479dac STR	X6, [SP, #64]

0x479db0 SUBS	X19, X8, #1

0x479db4 STP	X3, X4, [X29, #952]

0x479db8 STUR	X2, [X29, #432]

0x479dbc B.LT	479e2c

0x479dc0 LDR	W1, [X0]

0x479dc4 ORR	X21, XZR, X5

0x479dc8 MOVZ	W8, #1

0x479dcc ADRP	X0,

0x479dd0 ADD	X0, X0, #1104

0x479dd4 SUB	X3, X29, #52

0x479dd8 STP	X19, XZR, [X29, #984]

0x479ddc SUB	X4, X29, #32

0x479de0 SUB	X5, X29, #40

0x479de4 SUB	X6, X29, #48

0x479de8 MOVZ	W2, #34

0x479dec STUR	X8, [X29, #464]

0x479df0 STUR	WZR, [X29, #460]

0x479df4 MOVZ	W7, #1

0x479df8 STR	X8, [SP]

0x479dfc STR	W1, [SP, #20]

0x479e00 BL	4103d0

0x479e04 LDP	X8, X27, [X29, #984]

0x479e08 CMP	X8, X19

0x479e0c CSEL	X8, X8, X19, #11

0x479e10 CMP	X27, X8

0x479e14 STUR	X8, [X29, #472]

0x479e18 B.LE	479e50

0x479e1c LDR	W1, [SP, #20]

0x479e20 ADRP	X0,

0x479e24 ADD	X0, X0, #1128

0x479e28 BL	410150

0x479e2c LDP	D9, D8, [SP, #160]

0x479e30 LDP	X20, X19, [SP, #256]

0x479e34 LDP	X22, X21, [SP, #240]

0x479e38 LDP	X24, X23, [SP, #224]

0x479e3c LDP	X26, X25, [SP, #208]

0x479e40 LDP	X28, X27, [SP, #192]

0x479e44 LDP	X29, X30, [SP, #176]

0x479e48 ADD	SP, SP, #272

0x479e4c RET

0x479e50 LDR	X9, [X29, #144]

0x479e54 LDR	X26, [X29, #96]

0x479e58 CNTW	X25, ALL

0x479e5c FMOV	D8, #0.5000000

0x479e60 ORR	X19, XZR, #0x55

0x479e64 STR	X21, [SP, #24]

0x479e68 MOVK	X19, #16373

0x479e6c PTRUE	P0.D, ALL

0x479e70 STR	X9, [SP, #40]

0x479e74 LDR	X9, [X29, #136]

0x479e78 STR	X9, [SP, #32]

0x479e7c LDR	X9, [X29, #128]

0x479e80 STR	X9, [SP, #48]

0x479e84 LDP	X9, X28, [X29, #112]

0x479e88 STR	X9, [SP, #80]

0x479e8c LDR	X9, [X29, #104]

0x479e90 STR	X9, [SP, #72]

0x479e94 MOVZ	W9, #8

0x479e98 CMP	X25, #8

0x479e9c CSEL	X20, X25, X9, #8

0x479ea0 B	479ed0

    (2548) 0x479ea4 ADRP	X0,

    (2548) 0x479ea8 ADD	X0, X0, #3665

    (2548) 0x479eac MOVZ	W1, #3540

    (2548) 0x479eb0 MOVZ	W2, #12

    (2548) 0x479eb4 ORR	X3, XZR, XZR

    (2548) 0x479eb8 BL	4ad5e0

    (2548) 0x479ebc LDUR	X8, [X29, #472]

    (2548) 0x479ec0 PTRUE	P0.D, ALL

    (2548) 0x479ec4 CMP	X27, X8

    (2548) 0x479ec8 ADD	X27, X27, #1

    (2548) 0x479ecc B.GE	479e1c

    (2548) 0x479ed0 LDP	X10, X9, [X29, #944]

    (2548) 0x479ed4 LDR	X9, [X9]

    (2548) 0x479ed8 LDR	X10, [X10]

    (2548) 0x479edc SDIV	X11, X9, X10

    (2548) 0x479ee0 MSUB	X9, X11, X10, X9

    (2548) 0x479ee4 ADD	X10, X27, #1

    (2548) 0x479ee8 MADD	X12, X11, X27, X9

    (2548) 0x479eec MADD	X13, X11, X10, X9

    (2548) 0x479ef0 ADD	X11, X11, #1

    (2548) 0x479ef4 MUL	X14, X11, X27

    (2548) 0x479ef8 MUL	X10, X10, X11

    (2548) 0x479efc LDUR	X11, [X29, #448]

    (2548) 0x479f00 CMP	X27, X9

    (2548) 0x479f04 CSEL	X9, X12, X14, #10

    (2548) 0x479f08 CSEL	X10, X13, X10, #10

    (2548) 0x479f0c LDR	X11, [X11]

    (2548) 0x479f10 CMP	X11, #2

    (2548) 0x479f14 B.GT	47a0e4

    (2548) 0x479f18 CMP	X11, #1

    (2548) 0x479f1c B.EQ	47a3f0

    (2548) 0x479f20 CMP	X11, #2

    (2548) 0x479f24 B.NE	47a828

    (2548) 0x479f28 CMP	X10, X9

    (2548) 0x479f2c B.LE	47a828

    (2548) 0x479f30 LDP	X12, X14, [SP, #64]

    (2548) 0x479f34 LDR	X13, [SP, #48]

    (2548) 0x479f38 LDR	X11, [X21]

    (2548) 0x479f3c LDR	X17, [X12]

    (2548) 0x479f40 LDP	X15, X12, [SP, #80]

    (2548) 0x479f44 LDR	X13, [X13]

    (2548) 0x479f48 LDR	X14, [X14]

    (2548) 0x479f4c LDR	X12, [X12]

    (2548) 0x479f50 LDR	X15, [X15]

    (2548) 0x479f54 LDR	X16, [X12, X9,LSL #3]

    (2548) 0x479f58 CBZ	X17, 47a920

    (2548) 0x479f5c LDP	X18, X0, [SP, #32]

    (2548) 0x479f60 ORR	X2, XZR, X9

    (2548) 0x479f64 LDR	X0, [X0]

    (2548) 0x479f68 LDR	X18, [X18]

    (2548) 0x479f6c ADD	X1, X0, #8

    (2548) 0x479f70 B	479f8c

0x479f74 HINT	#0

0x479f78 HINT	#0

0x479f7c HINT	#0

      (2576) 0x479f80 CMP	X2, X10

      (2576) 0x479f84 ORR	X16, XZR, X4

      (2576) 0x479f88 B.EQ	47a828

      (2576) 0x479f8c ORR	X3, XZR, X2

      (2576) 0x479f90 STR	XZR, [X11, X2,LSL #3]

      (2576) 0x479f94 LDR	X5, [X17, X2,LSL #3]

      (2576) 0x479f98 ADD	X2, X2, #1

      (2576) 0x479f9c MOVI	D0, #0

      (2576) 0x479fa0 LDR	X4, [X12, X2,LSL #3]

      (2576) 0x479fa4 SUBS	X6, X4, X16

      (2576) 0x479fa8 B.LE	47a000

      (2576) 0x479fac LDR	X22, [X26]

      (2576) 0x479fb0 ADD	X7, X13, X16,LSL #3

      (2576) 0x479fb4 ADD	X16, X22, X16,LSL #3

      (2576) 0x479fb8 B	479fcc

0x479fbc HINT	#0

        (2578) 0x479fc0 SUBS	X6, X6, #1

        (2578) 0x479fc4 ADD	X16, X16, #8

        (2578) 0x479fc8 B.EQ	47a000

        (2578) 0x479fcc LDR	X22, [X7], #8

        (2578) 0x479fd0 CMP	X22, X3

        (2578) 0x479fd4 CCMP	X22, X9, #8, #1

        (2578) 0x479fd8 CCMP	X22, X10, #0, #10

        (2578) 0x479fdc B.LT	479fc0

        (2578) 0x479fe0 LDR	X22, [X17, X22,LSL #3]

        (2578) 0x479fe4 CMP	X5, X22

        (2578) 0x479fe8 B.NE	479fc0

        (2578) 0x479fec LDR	D1, [X16]

        (2578) 0x479ff0 FABS	D1, D1

        (2578) 0x479ff4 FADD	D0, D0, D1

        (2578) 0x479ff8 STR	D0, [X11, X3,LSL #3]

        (2578) 0x479ffc B	479fc0

      (2576) 0x47a000 CBZ	X14, 479f80

      (2576) 0x47a004 LDR	X6, [X15, X3,LSL #3]

      (2576) 0x47a008 LDR	X16, [X15, X2,LSL #3]

      (2576) 0x47a00c CMP	X16, X6

      (2576) 0x47a010 B.LE	479f80

      (2576) 0x47a014 LDR	X7, [X28]

      (2576) 0x47a018 SUB	W22, W16, W6

      (2576) 0x47a01c TBNZ	W22, #0, 47a034

      (2576) 0x47a020 ORR	X22, XZR, X6

      (2576) 0x47a024 ADD	X6, X6, #1

      (2576) 0x47a028 CMP	X16, X6

      (2576) 0x47a02c B.EQ	479f80

      (2576) 0x47a030 B	47a064

      (2576) 0x47a034 LDR	X22, [X0, X6,LSL #3]

      (2576) 0x47a038 LDR	X22, [X18, X22,LSL #3]

      (2576) 0x47a03c CMP	X5, X22

      (2576) 0x47a040 B.NE	47a054

      (2576) 0x47a044 LDR	D1, [X7, X6,LSL #3]

      (2576) 0x47a048 FABS	D1, D1

      (2576) 0x47a04c FADD	D0, D0, D1

      (2576) 0x47a050 STR	D0, [X11, X3,LSL #3]

      (2576) 0x47a054 ADD	X22, X6, #1

      (2576) 0x47a058 ADD	X6, X6, #1

      (2576) 0x47a05c CMP	X16, X6

      (2576) 0x47a060 B.EQ	479f80

      (2576) 0x47a064 ADD	X7, X7, X22,LSL #3

      (2576) 0x47a068 SUB	X16, X16, X22

      (2576) 0x47a06c ADD	X6, X1, X22,LSL #3

      (2576) 0x47a070 ADD	X7, X7, #8

      (2576) 0x47a074 B	47a08c

0x47a078 HINT	#0

0x47a07c HINT	#0

        (2577) 0x47a080 SUBS	X16, X16, #2

        (2577) 0x47a084 ADD	X7, X7, #16

        (2577) 0x47a088 B.EQ	479f80

        (2577) 0x47a08c LDUR	X22, [X6, #504]

        (2577) 0x47a090 LDR	X22, [X18, X22,LSL #3]

        (2577) 0x47a094 CMP	X5, X22

        (2577) 0x47a098 B.NE	47a0c0

        (2577) 0x47a09c LDUR	D1, [X7, #504]

        (2577) 0x47a0a0 FABS	D1, D1

        (2577) 0x47a0a4 FADD	D0, D0, D1

        (2577) 0x47a0a8 STR	D0, [X11, X3,LSL #3]

        (2577) 0x47a0ac LDR	X22, [X6], #16

        (2577) 0x47a0b0 LDR	X22, [X18, X22,LSL #3]

        (2577) 0x47a0b4 CMP	X5, X22

        (2577) 0x47a0b8 B.NE	47a080

        (2577) 0x47a0bc B	47a0d0

        (2577) 0x47a0c0 LDR	X22, [X6], #16

        (2577) 0x47a0c4 LDR	X22, [X18, X22,LSL #3]

        (2577) 0x47a0c8 CMP	X5, X22

        (2577) 0x47a0cc B.NE	47a080

        (2577) 0x47a0d0 LDR	D1, [X7]

        (2577) 0x47a0d4 FABS	D1, D1

        (2577) 0x47a0d8 FADD	D0, D0, D1

        (2577) 0x47a0dc STR	D0, [X11, X3,LSL #3]

        (2577) 0x47a0e0 B	47a080

    (2548) 0x47a0e4 CMP	X11, #3

    (2548) 0x47a0e8 B.EQ	47a60c

    (2548) 0x47a0ec CMP	X11, #4

    (2548) 0x47a0f0 B.NE	47a828

    (2548) 0x47a0f4 CMP	X10, X9

    (2548) 0x47a0f8 B.LE	47a828

    (2548) 0x47a0fc LDP	X18, X14, [SP, #40]

    (2548) 0x47a100 LDP	X12, X15, [SP, #64]

    (2548) 0x47a104 ORR	X3, XZR, X9

    (2548) 0x47a108 LDR	X17, [SP, #32]

    (2548) 0x47a10c LDR	X0, [X28]

    (2548) 0x47a110 ADD	X2, X0, #16

    (2548) 0x47a114 LDP	X16, X13, [SP, #80]

    (2548) 0x47a118 LDR	X18, [X18]

    (2548) 0x47a11c LDR	X11, [X21]

    (2548) 0x47a120 LDR	X12, [X12]

    (2548) 0x47a124 LDR	X13, [X13]

    (2548) 0x47a128 LDR	X14, [X14]

    (2548) 0x47a12c LDR	X15, [X15]

    (2548) 0x47a130 LDR	X16, [X16]

    (2548) 0x47a134 ADD	X1, X18, #8

    (2548) 0x47a138 LDR	X17, [X17]

    (2548) 0x47a13c B	47a14c

      (2555) 0x47a140 ADD	X3, X3, #1

      (2555) 0x47a144 CMP	X3, X10

      (2555) 0x47a148 B.EQ	47a828

      (2555) 0x47a14c STR	XZR, [X11, X3,LSL #3]

      (2555) 0x47a150 CBZ	X12, 47a220

      (2555) 0x47a154 ADD	X5, X3, #1

      (2555) 0x47a158 LDR	X22, [X13, X3,LSL #3]

      (2555) 0x47a15c LDR	X4, [X12, X3,LSL #3]

      (2555) 0x47a160 MOVI	D0, #0

      (2555) 0x47a164 LDR	X6, [X13, X5,LSL #3]

      (2555) 0x47a168 SUBS	X6, X6, X22

      (2555) 0x47a16c B.LE	47a1e0

      (2555) 0x47a170 LDR	X23, [X26]

      (2555) 0x47a174 ADD	X7, X14, X22,LSL #3

      (2555) 0x47a178 ADD	X30, X23, X22,LSL #3

      (2555) 0x47a17c B	47a18c

        (2560) 0x47a180 SUBS	X6, X6, #1

        (2560) 0x47a184 ADD	X30, X30, #8

        (2560) 0x47a188 B.EQ	47a1e0

        (2560) 0x47a18c LDR	X22, [X7], #8

        (2560) 0x47a190 CMP	X22, X3

        (2560) 0x47a194 CCMP	X22, X9, #8, #1

        (2560) 0x47a198 CCMP	X22, X10, #0, #10

        (2560) 0x47a19c B.LT	47a180

        (2560) 0x47a1a0 LDR	X23, [X12, X22,LSL #3]

        (2560) 0x47a1a4 CMP	X4, X23

        (2560) 0x47a1a8 B.NE	47a180

        (2560) 0x47a1ac LDR	D1, [X30]

        (2560) 0x47a1b0 CMP	X22, X3

        (2560) 0x47a1b4 FABS	D1, D1

        (2560) 0x47a1b8 FMADD	D2, D1, D8, D0

        (2560) 0x47a1bc FADD	D0, D0, D1

        (2560) 0x47a1c0 FCSEL	D9, D9, D1, #1

        (2560) 0x47a1c4 FCSEL	D0, D2, D0, #1

        (2560) 0x47a1c8 STR	D0, [X11, X3,LSL #3]

        (2560) 0x47a1cc B	47a180

0x47a1d0 HINT	#0

0x47a1d4 HINT	#0

0x47a1d8 HINT	#0

0x47a1dc HINT	#0

      (2555) 0x47a1e0 CBZ	X15, 47a360

      (2555) 0x47a1e4 LDR	X6, [X16, X3,LSL #3]

      (2555) 0x47a1e8 LDR	X5, [X16, X5,LSL #3]

      (2555) 0x47a1ec CMP	X5, X6

      (2555) 0x47a1f0 B.LE	47a360

      (2555) 0x47a1f4 LDR	X7, [X28]

      (2555) 0x47a1f8 SUB	W22, W5, W6

      (2555) 0x47a1fc TBNZ	W22, #0, 47a330

      (2555) 0x47a200 ORR	X22, XZR, X6

      (2555) 0x47a204 ADD	X6, X6, #1

      (2555) 0x47a208 CMP	X5, X6

      (2555) 0x47a20c B.EQ	47a360

      (2555) 0x47a210 B	47a378

0x47a214 HINT	#0

0x47a218 HINT	#0

0x47a21c HINT	#0

      (2555) 0x47a220 ADD	X4, X3, #1

      (2555) 0x47a224 LDR	X7, [X13, X3,LSL #3]

      (2555) 0x47a228 MOVI	D0, #0

      (2555) 0x47a22c LDR	X5, [X13, X4,LSL #3]

      (2555) 0x47a230 SUBS	X5, X5, X7

      (2555) 0x47a234 B.LE	47a28c

      (2555) 0x47a238 LDR	X22, [X26]

      (2555) 0x47a23c ADD	X6, X14, X7,LSL #3

      (2555) 0x47a240 ADD	X7, X22, X7,LSL #3

      (2555) 0x47a244 B	47a254

        (2558) 0x47a248 ADD	X7, X7, #8

        (2558) 0x47a24c SUBS	X5, X5, #1

        (2558) 0x47a250 B.EQ	47a28c

        (2558) 0x47a254 LDR	X22, [X6], #8

        (2558) 0x47a258 CMP	X22, X3

        (2558) 0x47a25c CCMP	X22, X9, #8, #1

        (2558) 0x47a260 CCMP	X22, X10, #0, #10

        (2558) 0x47a264 B.LT	47a248

        (2558) 0x47a268 LDR	D1, [X7]

        (2558) 0x47a26c CMP	X22, X3

        (2558) 0x47a270 FABS	D1, D1

        (2558) 0x47a274 FMADD	D2, D1, D8, D0

        (2558) 0x47a278 FADD	D0, D0, D1

        (2558) 0x47a27c FCSEL	D9, D9, D1, #1

        (2558) 0x47a280 FCSEL	D0, D2, D0, #1

        (2558) 0x47a284 STR	D0, [X11, X3,LSL #3]

        (2558) 0x47a288 B	47a248

      (2555) 0x47a28c CBZ	X15, 47a360

      (2555) 0x47a290 LDR	X5, [X16, X3,LSL #3]

      (2555) 0x47a294 LDR	X4, [X16, X4,LSL #3]

      (2555) 0x47a298 SUBS	X6, X5, X4

      (2555) 0x47a29c B.GE	47a360

      (2555) 0x47a2a0 SUB	W7, W4, W5

      (2555) 0x47a2a4 ANDS	X7, X7, #0x3

      (2555) 0x47a2a8 B.EQ	47a2c8

        (2557) 0x47a2ac LDR	D1, [X0, X5,LSL #3]

        (2557) 0x47a2b0 ADD	X5, X5, #1

        (2557) 0x47a2b4 SUBS	X7, X7, #1

        (2557) 0x47a2b8 FABS	D1, D1

        (2557) 0x47a2bc FMADD	D0, D1, D8, D0

        (2557) 0x47a2c0 STR	D0, [X11, X3,LSL #3]

        (2557) 0x47a2c4 B.NE	47a2ac

      (2555) 0x47a2c8 CMN	X6, #4

      (2555) 0x47a2cc B.HI	47a360

      (2555) 0x47a2d0 SUB	X4, X4, X5

      (2555) 0x47a2d4 ADD	X5, X2, X5,LSL #3

      (2555) 0x47a2d8 HINT	#0

      (2555) 0x47a2dc HINT	#0

        (2556) 0x47a2e0 LDUR	D1, [X5, #496]

        (2556) 0x47a2e4 SUBS	X4, X4, #4

        (2556) 0x47a2e8 FABS	D1, D1

        (2556) 0x47a2ec FMADD	D0, D1, D8, D0

        (2556) 0x47a2f0 STR	D0, [X11, X3,LSL #3]

        (2556) 0x47a2f4 LDUR	D1, [X5, #504]

        (2556) 0x47a2f8 FABS	D1, D1

        (2556) 0x47a2fc FMADD	D0, D1, D8, D0

        (2556) 0x47a300 STR	D0, [X11, X3,LSL #3]

        (2556) 0x47a304 LDR	D1, [X5]

        (2556) 0x47a308 FABS	D1, D1

        (2556) 0x47a30c FMADD	D0, D1, D8, D0

        (2556) 0x47a310 STR	D0, [X11, X3,LSL #3]

        (2556) 0x47a314 LDR	D1, [X5, #8]

        (2556) 0x47a318 ADD	X5, X5, #32

        (2556) 0x47a31c FABS	D1, D1

        (2556) 0x47a320 FMADD	D0, D1, D8, D0

        (2556) 0x47a324 STR	D0, [X11, X3,LSL #3]

        (2556) 0x47a328 B.NE	47a2e0

      (2555) 0x47a32c B	47a360

      (2555) 0x47a330 LDR	X22, [X18, X6,LSL #3]

      (2555) 0x47a334 LDR	X22, [X17, X22,LSL #3]

      (2555) 0x47a338 CMP	X4, X22

      (2555) 0x47a33c B.NE	47a350

      (2555) 0x47a340 LDR	D1, [X7, X6,LSL #3]

      (2555) 0x47a344 FABS	D1, D1

      (2555) 0x47a348 FMADD	D0, D1, D8, D0

      (2555) 0x47a34c STR	D0, [X11, X3,LSL #3]

      (2555) 0x47a350 ADD	X22, X6, #1

      (2555) 0x47a354 ADD	X6, X6, #1

      (2555) 0x47a358 CMP	X5, X6

      (2555) 0x47a35c B.NE	47a378

      (2555) 0x47a360 FMOV	D1, X19

      (2555) 0x47a364 FMUL	D1, D9, D1

      (2555) 0x47a368 FCMP	D0, D1

      (2555) 0x47a36c B.HI	47a140

      (2555) 0x47a370 STR	D9, [X11, X3,LSL #3]

      (2555) 0x47a374 B	47a140

      (2555) 0x47a378 ADD	X7, X7, X22,LSL #3

      (2555) 0x47a37c SUB	X5, X5, X22

      (2555) 0x47a380 ADD	X6, X1, X22,LSL #3

      (2555) 0x47a384 ADD	X7, X7, #8

      (2555) 0x47a388 B	47a398

        (2559) 0x47a38c SUBS	X5, X5, #2

        (2559) 0x47a390 ADD	X7, X7, #16

        (2559) 0x47a394 B.EQ	47a360

        (2559) 0x47a398 LDUR	X22, [X6, #504]

        (2559) 0x47a39c LDR	X22, [X17, X22,LSL #3]

        (2559) 0x47a3a0 CMP	X4, X22

        (2559) 0x47a3a4 B.NE	47a3cc

        (2559) 0x47a3a8 LDUR	D1, [X7, #504]

        (2559) 0x47a3ac FABS	D1, D1

        (2559) 0x47a3b0 FMADD	D0, D1, D8, D0

        (2559) 0x47a3b4 STR	D0, [X11, X3,LSL #3]

        (2559) 0x47a3b8 LDR	X22, [X6], #16

        (2559) 0x47a3bc LDR	X22, [X17, X22,LSL #3]

        (2559) 0x47a3c0 CMP	X4, X22

        (2559) 0x47a3c4 B.NE	47a38c

        (2559) 0x47a3c8 B	47a3dc

        (2559) 0x47a3cc LDR	X22, [X6], #16

        (2559) 0x47a3d0 LDR	X22, [X17, X22,LSL #3]

        (2559) 0x47a3d4 CMP	X4, X22

        (2559) 0x47a3d8 B.NE	47a38c

        (2559) 0x47a3dc LDR	D1, [X7]

        (2559) 0x47a3e0 FABS	D1, D1

        (2559) 0x47a3e4 FMADD	D0, D1, D8, D0

        (2559) 0x47a3e8 STR	D0, [X11, X3,LSL #3]

        (2559) 0x47a3ec B	47a38c

    (2548) 0x47a3f0 CMP	X10, X9

    (2548) 0x47a3f4 B.LE	47a828

    (2548) 0x47a3f8 LDP	X12, X13, [SP, #64]

    (2548) 0x47a3fc LDR	X11, [X21]

    (2548) 0x47a400 LDR	X16, [X12]

    (2548) 0x47a404 LDP	X14, X12, [SP, #80]

    (2548) 0x47a408 LDR	X13, [X13]

    (2548) 0x47a40c LDR	X12, [X12]

    (2548) 0x47a410 LDR	X14, [X14]

    (2548) 0x47a414 LDR	X15, [X12, X9,LSL #3]

    (2548) 0x47a418 CBZ	X16, 47ab98

    (2548) 0x47a41c LDP	X0, X17, [SP, #40]

    (2548) 0x47a420 LDR	X18, [SP, #32]

    (2548) 0x47a424 ORR	X3, XZR, X9

    (2548) 0x47a428 LDR	X17, [X17]

    (2548) 0x47a42c LDR	X0, [X0]

    (2548) 0x47a430 LDR	X18, [X18]

    (2548) 0x47a434 ADD	X1, X17, #8

    (2548) 0x47a438 ADD	X2, X0, #8

    (2548) 0x47a43c B	47a448

      (2567) 0x47a440 CMP	X3, X10

      (2567) 0x47a444 B.EQ	47a828

      (2567) 0x47a448 ORR	X4, XZR, X3

      (2567) 0x47a44c STR	XZR, [X11, X3,LSL #3]

      (2567) 0x47a450 LDR	X5, [X16, X3,LSL #3]

      (2567) 0x47a454 ADD	X3, X3, #1

      (2567) 0x47a458 ORR	X6, XZR, X15

      (2567) 0x47a45c MOVI	D0, #0

      (2567) 0x47a460 LDR	X15, [X12, X3,LSL #3]

      (2567) 0x47a464 CMP	X15, X6

      (2567) 0x47a468 B.LE	47a4a8

      (2567) 0x47a46c LDR	X30, [X26]

      (2567) 0x47a470 SUB	W7, W15, W6

      (2567) 0x47a474 ORR	X22, XZR, X6

      (2567) 0x47a478 TBZ	W7, #0, 47a49c

      (2567) 0x47a47c LDR	X7, [X17, X6,LSL #3]

      (2567) 0x47a480 LDR	X7, [X16, X7,LSL #3]

      (2567) 0x47a484 CMP	X5, X7

      (2567) 0x47a488 B.NE	47a498

      (2567) 0x47a48c LDR	D0, [X30, X6,LSL #3]

      (2567) 0x47a490 FABS	D0, D0

      (2567) 0x47a494 STR	D0, [X11, X4,LSL #3]

      (2567) 0x47a498 ADD	X22, X6, #1

      (2567) 0x47a49c ADD	X6, X6, #1

      (2567) 0x47a4a0 CMP	X15, X6

      (2567) 0x47a4a4 B.NE	47a4e0

      (2567) 0x47a4a8 CBZ	X13, 47a440

      (2567) 0x47a4ac LDR	X7, [X14, X4,LSL #3]

      (2567) 0x47a4b0 LDR	X6, [X14, X3,LSL #3]

      (2567) 0x47a4b4 CMP	X6, X7

      (2567) 0x47a4b8 B.LE	47a440

      (2567) 0x47a4bc LDR	X30, [X28]

      (2567) 0x47a4c0 SUB	W22, W6, W7

      (2567) 0x47a4c4 TBNZ	W22, #0, 47a564

      (2567) 0x47a4c8 ORR	X22, XZR, X7

      (2567) 0x47a4cc ADD	X7, X7, #1

      (2567) 0x47a4d0 CMP	X6, X7

      (2567) 0x47a4d4 B.EQ	47a440

      (2567) 0x47a4d8 B	47a594

0x47a4dc HINT	#0

      (2567) 0x47a4e0 SUB	X6, X15, X22

      (2567) 0x47a4e4 ADD	X7, X1, X22,LSL #3

      (2567) 0x47a4e8 ADD	X22, X30, X22,LSL #3

      (2567) 0x47a4ec ADD	X30, X22, #8

      (2567) 0x47a4f0 B	47a50c

0x47a4f4 HINT	#0

0x47a4f8 HINT	#0

0x47a4fc HINT	#0

        (2569) 0x47a500 SUBS	X6, X6, #2

        (2569) 0x47a504 ADD	X30, X30, #16

        (2569) 0x47a508 B.EQ	47a4a8

        (2569) 0x47a50c LDUR	X22, [X7, #504]

        (2569) 0x47a510 LDR	X22, [X16, X22,LSL #3]

        (2569) 0x47a514 CMP	X5, X22

        (2569) 0x47a518 B.NE	47a540

        (2569) 0x47a51c LDUR	D1, [X30, #504]

        (2569) 0x47a520 FABS	D1, D1

        (2569) 0x47a524 FADD	D0, D0, D1

        (2569) 0x47a528 STR	D0, [X11, X4,LSL #3]

        (2569) 0x47a52c LDR	X22, [X7], #16

        (2569) 0x47a530 LDR	X22, [X16, X22,LSL #3]

        (2569) 0x47a534 CMP	X5, X22

        (2569) 0x47a538 B.NE	47a500

        (2569) 0x47a53c B	47a550

        (2569) 0x47a540 LDR	X22, [X7], #16

        (2569) 0x47a544 LDR	X22, [X16, X22,LSL #3]

        (2569) 0x47a548 CMP	X5, X22

        (2569) 0x47a54c B.NE	47a500

        (2569) 0x47a550 LDR	D1, [X30]

        (2569) 0x47a554 FABS	D1, D1

        (2569) 0x47a558 FADD	D0, D0, D1

        (2569) 0x47a55c STR	D0, [X11, X4,LSL #3]

        (2569) 0x47a560 B	47a500

      (2567) 0x47a564 LDR	X22, [X0, X7,LSL #3]

      (2567) 0x47a568 LDR	X22, [X18, X22,LSL #3]

      (2567) 0x47a56c CMP	X5, X22

      (2567) 0x47a570 B.NE	47a584

      (2567) 0x47a574 LDR	D1, [X30, X7,LSL #3]

      (2567) 0x47a578 FABS	D1, D1

      (2567) 0x47a57c FADD	D0, D0, D1

      (2567) 0x47a580 STR	D0, [X11, X4,LSL #3]

      (2567) 0x47a584 ADD	X22, X7, #1

      (2567) 0x47a588 ADD	X7, X7, #1

      (2567) 0x47a58c CMP	X6, X7

      (2567) 0x47a590 B.EQ	47a440

      (2567) 0x47a594 SUB	X6, X6, X22

      (2567) 0x47a598 ADD	X7, X2, X22,LSL #3

      (2567) 0x47a59c ADD	X22, X30, X22,LSL #3

      (2567) 0x47a5a0 ADD	X30, X22, #8

      (2567) 0x47a5a4 B	47a5b4

        (2568) 0x47a5a8 SUBS	X6, X6, #2

        (2568) 0x47a5ac ADD	X30, X30, #16

        (2568) 0x47a5b0 B.EQ	47a440

        (2568) 0x47a5b4 LDUR	X22, [X7, #504]

        (2568) 0x47a5b8 LDR	X22, [X18, X22,LSL #3]

        (2568) 0x47a5bc CMP	X5, X22

        (2568) 0x47a5c0 B.NE	47a5e8

        (2568) 0x47a5c4 LDUR	D1, [X30, #504]

        (2568) 0x47a5c8 FABS	D1, D1

        (2568) 0x47a5cc FADD	D0, D0, D1

        (2568) 0x47a5d0 STR	D0, [X11, X4,LSL #3]

        (2568) 0x47a5d4 LDR	X22, [X7], #16

        (2568) 0x47a5d8 LDR	X22, [X18, X22,LSL #3]

        (2568) 0x47a5dc CMP	X5, X22

        (2568) 0x47a5e0 B.NE	47a5a8

        (2568) 0x47a5e4 B	47a5f8

        (2568) 0x47a5e8 LDR	X22, [X7], #16

        (2568) 0x47a5ec LDR	X22, [X18, X22,LSL #3]

        (2568) 0x47a5f0 CMP	X5, X22

        (2568) 0x47a5f4 B.NE	47a5a8

        (2568) 0x47a5f8 LDR	D1, [X30]

        (2568) 0x47a5fc FABS	D1, D1

        (2568) 0x47a600 FADD	D0, D0, D1

        (2568) 0x47a604 STR	D0, [X11, X4,LSL #3]

        (2568) 0x47a608 B	47a5a8

    (2548) 0x47a60c CMP	X10, X9

    (2548) 0x47a610 B.LE	47a828

    (2548) 0x47a614 LDP	X15, X12, [SP, #80]

    (2548) 0x47a618 LDR	X14, [SP, #72]

    (2548) 0x47a61c UBFM	X0, X9, #61, #60

    (2548) 0x47a620 RDVL	X1, #1

    (2548) 0x47a624 ORR	X4, XZR, X9

    (2548) 0x47a628 LDR	X11, [X21]

    (2548) 0x47a62c ORR	X21, XZR, X8

    (2548) 0x47a630 LDR	X13, [X26]

    (2548) 0x47a634 LDR	X16, [X28]

    (2548) 0x47a638 ADD	X17, X11, X9,LSL #3

    (2548) 0x47a63c LDR	X12, [X12]

    (2548) 0x47a640 LDR	X14, [X14]

    (2548) 0x47a644 LDR	X15, [X15]

    (2548) 0x47a648 ADD	X18, X11, X10,LSL #3

    (2548) 0x47a64c ADD	X8, X16, X1

    (2548) 0x47a650 ADD	X2, X16, #16

    (2548) 0x47a654 STR	X8, [SP, #56]

    (2548) 0x47a658 ORR	X8, XZR, X21

    (2548) 0x47a65c LDR	X3, [X12, X0]

    (2548) 0x47a660 ADD	X0, X13, #16

    (2548) 0x47a664 B	47a670

      (2549) 0x47a668 CMP	X4, X10

      (2549) 0x47a66c B.EQ	47a824

      (2549) 0x47a670 ORR	X5, XZR, X4

      (2549) 0x47a674 STR	XZR, [X11, X4,LSL #3]

      (2549) 0x47a678 ADD	X4, X4, #1

      (2549) 0x47a67c ORR	X6, XZR, X3

      (2549) 0x47a680 MOVI	D0, #0

      (2549) 0x47a684 LDR	X3, [X12, X4,LSL #3]

      (2549) 0x47a688 SUBS	X7, X6, X3

      (2549) 0x47a68c B.GE	47a704

      (2549) 0x47a690 SUB	W1, W3, W6

      (2549) 0x47a694 MOVI	D0, #0

      (2549) 0x47a698 ANDS	X1, X1, #0x3

      (2549) 0x47a69c B.EQ	47a6b8

        (2554) 0x47a6a0 LDR	D1, [X13, X6,LSL #3]

        (2554) 0x47a6a4 ADD	X6, X6, #1

        (2554) 0x47a6a8 SUBS	X1, X1, #1

        (2554) 0x47a6ac FMADD	D0, D1, D1, D0

        (2554) 0x47a6b0 STR	D0, [X11, X5,LSL #3]

        (2554) 0x47a6b4 B.NE	47a6a0

      (2549) 0x47a6b8 CMN	X7, #4

      (2549) 0x47a6bc B.HI	47a704

      (2549) 0x47a6c0 SUB	X7, X3, X6

      (2549) 0x47a6c4 ADD	X6, X0, X6,LSL #3

        (2553) 0x47a6c8 LDUR	D1, [X6, #496]

        (2553) 0x47a6cc SUBS	X7, X7, #4

        (2553) 0x47a6d0 FMADD	D0, D1, D1, D0

        (2553) 0x47a6d4 STR	D0, [X11, X5,LSL #3]

        (2553) 0x47a6d8 LDUR	D1, [X6, #504]

        (2553) 0x47a6dc FMADD	D0, D1, D1, D0

        (2553) 0x47a6e0 STR	D0, [X11, X5,LSL #3]

        (2553) 0x47a6e4 LDR	D1, [X6]

        (2553) 0x47a6e8 FMADD	D0, D1, D1, D0

        (2553) 0x47a6ec STR	D0, [X11, X5,LSL #3]

        (2553) 0x47a6f0 LDR	D1, [X6, #8]

        (2553) 0x47a6f4 ADD	X6, X6, #32

        (2553) 0x47a6f8 FMADD	D0, D1, D1, D0

        (2553) 0x47a6fc STR	D0, [X11, X5,LSL #3]

        (2553) 0x47a700 B.NE	47a6c8

      (2549) 0x47a704 CBZ	X14, 47a668

      (2549) 0x47a708 LDR	X1, [X15, X5,LSL #3]

      (2549) 0x47a70c LDR	X6, [X15, X4,LSL #3]

      (2549) 0x47a710 SUBS	X30, X6, X1

      (2549) 0x47a714 B.LE	47a668

      (2549) 0x47a718 CMP	X30, X20

      (2549) 0x47a71c B.CC	47a80c

      (2549) 0x47a720 ADD	X7, X16, X6,LSL #3

      (2549) 0x47a724 ADD	X22, X16, X1,LSL #3

      (2549) 0x47a728 CMP	X17, X7

      (2549) 0x47a72c CCMP	X22, X18, #2, #3

      (2549) 0x47a730 B.CC	47a80c

      (2549) 0x47a734 LDR	X8, [SP, #56]

      (2549) 0x47a738 SUB	X7, XZR, X25

      (2549) 0x47a73c ORR	X24, XZR, XZR

      (2549) 0x47a740 AND	X23, X30, X7

      (2549) 0x47a744 ADD	X7, X1, X23

      (2549) 0x47a748 ADD	X1, X8, X1,LSL #3

        (2552) 0x47a74c LD1D	{Z1.D}, P0/Z, [X22, X24,LSL #3]

        (2552) 0x47a750 LD1D	{Z2.D}, P0/Z, [X1, X24,LSL #3]

        (2552) 0x47a754 ADD	X24, X24, X25

        (2552) 0x47a758 CMP	X23, X24

        (2552) 0x47a75c FMUL	Z1.D, Z1.D, Z1.D

        (2552) 0x47a760 FMUL	Z2.D, Z2.D, Z2.D

        (2552) 0x47a764 FADDA	D0, P0, D0, Z1.D

        (2552) 0x47a768 FADDA	D0, P0, D0, Z2.D

        (2552) 0x47a76c B.NE	47a74c

      (2549) 0x47a770 CMP	X30, X23

      (2549) 0x47a774 STR	D0, [X11, X5,LSL #3]

      (2549) 0x47a778 ORR	X8, XZR, X21

      (2549) 0x47a77c B.EQ	47a668

      (2549) 0x47a780 SUB	W1, W6, W7

      (2549) 0x47a784 ORR	X22, XZR, X7

      (2549) 0x47a788 ANDS	X1, X1, #0x3

      (2549) 0x47a78c B.EQ	47a7b8

      (2549) 0x47a790 HINT	#0

      (2549) 0x47a794 HINT	#0

      (2549) 0x47a798 HINT	#0

      (2549) 0x47a79c HINT	#0

        (2550) 0x47a7a0 LDR	D1, [X16, X22,LSL #3]

        (2550) 0x47a7a4 ADD	X22, X22, #1

        (2550) 0x47a7a8 SUBS	X1, X1, #1

        (2550) 0x47a7ac FMADD	D0, D1, D1, D0

        (2550) 0x47a7b0 STR	D0, [X11, X5,LSL #3]

        (2550) 0x47a7b4 B.NE	47a7a0

      (2549) 0x47a7b8 SUB	X1, X7, X6

      (2549) 0x47a7bc CMN	X1, #4

      (2549) 0x47a7c0 B.HI	47a668

      (2549) 0x47a7c4 SUB	X6, X6, X22

      (2549) 0x47a7c8 ADD	X7, X2, X22,LSL #3

        (2551) 0x47a7cc LDUR	D1, [X7, #496]

        (2551) 0x47a7d0 SUBS	X6, X6, #4

        (2551) 0x47a7d4 FMADD	D0, D1, D1, D0

        (2551) 0x47a7d8 STR	D0, [X11, X5,LSL #3]

        (2551) 0x47a7dc LDUR	D1, [X7, #504]

        (2551) 0x47a7e0 FMADD	D0, D1, D1, D0

        (2551) 0x47a7e4 STR	D0, [X11, X5,LSL #3]

        (2551) 0x47a7e8 LDR	D1, [X7]

        (2551) 0x47a7ec FMADD	D0, D1, D1, D0

        (2551) 0x47a7f0 STR	D0, [X11, X5,LSL #3]

        (2551) 0x47a7f4 LDR	D1, [X7, #8]

        (2551) 0x47a7f8 ADD	X7, X7, #32

        (2551) 0x47a7fc FMADD	D0, D1, D1, D0

        (2551) 0x47a800 STR	D0, [X11, X5,LSL #3]

        (2551) 0x47a804 B.NE	47a7cc

      (2549) 0x47a808 B	47a668

      (2549) 0x47a80c ORR	X7, XZR, X1

      (2549) 0x47a810 SUB	W1, W6, W7

      (2549) 0x47a814 ORR	X22, XZR, X7

      (2549) 0x47a818 ANDS	X1, X1, #0x3

      (2549) 0x47a81c B.NE	47a7a0

      (2549) 0x47a820 B	47a7b8

    (2548) 0x47a824 LDR	X21, [SP, #24]

    (2548) 0x47a828 SUBS	X11, X10, X9

    (2548) 0x47a82c B.LE	479ec4

    (2548) 0x47a830 LDR	X13, [SP, #88]

    (2548) 0x47a834 LDR	X12, [X26]

    (2548) 0x47a838 LDR	X14, [X21]

    (2548) 0x47a83c ORR	X15, XZR, X9

    (2548) 0x47a840 LDR	X13, [X13]

    (2548) 0x47a844 TBZ	W11, #0, 47a868

    (2548) 0x47a848 LDR	X15, [X13, X9,LSL #3]

    (2548) 0x47a84c LDR	D0, [X12, X15,LSL #3]

    (2548) 0x47a850 FCMP	D0, #0

    (2548) 0x47a854 B.PL	47a864

    (2548) 0x47a858 LDR	D0, [X14, X9,LSL #3]

    (2548) 0x47a85c FNEG	D0, D0

    (2548) 0x47a860 STR	D0, [X14, X9,LSL #3]

    (2548) 0x47a864 ADD	X15, X9, #1

    (2548) 0x47a868 ADD	X16, X9, #1

    (2548) 0x47a86c CMP	X10, X16

    (2548) 0x47a870 B.NE	47a8a0

    (2548) 0x47a874 LDR	X10, [X21]

    (2548) 0x47a878 ADD	X9, X10, X9,LSL #3

    (2548) 0x47a87c HINT	#0

      (2579) 0x47a880 LDR	D0, [X9], #8

      (2579) 0x47a884 FCMP	D0, #0

      (2579) 0x47a888 B.EQ	479ea4

      (2579) 0x47a88c SUBS	X11, X11, #1

      (2579) 0x47a890 B.NE	47a880

    (2548) 0x47a894 B	479ec4

0x47a898 HINT	#0

0x47a89c HINT	#0

    (2548) 0x47a8a0 ADD	X13, X13, X15,LSL #3

    (2548) 0x47a8a4 ADD	X14, X14, X15,LSL #3

    (2548) 0x47a8a8 SUB	X10, X10, X15

    (2548) 0x47a8ac ADD	X13, X13, #8

    (2548) 0x47a8b0 ADD	X14, X14, #8

    (2548) 0x47a8b4 B	47a8cc

0x47a8b8 HINT	#0

0x47a8bc HINT	#0

      (2580) 0x47a8c0 SUBS	X10, X10, #2

      (2580) 0x47a8c4 ADD	X14, X14, #16

      (2580) 0x47a8c8 B.EQ	47a874

      (2580) 0x47a8cc LDUR	X15, [X13, #504]

      (2580) 0x47a8d0 LDR	D0, [X12, X15,LSL #3]

      (2580) 0x47a8d4 FCMP	D0, #0

      (2580) 0x47a8d8 B.PL	47a900

      (2580) 0x47a8dc LDUR	D0, [X14, #504]

      (2580) 0x47a8e0 FNEG	D0, D0

      (2580) 0x47a8e4 STUR	D0, [X14, #504]

      (2580) 0x47a8e8 LDR	X15, [X13], #16

      (2580) 0x47a8ec LDR	D0, [X12, X15,LSL #3]

      (2580) 0x47a8f0 FCMP	D0, #0

      (2580) 0x47a8f4 B.PL	47a8c0

      (2580) 0x47a8f8 B	47a910

0x47a8fc HINT	#0

      (2580) 0x47a900 LDR	X15, [X13], #16

      (2580) 0x47a904 LDR	D0, [X12, X15,LSL #3]

      (2580) 0x47a908 FCMP	D0, #0

      (2580) 0x47a90c B.PL	47a8c0

      (2580) 0x47a910 LDR	D0, [X14]

      (2580) 0x47a914 FNEG	D0, D0

      (2580) 0x47a918 STR	D0, [X14]

      (2580) 0x47a91c B	47a8c0

  (2570) 0x47a920 LDR	X18, [X28]

  (2570) 0x47a924 RDVL	X2, #1

  (2570) 0x47a928 ADD	X17, X11, X9,LSL #3

  (2570) 0x47a92c ADD	X0, X11, X10,LSL #3

  (2570) 0x47a930 ADD	X1, X13, #8

  (2570) 0x47a934 ORR	X4, XZR, X9

  (2570) 0x47a938 ADD	X2, X18, X2

  (2570) 0x47a93c ADD	X3, X18, #16

  (2570) 0x47a940 STR	X2, [SP, #56]

  (2570) 0x47a944 B	47a950

  (2570) 0x47a948 CMP	X4, X10

  (2570) 0x47a94c B.EQ	47a828

  (2570) 0x47a950 ORR	X5, XZR, X4

  (2570) 0x47a954 STR	XZR, [X11, X4,LSL #3]

  (2570) 0x47a958 ADD	X4, X4, #1

  (2570) 0x47a95c ORR	X6, XZR, X16

  (2570) 0x47a960 MOVI	D0, #0

  (2570) 0x47a964 LDR	X16, [X12, X4,LSL #3]

  (2570) 0x47a968 CMP	X16, X6

  (2570) 0x47a96c B.LE	47a9b8

  (2570) 0x47a970 LDR	X7, [X26]

  (2570) 0x47a974 MOVI	D0, #0

  (2570) 0x47a978 SUB	W22, W16, W6

  (2570) 0x47a97c ORR	X2, XZR, X6

  (2570) 0x47a980 TBZ	W22, #0, 47a9ac

  (2570) 0x47a984 LDR	X2, [X13, X6,LSL #3]

  (2570) 0x47a988 MOVI	D0, #0

  (2570) 0x47a98c CMP	X2, X5

  (2570) 0x47a990 CCMP	X2, X9, #8, #1

  (2570) 0x47a994 CCMP	X2, X10, #0, #10

  (2570) 0x47a998 B.LT	47a9a8

  (2570) 0x47a99c LDR	D0, [X7, X6,LSL #3]

  (2570) 0x47a9a0 FABS	D0, D0

  (2570) 0x47a9a4 STR	D0, [X11, X5,LSL #3]

  (2570) 0x47a9a8 ADD	X2, X6, #1

  (2570) 0x47a9ac ADD	X6, X6, #1

  (2570) 0x47a9b0 CMP	X16, X6

  (2570) 0x47a9b4 B.NE	47aa8c

  (2570) 0x47a9b8 CBZ	X14, 47a948

  (2570) 0x47a9bc LDR	X24, [X15, X5,LSL #3]

  (2570) 0x47a9c0 LDR	X6, [X15, X4,LSL #3]

  (2570) 0x47a9c4 SUBS	X30, X6, X24

  (2570) 0x47a9c8 B.LE	47a948

  (2570) 0x47a9cc CMP	X30, X20

  (2570) 0x47a9d0 B.CC	47ab20

  (2570) 0x47a9d4 ADD	X2, X18, X6,LSL #3

  (2570) 0x47a9d8 ADD	X22, X18, X24,LSL #3

  (2570) 0x47a9dc CMP	X17, X2

  (2570) 0x47a9e0 CCMP	X22, X0, #2, #3

  (2570) 0x47a9e4 B.CC	47ab20

  (2570) 0x47a9e8 LDR	X3, [SP, #56]

  (2570) 0x47a9ec SUB	X7, XZR, X25

  (2570) 0x47a9f0 ORR	X2, XZR, XZR

  (2570) 0x47a9f4 AND	X23, X30, X7

  (2570) 0x47a9f8 ADD	X7, X24, X23

  (2570) 0x47a9fc ADD	X24, X3, X24,LSL #3

    (2572) 0x47aa00 LD1D	{Z1.D}, P0/Z, [X22, X2,LSL #3]

    (2572) 0x47aa04 LD1D	{Z2.D}, P0/Z, [X24, X2,LSL #3]

    (2572) 0x47aa08 ADD	X2, X2, X25

    (2572) 0x47aa0c CMP	X23, X2

    (2572) 0x47aa10 FABS	Z1.D, P0/M, Z1.D

    (2572) 0x47aa14 FABS	Z2.D, P0/M, Z2.D

    (2572) 0x47aa18 FADDA	D0, P0, D0, Z1.D

    (2572) 0x47aa1c FADDA	D0, P0, D0, Z2.D

    (2572) 0x47aa20 B.NE	47aa00

  (2570) 0x47aa24 CMP	X30, X23

  (2570) 0x47aa28 ADD	X3, X18, #16

  (2570) 0x47aa2c STR	D0, [X11, X5,LSL #3]

  (2570) 0x47aa30 B.EQ	47a948

  (2570) 0x47aa34 HINT	#0

  (2570) 0x47aa38 HINT	#0

  (2570) 0x47aa3c HINT	#0

  (2570) 0x47aa40 SUB	W2, W6, W7

  (2570) 0x47aa44 ANDS	X22, X2, #0x3

  (2570) 0x47aa48 B.EQ	47ab30

  (2574) 0x47aa4c ORR	X2, XZR, X7

  (2574) 0x47aa50 HINT	#0

  (2574) 0x47aa54 HINT	#0

  (2574) 0x47aa58 HINT	#0

  (2574) 0x47aa5c HINT	#0

  (2547) 0x47aa60 LDR	D1, [X18, X2,LSL #3]

  (2547) 0x47aa64 ADD	X2, X2, #1

  (2547) 0x47aa68 SUBS	X22, X22, #1

  (2547) 0x47aa6c FABS	D1, D1

  (2547) 0x47aa70 FADD	D0, D0, D1

  (2547) 0x47aa74 STR	D0, [X11, X5,LSL #3]

  (2547) 0x47aa78 B.NE	47aa60

(2571) 0x47aa7c SUB	X7, X7, X6

(2571) 0x47aa80 CMN	X7, #4

(2571) 0x47aa84 B.HI	47a948

(2571) 0x47aa88 B	47ab40

  (2570) 0x47aa8c ADD	X7, X7, X2,LSL #3

  (2570) 0x47aa90 SUB	X6, X16, X2

  (2570) 0x47aa94 ADD	X30, X1, X2,LSL #3

  (2570) 0x47aa98 ADD	X7, X7, #8

  (2570) 0x47aa9c B	47aaac

    (2575) 0x47aaa0 SUBS	X6, X6, #2

    (2575) 0x47aaa4 ADD	X7, X7, #16

    (2575) 0x47aaa8 B.EQ	47a9b8

    (2575) 0x47aaac LDUR	X2, [X30, #504]

    (2575) 0x47aab0 CMP	X2, X5

    (2575) 0x47aab4 CCMP	X2, X9, #8, #1

    (2575) 0x47aab8 CCMP	X2, X10, #0, #10

    (2575) 0x47aabc B.LT	47aae8

    (2575) 0x47aac0 LDUR	D1, [X7, #504]

    (2575) 0x47aac4 FABS	D1, D1

    (2575) 0x47aac8 FADD	D0, D0, D1

    (2575) 0x47aacc STR	D0, [X11, X5,LSL #3]

    (2575) 0x47aad0 LDR	X2, [X30], #16

    (2575) 0x47aad4 CMP	X2, X5

    (2575) 0x47aad8 CCMP	X2, X9, #8, #1

    (2575) 0x47aadc CCMP	X2, X10, #0, #10

    (2575) 0x47aae0 B.LT	47aaa0

    (2575) 0x47aae4 B	47aafc

    (2575) 0x47aae8 LDR	X2, [X30], #16

    (2575) 0x47aaec CMP	X2, X5

    (2575) 0x47aaf0 CCMP	X2, X9, #8, #1

    (2575) 0x47aaf4 CCMP	X2, X10, #0, #10

    (2575) 0x47aaf8 B.LT	47aaa0

    (2575) 0x47aafc LDR	D1, [X7]

    (2575) 0x47ab00 FABS	D1, D1

    (2575) 0x47ab04 FADD	D0, D0, D1

    (2575) 0x47ab08 STR	D0, [X11, X5,LSL #3]

    (2575) 0x47ab0c B	47aaa0

0x47ab10 HINT	#0

0x47ab14 HINT	#0

0x47ab18 HINT	#0

0x47ab1c HINT	#0

(2571) 0x47ab20 ORR	X7, XZR, X24

(2571) 0x47ab24 SUB	W2, W6, W7

(2571) 0x47ab28 ANDS	X22, X2, #0x3

(2571) 0x47ab2c B.NE	47aa4c

  (2570) 0x47ab30 ORR	X2, XZR, X7

  (2570) 0x47ab34 SUB	X7, X7, X6

  (2570) 0x47ab38 CMN	X7, #4

  (2570) 0x47ab3c B.HI	47a948

  (2570) 0x47ab40 SUB	X6, X6, X2

  (2570) 0x47ab44 ADD	X7, X3, X2,LSL #3

    (2573) 0x47ab48 LDUR	D1, [X7, #496]

    (2573) 0x47ab4c SUBS	X6, X6, #4

    (2573) 0x47ab50 FABS	D1, D1

    (2573) 0x47ab54 FADD	D0, D0, D1

    (2573) 0x47ab58 STR	D0, [X11, X5,LSL #3]

    (2573) 0x47ab5c LDUR	D1, [X7, #504]

    (2573) 0x47ab60 FABS	D1, D1

    (2573) 0x47ab64 FADD	D0, D0, D1

    (2573) 0x47ab68 STR	D0, [X11, X5,LSL #3]

    (2573) 0x47ab6c LDR	D1, [X7]

    (2573) 0x47ab70 FABS	D1, D1

    (2573) 0x47ab74 FADD	D0, D0, D1

    (2573) 0x47ab78 STR	D0, [X11, X5,LSL #3]

    (2573) 0x47ab7c LDR	D1, [X7, #8]

    (2573) 0x47ab80 ADD	X7, X7, #32

    (2573) 0x47ab84 FABS	D1, D1

    (2573) 0x47ab88 FADD	D0, D0, D1

    (2573) 0x47ab8c STR	D0, [X11, X5,LSL #3]

    (2573) 0x47ab90 B.NE	47ab48

  (2570) 0x47ab94 B	47a948

    (2548) 0x47ab98 LDR	X16, [X26]

    (2548) 0x47ab9c LDR	X0, [X28]

    (2548) 0x47aba0 RDVL	X2, #1

    (2548) 0x47aba4 ADD	X17, X11, X9,LSL #3

    (2548) 0x47aba8 ADD	X18, X11, X10,LSL #3

    (2548) 0x47abac ORR	X4, XZR, X9

    (2548) 0x47abb0 ADD	X1, X16, #16

    (2548) 0x47abb4 ADD	X2, X0, X2

    (2548) 0x47abb8 ADD	X3, X0, #16

    (2548) 0x47abbc STR	X2, [SP, #56]

    (2548) 0x47abc0 B	47abcc

      (2561) 0x47abc4 CMP	X4, X10

      (2561) 0x47abc8 B.EQ	47a828

      (2561) 0x47abcc ORR	X5, XZR, X4

      (2561) 0x47abd0 STR	XZR, [X11, X4,LSL #3]

      (2561) 0x47abd4 ADD	X4, X4, #1

      (2561) 0x47abd8 ORR	X6, XZR, X15

      (2561) 0x47abdc MOVI	D0, #0

      (2561) 0x47abe0 LDR	X15, [X12, X4,LSL #3]

      (2561) 0x47abe4 SUBS	X7, X6, X15

      (2561) 0x47abe8 B.GE	47ac78

      (2561) 0x47abec SUB	W2, W15, W6

      (2561) 0x47abf0 MOVI	D0, #0

      (2561) 0x47abf4 ANDS	X2, X2, #0x3

      (2561) 0x47abf8 B.EQ	47ac1c

      (2561) 0x47abfc HINT	#0

        (2566) 0x47ac00 LDR	D1, [X16, X6,LSL #3]

        (2566) 0x47ac04 ADD	X6, X6, #1

        (2566) 0x47ac08 SUBS	X2, X2, #1

        (2566) 0x47ac0c FABS	D1, D1

        (2566) 0x47ac10 FADD	D0, D0, D1

        (2566) 0x47ac14 STR	D0, [X11, X5,LSL #3]

        (2566) 0x47ac18 B.NE	47ac00

      (2561) 0x47ac1c CMN	X7, #4

      (2561) 0x47ac20 B.HI	47ac78

      (2561) 0x47ac24 SUB	X7, X15, X6

      (2561) 0x47ac28 ADD	X6, X1, X6,LSL #3

        (2565) 0x47ac2c LDUR	D1, [X6, #496]

        (2565) 0x47ac30 SUBS	X7, X7, #4

        (2565) 0x47ac34 FABS	D1, D1

        (2565) 0x47ac38 FADD	D0, D0, D1

        (2565) 0x47ac3c STR	D0, [X11, X5,LSL #3]

        (2565) 0x47ac40 LDUR	D1, [X6, #504]

        (2565) 0x47ac44 FABS	D1, D1

        (2565) 0x47ac48 FADD	D0, D0, D1

        (2565) 0x47ac4c STR	D0, [X11, X5,LSL #3]

        (2565) 0x47ac50 LDR	D1, [X6]

        (2565) 0x47ac54 FABS	D1, D1

        (2565) 0x47ac58 FADD	D0, D0, D1

        (2565) 0x47ac5c STR	D0, [X11, X5,LSL #3]

        (2565) 0x47ac60 LDR	D1, [X6, #8]

        (2565) 0x47ac64 ADD	X6, X6, #32

        (2565) 0x47ac68 FABS	D1, D1

        (2565) 0x47ac6c FADD	D0, D0, D1

        (2565) 0x47ac70 STR	D0, [X11, X5,LSL #3]

        (2565) 0x47ac74 B.NE	47ac2c

      (2561) 0x47ac78 CBZ	X13, 47abc4

      (2561) 0x47ac7c LDR	X24, [X14, X5,LSL #3]

      (2561) 0x47ac80 LDR	X6, [X14, X4,LSL #3]

      (2561) 0x47ac84 SUBS	X30, X6, X24

      (2561) 0x47ac88 B.LE	47abc4

      (2561) 0x47ac8c CMP	X30, X20

      (2561) 0x47ac90 B.CC	47ad4c

      (2561) 0x47ac94 ADD	X2, X0, X6,LSL #3

      (2561) 0x47ac98 ADD	X22, X0, X24,LSL #3

      (2561) 0x47ac9c CMP	X17, X2

      (2561) 0x47aca0 CCMP	X22, X18, #2, #3

      (2561) 0x47aca4 B.CC	47ad4c

      (2561) 0x47aca8 LDR	X3, [SP, #56]

      (2561) 0x47acac SUB	X7, XZR, X25

      (2561) 0x47acb0 ORR	X2, XZR, XZR

      (2561) 0x47acb4 AND	X23, X30, X7

      (2561) 0x47acb8 ADD	X7, X24, X23

      (2561) 0x47acbc ADD	X24, X3, X24,LSL #3

        (2564) 0x47acc0 LD1D	{Z1.D}, P0/Z, [X22, X2,LSL #3]

        (2564) 0x47acc4 LD1D	{Z2.D}, P0/Z, [X24, X2,LSL #3]

        (2564) 0x47acc8 ADD	X2, X2, X25

        (2564) 0x47accc CMP	X23, X2

        (2564) 0x47acd0 FABS	Z1.D, P0/M, Z1.D

        (2564) 0x47acd4 FABS	Z2.D, P0/M, Z2.D

        (2564) 0x47acd8 FADDA	D0, P0, D0, Z1.D

        (2564) 0x47acdc FADDA	D0, P0, D0, Z2.D

        (2564) 0x47ace0 B.NE	47acc0

      (2561) 0x47ace4 CMP	X30, X23

      (2561) 0x47ace8 ADD	X3, X0, #16

      (2561) 0x47acec STR	D0, [X11, X5,LSL #3]

      (2561) 0x47acf0 B.EQ	47abc4

      (2561) 0x47acf4 HINT	#0

      (2561) 0x47acf8 HINT	#0

      (2561) 0x47acfc HINT	#0

      (2561) 0x47ad00 SUB	W2, W6, W7

      (2561) 0x47ad04 ANDS	X22, X2, #0x3

      (2561) 0x47ad08 B.EQ	47ad5c

      (2561) 0x47ad0c ORR	X2, XZR, X7

      (2561) 0x47ad10 HINT	#0

      (2561) 0x47ad14 HINT	#0

      (2561) 0x47ad18 HINT	#0

      (2561) 0x47ad1c HINT	#0

        (2562) 0x47ad20 LDR	D1, [X0, X2,LSL #3]

        (2562) 0x47ad24 ADD	X2, X2, #1

        (2562) 0x47ad28 SUBS	X22, X22, #1

        (2562) 0x47ad2c FABS	D1, D1

        (2562) 0x47ad30 FADD	D0, D0, D1

        (2562) 0x47ad34 STR	D0, [X11, X5,LSL #3]

        (2562) 0x47ad38 B.NE	47ad20

      (2561) 0x47ad3c SUB	X7, X7, X6

      (2561) 0x47ad40 CMN	X7, #4

      (2561) 0x47ad44 B.HI	47abc4

      (2561) 0x47ad48 B	47ad6c

      (2561) 0x47ad4c ORR	X7, XZR, X24

      (2561) 0x47ad50 SUB	W2, W6, W7

      (2561) 0x47ad54 ANDS	X22, X2, #0x3

      (2561) 0x47ad58 B.NE	47ad0c

      (2561) 0x47ad5c ORR	X2, XZR, X7

      (2561) 0x47ad60 SUB	X7, X7, X6

      (2561) 0x47ad64 CMN	X7, #4

      (2561) 0x47ad68 B.HI	47abc4

      (2561) 0x47ad6c SUB	X6, X6, X2

      (2561) 0x47ad70 ADD	X7, X3, X2,LSL #3

      (2561) 0x47ad74 HINT	#0

      (2561) 0x47ad78 HINT	#0

      (2561) 0x47ad7c HINT	#0

        (2563) 0x47ad80 LDUR	D1, [X7, #496]

        (2563) 0x47ad84 SUBS	X6, X6, #4

        (2563) 0x47ad88 FABS	D1, D1

        (2563) 0x47ad8c FADD	D0, D0, D1

        (2563) 0x47ad90 STR	D0, [X11, X5,LSL #3]

        (2563) 0x47ad94 LDUR	D1, [X7, #504]

        (2563) 0x47ad98 FABS	D1, D1

        (2563) 0x47ad9c FADD	D0, D0, D1

        (2563) 0x47ada0 STR	D0, [X11, X5,LSL #3]

        (2563) 0x47ada4 LDR	D1, [X7]

        (2563) 0x47ada8 FABS	D1, D1

        (2563) 0x47adac FADD	D0, D0, D1

        (2563) 0x47adb0 STR	D0, [X11, X5,LSL #3]

        (2563) 0x47adb4 LDR	D1, [X7, #8]

        (2563) 0x47adb8 ADD	X7, X7, #32

        (2563) 0x47adbc FABS	D1, D1

        (2563) 0x47adc0 FADD	D0, D0, D1

        (2563) 0x47adc4 STR	D0, [X11, X5,LSL #3]

        (2563) 0x47adc8 B.NE	47ad80

      (2561) 0x47adcc B	47abc4

Coverage (%)	Name	Source Location	Module
►98.43+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.57+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_ParCSRComputeL1NormsThre[...]	ams.c:3546	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:1358	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	ams.c:3363-3540
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3363-3409,3416-3451,3458-3481,3493-3507,3517-3540.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.50 to 2.00 cycles (6.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 32% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 13.50 to 6.06 cycles (2.23x speedup).

Details

3% of VPU instructions are used in vector version (process two or more data elements in vector registers):

6% of VPU loads are used in vector version.
4% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3363
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3363

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 6 bytes. The binary function is storing 6 bytes.

General properties

nb instructions	99
nb uops	73
loop length	396
used w registers	6
used x registers	22
used b registers	0
used h registers	0
used s registers	1
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	25

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.13 cycles
front end	9.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	7.00	7.00	7.00	7.00	0.50	0.50	0.50	0.50	13.50	13.17	13.33	11.00	11.00
cycles	3.00	3.00	7.00	7.00	7.00	7.00	0.50	0.50	0.50	0.50	13.50	13.17	13.33	11.00	11.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.13
Dispatch	13.50
Overall L1	13.50

Vectorization ratios

INT

all	3%
load	6%
store	4%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	3%
load	6%
store	4%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	32%
load	35%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	28%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	32%
load	35%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.50 cycles. At this rate:

0% of peak load performance is reached (0.44 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.44 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 479d80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP D9, D8, [SP, #160]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X7, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUBS X19, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STP X3, X4, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X2, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LT 479e2c <hypre_ParCSRComputeL1NormsThreads.omp_outlined+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR X21, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <4eedcc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1104	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X3, X29, #52	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, XZR, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X4, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR WZR, [X29, #460]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W1, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 4103d0 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X27, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X8, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X8, X8, X19, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X27, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LE 479e50 <hypre_ParCSRComputeL1NormsThreads.omp_outlined+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <4eee20>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410150 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D9, D8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X26, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTW X25, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
FMOV D8, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR X19, XZR, #0x55	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X21, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVK X19, #16373	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
STR X9, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X9, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X9, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X9, X28, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X9, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X9, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP X25, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSEL X20, X25, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 479ed0 <hypre_ParCSRComputeL1NormsThreads.omp_outlined+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	ams.c:3363-3540
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3363-3409,3416-3451,3458-3481,3493-3507,3517-3540.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.50 to 2.00 cycles (6.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

3% of VPU instructions are used in vector version (process two or more data elements in vector registers):

6% of VPU loads are used in vector version.
4% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3363
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3363

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 6 bytes. The binary function is storing 6 bytes.

General properties

nb instructions	99
nb uops	73
loop length	396
used w registers	6
used x registers	22
used b registers	0
used h registers	0
used s registers	1
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	25

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.13 cycles
front end	9.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	7.00	7.00	7.00	7.00	0.50	0.50	0.50	0.50	13.50	13.17	13.33	11.00	11.00
cycles	3.00	3.00	7.00	7.00	7.00	7.00	0.50	0.50	0.50	0.50	13.50	13.17	13.33	11.00	11.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.13
Dispatch	13.50
Overall L1	13.50

Vectorization ratios

INT

all	3%
load	6%
store	4%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	3%
load	6%
store	4%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	32%
load	35%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	28%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	32%
load	35%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.50 cycles. At this rate:

0% of peak load performance is reached (0.44 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.44 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 479d80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP D9, D8, [SP, #160]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X7, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUBS X19, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STP X3, X4, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X2, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LT 479e2c <hypre_ParCSRComputeL1NormsThreads.omp_outlined+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR X21, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <4eedcc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1104	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X3, X29, #52	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, XZR, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X4, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X6, X29, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR WZR, [X29, #460]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W1, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 4103d0 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X27, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X8, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X8, X8, X19, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X27, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LE 479e50 <hypre_ParCSRComputeL1NormsThreads.omp_outlined+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <4eee20>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410150 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D9, D8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X23, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X26, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTW X25, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
FMOV D8, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR X19, XZR, #0x55	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X21, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVK X19, #16373	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
STR X9, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X9, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X9, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X9, X28, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X9, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X9, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP X25, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSEL X20, X25, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 479ed0 <hypre_ParCSRComputeL1NormsThreads.omp_outlined+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼hypre_ParCSRComputeL1NormsThreads.omp_outlined–	0.20	0.10
▼Loop 2571 - ams.c:3365-3540 - exec–	0.00	0.00
○Loop 2574 - ams.c:3431-3431 - exec	0.00	0.00
▼Loop 2570 - ams.c:3365-3540 - exec–	0.00	0.00
▼Loop 2548 - ams.c:3365-3540 - exec–	0.00	0.00
○Loop 2580 - ams.c:3532-3534 - exec	0.05	0.02
▼Loop 2561 - ams.c:3382-3394 - exec–	0.01	0.01
○Loop 2565 - ams.c:3388-3389 - exec	0.12	0.04
○Loop 2566 - ams.c:3388-3389 - exec	0.02	0.01
○Loop 2562 - ams.c:3393-3394 - exec	0.00	0.00
○Loop 2563 - ams.c:3393-3394 - exec	0.00	0.00
○Loop 2564 - ams.c:3393-3394 - exec	0.00	0.00
○Loop 2579 - ams.c:3536-3538 - exec	0.00	0.00
▼Loop 2576 - ams.c:3416-3451 - exec–	0.00	0.00
○Loop 2577 - ams.c:3449-3451 - exec	0.00	0.00
○Loop 2578 - ams.c:3439-3444 - exec	0.00	0.00
▼Loop 2567 - ams.c:3382-3409 - exec–	0.00	0.00
○Loop 2568 - ams.c:3407-3409 - exec	0.00	0.00
○Loop 2569 - ams.c:3401-3403 - exec	0.00	0.00
▼Loop 2555 - ams.c:3470-3527 - exec–	0.00	0.00
○Loop 2557 - ams.c:3493-3494 - exec	0.00	0.00
○Loop 2560 - ams.c:3501-3507 - exec	0.00	0.00
○Loop 2559 - ams.c:3519-3521 - exec	0.00	0.00
○Loop 2558 - ams.c:3476-3481 - exec	0.00	0.00
○Loop 2556 - ams.c:3493-3494 - exec	0.00	0.00
▼Loop 2549 - ams.c:3458-3465 - exec–	0.00	0.00
○Loop 2553 - ams.c:3461-3462 - exec	0.00	0.00
○Loop 2551 - ams.c:3464-3465 - exec	0.00	0.00
○Loop 2554 - ams.c:3461-3462 - exec	0.00	0.00
○Loop 2550 - ams.c:3464-3465 - exec	0.00	0.00
○Loop 2552 - ams.c:3464-3465 - exec	0.00	0.00
○Loop 2572 - ams.c:3431-3432 - exec	0.00	0.00
○Loop 2575 - ams.c:3422-3426 - exec	0.00	0.00
○Loop 2573 - ams.c:3431-3432 - exec	0.00	0.00
○Loop 2547 - ams.c:3431-3432 - exec	0.00	0.00

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Matching between your function (in the source code) and the binary function

General properties

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