OV - exec - Function hypre_IJMatrixSetValuesOMPParCSR.omp

	Function: hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14	Module: exec	Source: IJMatrix_parcsr.c:3240-3484 [...]	Coverage (incl. loops): 0.19% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 3240 - 3484

--------------------------------------------------------------------------------

3240: #pragma omp parallel

[...]

3256:          num_threads = hypre_NumActiveThreads();

3257:          my_thread_num = hypre_GetThreadNum();

3258:

3259:          len = nrows/num_threads;

3260:          rest = nrows - len*num_threads;

3261:

3262:          if (my_thread_num < rest)

3263:          {

3264:             ns = my_thread_num*(len+1);

3265:             ne = (my_thread_num+1)*(len+1);

3266:          }

3267:          else

3268:          {

3269:             ns = my_thread_num*len+rest;

3270:             ne = (my_thread_num+1)*len+rest;

3271:          }

3272:

3273:          value_start[my_thread_num] = 0;

3274:          for (ii=ns; ii < ne; ii++)

3275:             value_start[my_thread_num] += ncols[ii];

3276:

3277: #ifdef HYPRE_USING_OPENMP

3278: #pragma omp barrier

3279: #endif

3280:          if (my_thread_num == 0)

3281:          {

3282:             for (i=0; i < max_num_threads; i++)

3283:                value_start[i+1] += value_start[i];

3284:          }

3285: #ifdef HYPRE_USING_OPENMP

3286: #pragma omp barrier

3287: #endif

3288:          indx = 0;

3289:          if (my_thread_num)

3290:             indx = value_start[my_thread_num-1];

3291:          for (ii=ns; ii < ne; ii++)

3292:          {

3293:             row = rows[ii];

3294:             n = ncols[ii];

3295:             /* processor owns the row */

3296:             if (row >= row_partitioning[pstart] && row < row_partitioning[pstart+1])

3297:             {

3298:                row_local = row - row_partitioning[pstart];

3299:                /* compute local row number */

3300:                if (need_aux)

3301:                {

3302:                   local_j = aux_j[row_local];

3303:                   local_data = aux_data[row_local];

3304:    	          space = row_space[row_local];

3305:    	          old_size = row_length[row_local];

3306:    	          size = space - old_size;

3307:    	          if (size < n)

3308:       	          {

3309:       	             size = n - size;

3310:       	             tmp_j = hypre_CTAlloc(HYPRE_Int,size);

3311:       	             tmp_data = hypre_CTAlloc(HYPRE_Complex,size);

3312:       	          }

3313:       	          tmp_indx = 0;

3314:       	          not_found = 1;

3315:       	          size = old_size;

3316:                   for (i=0; i < n; i++)

3317:       	          {

3318:       	             for (j=0; j < old_size; j++)

3319:       	             {

3320:       	                if (local_j[j] == cols[indx])

3321:       	                {

3322:                            local_data[j] = values[indx];

3323:       		           not_found = 0;

3324:       		           break;

3325:       	                }

3326:       	             }

3327:       	             if (not_found)

3328:       	             {

3329:       	                if (size < space)

3330:       	                {

3331:       	                   local_j[size] = cols[indx];

3332:       	                   local_data[size++] = values[indx];

3333:       	                }

3334:       	                else

3335:       	                {

3336:       	                   tmp_j[tmp_indx] = cols[indx];

3337:       	                   tmp_data[tmp_indx++] = values[indx];

3338:       	                }

3339:       	             }

3340:       	             not_found = 1;

3341:         	     indx++;

3342:       	          }

3343:

3344:                   row_length[row_local] = size+tmp_indx;

3345:

3346:                   if (tmp_indx)

3347:                   {

3348:    	             aux_j[row_local] = hypre_TReAlloc(aux_j[row_local],HYPRE_Int,

3349:                                                     size+tmp_indx);

3350:    	             aux_data[row_local] = hypre_TReAlloc(aux_data[row_local],

3351:                                                        HYPRE_Complex,size+tmp_indx);

3352:                      row_space[row_local] = size+tmp_indx;

[...]

3359:    	          for (i=0; i < tmp_indx; i++)

3360:    	          {

3361:    	             local_j[cnt] = tmp_j[i];

3362:    	             local_data[cnt++] = tmp_data[i];

3363: 	          }

3364:

3365: 	          if (tmp_j)

3366: 	          {

3367: 	             hypre_TFree(tmp_j);

3368: 	             hypre_TFree(tmp_data);

[...]

3376: 	          offd_indx = hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local];

3377: 	          diag_indx = hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local];

[...]

3383:   	          for (i=0; i < n; i++)

3384: 	          {

3385: 	             if (cols[indx] < col_0 || cols[indx] > col_n)

3386:                      /* insert into offd */

3387: 	             {

3388: 	                for (j=offd_i[row_local]; j < offd_indx; j++)

3389: 	                {

3390: 		           if (offd_j[j] == cols[indx])

[...]

3399: 	                   if (cnt_offd < offd_space)

3400: 	                   {

3401: 	                      offd_j[cnt_offd] = cols[indx];

3402: 	                      offd_data[cnt_offd++] = values[indx];

3403: 	                   }

3404: 	                   else

3405: 	 	           {

3406:                               hypre_error(HYPRE_ERROR_GENERIC);

3407: #ifdef HYPRE_USING_OPENMP

3408: #pragma omp atomic

3409: #endif

3410:                               error_flag++;

3411: 	    	              if (print_level)

[...]

3417: 	                }

3418: 	                not_found = 1;

3419: 	             }

3420: 	             else  /* insert into diag */

3421: 	             {

3422: 	                for (j=diag_i[row_local]; j < diag_indx; j++)

3423: 	                {

3424: 		           if (diag_j[j] == cols[indx])

[...]

3433: 	                   if (cnt_diag < diag_space)

3434: 	                   {

3435: 	                      diag_j[cnt_diag] = cols[indx];

3436: 	                      diag_data[cnt_diag++] = values[indx];

3437: 	                   }

3438: 	                   else

3439: 	 	           {

3440:                               hypre_error(HYPRE_ERROR_GENERIC);

3441: #ifdef HYPRE_USING_OPENMP

3442: #pragma omp atomic

3443: #endif

3444:                               error_flag++;

3445: 	    	              if (print_level)

[...]

3454: 	             indx++;

3455: 	          }

3456:

3457:                   hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local] = cnt_diag;

3458:                   hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local] = cnt_offd;

[...]

3466:                indx +=  n;

3467:    	       if (aux_matrix)

3468:                {

3469:                   col_indx = 0;

3470:                   for (i=0; i < off_proc_i_indx; i=i+2)

3471:                   {

3472: 	             row_len = off_proc_i[i+1];

3473: 	             if (off_proc_i[i] == row)

3474: 		     {

3475: 		        for (j=0; j < n; j++)

3476: 		        {

3477: 			   cnt1 = col_indx;

3478: 			   for (k=0; k < row_len; k++)

3479: 			   {

3480: 			      if (off_proc_j[cnt1] == cols[j])

3481: 			      {

3482:                                  off_proc_j[cnt1++] = -1;

3483:                		         /*cancel_indx++;*/

3484: 	                         offproc_cnt[my_thread_num]++;

0x49a350 SUB	SP, SP, #368

0x49a354 STP	X29, X30, [SP, #272]

0x49a358 STP	X28, X27, [SP, #288]

0x49a35c STP	X26, X25, [SP, #304]

0x49a360 STP	X24, X23, [SP, #320]

0x49a364 STP	X22, X21, [SP, #336]

0x49a368 STP	X20, X19, [SP, #352]

0x49a36c ADD	X29, SP, #272

0x49a370 ORR	X28, XZR, X7

0x49a374 STUR	X6, [X29, #456]

0x49a378 ORR	X24, XZR, X5

0x49a37c ORR	X21, XZR, X4

0x49a380 ORR	X23, XZR, X3

0x49a384 ORR	X26, XZR, X2

0x49a388 ORR	X25, XZR, X0

0x49a38c BL	4acc30

0x49a390 ORR	X27, XZR, X0

0x49a394 BL	4acc50

0x49a398 LDR	X8, [X26]

0x49a39c ORR	X22, XZR, X0

0x49a3a0 SDIV	X10, X8, X27

0x49a3a4 ADD	X13, X10, #1

0x49a3a8 MSUB	X11, X10, X27, X8

0x49a3ac ADD	X8, X0, #1

0x49a3b0 MADD	X12, X10, X8, X11

0x49a3b4 MUL	X14, X13, X0

0x49a3b8 MUL	X8, X13, X8

0x49a3bc LDR	X13, [X23]

0x49a3c0 MADD	X9, X10, X0, X11

0x49a3c4 CMP	X0, X11

0x49a3c8 CSEL	X17, X12, X8, #10

0x49a3cc CSEL	X18, X9, X14, #10

0x49a3d0 CMP	X18, X17

0x49a3d4 ADD	X8, X13, X0,LSL #3

0x49a3d8 STR	XZR, [X8]

0x49a3dc B.GE	49a4b8

0x49a3e0 CMP	X22, X11

0x49a3e4 CSEL	X11, X22, X11, #11

0x49a3e8 LDR	X9, [X21]

0x49a3ec CNTW	X12, ALL

0x49a3f0 MADD	X10, X22, X10, X11

0x49a3f4 SUB	X11, X17, X10

0x49a3f8 MOVZ	W10, #16

0x49a3fc CMP	X12, #16

0x49a400 CSEL	X10, X12, X10, #8

0x49a404 CMP	X11, X10

0x49a408 B.CC	49a498

0x49a40c ADD	X10, X13, X22,LSL #3

0x49a410 ADD	X14, X9, X17,LSL #3

0x49a414 ADD	X13, X9, X18,LSL #3

0x49a418 ADD	X10, X10, #8

0x49a41c CMP	X8, X14

0x49a420 CCMP	X13, X10, #2, #3

0x49a424 B.CC	49a498

0x49a428 RDVL	X16, #1

0x49a42c SUB	X10, XZR, X12

0x49a430 MOVI	V0.2D, #0

0x49a434 MOVI	V1.2D, #0

0x49a438 ORR	X15, XZR, XZR

0x49a43c AND	X14, X11, X10

0x49a440 PTRUE	P0.D, ALL

0x49a444 ADD	X16, X16, X18,LSL #3

0x49a448 ADD	X10, X18, X14

0x49a44c ADD	X16, X9, X16

0x49a450 HINT	#0

0x49a454 HINT	#0

0x49a458 HINT	#0

0x49a45c HINT	#0

(3296) 0x49a460 LD1D	{Z2.D}, P0/Z, [X13, X15,LSL #3]

(3296) 0x49a464 LD1D	{Z3.D}, P0/Z, [X16, X15,LSL #3]

(3296) 0x49a468 ADD	X15, X15, X12

(3296) 0x49a46c CMP	X14, X15

(3296) 0x49a470 ADD	Z0.D, Z0.D, Z2.D

(3296) 0x49a474 ADD	Z1.D, Z1.D, Z3.D

(3296) 0x49a478 B.NE	49a460

0x49a47c ADD	Z0.D, Z1.D, Z0.D

0x49a480 CMP	X11, X14

0x49a484 UADDV	D0, P0, Z0.D

0x49a488 FMOV	X12, D0

0x49a48c STR	X12, [X8]

0x49a490 B.NE	49a4a0

0x49a494 B	49a4b8

0x49a498 ORR	X12, XZR, XZR

0x49a49c ORR	X10, XZR, X18

(3295) 0x49a4a0 LDR	X11, [X9, X10,LSL #3]

(3295) 0x49a4a4 ADD	X10, X10, #1

(3295) 0x49a4a8 CMP	X10, X17

(3295) 0x49a4ac ADD	X12, X12, X11

(3295) 0x49a4b0 STR	X12, [X8]

(3295) 0x49a4b4 B.LT	49a4a0

0x49a4b8 LDR	W25, [X25]

0x49a4bc ADRP	X0,

0x49a4c0 ADD	X0, X0, #3816

0x49a4c4 ORR	X19, XZR, X18

0x49a4c8 STUR	X17, [X29, #432]

0x49a4cc ORR	W1, WZR, W25

0x49a4d0 BL	4104c0

0x49a4d4 CBNZ	X22, 49a51c

0x49a4d8 LDR	X8, [X24]

0x49a4dc CMP	X8, #1

0x49a4e0 B.LT	49a51c

0x49a4e4 LDR	X8, [X23]

0x49a4e8 ORR	X10, XZR, XZR

0x49a4ec LDR	X9, [X8], #8

0x49a4f0 HINT	#0

0x49a4f4 HINT	#0

0x49a4f8 HINT	#0

0x49a4fc HINT	#0

(3294) 0x49a500 LDR	X11, [X8, X10,LSL #3]

(3294) 0x49a504 ADD	X9, X11, X9

(3294) 0x49a508 STR	X9, [X8, X10,LSL #3]

(3294) 0x49a50c ADD	X10, X10, #1

(3294) 0x49a510 LDR	X11, [X24]

(3294) 0x49a514 CMP	X10, X11

(3294) 0x49a518 B.LT	49a500

0x49a51c ADRP	X0,

0x49a520 ADD	X0, X0, #3840

0x49a524 ORR	W1, WZR, W25

0x49a528 BL	4104c0

0x49a52c CBZ	X22, 49a554

0x49a530 LDR	X8, [X23]

0x49a534 ADD	X8, X8, X22,LSL #3

0x49a538 LDUR	X24, [X8, #504]

0x49a53c LDUR	X7, [X29, #432]

0x49a540 LDUR	X11, [X29, #456]

0x49a544 ORR	X30, XZR, X19

0x49a548 CMP	X19, X7

0x49a54c B.LT	49a56c

0x49a550 B	49addc

0x49a554 ORR	X24, XZR, XZR

0x49a558 LDUR	X7, [X29, #432]

0x49a55c LDUR	X11, [X29, #456]

0x49a560 ORR	X30, XZR, X19

0x49a564 CMP	X19, X7

0x49a568 B.GE	49addc

0x49a56c LDR	X8, [X29, #256]

0x49a570 CNTW	X9, ALL

0x49a574 LDP	X3, X19, [X29, #264]

0x49a578 LDR	X6, [X29, #160]

0x49a57c MOVN	X27, #0

0x49a580 STUR	XZR, [X29, #464]

0x49a584 STR	X28, [SP, #104]

0x49a588 STR	X8, [SP, #136]

0x49a58c LDP	X8, X4, [X29, #240]

0x49a590 STP	X3, X21, [X29, #928]

0x49a594 STR	X8, [SP, #80]

0x49a598 LDR	X8, [X29, #232]

0x49a59c STUR	X4, [X29, #408]

0x49a5a0 STR	X8, [SP, #72]

0x49a5a4 LDR	X8, [X29, #224]

0x49a5a8 STR	X8, [SP, #24]

0x49a5ac LDR	X8, [X29, #216]

0x49a5b0 STR	X8, [SP, #16]

0x49a5b4 LDR	X8, [X29, #208]

0x49a5b8 STR	X8, [SP, #64]

0x49a5bc LDR	X8, [X29, #200]

0x49a5c0 STR	X8, [SP, #56]

0x49a5c4 LDP	X10, X8, [X29, #184]

0x49a5c8 STP	X10, X8, [X29, #984]

0x49a5cc MOVZ	W8, #8

0x49a5d0 CMP	X9, #8

0x49a5d4 CSEL	X8, X9, X8, #8

0x49a5d8 LDR	X10, [X29, #176]

0x49a5dc STR	X8, [SP, #32]

0x49a5e0 LDR	X8, [X29, #168]

0x49a5e4 STP	X8, X10, [SP, #40]

0x49a5e8 SUB	X8, XZR, X9

0x49a5ec STR	X8, [SP, #8]

0x49a5f0 LDR	X8, [X29, #152]

0x49a5f4 STR	X8, [SP, #96]

0x49a5f8 LDP	X8, X9, [X29, #136]

0x49a5fc STUR	X8, [X29, #448]

0x49a600 LDR	X8, [X29, #128]

0x49a604 STUR	X9, [X29, #496]

0x49a608 STR	X8, [SP, #120]

0x49a60c LDR	X8, [X29, #120]

0x49a610 STR	X8, [SP, #112]

0x49a614 LDR	X8, [X29, #112]

0x49a618 STR	X8, [SP, #128]

0x49a61c LDP	X26, X8, [X29, #96]

0x49a620 STP	X8, X6, [X29, #904]

0x49a624 STUR	X26, [X29, #384]

0x49a628 B	49a63c

      (3279) 0x49a62c ORR	X11, XZR, X5

      (3279) 0x49a630 ADD	X30, X30, #1

      (3279) 0x49a634 CMP	X30, X7

      (3279) 0x49a638 B.GE	49addc

      (3279) 0x49a63c LDR	X8, [X11]

      (3279) 0x49a640 LDR	X9, [X26]

      (3279) 0x49a644 LDR	X25, [X8, X30,LSL #3]

      (3279) 0x49a648 LDR	X8, [X21]

      (3279) 0x49a64c LDR	X20, [X8, X30,LSL #3]

      (3279) 0x49a650 LDR	X8, [X28]

      (3279) 0x49a654 ADD	X8, X8, X9,LSL #3

      (3279) 0x49a658 LDR	X9, [X8]

      (3279) 0x49a65c SUBS	X9, X25, X9

      (3279) 0x49a660 STUR	X9, [X29, #488]

      (3279) 0x49a664 B.LT	49a724

      (3279) 0x49a668 LDR	X8, [X8, #8]

      (3279) 0x49a66c CMP	X25, X8

      (3279) 0x49a670 B.GE	49a724

      (3279) 0x49a674 LDUR	X8, [X29, #392]

      (3279) 0x49a678 LDR	X8, [X8]

      (3279) 0x49a67c CBZ	X8, 49a88c

    (3287) 0x49a680 LDR	X16, [SP, #128]

    (3287) 0x49a684 LDUR	X9, [X29, #488]

    (3287) 0x49a688 STUR	X30, [X29, #440]

    (3287) 0x49a68c LDR	X8, [X16]

    (3287) 0x49a690 LDR	X25, [X8, X9,LSL #3]

    (3287) 0x49a694 LDR	X8, [SP, #112]

    (3287) 0x49a698 LDR	X8, [X8]

    (3287) 0x49a69c LDR	X23, [X8, X9,LSL #3]

    (3287) 0x49a6a0 LDR	X8, [SP, #120]

    (3287) 0x49a6a4 LDR	X8, [X8]

    (3287) 0x49a6a8 LDR	X17, [X8, X9,LSL #3]

    (3287) 0x49a6ac LDUR	X8, [X29, #448]

    (3287) 0x49a6b0 LDR	X8, [X8]

    (3287) 0x49a6b4 LDR	X26, [X8, X9,LSL #3]

    (3287) 0x49a6b8 SUB	X8, X17, X26

    (3287) 0x49a6bc SUBS	X21, X20, X8

    (3287) 0x49a6c0 B.LE	49a9d4

    (3287) 0x49a6c4 MOVZ	W1, #8

    (3287) 0x49a6c8 ORR	X0, XZR, X21

    (3287) 0x49a6cc STUR	X17, [X29, #464]

    (3287) 0x49a6d0 BL	4aaf00

    (3287) 0x49a6d4 MOVZ	W1, #8

    (3287) 0x49a6d8 ORR	X28, XZR, X0

    (3287) 0x49a6dc ORR	X0, XZR, X21

    (3287) 0x49a6e0 BL	4aaf00

    (3287) 0x49a6e4 LDUR	X17, [X29, #464]

    (3287) 0x49a6e8 ORR	X4, XZR, X28

    (3287) 0x49a6ec LDR	X28, [SP, #104]

    (3287) 0x49a6f0 LDR	X16, [SP, #128]

    (3287) 0x49a6f4 CMP	X20, #0

    (3287) 0x49a6f8 STUR	X0, [X29, #464]

    (3287) 0x49a6fc B.GT	49a9e8

    (3287) 0x49a700 LDP	X8, X11, [X29, #960]

    (3287) 0x49a704 LDUR	X9, [X29, #488]

    (3287) 0x49a708 LDR	X8, [X8]

    (3287) 0x49a70c STR	X26, [X8, X9,LSL #3]

    (3287) 0x49a710 LDUR	X6, [X29, #400]

    (3287) 0x49a714 LDUR	X21, [X29, #424]

    (3287) 0x49a718 LDUR	X26, [X29, #384]

    (3287) 0x49a71c CBNZ	X4, 49adac

    (3287) 0x49a720 B	49add0

      (3279) 0x49a724 LDR	X8, [X6]

      (3279) 0x49a728 LDR	X12, [X4]

      (3279) 0x49a72c ADD	X24, X20, X24

      (3279) 0x49a730 CMP	X8, #0

      (3279) 0x49a734 CCMP	X12, #1, #8, #1

      (3279) 0x49a738 B.LT	49a630

      (3279) 0x49a73c CMP	X20, #1

      (3279) 0x49a740 B.LT	49a630

      (3279) 0x49a744 LDR	X10, [SP, #136]

      (3279) 0x49a748 ORR	X5, XZR, X11

      (3279) 0x49a74c ORR	X8, XZR, XZR

      (3279) 0x49a750 ORR	X9, XZR, XZR

      (3279) 0x49a754 LDR	X10, [X10]

      (3279) 0x49a758 B	49a774

0x49a75c HINT	#0

        (3280) 0x49a760 LDR	X12, [X4]

        (3280) 0x49a764 ADD	X9, X9, #2

        (3280) 0x49a768 ADD	X8, X11, X8

        (3280) 0x49a76c CMP	X9, X12

        (3280) 0x49a770 B.GE	49a62c

        (3280) 0x49a774 ADD	X13, X10, X9,LSL #3

        (3280) 0x49a778 LDP	X13, X11, [X13]

        (3280) 0x49a77c CMP	X13, X25

        (3280) 0x49a780 B.NE	49a764

        (3280) 0x49a784 CMP	X11, #1

        (3280) 0x49a788 B.LT	49a764

        (3280) 0x49a78c LDUR	X14, [X29, #496]

        (3280) 0x49a790 LDR	X13, [X3]

        (3280) 0x49a794 AND	X15, X11, #0x0

        (3280) 0x49a798 ORR	X12, XZR, XZR

        (3280) 0x49a79c LDR	X14, [X14]

        (3280) 0x49a7a0 ADD	X16, X13, X8,LSL #3

        (3280) 0x49a7a4 ADD	X16, X16, #8

        (3280) 0x49a7a8 B	49a7b8

          (3281) 0x49a7ac ADD	X12, X12, #1

          (3281) 0x49a7b0 CMP	X12, X20

          (3281) 0x49a7b4 B.EQ	49a760

          (3281) 0x49a7b8 LDR	X17, [X19]

          (3281) 0x49a7bc CMP	X11, #1

          (3281) 0x49a7c0 ORR	X18, XZR, X8

          (3281) 0x49a7c4 B.EQ	49a868

          (3281) 0x49a7c8 AND	X18, X11, #0x0

          (3281) 0x49a7cc ORR	X0, XZR, X16

          (3281) 0x49a7d0 B	49a7ec

0x49a7d4 HINT	#0

0x49a7d8 HINT	#0

0x49a7dc HINT	#0

            (3282) 0x49a7e0 ADD	X0, X0, #16

            (3282) 0x49a7e4 SUBS	X18, X18, #2

            (3282) 0x49a7e8 B.EQ	49a860

            (3282) 0x49a7ec LDUR	X1, [X0, #504]

            (3282) 0x49a7f0 LDR	X2, [X14, X12,LSL #3]

            (3282) 0x49a7f4 CMP	X1, X2

            (3282) 0x49a7f8 B.EQ	49a820

            (3282) 0x49a7fc LDR	X1, [X0]

            (3282) 0x49a800 LDR	X2, [X14, X12,LSL #3]

            (3282) 0x49a804 CMP	X1, X2

            (3282) 0x49a808 B.NE	49a7e0

            (3282) 0x49a80c B	49a840

0x49a810 HINT	#0

0x49a814 HINT	#0

0x49a818 HINT	#0

0x49a81c HINT	#0

            (3282) 0x49a820 STUR	X27, [X0, #504]

            (3282) 0x49a824 LDR	X1, [X17, X22,LSL #3]

            (3282) 0x49a828 ADD	X1, X1, #1

            (3282) 0x49a82c STR	X1, [X17, X22,LSL #3]

            (3282) 0x49a830 LDR	X1, [X0]

            (3282) 0x49a834 LDR	X2, [X14, X12,LSL #3]

            (3282) 0x49a838 CMP	X1, X2

            (3282) 0x49a83c B.NE	49a7e0

            (3282) 0x49a840 STR	X27, [X0]

            (3282) 0x49a844 LDR	X1, [X17, X22,LSL #3]

            (3282) 0x49a848 ADD	X1, X1, #1

            (3282) 0x49a84c STR	X1, [X17, X22,LSL #3]

            (3282) 0x49a850 B	49a7e0

0x49a854 HINT	#0

0x49a858 HINT	#0

0x49a85c HINT	#0

          (3281) 0x49a860 ADD	X18, X8, X15

          (3281) 0x49a864 TBZ	W11, #0, 49a7ac

          (3281) 0x49a868 LDR	X0, [X13, X18,LSL #3]

          (3281) 0x49a86c LDR	X1, [X14, X12,LSL #3]

          (3281) 0x49a870 CMP	X0, X1

          (3281) 0x49a874 B.NE	49a7ac

          (3281) 0x49a878 STR	X27, [X13, X18,LSL #3]

          (3281) 0x49a87c LDR	X18, [X17, X22,LSL #3]

          (3281) 0x49a880 ADD	X18, X18, #1

          (3281) 0x49a884 STR	X18, [X17, X22,LSL #3]

          (3281) 0x49a888 B	49a7ac

      (3279) 0x49a88c LDR	X8, [X6]

      (3279) 0x49a890 LDUR	X23, [X29, #488]

      (3279) 0x49a894 CMP	X20, #1

      (3279) 0x49a898 LDP	X10, X9, [X8, #56]

      (3279) 0x49a89c UBFM	X12, X23, #61, #60

      (3279) 0x49a8a0 LDR	X8, [X9, X12]

      (3279) 0x49a8a4 LDR	X9, [X10, X12]

      (3279) 0x49a8a8 B.LT	49ab4c

      (3279) 0x49a8ac LDP	X11, X13, [SP, #40]

      (3279) 0x49a8b0 LDUR	X15, [X29, #496]

      (3279) 0x49a8b4 ADD	X14, X12, #8

      (3279) 0x49a8b8 ORR	X10, XZR, XZR

      (3279) 0x49a8bc ORR	X21, XZR, X8

      (3279) 0x49a8c0 ORR	X26, XZR, X9

      (3279) 0x49a8c4 LDR	X17, [SP, #96]

      (3279) 0x49a8c8 LDP	X16, X18, [SP, #72]

      (3279) 0x49a8cc LDR	X11, [X11]

      (3279) 0x49a8d0 LDR	X13, [X13]

      (3279) 0x49a8d4 LDP	X0, X1, [SP, #56]

      (3279) 0x49a8d8 LDR	X15, [X15]

      (3279) 0x49a8dc LDR	X16, [X16]

      (3279) 0x49a8e0 LDR	X17, [X17]

      (3279) 0x49a8e4 LDR	X18, [X18]

      (3279) 0x49a8e8 LDR	X0, [X0]

      (3279) 0x49a8ec LDR	X1, [X1]

      (3279) 0x49a8f0 LDR	X12, [X11, X14]

      (3279) 0x49a8f4 LDR	X14, [X13, X14]

      (3279) 0x49a8f8 B	49a918

0x49a8fc HINT	#0

        (3283) 0x49a900 LDR	D0, [X17, X24,LSL #3]

        (3283) 0x49a904 STR	D0, [X4]

        (3283) 0x49a908 ADD	X10, X10, #1

        (3283) 0x49a90c ADD	X24, X24, #1

        (3283) 0x49a910 CMP	X10, X20

        (3283) 0x49a914 B.EQ	49abec

        (3283) 0x49a918 LDP	X3, X4, [X29, #984]

        (3283) 0x49a91c LDR	X2, [X15, X24,LSL #3]

        (3283) 0x49a920 LDR	X3, [X3]

        (3283) 0x49a924 LDR	X4, [X4]

        (3283) 0x49a928 CMP	X2, X3

        (3283) 0x49a92c CCMP	X2, X4, #0, #10

        (3283) 0x49a930 B.LE	49a980

        (3283) 0x49a934 LDR	X5, [X13, X23,LSL #3]

        (3283) 0x49a938 SUBS	X3, X8, X5

        (3283) 0x49a93c B.LE	49a960

        (3283) 0x49a940 ADD	X4, X1, X5,LSL #3

        (3283) 0x49a944 ADD	X5, X0, X5,LSL #3

          (3285) 0x49a948 LDR	X6, [X5], #8

          (3285) 0x49a94c CMP	X6, X2

          (3285) 0x49a950 B.EQ	49a900

          (3285) 0x49a954 ADD	X4, X4, #8

          (3285) 0x49a958 SUBS	X3, X3, #1

          (3285) 0x49a95c B.NE	49a948

        (3283) 0x49a960 CMP	X21, X14

        (3283) 0x49a964 B.GE	49aba0

        (3283) 0x49a968 LDR	D0, [X17, X24,LSL #3]

        (3283) 0x49a96c STR	X2, [X0, X21,LSL #3]

        (3283) 0x49a970 STR	D0, [X1, X21,LSL #3]

        (3283) 0x49a974 ADD	X21, X21, #1

        (3283) 0x49a978 B	49a908

0x49a97c HINT	#0

        (3283) 0x49a980 LDR	X5, [X11, X23,LSL #3]

        (3283) 0x49a984 SUBS	X3, X9, X5

        (3283) 0x49a988 B.LE	49a9b8

        (3283) 0x49a98c ADD	X4, X18, X5,LSL #3

        (3283) 0x49a990 ADD	X5, X16, X5,LSL #3

        (3283) 0x49a994 HINT	#0

        (3283) 0x49a998 HINT	#0

        (3283) 0x49a99c HINT	#0

          (3284) 0x49a9a0 LDR	X6, [X5], #8

          (3284) 0x49a9a4 CMP	X6, X2

          (3284) 0x49a9a8 B.EQ	49a900

          (3284) 0x49a9ac ADD	X4, X4, #8

          (3284) 0x49a9b0 SUBS	X3, X3, #1

          (3284) 0x49a9b4 B.NE	49a9a0

        (3283) 0x49a9b8 CMP	X26, X12

        (3283) 0x49a9bc B.GE	49ac10

        (3283) 0x49a9c0 LDR	D0, [X17, X24,LSL #3]

        (3283) 0x49a9c4 STR	X2, [X16, X26,LSL #3]

        (3283) 0x49a9c8 STR	D0, [X18, X26,LSL #3]

        (3283) 0x49a9cc ADD	X26, X26, #1

        (3283) 0x49a9d0 B	49a908

    (3287) 0x49a9d4 LDUR	X0, [X29, #464]

    (3287) 0x49a9d8 ORR	X4, XZR, XZR

    (3287) 0x49a9dc CMP	X20, #0

    (3287) 0x49a9e0 STUR	X0, [X29, #464]

    (3287) 0x49a9e4 B.LE	49a700

  (3288) 0x49a9e8 LDUR	X9, [X29, #496]

  (3288) 0x49a9ec LDR	X10, [SP, #96]

  (3288) 0x49a9f0 ORR	X21, XZR, XZR

  (3288) 0x49a9f4 ORR	X8, XZR, XZR

  (3288) 0x49a9f8 ORR	X28, XZR, X26

  (3288) 0x49a9fc LDR	X9, [X9]

  (3288) 0x49aa00 LDR	X10, [X10]

  (3288) 0x49aa04 B	49aa28

  (3288) 0x49aa08 LDR	D0, [X10, X24,LSL #3]

  (3288) 0x49aa0c STR	X11, [X4, X21,LSL #3]

  (3288) 0x49aa10 STR	D0, [X0, X21,LSL #3]

  (3288) 0x49aa14 ADD	X21, X21, #1

  (3288) 0x49aa18 ADD	X8, X8, #1

  (3288) 0x49aa1c ADD	X24, X24, #1

  (3288) 0x49aa20 CMP	X8, X20

  (3288) 0x49aa24 B.EQ	49aa8c

  (3288) 0x49aa28 CMP	X26, #1

  (3288) 0x49aa2c B.LT	49aa58

(3289) 0x49aa30 LDR	X11, [X9, X24,LSL #3]

(3289) 0x49aa34 ORR	X13, XZR, X26

(3289) 0x49aa38 ORR	X14, XZR, X25

(3289) 0x49aa3c ORR	X12, XZR, X23

  (3290) 0x49aa40 LDR	X15, [X14], #8

  (3290) 0x49aa44 CMP	X15, X11

  (3290) 0x49aa48 B.EQ	49aa80

  (3290) 0x49aa4c ADD	X12, X12, #8

  (3290) 0x49aa50 SUBS	X13, X13, #1

  (3290) 0x49aa54 B.NE	49aa40

  (3288) 0x49aa58 LDR	X11, [X9, X24,LSL #3]

  (3288) 0x49aa5c CMP	X28, X17

  (3288) 0x49aa60 B.GE	49aa08

  (3288) 0x49aa64 LDR	D0, [X10, X24,LSL #3]

  (3288) 0x49aa68 STR	X11, [X25, X28,LSL #3]

  (3288) 0x49aa6c STR	D0, [X23, X28,LSL #3]

  (3288) 0x49aa70 ADD	X28, X28, #1

  (3288) 0x49aa74 B	49aa18

0x49aa78 HINT	#0

0x49aa7c HINT	#0

(3289) 0x49aa80 LDR	D0, [X10, X24,LSL #3]

(3289) 0x49aa84 STR	D0, [X12]

(3289) 0x49aa88 B	49aa18

  (3288) 0x49aa8c LDUR	X8, [X29, #448]

  (3288) 0x49aa90 LDUR	X23, [X29, #488]

  (3288) 0x49aa94 ADD	X9, X28, X21

  (3288) 0x49aa98 LDR	X8, [X8]

  (3288) 0x49aa9c STR	X9, [X8, X23,LSL #3]

  (3288) 0x49aaa0 CBZ	X21, 49ab30

  (3288) 0x49aaa4 LDR	X8, [X16]

  (3288) 0x49aaa8 UBFM	X20, X9, #61, #60

  (3288) 0x49aaac STR	X4, [SP, #88]

  (3288) 0x49aab0 ORR	X26, XZR, X16

  (3288) 0x49aab4 ORR	X1, XZR, X20

  (3288) 0x49aab8 LDR	X0, [X8, X23,LSL #3]

  (3288) 0x49aabc BL	4aaf70

  (3288) 0x49aac0 LDR	X8, [X26]

  (3288) 0x49aac4 LDR	X25, [SP, #112]

  (3288) 0x49aac8 ORR	X1, XZR, X20

  (3288) 0x49aacc STR	X0, [X8, X23,LSL #3]

  (3288) 0x49aad0 LDR	X8, [X25]

  (3288) 0x49aad4 LDR	X0, [X8, X23,LSL #3]

  (3288) 0x49aad8 BL	4aaf70

  (3288) 0x49aadc LDR	X8, [X25]

  (3288) 0x49aae0 LDUR	X6, [X29, #400]

  (3288) 0x49aae4 ADD	X9, X28, X21

  (3288) 0x49aae8 CMP	X21, #1

  (3288) 0x49aaec STR	X0, [X8, X23,LSL #3]

  (3288) 0x49aaf0 LDR	X8, [SP, #120]

  (3288) 0x49aaf4 LDR	X8, [X8]

  (3288) 0x49aaf8 STR	X9, [X8, X23,LSL #3]

  (3288) 0x49aafc B.LT	49ab58

  (3288) 0x49ab00 LDR	X8, [X26]

  (3288) 0x49ab04 LDR	X9, [SP, #32]

  (3288) 0x49ab08 LDP	X3, X18, [X29, #968]

  (3288) 0x49ab0c RDVL	X2, #2

  (3288) 0x49ab10 PTRUE	P0.B, ALL

  (3288) 0x49ab14 LDR	X4, [SP, #88]

  (3288) 0x49ab18 LDR	X8, [X8, X23,LSL #3]

  (3288) 0x49ab1c CMP	X21, X9

  (3288) 0x49ab20 B.CS	49ab74

  (3288) 0x49ab24 LDUR	X26, [X29, #384]

  (3288) 0x49ab28 ORR	X9, XZR, XZR

  (3288) 0x49ab2c B	49acbc

  (3288) 0x49ab30 LDR	X28, [SP, #104]

  (3288) 0x49ab34 LDUR	X11, [X29, #456]

  (3288) 0x49ab38 LDUR	X6, [X29, #400]

  (3288) 0x49ab3c LDUR	X21, [X29, #424]

  (3288) 0x49ab40 LDUR	X26, [X29, #384]

  (3288) 0x49ab44 CBNZ	X4, 49adac

  (3288) 0x49ab48 B	49add0

      (3279) 0x49ab4c ORR	X26, XZR, X9

      (3279) 0x49ab50 ORR	X21, XZR, X8

      (3279) 0x49ab54 B	49abec

  (3288) 0x49ab58 LDR	X28, [SP, #104]

  (3288) 0x49ab5c LDUR	X11, [X29, #456]

  (3288) 0x49ab60 LDR	X4, [SP, #88]

  (3288) 0x49ab64 LDUR	X21, [X29, #424]

  (3288) 0x49ab68 LDUR	X26, [X29, #384]

  (3288) 0x49ab6c CBNZ	X4, 49adac

  (3288) 0x49ab70 B	49add0

  (3288) 0x49ab74 SUB	X9, X8, X4

  (3288) 0x49ab78 LDUR	X26, [X29, #384]

  (3288) 0x49ab7c SUB	X10, X0, X18

  (3288) 0x49ab80 CNTW	X1, ALL

  (3288) 0x49ab84 ADD	X9, X9, X28,LSL #3

  (3288) 0x49ab88 ADD	X10, X10, X28,LSL #3

  (3288) 0x49ab8c CMP	X9, X2

  (3288) 0x49ab90 CCMP	X10, X2, #0, #2

  (3288) 0x49ab94 B.CS	49ac50

  (3288) 0x49ab98 ORR	X9, XZR, XZR

  (3288) 0x49ab9c B	49acbc

      (3279) 0x49aba0 ADRP	X0,

      (3279) 0x49aba4 ADD	X0, X0, #1539

      (3279) 0x49aba8 MOVZ	W1, #3406

      (3279) 0x49abac MOVZ	W2, #1

      (3279) 0x49abb0 ORR	X20, XZR, X30

      (3279) 0x49abb4 ORR	X3, XZR, XZR

      (3279) 0x49abb8 BL	4ad5e0

      (3279) 0x49abbc LDR	X8, [SP, #16]

      (3279) 0x49abc0 MOVZ	W9, #1

      (3279) 0x49abc4 ADRP	X0,

      (3279) 0x49abc8 ADD	X0, X0, #1879

      (3279) 0x49abcc LDADD	X9, X8, [X8]

      (3279) 0x49abd0 LDR	X8, [SP, #24]

      (3279) 0x49abd4 LDR	X8, [X8]

      (3279) 0x49abd8 CBZ	X8, 49abe4

      (3279) 0x49abdc ORR	X1, XZR, X25

      (3279) 0x49abe0 BL	4ab120

      (3279) 0x49abe4 LDUR	X7, [X29, #432]

      (3279) 0x49abe8 ORR	X30, XZR, X20

      (3279) 0x49abec LDP	X6, X4, [X29, #912]

      (3279) 0x49abf0 LDUR	X11, [X29, #456]

      (3279) 0x49abf4 LDR	X8, [X6]

      (3279) 0x49abf8 LDP	X9, X8, [X8, #56]

      (3279) 0x49abfc STR	X26, [X9, X23,LSL #3]

      (3279) 0x49ac00 STR	X21, [X8, X23,LSL #3]

      (3279) 0x49ac04 LDP	X3, X21, [X29, #928]

      (3279) 0x49ac08 LDUR	X26, [X29, #384]

      (3279) 0x49ac0c B	49a630

      (3279) 0x49ac10 ADRP	X0,

      (3279) 0x49ac14 ADD	X0, X0, #1539

      (3279) 0x49ac18 MOVZ	W1, #3440

      (3279) 0x49ac1c MOVZ	W2, #1

      (3279) 0x49ac20 ORR	X20, XZR, X30

      (3279) 0x49ac24 ORR	X3, XZR, XZR

      (3279) 0x49ac28 BL	4ad5e0

      (3279) 0x49ac2c LDR	X8, [SP, #16]

      (3279) 0x49ac30 MOVZ	W9, #1

      (3279) 0x49ac34 ADRP	X0,

      (3279) 0x49ac38 ADD	X0, X0, #1917

      (3279) 0x49ac3c LDADD	X9, X8, [X8]

      (3279) 0x49ac40 LDR	X8, [SP, #24]

      (3279) 0x49ac44 LDR	X8, [X8]

      (3279) 0x49ac48 CBNZ	X8, 49abdc

      (3279) 0x49ac4c B	49abe4

  (3288) 0x49ac50 LDR	X15, [SP, #8]

  (3288) 0x49ac54 UBFM	X13, X28, #61, #60

  (3288) 0x49ac58 RDVL	X14, #1

  (3288) 0x49ac5c ORR	X10, XZR, XZR

  (3288) 0x49ac60 ADD	X11, X0, X13

  (3288) 0x49ac64 ADD	X13, X8, X13

  (3288) 0x49ac68 ADD	X12, X11, X14

  (3288) 0x49ac6c ADD	X14, X13, X14

  (3288) 0x49ac70 AND	X9, X21, X15

  (3288) 0x49ac74 AND	X15, X21, X15

  (3288) 0x49ac78 ADD	X28, X28, X9

  (3288) 0x49ac7c HINT	#0

    (3291) 0x49ac80 ADD	X16, X4, X10

    (3291) 0x49ac84 LD1B	{Z0.B}, P0/Z, [X4, X10]

    (3291) 0x49ac88 ADD	X17, X18, X10

    (3291) 0x49ac8c SUBS	X15, X15, X1

    (3291) 0x49ac90 LDR	Z1, [X16, #1, MUL VL]

    (3291) 0x49ac94 ST1B	{Z0.B}, P0, [X13, X10]

    (3291) 0x49ac98 LD1B	{Z0.B}, P0/Z, [X18, X10]

    (3291) 0x49ac9c ST1B	{Z1.B}, P0, [X14, X10]

    (3291) 0x49aca0 LDR	Z1, [X17, #1, MUL VL]

    (3291) 0x49aca4 ST1B	{Z0.B}, P0, [X11, X10]

    (3291) 0x49aca8 ST1B	{Z1.B}, P0, [X12, X10]

    (3291) 0x49acac ADD	X10, X10, X2

    (3291) 0x49acb0 B.NE	49ac80

  (3288) 0x49acb4 CMP	X21, X9

  (3288) 0x49acb8 B.EQ	49ada0

  (3288) 0x49acbc SUB	W10, W21, W9

  (3288) 0x49acc0 ANDS	X11, X10, #0x3

  (3288) 0x49acc4 B.EQ	49ad14

  (3288) 0x49acc8 ADD	X12, X0, X28,LSL #3

  (3288) 0x49accc ADD	X13, X8, X28,LSL #3

  (3288) 0x49acd0 ADD	X14, X18, X9,LSL #3

  (3288) 0x49acd4 ADD	X15, X4, X9,LSL #3

  (3288) 0x49acd8 ORR	X10, XZR, XZR

  (3288) 0x49acdc HINT	#0

    (3293) 0x49ace0 LDR	D0, [X14, X10,LSL #3]

    (3293) 0x49ace4 LDR	X16, [X15, X10,LSL #3]

    (3293) 0x49ace8 STR	X16, [X13, X10,LSL #3]

    (3293) 0x49acec STR	D0, [X12, X10,LSL #3]

    (3293) 0x49acf0 ADD	X10, X10, #1

    (3293) 0x49acf4 CMP	X11, X10

    (3293) 0x49acf8 B.NE	49ace0

  (3288) 0x49acfc ADD	X28, X28, X10

  (3288) 0x49ad00 ADD	X11, X9, X10

  (3288) 0x49ad04 SUB	X9, X9, X21

  (3288) 0x49ad08 CMN	X9, #4

  (3288) 0x49ad0c B.LS	49ad24

  (3288) 0x49ad10 B	49ada0

  (3288) 0x49ad14 ORR	X11, XZR, X9

  (3288) 0x49ad18 SUB	X9, X9, X21

  (3288) 0x49ad1c CMN	X9, #4

  (3288) 0x49ad20 B.HI	49ada0

  (3288) 0x49ad24 ADD	X9, X4, X11,LSL #3

  (3288) 0x49ad28 ADD	X10, X18, X11,LSL #3

  (3288) 0x49ad2c ADD	X12, X0, X28,LSL #3

  (3288) 0x49ad30 ADD	X8, X8, X28,LSL #3

  (3288) 0x49ad34 SUB	X11, X21, X11

  (3288) 0x49ad38 ADD	X9, X9, #16

  (3288) 0x49ad3c ADD	X10, X10, #16

  (3288) 0x49ad40 ADD	X12, X12, #16

  (3288) 0x49ad44 ADD	X8, X8, #16

    (3292) 0x49ad48 LDUR	D0, [X10, #496]

    (3292) 0x49ad4c LDUR	X13, [X9, #496]

    (3292) 0x49ad50 SUBS	X11, X11, #4

    (3292) 0x49ad54 STUR	X13, [X8, #496]

    (3292) 0x49ad58 LDUR	X13, [X9, #504]

    (3292) 0x49ad5c STUR	D0, [X12, #496]

    (3292) 0x49ad60 LDUR	D0, [X10, #504]

    (3292) 0x49ad64 STUR	X13, [X8, #504]

    (3292) 0x49ad68 LDR	X13, [X9]

    (3292) 0x49ad6c STUR	D0, [X12, #504]

    (3292) 0x49ad70 LDR	D0, [X10]

    (3292) 0x49ad74 STR	X13, [X8]

    (3292) 0x49ad78 LDR	X13, [X9, #8]

    (3292) 0x49ad7c ADD	X9, X9, #32

    (3292) 0x49ad80 STR	X13, [X8, #8]

    (3292) 0x49ad84 ADD	X8, X8, #32

    (3292) 0x49ad88 STR	D0, [X12]

    (3292) 0x49ad8c LDR	D0, [X10, #8]

    (3292) 0x49ad90 ADD	X10, X10, #32

    (3292) 0x49ad94 STR	D0, [X12, #8]

    (3292) 0x49ad98 ADD	X12, X12, #32

    (3292) 0x49ad9c B.NE	49ad48

  (3288) 0x49ada0 LDR	X28, [SP, #104]

  (3288) 0x49ada4 LDUR	X21, [X29, #424]

  (3288) 0x49ada8 ORR	X11, XZR, X3

    (3286) 0x49adac ORR	X0, XZR, X4

    (3286) 0x49adb0 ORR	X20, XZR, X11

    (3286) 0x49adb4 ORR	X23, XZR, X6

    (3286) 0x49adb8 BL	4ab000

  (3288) 0x49adbc LDUR	X0, [X29, #464]

  (3288) 0x49adc0 BL	4ab000

  (3288) 0x49adc4 ORR	X6, XZR, X23

  (3288) 0x49adc8 ORR	X11, XZR, X20

  (3288) 0x49adcc STUR	XZR, [X29, #464]

    (3287) 0x49add0 LDP	X7, X30, [X29, #944]

    (3287) 0x49add4 LDP	X4, X3, [X29, #920]

    (3287) 0x49add8 B	49a630

0x49addc LDP	X20, X19, [SP, #352]

0x49ade0 LDP	X22, X21, [SP, #336]

0x49ade4 LDP	X24, X23, [SP, #320]

0x49ade8 LDP	X26, X25, [SP, #304]

0x49adec LDP	X28, X27, [SP, #288]

0x49adf0 LDP	X29, X30, [SP, #272]

0x49adf4 ADD	SP, SP, #368

0x49adf8 RET

0x49adfc HINT	#0

Coverage (%)	Name	Source Location	Module
►98.43+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.57+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_IJMatrixSetValuesOMPParC[...]	IJMatrix_parcsr.c:3509	exec
○	BuildIJLaplacian27pt	amg.c:2267	exec
○	main	amg.c:274	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	IJMatrix_parcsr.c:3240-3484
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3240,3256-3352,3359-3368,3376-3377,3383-3390,3399-3411,3417-3424,3433-3445,3454-3458,3466-3484.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.50 to 1.00 cycles (23.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 29% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 23.50 to 13.21 cycles (1.78x speedup).

Details

1% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
12% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3257
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3256
unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3278
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3286

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes.

General properties

nb instructions	187
nb uops	162
loop length	748
used w registers	5
used x registers	31
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	2
used z registers	2
nb stack references	27

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.25 cycles
front end	20.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	19.00	19.00	19.00	19.00	1.00	1.00	1.00	1.00	23.50	23.17	23.33	16.50	16.50
cycles	8.50	8.50	19.00	19.00	19.00	19.00	1.00	1.00	1.00	1.00	23.50	23.17	23.33	16.50	16.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	20.25
Dispatch	23.50
DIV/SQRT	5.00-20.00
Overall L1	23.50

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	0%
add-sub	12%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	0%
add-sub	12%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	29%
load	31%
store	32%
mul	25%
add-sub	34%
fma	25%
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	29%
load	31%
store	32%
mul	25%
add-sub	34%
fma	25%
div/sqrt	25%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.50 cycles. At this rate:

0% of peak load performance is reached (0.13 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 49a350

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #368	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X28, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STUR X6, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X24, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X23, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4acc30 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4acc50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SDIV X10, X8, X27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
ADD X13, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MSUB X11, X10, X27, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X8, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X12, X10, X8, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MUL X14, X13, X0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
MUL X8, X13, X8	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X13, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD X9, X10, X0, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X17, X12, X8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSEL X18, X9, X14, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X8, X13, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GE 49a4b8 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X22, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X11, X22, X11, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTW X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MADD X10, X22, X10, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB X11, X17, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X10, X12, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 49a498 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X10, X13, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X9, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X9, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X8, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X13, X10, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.CC 49a498 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
RDVL X16, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB X10, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVI V0.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V1.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR X15, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X14, X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD X16, X16, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X18, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X9, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADD Z0.D, Z1.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
CMP X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
UADDV D0, P0, Z0.D																			vect (100.0%)
FMOV X12, D0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.NE 49a4a0 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 49a4b8 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X12, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X10, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W25, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4ee4bc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3816	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X19, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STUR X17, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ X22, 49a51c <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 49a51c <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X9, [X8], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADRP X0, <4ee51c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3840	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X22, 49a554 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X8, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X24, [X8, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X7, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X30, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X19, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 49a56c <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 49addc <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0xa8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X7, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X30, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X19, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 49addc <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0xa8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTW X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDP X3, X19, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X6, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVN X27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STUR XZR, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X28, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X4, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X3, X21, [X29, #928]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X4, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X10, X8, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X8, X9, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X8, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X26, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X6, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X26, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 49a63c <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X20, X19, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #368	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	IJMatrix_parcsr.c:3240-3484
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

1% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
12% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3257
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3256
unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3278
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3286

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes.

General properties

nb instructions	187
nb uops	162
loop length	748
used w registers	5
used x registers	31
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	2
used z registers	2
nb stack references	27

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.25 cycles
front end	20.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	19.00	19.00	19.00	19.00	1.00	1.00	1.00	1.00	23.50	23.17	23.33	16.50	16.50
cycles	8.50	8.50	19.00	19.00	19.00	19.00	1.00	1.00	1.00	1.00	23.50	23.17	23.33	16.50	16.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	20.25
Dispatch	23.50
DIV/SQRT	5.00-20.00
Overall L1	23.50

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	0%
add-sub	12%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	0%
add-sub	12%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	29%
load	31%
store	32%
mul	25%
add-sub	34%
fma	25%
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	29%
load	31%
store	32%
mul	25%
add-sub	34%
fma	25%
div/sqrt	25%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.50 cycles. At this rate:

0% of peak load performance is reached (0.13 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 49a350

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #368	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X28, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STUR X6, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X24, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X23, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4acc30 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4acc50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SDIV X10, X8, X27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
ADD X13, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MSUB X11, X10, X27, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X8, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X12, X10, X8, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MUL X14, X13, X0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
MUL X8, X13, X8	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X13, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD X9, X10, X0, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X17, X12, X8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSEL X18, X9, X14, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X8, X13, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GE 49a4b8 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X22, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X11, X22, X11, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTW X12, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MADD X10, X22, X10, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB X11, X17, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X10, X12, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 49a498 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X10, X13, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X9, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X9, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X8, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X13, X10, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.CC 49a498 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
RDVL X16, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB X10, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVI V0.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI V1.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR X15, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
AND X14, X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD X16, X16, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X18, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X9, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADD Z0.D, Z1.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
CMP X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
UADDV D0, P0, Z0.D																			vect (100.0%)
FMOV X12, D0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
STR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.NE 49a4a0 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 49a4b8 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X12, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X10, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W25, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4ee4bc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3816	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X19, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STUR X17, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ X22, 49a51c <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 49a51c <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X9, [X8], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADRP X0, <4ee51c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #3840	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X22, 49a554 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X8, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X24, [X8, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X7, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X30, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X19, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 49a56c <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 49addc <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0xa8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X7, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X11, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X30, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X19, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 49addc <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0xa8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTW X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDP X3, X19, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X6, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVN X27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STUR XZR, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X28, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X4, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X3, X21, [X29, #928]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X4, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X10, X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X10, X8, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X8, X9, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X8, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X26, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X6, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X26, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 49a63c <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X20, X19, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #368	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.14–	0.19	0.09
○Loop 3296 - IJMatrix_parcsr.c:3274-3275 - exec	0.00	0.00
▼Loop 3289 - IJMatrix_parcsr.c:3291-3484 - exec–	0.00	0.00
▼Loop 3288 - IJMatrix_parcsr.c:3291-3484 - exec–	0.00	0.00
○Loop 3292 - IJMatrix_parcsr.c:3359-3362 - exec	0.00	0.00
○Loop 3286 - IJMatrix_parcsr.c:3367-3367 - exec	0.00	0.00
○Loop 3293 - IJMatrix_parcsr.c:3359-3362 - exec	0.00	0.00
○Loop 3291 - IJMatrix_parcsr.c:3359-3362 - exec	0.00	0.00
▼Loop 3287 - IJMatrix_parcsr.c:3291-3484 - exec–	0.00	0.00
▼Loop 3279 - IJMatrix_parcsr.c:3291-3484 - exec–	0.04	0.01
▼Loop 3283 - IJMatrix_parcsr.c:3383-3454 - exec–	0.15	0.05
○Loop 3284 - IJMatrix_parcsr.c:3422-3424 - exec	0.00	0.00
○Loop 3285 - IJMatrix_parcsr.c:3388-3390 - exec	0.00	0.00
▼Loop 3280 - IJMatrix_parcsr.c:3470-3484 - exec–	0.00	0.00
▼Loop 3281 - IJMatrix_parcsr.c:3475-3484 - exec–	0.00	0.00
○Loop 3282 - IJMatrix_parcsr.c:3478-3484 - exec	0.00	0.00
○Loop 3290 - IJMatrix_parcsr.c:3318-3320 - exec	0.00	0.00
○Loop 3294 - IJMatrix_parcsr.c:3282-3283 - exec	0.00	0.00
○Loop 3295 - IJMatrix_parcsr.c:3274-3275 - exec	0.00	0.00

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Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code