OV - exec - Function hypre_CSRMatrixMultiply.omp

	Function: hypre_CSRMatrixMultiply.omp_outlined	Module: exec	Source: csr_matop.c:185-302 [...]	Coverage (incl. loops): 0.68% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c: 185 - 302

--------------------------------------------------------------------------------

185: #pragma omp parallel private(ia, ib, ic, ja, jb, num_nonzeros, row_start, counter, a_entry, b_entry)

[...]

192:     ii = hypre_GetThreadNum();

193:     num_threads = hypre_NumActiveThreads();

194:

195:    size = nrows_A/num_threads;

196:    rest = nrows_A - size*num_threads;

197:     if (ii < rest)

198:     {

199:        ns = ii*size+ii;

200:        ne = (ii+1)*size+ii+1;

201:     }

202:     else

203:     {

204:        ns = ii*size+rest;

205:        ne = (ii+1)*size+rest;

206:     }

207:

208:     B_marker = hypre_CTAlloc(HYPRE_Int, ncols_B);

209:

210:     for (ib = 0; ib < ncols_B; ib++)

211:       B_marker[ib] = -1;

212:

213:     num_nonzeros = 0;

214:     for (ic = ns; ic < ne; ic++)

215:     {

216:         C_i[ic] = num_nonzeros;

217: 	if (allsquare)

218:         {

219:            B_marker[ic] = ic;

220:            num_nonzeros++;

221:         }

222: 	for (ia = A_i[ic]; ia < A_i[ic+1]; ia++)

223: 	{

224: 	   ja = A_j[ia];

225: 	   for (ib = B_i[ja]; ib < B_i[ja+1]; ib++)

226: 	   {

227: 	      jb = B_j[ib];

228: 	      if (B_marker[jb] != ic)

229: 	      {

230: 	 	 B_marker[jb] = ic;

231: 		 num_nonzeros++;

232: 	      }

233: 	   }

234:    	}

235:    }

236:    jj_count[ii] = num_nonzeros;

237:

238: #ifdef HYPRE_USING_OPENMP

239: #pragma omp barrier

240: #endif

241:

242:     if (ii)

243:     {

244:        jj = jj_count[0];

245:        for (i1 = 1; i1 < ii; i1++)

246:           jj += jj_count[i1];

247:

248:        for (i1 = ns; i1 < ne; i1++)

249:           C_i[i1] += jj;

250:     }

251:     else

252:     {

253:        C_i[nrows_A] = 0;

254:        for (i1 = 0; i1 < num_threads; i1++)

255:           C_i[nrows_A] += jj_count[i1];

256:

257:        C = hypre_CSRMatrixCreate(nrows_A, ncols_B, C_i[nrows_A]);

258:        hypre_CSRMatrixI(C) = C_i;

259:        hypre_CSRMatrixInitialize(C);

260:        C_j = hypre_CSRMatrixJ(C);

261:        C_data = hypre_CSRMatrixData(C);

262:     }

263:

264: #ifdef HYPRE_USING_OPENMP

265: #pragma omp barrier

266: #endif

267:

268:    for (ib = 0; ib < ncols_B; ib++)

269:       B_marker[ib] = -1;

270:

271:    counter = C_i[ns];

272:    for (ic = ns; ic < ne; ic++)

273:    {

274:       row_start = C_i[ic];

275:       if (allsquare)

276:       {

277:          B_marker[ic] = counter;

278:          C_data[counter] = 0;

279:          C_j[counter] = ic;

280:          counter++;

281:       }

282:       for (ia = A_i[ic]; ia < A_i[ic+1]; ia++)

283:       {

284: 	 ja = A_j[ia];

285: 	 a_entry = A_data[ia];

286: 	 for (ib = B_i[ja]; ib < B_i[ja+1]; ib++)

287: 	 {

288: 	    jb = B_j[ib];

289: 	    b_entry = B_data[ib];

290: 	    if (B_marker[jb] < row_start)

291: 	    {

292: 		B_marker[jb] = counter;

293: 		C_j[B_marker[jb]] = jb;

294: 		C_data[B_marker[jb]] = a_entry*b_entry;

295: 		counter++;

296: 	    }

297: 	    else

298: 		C_data[B_marker[jb]] += a_entry*b_entry;

299: 	}

300:       }

301:    }

302:    hypre_TFree(B_marker);

0x49ee00 SUB	SP, SP, #224

0x49ee04 STP	X29, X30, [SP, #128]

0x49ee08 STP	X28, X27, [SP, #144]

0x49ee0c STP	X26, X25, [SP, #160]

0x49ee10 STP	X24, X23, [SP, #176]

0x49ee14 STP	X22, X21, [SP, #192]

0x49ee18 STP	X20, X19, [SP, #208]

0x49ee1c ADD	X29, SP, #128

0x49ee20 STP	X6, X7, [X29, #976]

0x49ee24 STUR	X4, [X29, #496]

0x49ee28 ORR	X19, XZR, X5

0x49ee2c ORR	X24, XZR, X3

0x49ee30 ORR	X26, XZR, X2

0x49ee34 STR	X0, [SP, #64]

0x49ee38 LDP	X8, X9, [X29, #144]

0x49ee3c STUR	X9, [X29, #480]

0x49ee40 STR	X8, [SP, #40]

0x49ee44 LDR	X8, [X29, #120]

0x49ee48 LDP	X23, X22, [X29, #128]

0x49ee4c STR	X8, [SP, #32]

0x49ee50 LDP	X27, X8, [X29, #104]

0x49ee54 STUR	X8, [X29, #488]

0x49ee58 LDR	X8, [X29, #96]

0x49ee5c STUR	X8, [X29, #456]

0x49ee60 BL	4acc50

0x49ee64 ORR	X20, XZR, X0

0x49ee68 BL	4acc30

0x49ee6c LDR	X8, [X26]

0x49ee70 MOVZ	W1, #8

0x49ee74 STR	X20, [SP, #56]

0x49ee78 SDIV	X11, X8, X0

0x49ee7c STR	X11, [SP, #8]

0x49ee80 MSUB	X13, X11, X0, X8

0x49ee84 ADD	X8, X20, #1

0x49ee88 MADD	X9, X11, X20, X13

0x49ee8c MADD	X10, X11, X8, X13

0x49ee90 ADD	X11, X11, #1

0x49ee94 STP	X13, X0, [SP, #16]

0x49ee98 LDR	X0, [X24]

0x49ee9c MUL	X12, X11, X20

0x49eea0 MUL	X8, X8, X11

0x49eea4 CMP	X20, X13

0x49eea8 CSEL	X21, X9, X12, #10

0x49eeac CSEL	X28, X10, X8, #10

0x49eeb0 BL	4aaf00

0x49eeb4 LDR	X8, [X24]

0x49eeb8 ORR	X20, XZR, X0

0x49eebc CMP	X8, #1

0x49eec0 B.LT	49eee0

0x49eec4 MOVN	X9, #0

0x49eec8 ORR	X8, XZR, XZR

(3385) 0x49eecc STR	X9, [X20, X8,LSL #3]

(3385) 0x49eed0 ADD	X8, X8, #1

(3385) 0x49eed4 LDR	X10, [X24]

(3385) 0x49eed8 CMP	X8, X10

(3385) 0x49eedc B.LT	49eecc

0x49eee0 CMP	X21, X28

0x49eee4 B.GE	49efb4

0x49eee8 LDP	X3, X9, [X29, #1000]

0x49eeec LDP	X10, X11, [X29, #976]

0x49eef0 ORR	X8, XZR, XZR

0x49eef4 ORR	X13, XZR, X21

0x49eef8 LDUR	X12, [X29, #456]

0x49eefc LDR	X9, [X9]

0x49ef00 LDR	X10, [X10]

0x49ef04 LDR	X11, [X11]

0x49ef08 LDR	X12, [X12]

0x49ef0c B	49ef28

0x49ef10 HINT	#0

0x49ef14 HINT	#0

0x49ef18 HINT	#0

0x49ef1c HINT	#0

    (3381) 0x49ef20 CMP	X13, X28

    (3381) 0x49ef24 B.GE	49efbc

    (3381) 0x49ef28 STR	X8, [X9, X13,LSL #3]

    (3381) 0x49ef2c ORR	X14, XZR, X13

    (3381) 0x49ef30 LDR	X13, [X19]

    (3381) 0x49ef34 CBZ	X13, 49ef40

    (3381) 0x49ef38 ADD	X8, X8, #1

    (3381) 0x49ef3c STR	X14, [X20, X14,LSL #3]

    (3381) 0x49ef40 ADD	X13, X14, #1

    (3381) 0x49ef44 LDR	X15, [X10, X14,LSL #3]

    (3381) 0x49ef48 LDR	X0, [X10, X13,LSL #3]

    (3381) 0x49ef4c CMP	X15, X0

    (3381) 0x49ef50 B.GE	49ef20

  (3384) 0x49ef54 LDR	X16, [X27]

  (3384) 0x49ef58 B	49ef70

0x49ef5c HINT	#0

(3382) 0x49ef60 LDR	X0, [X10, X13,LSL #3]

  (3384) 0x49ef64 ADD	X15, X15, #1

  (3384) 0x49ef68 CMP	X15, X0

  (3384) 0x49ef6c B.GE	49ef20

  (3384) 0x49ef70 LDR	X17, [X11, X15,LSL #3]

  (3384) 0x49ef74 ADD	X17, X12, X17,LSL #3

  (3384) 0x49ef78 LDP	X18, X1, [X17]

  (3384) 0x49ef7c CMP	X18, X1

  (3384) 0x49ef80 B.LT	49ef94

  (3384) 0x49ef84 B	49ef64

  (3383) 0x49ef88 ADD	X18, X18, #1

  (3383) 0x49ef8c CMP	X18, X1

  (3383) 0x49ef90 B.GE	49ef60

  (3383) 0x49ef94 LDR	X0, [X16, X18,LSL #3]

  (3383) 0x49ef98 LDR	X2, [X20, X0,LSL #3]

  (3383) 0x49ef9c CMP	X2, X14

  (3383) 0x49efa0 B.EQ	49ef88

  (3383) 0x49efa4 STR	X14, [X20, X0,LSL #3]

  (3383) 0x49efa8 ADD	X8, X8, #1

  (3383) 0x49efac LDR	X1, [X17, #8]

  (3383) 0x49efb0 B	49ef88

0x49efb4 LDUR	X3, [X29, #488]

0x49efb8 ORR	X8, XZR, XZR

0x49efbc LDR	X9, [X3]

0x49efc0 LDR	X25, [SP, #56]

0x49efc4 ADRP	X0,

0x49efc8 ADD	X0, X0, #296

0x49efcc STR	X27, [SP, #48]

0x49efd0 ORR	X27, XZR, X3

0x49efd4 STR	X8, [X9, X25,LSL #3]

0x49efd8 LDR	X8, [SP, #64]

0x49efdc LDR	W1, [X8]

0x49efe0 STR	W1, [SP, #64]

0x49efe4 BL	4104c0

0x49efe8 CBZ	X25, 49f018

0x49efec LDR	X10, [X27]

0x49eff0 CNTW	X8, ALL

0x49eff4 CMP	X25, #2

0x49eff8 LDR	X9, [X10]

0x49effc B.LT	49f050

0x49f000 LDR	X27, [SP, #48]

0x49f004 SUB	X12, X25, #1

0x49f008 CMP	X12, X8

0x49f00c B.CS	49f058

0x49f010 MOVZ	W11, #1

0x49f014 B	49f0b8

0x49f018 LDUR	X8, [X29, #496]

0x49f01c LDR	X16, [SP, #24]

0x49f020 LDR	X9, [X26]

0x49f024 CMP	X16, #1

0x49f028 LDR	X8, [X8]

0x49f02c LDR	X27, [SP, #48]

0x49f030 STR	XZR, [X8, X9,LSL #3]

0x49f034 B.LT	49f1d4

0x49f038 LDUR	X9, [X29, #488]

0x49f03c CMP	X16, #1

0x49f040 LDR	X9, [X9]

0x49f044 B.NE	49f17c

0x49f048 ORR	X10, XZR, XZR

0x49f04c B	49f1c0

0x49f050 LDR	X27, [SP, #48]

0x49f054 B	49f0d0

0x49f058 PTRUE	P0.D, VL1

0x49f05c MOVI	V1.2D, #0

0x49f060 SUB	X11, XZR, X8

0x49f064 MOVI	V0.2D, #0

0x49f068 ORR	X14, XZR, XZR

0x49f06c AND	X13, X12, X11

0x49f070 RDVL	X15, #1

0x49f074 ORR	X11, X13, #0x1

0x49f078 CPY	Z1.D, P0/M, X9

0x49f07c ADD	X9, X10, #8

0x49f080 ADD	X15, X9, X15

0x49f084 PTRUE	P0.D, ALL

(3379) 0x49f088 LD1D	{Z2.D}, P0/Z, [X9, X14,LSL #3]

(3379) 0x49f08c LD1D	{Z3.D}, P0/Z, [X15, X14,LSL #3]

(3379) 0x49f090 ADD	X14, X14, X8

(3379) 0x49f094 CMP	X13, X14

(3379) 0x49f098 ADD	Z1.D, Z2.D, Z1.D

(3379) 0x49f09c ADD	Z0.D, Z3.D, Z0.D

(3379) 0x49f0a0 B.NE	49f088

0x49f0a4 ADD	Z0.D, Z0.D, Z1.D

0x49f0a8 CMP	X12, X13

0x49f0ac UADDV	D0, P0, Z0.D

0x49f0b0 FMOV	X9, D0

0x49f0b4 B.EQ	49f0d0

0x49f0b8 ADD	X10, X10, X11,LSL #3

0x49f0bc SUB	X11, X25, X11

(3380) 0x49f0c0 LDR	X12, [X10], #8

(3380) 0x49f0c4 SUBS	X11, X11, #1

(3380) 0x49f0c8 ADD	X9, X12, X9

(3380) 0x49f0cc B.NE	49f0c0

0x49f0d0 CMP	X21, X28

0x49f0d4 B.GE	49f218

0x49f0d8 LDP	X11, X12, [SP, #8]

0x49f0dc LDUR	X10, [X29, #496]

0x49f0e0 MUL	X11, X25, X11

0x49f0e4 LDR	X10, [X10]

0x49f0e8 CMP	X25, X12

0x49f0ec CSEL	X12, X25, X12, #11

0x49f0f0 ADD	X11, X11, X12

0x49f0f4 SUB	X12, X28, X11

0x49f0f8 ORR	X11, XZR, X21

0x49f0fc CMP	X12, X8

0x49f100 B.CC	49f160

0x49f104 RDVL	X16, #1

0x49f108 SUB	X11, XZR, X8

0x49f10c ADD	X15, X10, X21,LSL #3

0x49f110 ORR	X13, XZR, XZR

0x49f114 AND	X14, X12, X11

0x49f118 DUP	Z0.D, X9

0x49f11c ADD	X16, X16, X21,LSL #3

0x49f120 PTRUE	P0.D, ALL

0x49f124 ADD	X11, X21, X14

0x49f128 ADD	X16, X10, X16

(3378) 0x49f12c LD1D	{Z1.D}, P0/Z, [X15, X13,LSL #3]

(3378) 0x49f130 LD1D	{Z2.D}, P0/Z, [X16, X13,LSL #3]

(3378) 0x49f134 ADD	Z1.D, Z1.D, Z0.D

(3378) 0x49f138 ADD	Z2.D, Z2.D, Z0.D

(3378) 0x49f13c ST1D	{Z1.D}, P0, [X15, X13,LSL #3]

(3378) 0x49f140 ST1D	{Z2.D}, P0, [X16, X13,LSL #3]

(3378) 0x49f144 ADD	X13, X13, X8

(3378) 0x49f148 CMP	X14, X13

(3378) 0x49f14c B.NE	49f12c

0x49f150 CMP	X12, X14

0x49f154 B.EQ	49f218

0x49f158 HINT	#0

0x49f15c HINT	#0

(3377) 0x49f160 LDR	X8, [X10, X11,LSL #3]

(3377) 0x49f164 ADD	X8, X8, X9

(3377) 0x49f168 STR	X8, [X10, X11,LSL #3]

(3377) 0x49f16c ADD	X11, X11, #1

(3377) 0x49f170 CMP	X11, X28

(3377) 0x49f174 B.LT	49f160

0x49f178 B	49f218

0x49f17c AND	X11, X16, #0x0

0x49f180 ADD	X12, X9, #8

0x49f184 ORR	X10, XZR, XZR

(3376) 0x49f188 LDR	X14, [X26]

(3376) 0x49f18c LDUR	X13, [X12, #504]

(3376) 0x49f190 ADD	X10, X10, #2

(3376) 0x49f194 CMP	X11, X10

(3376) 0x49f198 LDR	X15, [X8, X14,LSL #3]

(3376) 0x49f19c ADD	X13, X15, X13

(3376) 0x49f1a0 STR	X13, [X8, X14,LSL #3]

(3376) 0x49f1a4 LDR	X14, [X26]

(3376) 0x49f1a8 LDR	X13, [X12], #16

(3376) 0x49f1ac LDR	X15, [X8, X14,LSL #3]

(3376) 0x49f1b0 ADD	X13, X15, X13

(3376) 0x49f1b4 STR	X13, [X8, X14,LSL #3]

(3376) 0x49f1b8 B.NE	49f188

0x49f1bc TBZ	W16, #0, 49f1d4

0x49f1c0 LDR	X9, [X9, X10,LSL #3]

0x49f1c4 LDR	X10, [X26]

0x49f1c8 LDR	X11, [X8, X10,LSL #3]

0x49f1cc ADD	X9, X11, X9

0x49f1d0 STR	X9, [X8, X10,LSL #3]

0x49f1d4 LDR	X0, [X26]

0x49f1d8 LDR	X1, [X24]

0x49f1dc LDR	X2, [X8, X0,LSL #3]

0x49f1e0 BL	49fdc0

0x49f1e4 LDR	X25, [SP, #32]

0x49f1e8 LDUR	X8, [X29, #496]

0x49f1ec STR	X0, [X25]

0x49f1f0 LDR	X8, [X8]

0x49f1f4 STR	X8, [X0]

0x49f1f8 LDR	X0, [X25]

0x49f1fc BL	49fe80

0x49f200 LDR	X8, [X25]

0x49f204 LDR	X8, [X8, #8]

0x49f208 STR	X8, [X23]

0x49f20c LDR	X8, [X25]

0x49f210 LDR	X8, [X8, #48]

0x49f214 STR	X8, [X22]

0x49f218 LDR	W1, [SP, #64]

0x49f21c ADRP	X0,

0x49f220 ADD	X0, X0, #320

0x49f224 BL	4104c0

0x49f228 LDR	X8, [X24]

0x49f22c CMP	X8, #1

0x49f230 B.LT	49f254

0x49f234 MOVN	X9, #0

0x49f238 ORR	X8, XZR, XZR

0x49f23c HINT	#0

(3375) 0x49f240 STR	X9, [X20, X8,LSL #3]

(3375) 0x49f244 ADD	X8, X8, #1

(3375) 0x49f248 LDR	X10, [X24]

(3375) 0x49f24c CMP	X8, X10

(3375) 0x49f250 B.LT	49f240

0x49f254 LDUR	X24, [X29, #480]

0x49f258 CMP	X21, X28

0x49f25c B.GE	49f378

0x49f260 LDUR	X8, [X29, #496]

0x49f264 LDP	X12, X13, [X29, #976]

0x49f268 LDR	X14, [SP, #40]

0x49f26c LDUR	X15, [X29, #456]

0x49f270 LDR	X10, [X22]

0x49f274 LDR	X11, [X23]

0x49f278 LDR	X8, [X8]

0x49f27c LDR	X12, [X12]

0x49f280 LDR	X13, [X13]

0x49f284 LDR	X14, [X14]

0x49f288 LDR	X15, [X15]

0x49f28c LDR	X9, [X8, X21,LSL #3]

0x49f290 B	49f2a8

0x49f294 HINT	#0

0x49f298 HINT	#0

0x49f29c HINT	#0

    (3370) 0x49f2a0 CMP	X21, X28

    (3370) 0x49f2a4 B.GE	49f378

    (3370) 0x49f2a8 LDR	X16, [X8, X21,LSL #3]

    (3370) 0x49f2ac LDR	X17, [X19]

    (3370) 0x49f2b0 CBZ	X17, 49f2c4

    (3370) 0x49f2b4 STR	X9, [X20, X21,LSL #3]

    (3370) 0x49f2b8 STR	XZR, [X10, X9,LSL #3]

    (3370) 0x49f2bc STR	X21, [X11, X9,LSL #3]

    (3370) 0x49f2c0 ADD	X9, X9, #1

    (3370) 0x49f2c4 LDR	X17, [X12, X21,LSL #3]

    (3370) 0x49f2c8 ADD	X21, X21, #1

    (3370) 0x49f2cc LDR	X3, [X12, X21,LSL #3]

    (3370) 0x49f2d0 CMP	X17, X3

    (3370) 0x49f2d4 B.GE	49f2a0

  (3371) 0x49f2d8 LDR	X18, [X27]

  (3371) 0x49f2dc LDR	X0, [X24]

  (3371) 0x49f2e0 B	49f2f4

  (3374) 0x49f2e4 LDR	X3, [X12, X21,LSL #3]

  (3371) 0x49f2e8 ADD	X17, X17, #1

  (3371) 0x49f2ec CMP	X17, X3

  (3371) 0x49f2f0 B.GE	49f2a0

  (3371) 0x49f2f4 LDR	X1, [X13, X17,LSL #3]

  (3371) 0x49f2f8 ADD	X1, X15, X1,LSL #3

  (3371) 0x49f2fc LDP	X2, X4, [X1]

  (3371) 0x49f300 CMP	X2, X4

  (3371) 0x49f304 B.GE	49f2e8

(3372) 0x49f308 LDR	D0, [X14, X17,LSL #3]

(3372) 0x49f30c LDR	X3, [X22]

(3372) 0x49f310 LDR	X5, [X23]

(3372) 0x49f314 B	49f348

0x49f318 HINT	#0

0x49f31c HINT	#0

(3372) 0x49f320 STR	X9, [X20, X6,LSL #3]

(3372) 0x49f324 STR	X6, [X5, X9,LSL #3]

(3372) 0x49f328 FMUL	D1, D0, D1

(3372) 0x49f32c ADD	X9, X9, #1

(3372) 0x49f330 LDR	X4, [X20, X6,LSL #3]

(3372) 0x49f334 STR	D1, [X3, X4,LSL #3]

(3372) 0x49f338 LDR	X4, [X1, #8]

(3372) 0x49f33c ADD	X2, X2, #1

(3372) 0x49f340 CMP	X2, X4

(3372) 0x49f344 B.GE	49f2e4

  (3373) 0x49f348 LDR	X6, [X18, X2,LSL #3]

  (3373) 0x49f34c LDR	D1, [X0, X2,LSL #3]

  (3373) 0x49f350 LDR	X7, [X20, X6,LSL #3]

  (3373) 0x49f354 CMP	X7, X16

  (3373) 0x49f358 B.LT	49f320

  (3373) 0x49f35c LDR	D2, [X3, X7,LSL #3]

  (3373) 0x49f360 FMADD	D1, D0, D1, D2

  (3373) 0x49f364 STR	D1, [X3, X7,LSL #3]

  (3373) 0x49f368 ADD	X2, X2, #1

  (3373) 0x49f36c CMP	X2, X4

  (3373) 0x49f370 B.LT	49f348

  (3374) 0x49f374 B	49f2e4

0x49f378 ORR	X0, XZR, X20

0x49f37c LDP	X20, X19, [SP, #208]

0x49f380 LDP	X22, X21, [SP, #192]

0x49f384 LDP	X24, X23, [SP, #176]

0x49f388 LDP	X26, X25, [SP, #160]

0x49f38c LDP	X28, X27, [SP, #144]

0x49f390 LDP	X29, X30, [SP, #128]

0x49f394 ADD	SP, SP, #224

0x49f398 B	4ab000

0x49f39c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.77+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.23+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_CSRMatrixMultiply	csr_matop.c:304	exec
○	hypre_ParTMatmul	par_csr_matop.c:3287	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:1228	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	csr_matop.c:185-302
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:185,192-302.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 31.67 to 5.00 cycles (6.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 33% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 31.67 to 24.31 cycles (1.30x speedup).

Details

3% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
50% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_CAlloc: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:208
hypre_CSRMatrixCreate: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:257
hypre_CSRMatrixInitialize: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:259
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:192
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:193
unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:239
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:265

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 6 bytes. The binary function is storing 3 bytes.

General properties

nb instructions	223
nb uops	208
loop length	892
used w registers	3
used x registers	30
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	2
used z registers	2
nb stack references	30

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	26.00 cycles
front end	26.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	14.00	14.00	22.00	22.00	22.00	22.00	1.50	1.50	1.00	1.00	31.67	31.67	31.67	13.00	13.00
cycles	14.00	14.00	22.00	22.00	22.00	22.00	1.50	1.50	1.00	1.00	31.67	31.67	31.67	13.00	13.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	26.00
Dispatch	31.67
DIV/SQRT	5.00-20.00
Overall L1	31.67

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	33%
load	25%
store	32%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	62%
fma	NA (no fma vectorizable/vectorized instructions)
other	32%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	33%
load	25%
store	32%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	62%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	32%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 31.67 cycles. At this rate:

0% of peak load performance is reached (0.19 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.09 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 49ee00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X6, X7, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X4, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X19, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X24, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X0, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X23, X22, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X27, X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4acc50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4acc30 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR X20, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SDIV X11, X8, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
STR X11, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MSUB X13, X11, X0, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X8, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X9, X11, X20, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD X10, X11, X8, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X13, X0, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X12, X11, X20	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
MUL X8, X8, X11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
CMP X20, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X21, X9, X12, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSEL X28, X10, X8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 49eee0 <hypre_CSRMatrixMultiply.omp_outlined+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X21, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 49efb4 <hypre_CSRMatrixMultiply.omp_outlined+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X3, X9, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X11, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X13, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X12, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 49ef28 <hypre_CSRMatrixMultiply.omp_outlined+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDUR X3, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4effc4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #296	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X27, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [X9, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR W1, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X25, 49f018 <hypre_CSRMatrixMultiply.omp_outlined+0x218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTW X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP X25, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B.LT 49f050 <hypre_CSRMatrixMultiply.omp_outlined+0x250>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X12, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X12, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 49f058 <hypre_CSRMatrixMultiply.omp_outlined+0x258>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 49f0b8 <hypre_CSRMatrixMultiply.omp_outlined+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X9, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LT 49f1d4 <hypre_CSRMatrixMultiply.omp_outlined+0x3d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B.NE 49f17c <hypre_CSRMatrixMultiply.omp_outlined+0x37c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 49f1c0 <hypre_CSRMatrixMultiply.omp_outlined+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 49f0d0 <hypre_CSRMatrixMultiply.omp_outlined+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PTRUE P0.D, VL1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
MOVI V1.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SUB X11, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI V0.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X13, X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RDVL X15, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ORR X11, X13, #0x1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CPY Z1.D, P0/M, X9	1	0	0	0	0	1	0	0.50	0.50	0	0	0	0	0	0	0	5	1	scal (25.0%)
ADD X9, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X9, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
CMP X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
UADDV D0, P0, Z0.D																			vect (100.0%)
FMOV X9, D0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 49f0d0 <hypre_CSRMatrixMultiply.omp_outlined+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X10, X10, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X11, X25, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X21, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 49f218 <hypre_CSRMatrixMultiply.omp_outlined+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X12, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDUR X10, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X11, X25, X11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X25, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X12, X25, X12, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X12, X28, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X11, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X12, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 49f160 <hypre_CSRMatrixMultiply.omp_outlined+0x360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
RDVL X16, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB X11, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X10, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X13, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X14, X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z0.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADD X16, X16, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD X11, X21, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X10, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X12, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 49f218 <hypre_CSRMatrixMultiply.omp_outlined+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
B 49f218 <hypre_CSRMatrixMultiply.omp_outlined+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X11, X16, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
TBZ W16, #0, 49f1d4 <hypre_CSRMatrixMultiply.omp_outlined+0x3d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X8, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [X8, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X2, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 49fdc0 <hypre_CSRMatrixCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 49fe80 <hypre_CSRMatrixInitialize>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W1, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <4ef21c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 49f254 <hypre_CSRMatrixMultiply.omp_outlined+0x454>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
LDUR X24, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 49f378 <hypre_CSRMatrixMultiply.omp_outlined+0x578>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X12, X13, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X15, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 49f2a8 <hypre_CSRMatrixMultiply.omp_outlined+0x4a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X20, X19, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4ab000 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	csr_matop.c:185-302
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:185,192-302.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 31.67 to 5.00 cycles (6.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

3% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
50% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_CAlloc: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:208
hypre_CSRMatrixCreate: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:257
hypre_CSRMatrixInitialize: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:259
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:192
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:193
unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:239
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:265

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 6 bytes. The binary function is storing 3 bytes.

General properties

nb instructions	223
nb uops	208
loop length	892
used w registers	3
used x registers	30
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	2
used z registers	2
nb stack references	30

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	26.00 cycles
front end	26.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	14.00	14.00	22.00	22.00	22.00	22.00	1.50	1.50	1.00	1.00	31.67	31.67	31.67	13.00	13.00
cycles	14.00	14.00	22.00	22.00	22.00	22.00	1.50	1.50	1.00	1.00	31.67	31.67	31.67	13.00	13.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	26.00
Dispatch	31.67
DIV/SQRT	5.00-20.00
Overall L1	31.67

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	33%
load	25%
store	32%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	62%
fma	NA (no fma vectorizable/vectorized instructions)
other	32%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	33%
load	25%
store	32%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	62%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	32%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 31.67 cycles. At this rate:

0% of peak load performance is reached (0.19 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.09 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 49ee00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X6, X7, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X4, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X19, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X24, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X0, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X8, X9, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X23, X22, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X27, X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4acc50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4acc30 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR X20, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SDIV X11, X8, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
STR X11, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MSUB X13, X11, X0, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X8, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X9, X11, X20, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD X10, X11, X8, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X13, X0, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X12, X11, X20	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
MUL X8, X8, X11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
CMP X20, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X21, X9, X12, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSEL X28, X10, X8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 4aaf00 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 49eee0 <hypre_CSRMatrixMultiply.omp_outlined+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X21, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 49efb4 <hypre_CSRMatrixMultiply.omp_outlined+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X3, X9, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X11, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X13, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X12, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 49ef28 <hypre_CSRMatrixMultiply.omp_outlined+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDUR X3, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4effc4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #296	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X27, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [X9, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR W1, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X25, 49f018 <hypre_CSRMatrixMultiply.omp_outlined+0x218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTW X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP X25, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B.LT 49f050 <hypre_CSRMatrixMultiply.omp_outlined+0x250>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X12, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X12, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CS 49f058 <hypre_CSRMatrixMultiply.omp_outlined+0x258>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 49f0b8 <hypre_CSRMatrixMultiply.omp_outlined+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X9, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LT 49f1d4 <hypre_CSRMatrixMultiply.omp_outlined+0x3d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B.NE 49f17c <hypre_CSRMatrixMultiply.omp_outlined+0x37c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 49f1c0 <hypre_CSRMatrixMultiply.omp_outlined+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 49f0d0 <hypre_CSRMatrixMultiply.omp_outlined+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PTRUE P0.D, VL1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
MOVI V1.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SUB X11, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI V0.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X13, X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RDVL X15, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ORR X11, X13, #0x1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CPY Z1.D, P0/M, X9	1	0	0	0	0	1	0	0.50	0.50	0	0	0	0	0	0	0	5	1	scal (25.0%)
ADD X9, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X9, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
CMP X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
UADDV D0, P0, Z0.D																			vect (100.0%)
FMOV X9, D0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 49f0d0 <hypre_CSRMatrixMultiply.omp_outlined+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X10, X10, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X11, X25, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X21, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 49f218 <hypre_CSRMatrixMultiply.omp_outlined+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X12, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDUR X10, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X11, X25, X11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X25, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X12, X25, X12, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X12, X28, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X11, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X12, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 49f160 <hypre_CSRMatrixMultiply.omp_outlined+0x360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
RDVL X16, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB X11, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X10, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X13, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X14, X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z0.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADD X16, X16, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD X11, X21, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X10, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X12, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 49f218 <hypre_CSRMatrixMultiply.omp_outlined+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
B 49f218 <hypre_CSRMatrixMultiply.omp_outlined+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X11, X16, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
TBZ W16, #0, 49f1d4 <hypre_CSRMatrixMultiply.omp_outlined+0x3d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X8, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [X8, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X2, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 49fdc0 <hypre_CSRMatrixCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 49fe80 <hypre_CSRMatrixInitialize>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W1, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADRP X0, <4ef21c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 49f254 <hypre_CSRMatrixMultiply.omp_outlined+0x454>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
LDUR X24, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 49f378 <hypre_CSRMatrixMultiply.omp_outlined+0x578>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X12, X13, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X15, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 49f2a8 <hypre_CSRMatrixMultiply.omp_outlined+0x4a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X20, X19, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4ab000 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixMultiply.omp_outlined–	0.68	0.33
▼Loop 3372 - csr_matop.c:272-298 - exec–	0.01	0.01
○Loop 3373 - csr_matop.c:286-298 - exec	0.35	0.12
▼Loop 3371 - csr_matop.c:272-286 - exec–	0.06	0.02
○Loop 3370 - csr_matop.c:272-282 - exec	0.00	0.00
○Loop 3374 - csr_matop.c:282-286 - exec	0.00	0.00
○Loop 3385 - csr_matop.c:210-211 - exec	0.01	0.01
○Loop 3375 - csr_matop.c:268-269 - exec	0.01	0.01
▼Loop 3382 - csr_matop.c:214-231 - exec–	0.00	0.00
○Loop 3383 - csr_matop.c:225-231 - exec	0.21	0.07
▼Loop 3384 - csr_matop.c:214-225 - exec–	0.04	0.01
○Loop 3381 - csr_matop.c:214-222 - exec	0.00	0.00
○Loop 3379 - csr_matop.c:245-246 - exec	0.00	0.00
○Loop 3377 - csr_matop.c:248-249 - exec	0.00	0.00
○Loop 3380 - csr_matop.c:245-246 - exec	0.00	0.00
○Loop 3376 - csr_matop.c:254-255 - exec	0.00	0.00
○Loop 3378 - csr_matop.c:248-249 - exec	0.00	0.00

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