OV - exec - Function hypre_CSRMatrixMatvecT.omp

	Function: hypre_CSRMatrixMatvecT.omp_outlined.23	Module: exec	Source: csr_matvec.c:554-579 [...]	Coverage (incl. loops): 0.79% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 554 - 579

--------------------------------------------------------------------------------

554: #pragma omp parallel private(i,jj,j,my_thread_num,offset)

555: #endif

556:          {

557:             my_thread_num = hypre_GetThreadNum();

558:             offset =  y_size*my_thread_num;

559: #ifdef HYPRE_USING_OPENMP

560: #pragma omp for HYPRE_SMP_SCHEDULE

561: #endif

562:             for (i = 0; i < num_rows; i++)

563:             {

564:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

565:                {

566:                   j = A_j[jj];

567:                   y_data_expand[offset + j] += A_data[jj] * x_data[i];

[...]

573: #pragma omp for HYPRE_SMP_SCHEDULE

574: #endif

575:             for (i = 0; i < y_size; i++)

576:             {

577:                for (j = 0; j < num_threads; j++)

578:                {

579:                   y_data[i] += y_data_expand[j*y_size + i];

0x4a46f0 SUB	SP, SP, #128

0x4a46f4 STP	X29, X30, [SP, #32]

0x4a46f8 STR	X27, [SP, #48]

0x4a46fc STP	X26, X25, [SP, #64]

0x4a4700 STP	X24, X23, [SP, #80]

0x4a4704 STP	X22, X21, [SP, #96]

0x4a4708 STP	X20, X19, [SP, #112]

0x4a470c ADD	X29, SP, #32

0x4a4710 ORR	X22, XZR, X7

0x4a4714 ORR	X20, XZR, X6

0x4a4718 ORR	X23, XZR, X5

0x4a471c ORR	X24, XZR, X4

0x4a4720 ORR	X19, XZR, X3

0x4a4724 ORR	X21, XZR, X2

0x4a4728 ORR	X26, XZR, X0

0x4a472c BL	4acc50

0x4a4730 LDR	X8, [X19]

0x4a4734 LDR	W19, [X26]

0x4a4738 SUBS	X27, X8, #1

0x4a473c B.LT	4a47b4

0x4a4740 LDR	X26, [X21]

0x4a4744 ORR	X25, XZR, X0

0x4a4748 MOVZ	W8, #1

0x4a474c ADRP	X0,

0x4a4750 ADD	X0, X0, #1400

0x4a4754 ADD	X3, SP, #12

0x4a4758 STR	XZR, [X29, #24]

0x4a475c ADD	X4, X29, #24

0x4a4760 SUB	X5, X29, #8

0x4a4764 ADD	X6, SP, #16

0x4a4768 MOVZ	W2, #34

0x4a476c STUR	X27, [X29, #504]

0x4a4770 STR	X8, [SP, #16]

0x4a4774 MOVZ	W7, #1

0x4a4778 STR	WZR, [SP, #12]

0x4a477c STR	X8, [SP]

0x4a4780 ORR	W1, WZR, W19

0x4a4784 BL	4103d0

0x4a4788 LDUR	X8, [X29, #504]

0x4a478c LDR	X9, [X29, #24]

0x4a4790 CMP	X8, X27

0x4a4794 CSEL	X8, X8, X27, #11

0x4a4798 CMP	X9, X8

0x4a479c STUR	X8, [X29, #504]

0x4a47a0 B.LE	4a4a00

0x4a47a4 ADRP	X0,

0x4a47a8 ADD	X0, X0, #1424

0x4a47ac ORR	W1, WZR, W19

0x4a47b0 BL	410150

0x4a47b4 ADRP	X0,

0x4a47b8 ADD	X0, X0, #1448

0x4a47bc ORR	W1, WZR, W19

0x4a47c0 BL	4104c0

0x4a47c4 LDR	X8, [X21]

0x4a47c8 SUBS	X22, X8, #1

0x4a47cc B.LT	4a49d0

0x4a47d0 MOVZ	W8, #1

0x4a47d4 ADRP	X0,

0x4a47d8 ADD	X0, X0, #1472

0x4a47dc ADD	X3, SP, #12

0x4a47e0 STR	XZR, [X29, #24]

0x4a47e4 STUR	X22, [X29, #504]

0x4a47e8 ADD	X4, X29, #24

0x4a47ec SUB	X5, X29, #8

0x4a47f0 ADD	X6, SP, #16

0x4a47f4 MOVZ	W2, #34

0x4a47f8 STR	X8, [SP, #16]

0x4a47fc STR	WZR, [SP, #12]

0x4a4800 MOVZ	W7, #1

0x4a4804 STR	X8, [SP]

0x4a4808 ORR	W1, WZR, W19

0x4a480c BL	4103d0

0x4a4810 LDUR	X8, [X29, #504]

0x4a4814 LDR	X9, [X29, #24]

0x4a4818 CMP	X8, X22

0x4a481c CSEL	X8, X8, X22, #11

0x4a4820 CMP	X9, X8

0x4a4824 STUR	X8, [X29, #504]

0x4a4828 B.GT	4a49c0

0x4a482c LDR	X10, [X29, #104]

0x4a4830 LDR	X10, [X10]

0x4a4834 CMP	X10, #1

0x4a4838 B.LT	4a49c0

0x4a483c LDR	X11, [X29, #112]

0x4a4840 LDR	X15, [X20]

0x4a4844 ADD	X13, X10, X8

0x4a4848 LDR	X17, [X21]

0x4a484c MOVZ	W0, #8

0x4a4850 PTRUE	P0.D, ALL

0x4a4854 ADD	X18, X15, X13,LSL #3

0x4a4858 LDR	X11, [X11]

0x4a485c CNTW	X13, ALL

0x4a4860 CMP	X13, #8

0x4a4864 CSEL	X0, X13, X0, #8

0x4a4868 CMP	X10, X0

0x4a486c ADD	X14, X11, X9,LSL #3

0x4a4870 ADD	X12, X11, X8,LSL #3

0x4a4874 CCMP	X17, #1, #0, #2

0x4a4878 ADD	X16, X12, #8

0x4a487c ADD	X12, X15, X9,LSL #3

0x4a4880 CSINC	W0, WZR, WZR, #1

0x4a4884 CMP	X14, X18

0x4a4888 SUB	X14, XZR, X13

0x4a488c CCMP	X12, X16, #2, #3

0x4a4890 RDVL	X16, #1

0x4a4894 AND	X14, X10, X14

0x4a4898 CSINC	W18, WZR, WZR, #2

0x4a489c ADD	X16, X16, X9,LSL #3

0x4a48a0 ORN	W18, W18, W0

0x4a48a4 ADD	X15, X15, X16

0x4a48a8 UBFM	X16, X17, #61, #60

0x4a48ac UBFM	X17, X17, #59, #58

0x4a48b0 B	4a48d4

0x4a48b4 HINT	#0

0x4a48b8 HINT	#0

0x4a48bc HINT	#0

(3549) 0x4a48c0 CMP	X9, X8

(3549) 0x4a48c4 ADD	X9, X9, #1

(3549) 0x4a48c8 ADD	X15, X15, #8

(3549) 0x4a48cc ADD	X12, X12, #8

(3549) 0x4a48d0 B.EQ	4a49c0

(3549) 0x4a48d4 LDR	D0, [X11, X9,LSL #3]

(3549) 0x4a48d8 ORR	X0, XZR, XZR

(3549) 0x4a48dc TBNZ	W18, #0, 4a490c

  (3552) 0x4a48e0 LD1D	{Z1.D}, P0/Z, [X12, X0,LSL #3]

  (3552) 0x4a48e4 LD1D	{Z2.D}, P0/Z, [X15, X0,LSL #3]

  (3552) 0x4a48e8 ADD	X0, X0, X13

  (3552) 0x4a48ec CMP	X14, X0

  (3552) 0x4a48f0 FADDA	D0, P0, D0, Z1.D

  (3552) 0x4a48f4 FADDA	D0, P0, D0, Z2.D

  (3552) 0x4a48f8 B.NE	4a48e0

(3549) 0x4a48fc CMP	X10, X14

(3549) 0x4a4900 STR	D0, [X11, X9,LSL #3]

(3549) 0x4a4904 ORR	X0, XZR, X14

(3549) 0x4a4908 B.EQ	4a48c0

(3549) 0x4a490c SUB	W1, W10, W0

(3549) 0x4a4910 ANDS	X2, X1, #0x3

(3549) 0x4a4914 B.EQ	4a494c

(3549) 0x4a4918 MUL	X3, X16, X0

(3549) 0x4a491c ORR	X1, XZR, X0

  (3551) 0x4a4920 LDR	D1, [X12, X3]

  (3551) 0x4a4924 ADD	X1, X1, #1

  (3551) 0x4a4928 ADD	X3, X3, X16

  (3551) 0x4a492c SUBS	X2, X2, #1

  (3551) 0x4a4930 FADD	D0, D1, D0

  (3551) 0x4a4934 STR	D0, [X11, X9,LSL #3]

  (3551) 0x4a4938 B.NE	4a4920

(3549) 0x4a493c SUB	X0, X0, X10

(3549) 0x4a4940 CMN	X0, #4

(3549) 0x4a4944 B.HI	4a48c0

(3549) 0x4a4948 B	4a495c

(3549) 0x4a494c ORR	X1, XZR, X0

(3549) 0x4a4950 SUB	X0, X0, X10

(3549) 0x4a4954 CMN	X0, #4

(3549) 0x4a4958 B.HI	4a48c0

(3549) 0x4a495c ADD	X2, X1, #3

(3549) 0x4a4960 ADD	X3, X1, #2

(3549) 0x4a4964 SUB	X0, X10, X1

(3549) 0x4a4968 MADD	X4, X16, X1, X16

(3549) 0x4a496c ORR	X5, XZR, X12

(3549) 0x4a4970 MUL	X1, X16, X1

(3549) 0x4a4974 MUL	X2, X16, X2

(3549) 0x4a4978 MUL	X3, X16, X3

(3549) 0x4a497c HINT	#0

  (3550) 0x4a4980 LDR	D1, [X5, X1]

  (3550) 0x4a4984 SUBS	X0, X0, #4

  (3550) 0x4a4988 FADD	D0, D1, D0

  (3550) 0x4a498c STR	D0, [X11, X9,LSL #3]

  (3550) 0x4a4990 LDR	D1, [X5, X4]

  (3550) 0x4a4994 FADD	D0, D1, D0

  (3550) 0x4a4998 STR	D0, [X11, X9,LSL #3]

  (3550) 0x4a499c LDR	D1, [X5, X3]

  (3550) 0x4a49a0 FADD	D0, D1, D0

  (3550) 0x4a49a4 STR	D0, [X11, X9,LSL #3]

  (3550) 0x4a49a8 LDR	D1, [X5, X2]

  (3550) 0x4a49ac ADD	X5, X5, X17

  (3550) 0x4a49b0 FADD	D0, D1, D0

  (3550) 0x4a49b4 STR	D0, [X11, X9,LSL #3]

  (3550) 0x4a49b8 B.NE	4a4980

(3549) 0x4a49bc B	4a48c0

0x4a49c0 ADRP	X0,

0x4a49c4 ADD	X0, X0, #1496

0x4a49c8 ORR	W1, WZR, W19

0x4a49cc BL	410150

0x4a49d0 ADRP	X0,

0x4a49d4 ADD	X0, X0, #1520

0x4a49d8 ORR	W1, WZR, W19

0x4a49dc BL	4104c0

0x4a49e0 LDP	X20, X19, [SP, #112]

0x4a49e4 LDP	X22, X21, [SP, #96]

0x4a49e8 LDR	X27, [SP, #48]

0x4a49ec LDP	X24, X23, [SP, #80]

0x4a49f0 LDP	X26, X25, [SP, #64]

0x4a49f4 LDP	X29, X30, [SP, #32]

0x4a49f8 ADD	SP, SP, #128

0x4a49fc RET

0x4a4a00 LDR	X13, [X29, #96]

0x4a4a04 LDR	X10, [X24]

0x4a4a08 LDR	X11, [X23]

0x4a4a0c MUL	X14, X26, X25

0x4a4a10 ADD	X17, X11, #16

0x4a4a14 LDR	X12, [X22]

0x4a4a18 LDR	X15, [X20]

0x4a4a1c LDR	X13, [X13]

0x4a4a20 LDR	X16, [X10, X9,LSL #3]

0x4a4a24 ADD	X14, X15, X14,LSL #3

0x4a4a28 ADD	X15, X12, #16

0x4a4a2c B	4a4a4c

0x4a4a30 HINT	#0

0x4a4a34 HINT	#0

0x4a4a38 HINT	#0

0x4a4a3c HINT	#0

(3553) 0x4a4a40 CMP	X9, X8

(3553) 0x4a4a44 ORR	X9, XZR, X18

(3553) 0x4a4a48 B.EQ	4a47a4

(3553) 0x4a4a4c ADD	X18, X9, #1

(3553) 0x4a4a50 ORR	X0, XZR, X16

(3553) 0x4a4a54 LDR	X16, [X10, X18,LSL #3]

(3553) 0x4a4a58 SUBS	X1, X0, X16

(3553) 0x4a4a5c B.GE	4a4a40

(3553) 0x4a4a60 SUB	W2, W16, W0

(3553) 0x4a4a64 ANDS	X2, X2, #0x3

(3553) 0x4a4a68 B.EQ	4a4a90

  (3555) 0x4a4a6c LDR	X3, [X11, X0,LSL #3]

  (3555) 0x4a4a70 LDR	D0, [X12, X0,LSL #3]

  (3555) 0x4a4a74 LDR	D1, [X13, X9,LSL #3]

  (3555) 0x4a4a78 ADD	X0, X0, #1

  (3555) 0x4a4a7c SUBS	X2, X2, #1

  (3555) 0x4a4a80 LDR	D2, [X14, X3,LSL #3]

  (3555) 0x4a4a84 FMADD	D0, D0, D1, D2

  (3555) 0x4a4a88 STR	D0, [X14, X3,LSL #3]

  (3555) 0x4a4a8c B.NE	4a4a6c

(3553) 0x4a4a90 CMN	X1, #4

(3553) 0x4a4a94 B.HI	4a4a40

(3553) 0x4a4a98 SUB	X1, X16, X0

(3553) 0x4a4a9c ADD	X2, X15, X0,LSL #3

(3553) 0x4a4aa0 ADD	X0, X17, X0,LSL #3

  (3554) 0x4a4aa4 LDUR	X3, [X0, #496]

  (3554) 0x4a4aa8 LDUR	D0, [X2, #496]

  (3554) 0x4a4aac LDR	D1, [X13, X9,LSL #3]

  (3554) 0x4a4ab0 SUBS	X1, X1, #4

  (3554) 0x4a4ab4 LDR	D2, [X14, X3,LSL #3]

  (3554) 0x4a4ab8 FMADD	D0, D0, D1, D2

  (3554) 0x4a4abc STR	D0, [X14, X3,LSL #3]

  (3554) 0x4a4ac0 LDUR	X3, [X0, #504]

  (3554) 0x4a4ac4 LDUR	D0, [X2, #504]

  (3554) 0x4a4ac8 LDR	D1, [X13, X9,LSL #3]

  (3554) 0x4a4acc LDR	D2, [X14, X3,LSL #3]

  (3554) 0x4a4ad0 FMADD	D0, D0, D1, D2

  (3554) 0x4a4ad4 STR	D0, [X14, X3,LSL #3]

  (3554) 0x4a4ad8 LDR	X3, [X0]

  (3554) 0x4a4adc LDR	D0, [X2]

  (3554) 0x4a4ae0 LDR	D1, [X13, X9,LSL #3]

  (3554) 0x4a4ae4 LDR	D2, [X14, X3,LSL #3]

  (3554) 0x4a4ae8 FMADD	D0, D0, D1, D2

  (3554) 0x4a4aec STR	D0, [X14, X3,LSL #3]

  (3554) 0x4a4af0 LDR	X3, [X0, #8]

  (3554) 0x4a4af4 LDR	D0, [X2, #8]

  (3554) 0x4a4af8 LDR	D1, [X13, X9,LSL #3]

  (3554) 0x4a4afc ADD	X2, X2, #32

  (3554) 0x4a4b00 ADD	X0, X0, #32

  (3554) 0x4a4b04 LDR	D2, [X14, X3,LSL #3]

  (3554) 0x4a4b08 FMADD	D0, D0, D1, D2

  (3554) 0x4a4b0c STR	D0, [X14, X3,LSL #3]

  (3554) 0x4a4b10 B.NE	4a4aa4

(3553) 0x4a4b14 B	4a4a40

0x4a4b18 HINT	#0

0x4a4b1c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.62+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.30+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_CSRMatrixMatvecT	csr_matvec.c:603	exec
○	hypre_ParCSRMatrixMatvecT	par_csr_matvec.c:432	exec
○	hypre_BoomerAMGCycle	par_cycle.c:435	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:274	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	csr_matvec.c:554-579
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:554-567,573-579.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 22.00 to 1.25 cycles (17.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 22.00 to 11.22 cycles (1.96x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:557
unknown: 6 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:573
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:573
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:573

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes. The binary function is storing 6 bytes.

General properties

nb instructions	150
nb uops	141
loop length	600
used w registers	8
used x registers	30
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.63 cycles
front end	17.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	7.50	7.50	22.00	22.00	22.00	22.00	0.00	0.00	0.00	0.00	15.00	15.00	15.00	9.00	9.00
cycles	7.50	7.50	22.00	22.00	22.00	22.00	0.00	0.00	0.00	0.00	15.00	15.00	15.00	9.00	9.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.63
Dispatch	22.00
Overall L1	22.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	24%
load	25%
store	30%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.00 cycles. At this rate:

0% of peak load performance is reached (0.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.27 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4a46f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X23, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X19, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4acc50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W19, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS X27, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4a47b4 <hypre_CSRMatrixMatvecT.omp_outlined.23+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X26, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <4ef74c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #1400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, SP, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR XZR, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STUR X27, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR WZR, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4103d0 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X9, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X8, X8, X27, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LE 4a4a00 <hypre_CSRMatrixMatvecT.omp_outlined.23+0x310>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4ef7a4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #1424	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410150 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4ef7b4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #1448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUBS X22, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 4a49d0 <hypre_CSRMatrixMatvecT.omp_outlined.23+0x2e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <4ef7d4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #1472	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, SP, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR XZR, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X22, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4103d0 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X9, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X8, X8, X22, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GT 4a49c0 <hypre_CSRMatrixMatvecT.omp_outlined.23+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4a49c0 <hypre_CSRMatrixMatvecT.omp_outlined.23+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X17, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ W0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD X18, X15, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X0, X13, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X14, X11, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X12, X11, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CCMP X17, #1, #0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X12, X15, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSINC W0, WZR, WZR, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP X14, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
SUB X14, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CCMP X12, X16, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
RDVL X16, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
AND X14, X10, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC W18, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X16, X16, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORN W18, W18, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X15, X15, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X16, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X17, X17, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4a48d4 <hypre_CSRMatrixMatvecT.omp_outlined.23+0x1e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADRP X0, <4ef9c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #1496	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410150 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4ef9d0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #1520	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X14, X26, X25	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X17, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X12, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X14, X15, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4a4a4c <hypre_CSRMatrixMatvecT.omp_outlined.23+0x35c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	csr_matvec.c:554-579
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:554-567,573-579.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:557
unknown: 6 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:573
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:573
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:573

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes. The binary function is storing 6 bytes.

General properties

nb instructions	150
nb uops	141
loop length	600
used w registers	8
used x registers	30
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.63 cycles
front end	17.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	7.50	7.50	22.00	22.00	22.00	22.00	0.00	0.00	0.00	0.00	15.00	15.00	15.00	9.00	9.00
cycles	7.50	7.50	22.00	22.00	22.00	22.00	0.00	0.00	0.00	0.00	15.00	15.00	15.00	9.00	9.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.63
Dispatch	22.00
Overall L1	22.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	24%
load	25%
store	30%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.00 cycles. At this rate:

0% of peak load performance is reached (0.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.27 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4a46f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X23, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X19, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4acc50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W19, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS X27, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4a47b4 <hypre_CSRMatrixMatvecT.omp_outlined.23+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X26, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <4ef74c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #1400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, SP, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR XZR, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STUR X27, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR WZR, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4103d0 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X9, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X8, X8, X27, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LE 4a4a00 <hypre_CSRMatrixMatvecT.omp_outlined.23+0x310>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4ef7a4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #1424	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410150 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4ef7b4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #1448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUBS X22, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 4a49d0 <hypre_CSRMatrixMatvecT.omp_outlined.23+0x2e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <4ef7d4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #1472	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, SP, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR XZR, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR X22, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4103d0 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X9, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X8, X8, X22, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GT 4a49c0 <hypre_CSRMatrixMatvecT.omp_outlined.23+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4a49c0 <hypre_CSRMatrixMatvecT.omp_outlined.23+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X17, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ W0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD X18, X15, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTW X13, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X0, X13, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X14, X11, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X12, X11, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CCMP X17, #1, #0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X12, X15, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSINC W0, WZR, WZR, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP X14, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
SUB X14, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CCMP X12, X16, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
RDVL X16, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
AND X14, X10, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CSINC W18, WZR, WZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X16, X16, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORN W18, W18, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X15, X15, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X16, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X17, X17, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4a48d4 <hypre_CSRMatrixMatvecT.omp_outlined.23+0x1e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADRP X0, <4ef9c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #1496	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410150 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4ef9d0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X0, #1520	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4104c0 <@plt_start@+0x4a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X14, X26, X25	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X17, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X12, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X14, X15, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 4a4a4c <hypre_CSRMatrixMatvecT.omp_outlined.23+0x35c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixMatvecT.omp_outlined.23–	0.79	0.38
▼Loop 3553 - csr_matvec.c:560-567 - exec–	0.10	0.04
○Loop 3555 - csr_matvec.c:564-567 - exec	0.46	0.16
○Loop 3554 - csr_matvec.c:564-567 - exec	0.12	0.04
▼Loop 3549 - csr_matvec.c:573-579 - exec–	0.00	0.00
○Loop 3550 - csr_matvec.c:577-579 - exec	0.11	0.04
○Loop 3551 - csr_matvec.c:577-579 - exec	0.00	0.00
○Loop 3552 - csr_matvec.c:577-579 - exec	0.00	0.00

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ASM code

Code clean check

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Vectorization

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Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code