OV - exec - Loop 2755

	Loop Id: 2755	Module: exec	Source: par_csr_matop.c:127-242 [...]	Coverage: 0.02%

0x483fc0 CMP	X30, X21

0x483fc4 STR	X23, [X5, X26,LSL #3]

0x483fc8 STR	X20, [X7, X26,LSL #3]

0x483fcc ORR	X19, XZR, X21

0x483fd0 ORR	X20, XZR, X24

0x483fd4 ORR	X23, XZR, X6

0x483fd8 ORR	X26, XZR, X30

0x483fdc B.EQ	4841e0

0x483fe0 LDUR	X8, [X29, #496]

0x483fe4 LDR	X8, [X8]

0x483fe8 CBZ	X8, 483ff4

0x483fec ADD	X6, X23, #1

0x483ff0 STR	X23, [X0, X26,LSL #3]

0x483ff4 LDR	X8, [X15]

0x483ff8 CBZ	X8, 4840c0

0x483ffc LDUR	X8, [X29, #488]

0x484000 ADD	X13, X8, X26,LSL #3

0x484004 LDP	X14, X8, [X13]

0x484008 CMP	X14, X8

0x48400c B.GE	4840e0

0x484010 LDR	X8, [SP, #72]

0x484014 ORR	X24, XZR, X20

0x484018 LDR	X19, [X8]

0x48401c LDUR	X8, [X29, #448]

0x484020 LDR	X27, [X8]

0x484024 B	484038

  (2759) 0x484028 LDR	X8, [X13, #8]

  (2759) 0x48402c ADD	X14, X14, #1

  (2759) 0x484030 CMP	X14, X8

  (2759) 0x484034 B.GE	4840c4

  (2759) 0x484038 LDR	X28, [X17, X14,LSL #3]

  (2759) 0x48403c ADD	X8, X28, #1

  (2759) 0x484040 LDR	X9, [X18, X28,LSL #3]

  (2759) 0x484044 LDR	X10, [X18, X8,LSL #3]

  (2759) 0x484048 B	484050

    (2761) 0x48404c ADD	X9, X9, #1

    (2761) 0x484050 CMP	X9, X10

    (2761) 0x484054 B.GE	484080

    (2761) 0x484058 LDR	X25, [X22]

    (2761) 0x48405c LDR	X12, [X19, X9,LSL #3]

    (2761) 0x484060 ADD	X30, X0, X25,LSL #3

    (2761) 0x484064 LDR	X25, [X30, X12,LSL #3]

    (2761) 0x484068 CMP	X25, X20

    (2761) 0x48406c B.GE	48404c

    (2761) 0x484070 STR	X24, [X30, X12,LSL #3]

    (2761) 0x484074 ADD	X24, X24, #1

    (2761) 0x484078 LDR	X10, [X18, X8,LSL #3]

    (2761) 0x48407c B	48404c

  (2759) 0x484080 LDR	X9, [X1, X28,LSL #3]

  (2759) 0x484084 LDR	X10, [X1, X8,LSL #3]

  (2759) 0x484088 B	484090

    (2760) 0x48408c ADD	X9, X9, #1

    (2760) 0x484090 CMP	X9, X10

    (2760) 0x484094 B.GE	484028

    (2760) 0x484098 LDR	X12, [X27, X9,LSL #3]

    (2760) 0x48409c LDR	X25, [X0, X12,LSL #3]

    (2760) 0x4840a0 CMP	X25, X23

    (2760) 0x4840a4 B.GE	48408c

    (2760) 0x4840a8 STR	X6, [X0, X12,LSL #3]

    (2760) 0x4840ac ADD	X6, X6, #1

    (2760) 0x4840b0 LDR	X10, [X1, X8,LSL #3]

    (2760) 0x4840b4 B	48408c

0x4840c0 ORR	X24, XZR, X20

0x4840c4 ADD	X30, X26, #1

0x4840c8 LDR	X28, [X2, X26,LSL #3]

0x4840cc LDR	X8, [X2, X30,LSL #3]

0x4840d0 CMP	X28, X8

0x4840d4 B.GE	483fc0

0x4840e0 ORR	X24, XZR, X20

0x4840e4 ADD	X30, X26, #1

0x4840e8 LDR	X28, [X2, X26,LSL #3]

0x4840ec LDR	X8, [X2, X30,LSL #3]

0x4840f0 CMP	X28, X8

0x4840f4 B.GE	483fc0

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 127 - 242

--------------------------------------------------------------------------------

127:     for (i1 = ns; i1 < ne; i1++)

[...]

135:       if ( allsquare ) {

136:          B_marker[i1] = jj_count_diag;

137:          jj_count_diag++;

[...]

144:       if (num_cols_offd_A)

145:       {

146:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

147:          {

148:             i2 = A_offd_j[jj2];

[...]

154:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

155:             {

156:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

164:                if (B_marker[i3] < jj_row_begin_offd)

165:                {

166:                   B_marker[i3] = jj_count_offd;

167:                   jj_count_offd++;

168:                }

169:             }

170:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

171:             {

172:                i3 = B_ext_diag_j[jj3];

173:

174:                if (B_marker[i3] < jj_row_begin_diag)

175:                {

176:                   B_marker[i3] = jj_count_diag;

177:                   jj_count_diag++;

[...]

187:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

[...]

241:       (*C_diag_i)[i1] = jj_row_begin_diag;

242:       (*C_offd_i)[i1] = jj_row_begin_offd;

Coverage (%)	Name	Source Location	Module
►97.59+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►2.41+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_ParMatmul_RowSizes	par_csr_matop.c:286	exec
○	hypre_ParMatmul	par_csr_matop.c:811	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:1226	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P10,
Function	hypre_ParMatmul_RowSizes.omp_outlined
Source	par_csr_matop.c:127-127,par_csr_matop.c:135-137,par_csr_matop.c:144-146,par_csr_matop.c:170-170,par_csr_matop.c:187-187,par_csr_matop.c:241-242
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.50
CQA cycles if no scalar integer	5.50
CQA cycles if FP arith vectorized	5.50
CQA cycles if fully vectorized	1.38
Front-end cycles	4.75
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	3.75
P3 cycles	3.75
P4 cycles	3.75
P5 cycles	3.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	5.50
P11 cycles	5.17
P12 cycles	5.33
P13 cycles	1.50
P14 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	38.00
Nb uops	38.00
Nb loads	NA
Nb stores	3.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P10,
Function	hypre_ParMatmul_RowSizes.omp_outlined
Source	par_csr_matop.c:127-127,par_csr_matop.c:135-137,par_csr_matop.c:144-146,par_csr_matop.c:170-170,par_csr_matop.c:187-187,par_csr_matop.c:241-242
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.50
CQA cycles if no scalar integer	5.50
CQA cycles if FP arith vectorized	5.50
CQA cycles if fully vectorized	1.38
Front-end cycles	4.75
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	3.75
P3 cycles	3.75
P4 cycles	3.75
P5 cycles	3.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	5.50
P11 cycles	5.17
P12 cycles	5.33
P13 cycles	1.50
P14 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	38.00
Nb uops	38.00
Nb loads	NA
Nb stores	3.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParMatmul_RowSizes.omp_outlined
Source file and lines	par_csr_matop.c:127-242
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,135-137,144-148,154-156,164-177,187,241-242.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,135-137,144-146,170,187,241-242.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.50 to 1.37 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	38
nb uops	38
loop length	152
used w registers	0
used x registers	20
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.75 cycles
front end	4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	5.50	5.17	5.33	1.50	1.50
cycles	3.50	3.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	5.50	5.17	5.33	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.75
Dispatch	5.50
Overall L1	5.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.50 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 483fc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
CMP X30, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
STR X23, [X5, X26,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X20, [X7, X26,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X20, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X23, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X26, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B.EQ 4841e0 <hypre_ParMatmul_RowSizes.omp_outlined+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #496]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 483ff4 <hypre_ParMatmul_RowSizes.omp_outlined+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X6, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X23, [X0, X26,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X15]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 4840c0 <hypre_ParMatmul_RowSizes.omp_outlined+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #488]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X8, X26,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDP X14, X8, [X13]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP X14, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4840e0 <hypre_ParMatmul_RowSizes.omp_outlined+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X24, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X19, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X27, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 484038 <hypre_ParMatmul_RowSizes.omp_outlined+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X30, X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X28, [X2, X26,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X2, X30,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X28, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 483fc0 <hypre_ParMatmul_RowSizes.omp_outlined+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X30, X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X28, [X2, X26,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X2, X30,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X28, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.GE 483fc0 <hypre_ParMatmul_RowSizes.omp_outlined+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_ParMatmul_RowSizes.omp_outlined
Source file and lines	par_csr_matop.c:127-242
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

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potential
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Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.50 to 1.37 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	38
nb uops	38
loop length	152
used w registers	0
used x registers	20
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.75 cycles
front end	4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	5.50	5.17	5.33	1.50	1.50
cycles	3.50	3.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	5.50	5.17	5.33	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.75
Dispatch	5.50
Overall L1	5.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.50 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 483fc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
CMP X30, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
STR X23, [X5, X26,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X20, [X7, X26,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X20, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X23, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X26, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B.EQ 4841e0 <hypre_ParMatmul_RowSizes.omp_outlined+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #496]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 483ff4 <hypre_ParMatmul_RowSizes.omp_outlined+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X6, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X23, [X0, X26,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X15]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 4840c0 <hypre_ParMatmul_RowSizes.omp_outlined+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #488]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X8, X26,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDP X14, X8, [X13]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP X14, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4840e0 <hypre_ParMatmul_RowSizes.omp_outlined+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X24, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X19, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X27, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 484038 <hypre_ParMatmul_RowSizes.omp_outlined+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X30, X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X28, [X2, X26,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X2, X30,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X28, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 483fc0 <hypre_ParMatmul_RowSizes.omp_outlined+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X30, X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X28, [X2, X26,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X2, X30,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X28, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.GE 483fc0 <hypre_ParMatmul_RowSizes.omp_outlined+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code