OV - exec - Loop 3553

0x4a4a40 CMP	X9, X8

0x4a4a44 ORR	X9, XZR, X18

0x4a4a48 B.EQ	4a47a4

0x4a4a4c ADD	X18, X9, #1

0x4a4a50 ORR	X0, XZR, X16

0x4a4a54 LDR	X16, [X10, X18,LSL #3]

0x4a4a58 SUBS	X1, X0, X16

0x4a4a5c B.GE	4a4a40

0x4a4a60 SUB	W2, W16, W0

0x4a4a64 ANDS	X2, X2, #0x3

0x4a4a68 B.EQ	4a4a90

  (3555) 0x4a4a6c LDR	X3, [X11, X0,LSL #3]

  (3555) 0x4a4a70 LDR	D0, [X12, X0,LSL #3]

  (3555) 0x4a4a74 LDR	D1, [X13, X9,LSL #3]

  (3555) 0x4a4a78 ADD	X0, X0, #1

  (3555) 0x4a4a7c SUBS	X2, X2, #1

  (3555) 0x4a4a80 LDR	D2, [X14, X3,LSL #3]

  (3555) 0x4a4a84 FMADD	D0, D0, D1, D2

  (3555) 0x4a4a88 STR	D0, [X14, X3,LSL #3]

  (3555) 0x4a4a8c B.NE	4a4a6c

0x4a4a90 CMN	X1, #4

0x4a4a94 B.HI	4a4a40

0x4a4a98 SUB	X1, X16, X0

0x4a4a9c ADD	X2, X15, X0,LSL #3

0x4a4aa0 ADD	X0, X17, X0,LSL #3

  (3554) 0x4a4aa4 LDUR	X3, [X0, #496]

  (3554) 0x4a4aa8 LDUR	D0, [X2, #496]

  (3554) 0x4a4aac LDR	D1, [X13, X9,LSL #3]

  (3554) 0x4a4ab0 SUBS	X1, X1, #4

  (3554) 0x4a4ab4 LDR	D2, [X14, X3,LSL #3]

  (3554) 0x4a4ab8 FMADD	D0, D0, D1, D2

  (3554) 0x4a4abc STR	D0, [X14, X3,LSL #3]

  (3554) 0x4a4ac0 LDUR	X3, [X0, #504]

  (3554) 0x4a4ac4 LDUR	D0, [X2, #504]

  (3554) 0x4a4ac8 LDR	D1, [X13, X9,LSL #3]

  (3554) 0x4a4acc LDR	D2, [X14, X3,LSL #3]

  (3554) 0x4a4ad0 FMADD	D0, D0, D1, D2

  (3554) 0x4a4ad4 STR	D0, [X14, X3,LSL #3]

  (3554) 0x4a4ad8 LDR	X3, [X0]

  (3554) 0x4a4adc LDR	D0, [X2]

  (3554) 0x4a4ae0 LDR	D1, [X13, X9,LSL #3]

  (3554) 0x4a4ae4 LDR	D2, [X14, X3,LSL #3]

  (3554) 0x4a4ae8 FMADD	D0, D0, D1, D2

  (3554) 0x4a4aec STR	D0, [X14, X3,LSL #3]

  (3554) 0x4a4af0 LDR	X3, [X0, #8]

  (3554) 0x4a4af4 LDR	D0, [X2, #8]

  (3554) 0x4a4af8 LDR	D1, [X13, X9,LSL #3]

  (3554) 0x4a4afc ADD	X2, X2, #32

  (3554) 0x4a4b00 ADD	X0, X0, #32

  (3554) 0x4a4b04 LDR	D2, [X14, X3,LSL #3]

  (3554) 0x4a4b08 FMADD	D0, D0, D1, D2

  (3554) 0x4a4b0c STR	D0, [X14, X3,LSL #3]

  (3554) 0x4a4b10 B.NE	4a4aa4

0x4a4b14 B	4a4a40

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 560 - 567

--------------------------------------------------------------------------------

560: #pragma omp for HYPRE_SMP_SCHEDULE

561: #endif

562:             for (i = 0; i < num_rows; i++)

563:             {

564:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

565:                {

566:                   j = A_j[jj];

567:                   y_data_expand[offset + j] += A_data[jj] * x_data[i];

Coverage (%)	Name	Source Location	Module
►97.79+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►2.21+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_CSRMatrixMatvecT	csr_matvec.c:603	exec
○	hypre_ParCSRMatrixMatvecT	par_csr_matvec.c:432	exec
○	hypre_BoomerAMGCycle	par_cycle.c:435	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:274	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.89
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	P2, P3, P4, P5,
Function	hypre_CSRMatrixMatvecT.omp_outlined.23
Source	csr_matvec.c:560-560,csr_matvec.c:564-564
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.75
CQA cycles if no scalar integer	2.75
CQA cycles if FP arith vectorized	2.75
CQA cycles if fully vectorized	0.56
Front-end cycles	2.13
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	2.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.33
P11 cycles	0.33
P12 cycles	0.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	17.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.61
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	21.88
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.89
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	P2, P3, P4, P5,
Function	hypre_CSRMatrixMatvecT.omp_outlined.23
Source	csr_matvec.c:560-560,csr_matvec.c:564-564
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.75
CQA cycles if no scalar integer	2.75
CQA cycles if FP arith vectorized	2.75
CQA cycles if fully vectorized	0.56
Front-end cycles	2.13
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	2.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.33
P11 cycles	0.33
P12 cycles	0.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	17.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.61
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	21.88
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_CSRMatrixMatvecT.omp_outlined.23
Source file and lines	csr_matvec.c:560-567
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560-567.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560,564.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.75 to 0.56 cycles (4.89x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	17
nb uops	17
loop length	68
used w registers	3
used x registers	11
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.13 cycles
front end	2.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00
cycles	2.50	2.50	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.13
Dispatch	2.75
Overall L1	2.75

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	23%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	21%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.75 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4a4a40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput	Vectorization
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
ORR X9, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
B.EQ 4a47a4 <hypre_CSRMatrixMatvecT.omp_outlined.23+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ADD X18, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
ORR X0, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
LDR X16, [X10, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
SUBS X1, X0, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.GE 4a4a40 <hypre_CSRMatrixMatvecT.omp_outlined.23+0x350>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SUB W2, W16, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
ANDS X2, X2, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.EQ 4a4a90 <hypre_CSRMatrixMatvecT.omp_outlined.23+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
CMN X1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.HI 4a4a40 <hypre_CSRMatrixMatvecT.omp_outlined.23+0x350>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SUB X1, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD X2, X15, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD X0, X17, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
B 4a4a40 <hypre_CSRMatrixMatvecT.omp_outlined.23+0x350>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_CSRMatrixMatvecT.omp_outlined.23
Source file and lines	csr_matvec.c:560-567
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560-567.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:560,564.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.75 to 0.56 cycles (4.89x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	17
nb uops	17
loop length	68
used w registers	3
used x registers	11
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.13 cycles
front end	2.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00
cycles	2.50	2.50	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.13
Dispatch	2.75
Overall L1	2.75

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	23%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	21%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.75 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4a4a40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput	Vectorization
CMP X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
ORR X9, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
B.EQ 4a47a4 <hypre_CSRMatrixMatvecT.omp_outlined.23+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ADD X18, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
ORR X0, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
LDR X16, [X10, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
SUBS X1, X0, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.GE 4a4a40 <hypre_CSRMatrixMatvecT.omp_outlined.23+0x350>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SUB W2, W16, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (12.5%)
ANDS X2, X2, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.EQ 4a4a90 <hypre_CSRMatrixMatvecT.omp_outlined.23+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
CMN X1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.HI 4a4a40 <hypre_CSRMatrixMatvecT.omp_outlined.23+0x350>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SUB X1, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD X2, X15, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
ADD X0, X17, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
B 4a4a40 <hypre_CSRMatrixMatvecT.omp_outlined.23+0x350>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code