OV - exec - Loop 700

	Loop Id: 700	Module: exec	Source: par_multi_interp.c:939-999 [...]	Coverage: 0.30%

  (699) 0x435900 LDUR	X10, [X29, #472]

  (699) 0x435904 ADD	X18, X18, #1

  (699) 0x435908 CMP	X18, X10

  (699) 0x43590c B.GE	435b44

  (699) 0x435910 LDUR	X10, [X29, #440]

  (699) 0x435914 LDR	X1, [X10, X18,LSL #3]

  (699) 0x435918 STR	X8, [X11, X1,LSL #3]

  (699) 0x43591c STR	X9, [X12, X1,LSL #3]

  (699) 0x435920 ADD	X2, X1, #1

  (699) 0x435924 LDR	X3, [X13, X1,LSL #3]

  (699) 0x435928 LDR	X10, [X13, X2,LSL #3]

  (699) 0x43592c CMP	X3, X10

  (699) 0x435930 B.GE	435a40

0x435934 LDUR	X10, [X29, #480]

0x435938 LDR	X5, [X19]

0x43593c LDR	X4, [X10]

0x435940 LDUR	X10, [X29, #488]

0x435944 LDR	X6, [X10]

0x435948 LDUR	X10, [X29, #496]

0x43594c LDR	X7, [X10]

0x435950 B	435970

0x435960 LDR	X10, [X13, X2,LSL #3]

0x435964 ADD	X3, X3, #1

0x435968 CMP	X3, X10

0x43596c B.GE	435a40

0x435970 LDR	X10, [X14, X3,LSL #3]

0x435974 LDR	X25, [X21]

0x435978 LDR	X20, [X15, X10,LSL #3]

0x43597c SUB	X25, X25, #1

0x435980 CMP	X20, X25

0x435984 B.NE	435960

0x435988 ADD	X26, X10, #1

0x43598c LDR	X20, [X4, X26,LSL #3]

0x435990 CMP	X20, #1

0x435994 B.LT	4359e4

0x435998 LDR	X30, [X11, X10,LSL #3]

0x43599c ADD	X25, X20, X30

0x4359a0 B	4359b0

  (702) 0x4359a4 ADD	X30, X30, #1

  (702) 0x4359a8 CMP	X30, X25

  (702) 0x4359ac B.GE	4359e4

  (702) 0x4359b0 LDR	X20, [X21]

  (702) 0x4359b4 ADD	X20, X5, X20,LSL #3

  (702) 0x4359b8 LDUR	X20, [X20, #504]

  (702) 0x4359bc LDR	X28, [X20, X30,LSL #3]

  (702) 0x4359c0 LDR	X20, [X22, X28,LSL #3]

  (702) 0x4359c4 CMP	X20, X1

  (702) 0x4359c8 B.EQ	4359a4

  (702) 0x4359cc LDR	X20, [X4, X2,LSL #3]

  (702) 0x4359d0 ADD	X8, X8, #1

  (702) 0x4359d4 ADD	X20, X20, #1

  (702) 0x4359d8 STR	X20, [X4, X2,LSL #3]

  (702) 0x4359dc STR	X1, [X22, X28,LSL #3]

  (702) 0x4359e0 B	4359a4

0x4359e4 LDR	X20, [X6, X26,LSL #3]

0x4359e8 CMP	X20, #1

0x4359ec B.LT	435960

  (699) 0x435a40 LDR	X3, [X16, X1,LSL #3]

  (699) 0x435a44 LDR	X10, [X16, X2,LSL #3]

  (699) 0x435a48 CMP	X3, X10

  (699) 0x435a4c B.GE	435900

  (699) 0x435a50 LDP	X4, X5, [X29, #960]

  (699) 0x435a54 LDUR	X6, [X29, #464]

  (699) 0x435a58 LDR	X4, [X4]

  (699) 0x435a5c LDR	X5, [X5]

  (699) 0x435a60 LDR	X6, [X6]

  (699) 0x435a64 B	435a78

    (703) 0x435a68 LDR	X10, [X16, X2,LSL #3]

    (703) 0x435a6c ADD	X3, X3, #1

    (703) 0x435a70 CMP	X3, X10

    (703) 0x435a74 B.GE	435900

    (703) 0x435a78 LDR	X7, [X17, X3,LSL #3]

    (703) 0x435a7c LDR	X25, [X21]

    (703) 0x435a80 LDR	X20, [X0, X7,LSL #3]

    (703) 0x435a84 SUB	X25, X25, #1

    (703) 0x435a88 CMP	X20, X25

    (703) 0x435a8c B.NE	435a6c

    (703) 0x435a90 ADD	X20, X5, X7,LSL #3

    (703) 0x435a94 LDR	X20, [X20, #8]

    (703) 0x435a98 CMP	X20, #1

    (703) 0x435a9c B.LT	435a6c

    (703) 0x435aa0 UBFM	X10, X7, #61, #60

    (703) 0x435aa4 LDR	X7, [X4, X10]

    (703) 0x435aa8 LDUR	X10, [X29, #488]

    (703) 0x435aac LDR	X26, [X10]

    (703) 0x435ab0 LDUR	X10, [X29, #480]

    (703) 0x435ab4 ADD	X30, X20, X7

    (703) 0x435ab8 LDR	X10, [X10]

    (703) 0x435abc B	435acc

      (704) 0x435ac0 ADD	X7, X7, #1

      (704) 0x435ac4 CMP	X7, X30

      (704) 0x435ac8 B.GE	435a68

      (704) 0x435acc LDR	X20, [X21]

      (704) 0x435ad0 LDR	X20, [X6, X20,LSL #3]

      (704) 0x435ad4 LDR	X25, [X20, X7,LSL #3]

      (704) 0x435ad8 TBNZ	X25, #63, 435b00

      (704) 0x435adc LDR	X20, [X23, X25,LSL #3]

      (704) 0x435ae0 CMP	X20, X1

      (704) 0x435ae4 B.EQ	435ac0

      (704) 0x435ae8 LDR	X20, [X26, X2,LSL #3]

      (704) 0x435aec ADD	X9, X9, #1

      (704) 0x435af0 ADD	X20, X20, #1

      (704) 0x435af4 STR	X20, [X26, X2,LSL #3]

      (704) 0x435af8 STR	X1, [X23, X25,LSL #3]

      (704) 0x435afc B	435ac0

      (704) 0x435b00 ORN	X25, XZR, X25

      (704) 0x435b04 LDR	X20, [X22, X25,LSL #3]

      (704) 0x435b08 CMP	X20, X1

      (704) 0x435b0c B.EQ	435ac0

      (704) 0x435b10 LDR	X20, [X10, X2,LSL #3]

      (704) 0x435b14 ADD	X8, X8, #1

      (704) 0x435b18 ADD	X20, X20, #1

      (704) 0x435b1c STR	X20, [X10, X2,LSL #3]

      (704) 0x435b20 STR	X1, [X22, X25,LSL #3]

      (704) 0x435b24 B	435ac0

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 939 - 999

--------------------------------------------------------------------------------

939:           for (i=thread_start; i < thread_stop; i++)

940:           {

941:              i1 = pass_array[i];

942:              P_diag_start[i1] = cnt_nz;

943:              P_offd_start[i1] = cnt_nz_offd;

944:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

945:              {

946:                 j1 = S_diag_j[j];

947:                 if (assigned[j1] == pass-1)

948:                 {

949:                    j_start = P_diag_start[j1];

950:                    j_end = j_start+P_diag_i[j1+1];

951:                    for (k=j_start; k < j_end; k++)

952:                    {

953:                       k1 = P_diag_pass[pass-1][k];

954:                       if (P_marker[k1] != i1)

955:                       {

956:                          cnt_nz++;

957:                          P_diag_i[i1+1]++;

958:                          P_marker[k1] = i1;

959:                       }

960:                    }

961:                    j_start = P_offd_start[j1];

962:                    j_end = j_start+P_offd_i[j1+1];

963:                    for (k=j_start; k < j_end; k++)

[...]

976:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

977:              {

978:                 j1 = S_offd_j[j];

979:                 if (assigned_offd[j1] == pass-1)

980:                 {

981:                    j_start = Pext_start[j1];

982:                    j_end = j_start+Pext_i[j1+1];

983:                    for (k=j_start; k < j_end; k++)

984:                    {

985:                       k1 = Pext_pass[pass][k];

986:                       if (k1 < 0)

987:                       {

988:                          if (P_marker[-k1-1] != i1)

989:                          {

990:                             cnt_nz++;

991:                             P_diag_i[i1+1]++;

992:                             P_marker[-k1-1] = i1;

993:                          }

994:                       }

995:                       else if (P_marker_offd[k1] != i1)

996:                       {

997:                          cnt_nz_offd++;

998:                          P_offd_i[i1+1]++;

999:                          P_marker_offd[k1] = i1;

Coverage (%)	Name	Source Location	Module
►98.56+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.44+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:693	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:785	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass.omp_outlined.9
Source	par_multi_interp.c:944-947,par_multi_interp.c:950-951,par_multi_interp.c:962-963
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.67
CQA cycles if no scalar integer	4.67
CQA cycles if FP arith vectorized	4.67
CQA cycles if fully vectorized	1.17
Front-end cycles	3.50
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	4.67
P11 cycles	4.67
P12 cycles	4.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	28.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P10, P11, P12,
Function	hypre_BoomerAMGBuildMultipass.omp_outlined.9
Source	par_multi_interp.c:944-947,par_multi_interp.c:950-951,par_multi_interp.c:962-963
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.67
CQA cycles if no scalar integer	4.67
CQA cycles if FP arith vectorized	4.67
CQA cycles if fully vectorized	1.17
Front-end cycles	3.50
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	4.67
P11 cycles	4.67
P12 cycles	4.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	28.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass.omp_outlined.9
Source file and lines	par_multi_interp.c:939-999
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-963,976-999.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:944-947,950-951,962-963.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.67 to 1.17 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	28
nb uops	28
loop length	112
used w registers	0
used x registers	18
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00
cycles	3.00	3.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.50
Dispatch	4.67
Overall L1	4.67

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.67 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 435960

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X5, [X19]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
LDR X4, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDUR X10, [X29, #488]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X6, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDUR X10, [X29, #496]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X7, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
B 435970 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
CMP X3, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.GE 435a40 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X14, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X25, [X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
LDR X20, [X15, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
SUB X25, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
CMP X20, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.NE 435960 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x2c0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ADD X26, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
LDR X20, [X4, X26,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.LT 4359e4 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x344>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [X11, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
ADD X25, X20, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
B 4359b0 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x310>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X20, [X6, X26,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	N/A
B.LT 435960 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x2c0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass.omp_outlined.9
Source file and lines	par_multi_interp.c:939-999
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.67 to 1.17 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	28
nb uops	28
loop length	112
used w registers	0
used x registers	18
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00
cycles	3.00	3.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.50
Dispatch	4.67
Overall L1	4.67

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.67 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 435960

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X5, [X19]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
LDR X4, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDUR X10, [X29, #488]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X6, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDUR X10, [X29, #496]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X7, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
B 435970 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
CMP X3, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.GE 435a40 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X14, X3,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X25, [X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
LDR X20, [X15, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
SUB X25, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
CMP X20, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.NE 435960 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x2c0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ADD X26, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	N/A
LDR X20, [X4, X26,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.LT 4359e4 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x344>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [X11, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
ADD X25, X20, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25	scal (25.0%)
B 4359b0 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x310>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X20, [X6, X26,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33	N/A
B.LT 435960 <hypre_BoomerAMGBuildMultipass.omp_outlined.9+0x2c0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code