OV - exec - Function hypre_BoomerAMGCoarsenPMIS._omp

	Function: hypre_BoomerAMGCoarsenPMIS._omp_fn.6	Module: exec	Source: par_coarsen.c:2354-2381	Coverage (incl. loops): 0.74% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2354 - 2381

--------------------------------------------------------------------------------

2354: #pragma omp parallel for private(ig, i, jS, j, jj) HYPRE_SMP_SCHEDULE

2355: #endif

2356:         for (ig = 0; ig < graph_size; ig++)

2357:         {

2358:            i = graph_array[ig];

2359:            if (measure_array[i] > 1)

2360:            {

2361:               for (jS = S_diag_i[i]; jS < S_diag_i[i+1]; jS++)

2362:               {

2363:                  j = S_diag_j[jS];

2364:                  if (measure_array[j] > 1)

2365:                  {

2366:                     if (measure_array[i] > measure_array[j])

2367:                        CF_marker[j] = 0;

2368:                     else if (measure_array[j] > measure_array[i])

2369:                        CF_marker[i] = 0;

2370:                  }

2371:               } /* for each local neighbor j of i */

2372:               for (jS = S_offd_i[i]; jS < S_offd_i[i+1]; jS++)

2373:               {

2374:                  jj = S_offd_j[jS];

2375:                  j = num_variables+jj;

2376:                  if (measure_array[j] > 1)

2377:                  {

2378:                     if (measure_array[i] > measure_array[j])

2379:                        CF_marker_offd[jj] = 0;

2380:                     else if (measure_array[j] > measure_array[i])

2381:                        CF_marker[i] = 0;

0x4272e0 STP	X29, X30, [SP, #976]!

0x4272e4 ADD	X29, SP, #0

0x4272e8 STP	X19, X20, [SP, #16]

0x4272ec ORR	X19, XZR, X0

0x4272f0 LDR	X0, [X0, #72]

0x4272f4 STR	X21, [SP, #32]

0x4272f8 LDR	X21, [X0]

0x4272fc BL	4100b0

0x427300 SBFM	X20, X0, #0, #31

0x427304 BL	410200

0x427308 SBFM	X3, X0, #0, #31

0x42730c SDIV	X10, X21, X20

0x427310 MSUB	X1, X10, X20, X21

0x427314 CMP	X3, X1

0x427318 B.LT	427454

0x42731c MADD	X4, X10, X3, X1

0x427320 ADD	X5, X10, X4

0x427324 CMP	X4, X5

0x427328 B.GE	42736c

0x42732c LDR	X6, [X19, #64]

0x427330 FMOV	D31, #1.0000000

0x427334 LDP	X14, X9, [X19]

0x427338 LDP	X13, X8, [X19, #16]

0x42733c ADD	X3, X6, X4,LSL #3

0x427340 ADD	X16, X6, X5,LSL #3

0x427344 LDP	X7, X11, [X19, #32]

0x427348 LDP	X15, X2, [X19, #48]

(109) 0x42734c LDR	X12, [X3]

(109) 0x427350 UBFM	X17, X12, #61, #60

(109) 0x427354 LDR	D30, [X2, X17]

(109) 0x427358 FCMPE	D30, D31

(109) 0x42735c B.GT	42737c

(109) 0x427360 ADD	X3, X3, #8

(109) 0x427364 CMP	X16, X3

(109) 0x427368 B.NE	42734c

0x42736c LDR	X21, [SP, #32]

0x427370 LDP	X19, X20, [SP, #16]

0x427374 LDP	X29, X30, [SP], #48

0x427378 RET

(109) 0x42737c ADD	X18, X17, #8

(109) 0x427380 LDR	X20, [X14, X17]

(109) 0x427384 ADD	X30, X14, X18

(109) 0x427388 LDR	X21, [X14, X18]

(109) 0x42738c CMP	X20, X21

(109) 0x427390 B.GE	4273c0

(109) 0x427394 HINT	#0

(109) 0x427398 HINT	#0

(109) 0x42739c HINT	#0

  (111) 0x4273a0 LDR	X19, [X9, X20,LSL #3]

  (111) 0x4273a4 UBFM	X0, X19, #61, #60

  (111) 0x4273a8 LDR	D0, [X2, X0]

  (111) 0x4273ac FCMPE	D0, D31

  (111) 0x4273b0 B.GT	427404

  (111) 0x4273b4 ADD	X20, X20, #1

  (111) 0x4273b8 CMP	X20, X21

  (111) 0x4273bc B.LT	4273a0

(109) 0x4273c0 LDR	X6, [X13, X17]

(109) 0x4273c4 ADD	X10, X13, X18

(109) 0x4273c8 LDR	X5, [X13, X18]

(109) 0x4273cc CMP	X6, X5

(109) 0x4273d0 B.GE	427360

(109) 0x4273d4 HINT	#0

(109) 0x4273d8 HINT	#0

(109) 0x4273dc HINT	#0

  (110) 0x4273e0 LDR	X1, [X8, X6,LSL #3]

  (110) 0x4273e4 ADD	X4, X7, X1

  (110) 0x4273e8 LDR	D29, [X2, X4,LSL #3]

  (110) 0x4273ec FCMPE	D29, D31

  (110) 0x4273f0 B.GT	427420

  (110) 0x4273f4 ADD	X6, X6, #1

  (110) 0x4273f8 CMP	X6, X5

  (110) 0x4273fc B.LT	4273e0

(109) 0x427400 B	427360

  (111) 0x427404 FCMPE	D30, D0

  (111) 0x427408 B.GT	427448

  (111) 0x42740c B.MI	427414

  (111) 0x427410 B	4273b4

  (111) 0x427414 STR	XZR, [X11, X17]

  (111) 0x427418 LDR	X21, [X30]

  (111) 0x42741c B	4273b4

  (110) 0x427420 FCMPE	D30, D29

  (110) 0x427424 B.GT	42743c

  (110) 0x427428 B.MI	427430

  (110) 0x42742c B	4273f4

  (110) 0x427430 STR	XZR, [X11, X17]

  (110) 0x427434 LDR	X5, [X10]

  (110) 0x427438 B	4273f4

  (110) 0x42743c STR	XZR, [X15, X1,LSL #3]

  (110) 0x427440 LDR	X5, [X10]

  (110) 0x427444 B	4273f4

  (111) 0x427448 STR	XZR, [X11, X0]

  (111) 0x42744c LDR	X21, [X30]

  (111) 0x427450 B	4273b4

0x427454 ADD	X10, X10, #1

0x427458 MOVZ	X1, #0

0x42745c B	42731c

Coverage (%)	Name	Source Location	Module
►98.74+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.19+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGCoarsenPMIS	par_coarsen.c:2393	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:612	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_coarsen.c:2354-2381
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354-2381.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 39% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 4.50 cycles (4.44x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	34
nb uops	34
loop length	136
used w registers	0
used x registers	22
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	0
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.25 cycles
front end	4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	4.25	4.25	4.25	4.25	0.25	0.25	0.25	0.25	4.50	4.17	4.33	1.50	1.50
cycles	3.00	3.00	4.25	4.25	4.25	4.25	0.25	0.25	0.25	0.25	4.50	4.17	4.33	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	4.25
Dispatch	4.50
DIV/SQRT	5.00-20.00
Overall L1	5.00-20.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	39%
load	40%
store	41%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
other	55%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	39%
load	40%
store	41%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4272e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4100b0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X20, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
BL 410200 <@plt_start@+0x1e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X3, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
SDIV X10, X21, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X1, X10, X20, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 427454 <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X4, X10, X3, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X5, X10, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X4, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42736c <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [X19, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FMOV D31, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDP X14, X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X13, X8, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ADD X3, X6, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X6, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X7, X11, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X15, X2, [X19, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X10, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 42731c <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_coarsen.c:2354-2381
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354-2381.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 39% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 4.50 cycles (4.44x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	34
nb uops	34
loop length	136
used w registers	0
used x registers	22
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	0
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.25 cycles
front end	4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	4.25	4.25	4.25	4.25	0.25	0.25	0.25	0.25	4.50	4.17	4.33	1.50	1.50
cycles	3.00	3.00	4.25	4.25	4.25	4.25	0.25	0.25	0.25	0.25	4.50	4.17	4.33	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	4.25
Dispatch	4.50
DIV/SQRT	5.00-20.00
Overall L1	5.00-20.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	39%
load	40%
store	41%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
other	55%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	39%
load	40%
store	41%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4272e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4100b0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X20, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
BL 410200 <@plt_start@+0x1e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X3, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
SDIV X10, X21, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X1, X10, X20, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 427454 <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X4, X10, X3, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X5, X10, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X4, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 42736c <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [X19, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FMOV D31, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDP X14, X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X13, X8, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ADD X3, X6, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X6, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X7, X11, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X15, X2, [X19, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X10, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 42731c <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCoarsenPMIS._omp_fn.6–	0.74	0.31
▼Loop 109 - par_coarsen.c:2359-2381 - exec–	0.05	0.01
○Loop 111 - par_coarsen.c:2361-2369 - exec	0.69	0.22
○Loop 110 - par_coarsen.c:2372-2381 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code