OV - exec - Function hypre_BoomerAMGCoarsenPMIS._omp

	Function: hypre_BoomerAMGCoarsenPMIS._omp_fn.2	Module: exec	Source: par_coarsen.c:2132-2136	Coverage (incl. loops): 0.45% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2132 - 2136

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2132: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

2133:    for (i=0; i < S_diag_i[num_variables]; i++)

2134:    {

2135: #pragma omp atomic

2136:       measure_array_temp[S_diag_j[i]]++;

0x428ca0 STP	X29, X30, [SP, #976]!

0x428ca4 ADD	X29, SP, #0

0x428ca8 STP	X19, X20, [SP, #16]

0x428cac ORR	X20, XZR, X0

0x428cb0 LDR	X0, [X0]

0x428cb4 LDR	X1, [X20, #16]

0x428cb8 STR	X21, [SP, #32]

0x428cbc LDR	X21, [X0, X1,LSL #3]

0x428cc0 BL	4100b0

0x428cc4 SBFM	X19, X0, #0, #31

0x428cc8 BL	410200

0x428ccc SBFM	X4, X0, #0, #31

0x428cd0 SDIV	X3, X21, X19

0x428cd4 MSUB	X2, X3, X19, X21

0x428cd8 CMP	X4, X2

0x428cdc B.LT	428e28

0x428ce0 MADD	X6, X3, X4, X2

0x428ce4 ADD	X7, X3, X6

0x428ce8 CMP	X6, X7

0x428cec B.GE	428e18

0x428cf0 LDR	X5, [X20, #8]

0x428cf4 MOVZ	X8, #1

0x428cf8 LDR	X9, [X20, #24]

0x428cfc ADD	X0, X5, X6,LSL #3

0x428d00 ADD	X10, X5, X7,LSL #3

0x428d04 SUB	X11, X10, X0

0x428d08 SUB	X12, X11, #8

0x428d0c UBFM	X13, X12, #3, #63

0x428d10 ADD	X14, X13, X8

0x428d14 ANDS	X15, X14, #0x7

0x428d18 B.EQ	428da8

0x428d1c CMP	X15, X8

0x428d20 B.EQ	428d94

0x428d24 CMP	X15, #2

0x428d28 B.EQ	428d88

0x428d2c CMP	X15, #3

0x428d30 B.EQ	428d7c

0x428d34 CMP	X15, #4

0x428d38 B.EQ	428d70

0x428d3c CMP	X15, #5

0x428d40 B.EQ	428d64

0x428d44 CMP	X15, #6

0x428d48 B.EQ	428d58

0x428d4c LDR	X16, [X0], #8

0x428d50 ADD	X17, X9, X16,LSL #3

0x428d54 LDADD	X8, X1, [X17]

0x428d58 LDR	X18, [X0], #8

0x428d5c ADD	X30, X9, X18,LSL #3

0x428d60 LDADD	X8, X1, [X30]

0x428d64 LDR	X20, [X0], #8

0x428d68 ADD	X1, X9, X20,LSL #3

0x428d6c LDADD	X8, X1, [X1]

0x428d70 LDR	X21, [X0], #8

0x428d74 ADD	X19, X9, X21,LSL #3

0x428d78 LDADD	X8, X1, [X19]

0x428d7c LDR	X4, [X0], #8

0x428d80 ADD	X3, X9, X4,LSL #3

0x428d84 LDADD	X8, X1, [X3]

0x428d88 LDR	X2, [X0], #8

0x428d8c ADD	X6, X9, X2,LSL #3

0x428d90 LDADD	X8, X1, [X6]

0x428d94 LDR	X7, [X0], #8

0x428d98 ADD	X5, X9, X7,LSL #3

0x428d9c LDADD	X8, X1, [X5]

0x428da0 CMP	X10, X0

0x428da4 B.EQ	428e18

(124) 0x428da8 ORR	X11, XZR, X0

(124) 0x428dac LDR	X12, [X11], #8

(124) 0x428db0 ADD	X13, X9, X12,LSL #3

(124) 0x428db4 LDADD	X8, X1, [X13]

(124) 0x428db8 LDR	X14, [X0, #8]

(124) 0x428dbc ADD	X15, X9, X14,LSL #3

(124) 0x428dc0 LDADD	X8, X1, [X15]

(124) 0x428dc4 LDR	X16, [X11, #8]

(124) 0x428dc8 ADD	X17, X9, X16,LSL #3

(124) 0x428dcc LDADD	X8, X1, [X17]

(124) 0x428dd0 LDR	X18, [X0, #24]

(124) 0x428dd4 ADD	X30, X9, X18,LSL #3

(124) 0x428dd8 LDADD	X8, X1, [X30]

(124) 0x428ddc LDR	X20, [X0, #32]

(124) 0x428de0 ADD	X1, X9, X20,LSL #3

(124) 0x428de4 LDADD	X8, X1, [X1]

(124) 0x428de8 LDR	X21, [X0, #40]

(124) 0x428dec ADD	X19, X9, X21,LSL #3

(124) 0x428df0 LDADD	X8, X1, [X19]

(124) 0x428df4 LDR	X4, [X0, #48]

(124) 0x428df8 ADD	X3, X9, X4,LSL #3

(124) 0x428dfc LDADD	X8, X1, [X3]

(124) 0x428e00 LDR	X2, [X0, #56]

(124) 0x428e04 ADD	X6, X9, X2,LSL #3

(124) 0x428e08 LDADD	X8, X1, [X6]

(124) 0x428e0c ADD	X0, X0, #64

(124) 0x428e10 CMP	X10, X0

(124) 0x428e14 B.NE	428da8

0x428e18 LDR	X21, [SP, #32]

0x428e1c LDP	X19, X20, [SP, #16]

0x428e20 LDP	X29, X30, [SP], #48

0x428e24 RET

0x428e28 ADD	X3, X3, #1

0x428e2c MOVZ	X2, #0

0x428e30 B	428ce0

0x428e34 HINT	#0

0x428e38 HINT	#0

0x428e3c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.50+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.44+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGCoarsenPMIS	par_coarsen.c:2139	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:612	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_coarsen.c:2132-2136
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2132-2136.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 28% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 10.75 cycles (1.86x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2133
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2133

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 56 bytes. The binary function is storing 56 bytes.

General properties

nb instructions	76
nb uops	66
loop length	304
used w registers	0
used x registers	25
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.25 cycles
front end	8.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	7.00	7.00	11.00	11.00	11.00	11.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	1.50	1.50
cycles	7.00	7.00	11.00	11.00	11.00	11.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	8.25
Dispatch	11.00
DIV/SQRT	5.00-20.00
Overall L1	11.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	28%
load	25%
store	41%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

2% of peak load performance is reached (2.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 428ca0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4100b0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410200 <@plt_start@+0x1e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X4, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
SDIV X3, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X2, X3, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 428e28 <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X6, X3, X4, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X7, X3, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X6, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 428e18 <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0x178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X9, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X5, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X5, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X11, X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X12, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X13, X12, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X15, X14, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 428da8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 428d94 <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 428d88 <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 428d7c <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 428d70 <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 428d64 <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 428d58 <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X17, X9, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDADD X8, X1, [X17]																			N/A
LDR X18, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X30, X9, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDADD X8, X1, [X30]																			N/A
LDR X20, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X9, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDADD X8, X1, [X1]																			N/A
LDR X21, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X19, X9, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDADD X8, X1, [X19]																			N/A
LDR X4, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X3, X9, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDADD X8, X1, [X3]																			N/A
LDR X2, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X6, X9, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDADD X8, X1, [X6]																			N/A
LDR X7, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X5, X9, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDADD X8, X1, [X5]																			N/A
CMP X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 428e18 <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0x178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 428ce0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_coarsen.c:2132-2136
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2132-2136.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 28% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 10.75 cycles (1.86x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2133
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2133

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 56 bytes. The binary function is storing 56 bytes.

General properties

nb instructions	76
nb uops	66
loop length	304
used w registers	0
used x registers	25
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.25 cycles
front end	8.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	7.00	7.00	11.00	11.00	11.00	11.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	1.50	1.50
cycles	7.00	7.00	11.00	11.00	11.00	11.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	8.25
Dispatch	11.00
DIV/SQRT	5.00-20.00
Overall L1	11.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	28%
load	25%
store	41%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

2% of peak load performance is reached (2.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 428ca0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4100b0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410200 <@plt_start@+0x1e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X4, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
SDIV X3, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X2, X3, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 428e28 <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X6, X3, X4, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X7, X3, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X6, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 428e18 <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0x178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X9, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X5, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X5, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X11, X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X12, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X13, X12, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X15, X14, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 428da8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 428d94 <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 428d88 <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 428d7c <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 428d70 <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 428d64 <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 428d58 <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X17, X9, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDADD X8, X1, [X17]																			N/A
LDR X18, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X30, X9, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDADD X8, X1, [X30]																			N/A
LDR X20, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X9, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDADD X8, X1, [X1]																			N/A
LDR X21, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X19, X9, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDADD X8, X1, [X19]																			N/A
LDR X4, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X3, X9, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDADD X8, X1, [X3]																			N/A
LDR X2, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X6, X9, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDADD X8, X1, [X6]																			N/A
LDR X7, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X5, X9, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDADD X8, X1, [X5]																			N/A
CMP X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 428e18 <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0x178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 428ce0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCoarsenPMIS._omp_fn.2–	0.45	0.19
○Loop 124 - par_coarsen.c:2135-2136 - exec	0.45	0.14

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code