OV - exec - Function hypre_BoomerAMGBuildMultipass._omp

	Function: hypre_BoomerAMGBuildMultipass._omp_fn.5	Module: exec	Source: par_multi_interp.c:891-1134 [...]	Coverage (incl. loops): 1.19% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 891 - 1134

--------------------------------------------------------------------------------

891:       #pragma omp parallel private(i,my_thread_num,num_threads,thread_start,thread_stop,cnt_nz,cnt_nz_offd,i1,j,j1,j_start,j_end,k1,k,P_marker,P_marker_offd)

[...]

900:           my_thread_num = hypre_GetThreadNum();

901:           num_threads = hypre_NumActiveThreads();

902:           thread_start = (pass_length/num_threads)*my_thread_num;

903:           if (my_thread_num == num_threads-1)

904:           {  thread_stop = pass_length; }

905:           else

906:           {  thread_stop = (pass_length/num_threads)*(my_thread_num+1); }

907:           thread_start += pass_pointer[pass];

908:           thread_stop += pass_pointer[pass];

909:

910:           /* Local initializations */

911:           cnt_nz = 0;

912:           cnt_nz_offd = 0;

913:

914:           /* This block of code is to go to the top of the parallel region starting before

915:            * the loop over num_passes. */

916:           P_marker = hypre_CTAlloc(HYPRE_Int, n_coarse); /* marks points to see if they're counted */

917:           for (i=0; i < n_coarse; i++)

918:           {   P_marker[i] = -1; }

919:           if (new_num_cols_offd == local_index+1)

920:           {

921:              P_marker_offd = hypre_CTAlloc(HYPRE_Int,new_num_cols_offd);

922:              for (i=0; i < new_num_cols_offd; i++)

923:              {   P_marker_offd[i] = -1; }

924:           }

925:           else if (n_coarse_offd)

926:           {

927:              P_marker_offd = hypre_CTAlloc(HYPRE_Int, n_coarse_offd);

[...]

939:           for (i=thread_start; i < thread_stop; i++)

940:           {

941:              i1 = pass_array[i];

942:              P_diag_start[i1] = cnt_nz;

943:              P_offd_start[i1] = cnt_nz_offd;

944:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

945:              {

946:                 j1 = S_diag_j[j];

947:                 if (assigned[j1] == pass-1)

948:                 {

949:                    j_start = P_diag_start[j1];

950:                    j_end = j_start+P_diag_i[j1+1];

951:                    for (k=j_start; k < j_end; k++)

952:                    {

953:                       k1 = P_diag_pass[pass-1][k];

954:                       if (P_marker[k1] != i1)

955:                       {

956:                          cnt_nz++;

957:                          P_diag_i[i1+1]++;

958:                          P_marker[k1] = i1;

959:                       }

960:                    }

961:                    j_start = P_offd_start[j1];

962:                    j_end = j_start+P_offd_i[j1+1];

963:                    for (k=j_start; k < j_end; k++)

964:                    {

965:                       k1 = P_offd_pass[pass-1][k];

966:                       if (P_marker_offd[k1] != i1)

967:                       {

968:                          cnt_nz_offd++;

969:                          P_offd_i[i1+1]++;

970:                          P_marker_offd[k1] = i1;

[...]

976:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

977:              {

978:                 j1 = S_offd_j[j];

979:                 if (assigned_offd[j1] == pass-1)

980:                 {

981:                    j_start = Pext_start[j1];

982:                    j_end = j_start+Pext_i[j1+1];

983:                    for (k=j_start; k < j_end; k++)

984:                    {

985:                       k1 = Pext_pass[pass][k];

986:                       if (k1 < 0)

987:                       {

988:                          if (P_marker[-k1-1] != i1)

989:                          {

990:                             cnt_nz++;

991:                             P_diag_i[i1+1]++;

992:                             P_marker[-k1-1] = i1;

993:                          }

994:                       }

995:                       else if (P_marker_offd[k1] != i1)

996:                       {

997:                          cnt_nz_offd++;

998:                          P_offd_i[i1+1]++;

999:                          P_marker_offd[k1] = i1;

[...]

1008:           if(my_thread_num == 0)

1009:           {   max_num_threads[0] = num_threads; }

1010:           cnt_nz_offd_per_thread[my_thread_num] = cnt_nz_offd;

1011:           cnt_nz_per_thread[my_thread_num] = cnt_nz;

1012: #ifdef HYPRE_USING_OPENMP

1013: #pragma omp barrier

1014: #endif

1015:           if(my_thread_num == 0)

1016:           {

1017:               for(i = 1; i < max_num_threads[0]; i++)

1018:               {

1019:                   cnt_nz_offd_per_thread[i] += cnt_nz_offd_per_thread[i-1];

1020:                   cnt_nz_per_thread[i] += cnt_nz_per_thread[i-1];

1021:               }

1022:           }

1023: #ifdef HYPRE_USING_OPENMP

1024: #pragma omp barrier

1025: #endif

1026:           if(my_thread_num > 0)

1027:           {

1028:               /* update this thread's section of P_diag_start and P_offd_start

1029:                * with the num of nz's counted by previous threads */

1030:               for (i=thread_start; i < thread_stop; i++)

1031:                {

1032:                    i1 = pass_array[i];

1033:                    P_diag_start[i1] += cnt_nz_per_thread[my_thread_num-1];

1034:                    P_offd_start[i1] += cnt_nz_offd_per_thread[my_thread_num-1];

[...]

1040:               cnt_nz = cnt_nz_per_thread[max_num_threads[0]-1];

1041:               cnt_nz_offd = cnt_nz_offd_per_thread[max_num_threads[0]-1];

1042:

1043:               /* Updated total nz count */

1044:               total_nz += cnt_nz;

1045:               total_nz_offd += cnt_nz_offd;

1046:

1047:               /* Allocate P_diag_pass and P_offd_pass for all threads */

1048:               P_diag_pass[pass] = hypre_CTAlloc(HYPRE_Int, cnt_nz);

1049:               if (cnt_nz_offd)

1050:                  P_offd_pass[pass] = hypre_CTAlloc(HYPRE_Int, cnt_nz_offd);

1051:               else if (num_procs > 1)

1052:                  P_offd_pass[pass] = NULL;

1053:           }

1054: #ifdef HYPRE_USING_OPENMP

1055: #pragma omp barrier

1056: #endif

1057:

1058:           /* offset cnt_nz and cnt_nz_offd to point to the starting

1059:            * point in P_diag_pass and P_offd_pass for each thread */

1060:           if(my_thread_num > 0)

1061:           {

1062:               cnt_nz = cnt_nz_per_thread[my_thread_num-1];

1063:               cnt_nz_offd = cnt_nz_offd_per_thread[my_thread_num-1];

1064:           }

1065:           else

1066:           {

1067:               cnt_nz = 0;

1068:               cnt_nz_offd = 0;

1069:           }

1070:

1071:           /* Set P_diag_pass and P_offd_pass */

1072:           for (i=thread_start; i < thread_stop; i++)

1073:           {

1074:              i1 = pass_array[i];

1075:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1076:              {

1077:                 j1 = S_diag_j[j];

1078:                 if (assigned[j1] == pass-1)

1079:                 {

1080:                    j_start = P_diag_start[j1];

1081:                    j_end = j_start+P_diag_i[j1+1];

1082:                    for (k=j_start; k < j_end; k++)

1083:                    {

1084:                       k1 = P_diag_pass[pass-1][k];

1085:                       if (P_marker[k1] != -i1-1)

1086:                       {

1087:                           P_diag_pass[pass][cnt_nz++] = k1;

1088:                           P_marker[k1] = -i1-1;

1089:                       }

1090:                    }

1091:                    j_start = P_offd_start[j1];

1092:                    j_end = j_start+P_offd_i[j1+1];

1093:                    for (k=j_start; k < j_end; k++)

1094:                    {

1095:                       k1 = P_offd_pass[pass-1][k];

1096:                       if (P_marker_offd[k1] != -i1-1)

1097:                       {

1098:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1099:                          P_marker_offd[k1] = -i1-1;

1100:                       }

1101:                    }

1102:                 }

1103:              }

1104:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1105:              {

1106:                 j1 = S_offd_j[j];

1107:                 if (assigned_offd[j1] == pass-1)

1108:                 {

1109:                    j_start = Pext_start[j1];

1110:                    j_end = j_start+Pext_i[j1+1];

1111:                    for (k=j_start; k < j_end; k++)

1112:                    {

1113:                       k1 = Pext_pass[pass][k];

1114:                       if (k1 < 0)

1115:                       {

1116:                          if (P_marker[-k1-1] != -i1-1)

1117:                          {

1118:                             P_diag_pass[pass][cnt_nz++] = -k1-1;

1119:                             P_marker[-k1-1] = -i1-1;

1120:                          }

1121:                       }

1122:                       else if (P_marker_offd[k1] != -i1-1)

1123:                       {

1124:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1125:                          P_marker_offd[k1] = -i1-1;

[...]

1132:           hypre_TFree(P_marker);

1133:           if ( (n_coarse_offd) || (new_num_cols_offd  == local_index+1) )

1134:           {    hypre_TFree(P_marker_offd); }

0x45520c STP	X29, X30, [SP, #736]!

0x455210 ORR	X3, XZR, X0

0x455214 ADD	X29, SP, #0

0x455218 STP	X19, X20, [SP, #16]

0x45521c STP	X21, X22, [SP, #32]

0x455220 STP	X23, X24, [SP, #48]

0x455224 STP	X25, X26, [SP, #64]

0x455228 STP	X27, X28, [SP, #80]

0x45522c LDP	X1, X18, [X3, #64]

0x455230 LDP	X10, X8, [X3, #88]

0x455234 LDP	X11, X26, [X0, #16]

0x455238 LDP	X12, X27, [X0]

0x45523c LDP	X23, X21, [X0, #32]

0x455240 STR	X1, [SP, #128]

0x455244 LDR	X0, [X0, #48]

0x455248 STP	X8, X10, [SP, #240]

0x45524c STP	X18, X11, [SP, #256]

0x455250 LDR	X2, [X3, #56]

0x455254 STR	X0, [SP, #208]

0x455258 LDR	X4, [X3, #80]

0x45525c STR	X3, [SP, #216]

0x455260 LDR	X5, [X3, #104]

0x455264 STR	X2, [SP, #104]

0x455268 STR	X12, [SP, #272]

0x45526c STR	X4, [SP, #136]

0x455270 STR	X5, [SP, #120]

0x455274 LDR	X6, [X3, #112]

0x455278 LDP	X20, X7, [X3, #200]

0x45527c LDP	X14, X13, [X3, #216]

0x455280 LDP	X22, X28, [X3, #128]

0x455284 LDP	X25, X24, [X3, #152]

0x455288 STP	X14, X7, [SP, #224]

0x45528c LDR	X9, [X3, #144]

0x455290 STR	X6, [SP, #112]

0x455294 LDR	X15, [X3, #184]

0x455298 STR	X13, [SP, #144]

0x45529c LDR	X16, [X3, #192]

0x4552a0 STR	X22, [SP, #160]

0x4552a4 UBFM	X22, X22, #61, #60

0x4552a8 STR	X9, [SP, #200]

0x4552ac STR	X15, [SP, #96]

0x4552b0 STR	X16, [SP, #192]

0x4552b4 BL	527b40

0x4552b8 STR	X0, [SP, #152]

0x4552bc BL	527b20

0x4552c0 SDIV	X11, X20, X0

0x4552c4 LDR	X1, [SP, #128]

0x4552c8 SUB	X12, X0, #1

0x4552cc STR	X0, [SP, #280]

0x4552d0 ORR	X0, XZR, X28

0x4552d4 LDR	X18, [SP, #152]

0x4552d8 LDR	X10, [X1, X22]

0x4552dc MOVZ	X1, #8

0x4552e0 CMP	X18, X12

0x4552e4 MUL	X8, X18, X11

0x4552e8 ADD	X2, X11, X8

0x4552ec ADD	X5, X8, X10

0x4552f0 CSEL	X4, X2, X20, #1

0x4552f4 ADD	X6, X4, X10

0x4552f8 STR	X8, [SP, #168]

0x4552fc STR	X5, [SP, #128]

0x455300 STR	X6, [SP, #176]

0x455304 STR	X4, [SP, #184]

0x455308 BL	524ea8

0x45530c CMP	X28, #0

0x455310 LDR	X9, [SP, #128]

0x455314 ORR	X20, XZR, X0

0x455318 LDP	X3, X14, [SP, #216]

0x45531c LDP	X4, X8, [SP, #232]

0x455320 LDP	X10, X18, [SP, #248]

0x455324 LDP	X11, X12, [SP, #264]

0x455328 LDR	X13, [SP, #144]

0x45532c B.LE	45536c

0x455330 UBFM	X2, X28, #61, #60

0x455334 MOVZ	W1, #255

0x455338 STR	X13, [SP, #128]

0x45533c STR	X14, [SP, #144]

0x455340 STP	X4, X8, [SP, #216]

0x455344 STP	X10, X18, [SP, #232]

0x455348 STP	X11, X12, [SP, #248]

0x45534c STP	X9, X3, [SP, #264]

0x455350 BL	410600

0x455354 LDR	X13, [SP, #128]

0x455358 LDP	X4, X8, [SP, #216]

0x45535c LDP	X10, X18, [SP, #232]

0x455360 LDP	X11, X12, [SP, #248]

0x455364 LDP	X9, X3, [SP, #264]

0x455368 LDR	X14, [SP, #144]

0x45536c LDR	X17, [SP, #96]

0x455370 LDR	X30, [SP, #192]

0x455374 ADD	X0, X17, #1

0x455378 STR	X0, [SP, #216]

0x45537c CMP	X30, X0

0x455380 B.EQ	456650

0x455384 LDR	X0, [SP, #200]

0x455388 CBNZ	X0, 4565d4

0x45538c LDR	X17, [SP, #184]

0x455390 ADD	X1, X10, X22

0x455394 ORR	X15, XZR, X9

0x455398 LDP	X7, X16, [SP, #160]

0x45539c MOVZ	X5, #0

0x4553a0 MOVZ	X6, #0

0x4553a4 ADD	X2, X8, X22

0x4553a8 STR	X1, [SP, #144]

0x4553ac SUB	X7, X7, #1

0x4553b0 CMP	X17, X16

0x4553b4 B.LE	4558dc

0x4553b8 LDR	X16, [SP, #136]

0x4553bc ORR	X30, XZR, X2

0x4553c0 STP	X13, X14, [SP, #224]

0x4553c4 LDR	X13, [SP, #208]

0x4553c8 STP	X10, X9, [SP, #256]

0x4553cc LDR	X9, [SP, #176]

0x4553d0 STP	X4, X8, [SP, #240]

0x4553d4 STR	X3, [SP, #272]

0x4553d8 HINT	#0

0x4553dc HINT	#0

(651) 0x4553e0 LDR	X14, [SP, #104]

(651) 0x4553e4 LDR	X0, [X14, X15,LSL #3]

(651) 0x4553e8 UBFM	X10, X0, #61, #60

(651) 0x4553ec ADD	X1, X10, #8

(651) 0x4553f0 STR	X6, [X18, X10]

(651) 0x4553f4 ADD	X4, X12, X1

(651) 0x4553f8 STR	X5, [X16, X10]

(651) 0x4553fc LDR	X3, [X12, X10]

(651) 0x455400 LDR	X8, [X12, X1]

(651) 0x455404 CMP	X3, X8

(651) 0x455408 B.GE	455774

(651) 0x45540c ORR	X28, XZR, X24

(651) 0x455410 STR	X9, [SP, #128]

(651) 0x455414 ORR	X9, XZR, X4

(651) 0x455418 B	455428

  (654) 0x45541c ADD	X3, X3, #1

  (654) 0x455420 CMP	X3, X8

  (654) 0x455424 B.GE	45576c

  (654) 0x455428 LDR	X24, [X27, X3,LSL #3]

  (654) 0x45542c UBFM	X2, X24, #61, #60

  (654) 0x455430 LDR	X17, [X25, X2]

  (654) 0x455434 STR	X2, [SP, #96]

  (654) 0x455438 CMP	X17, X7

  (654) 0x45543c B.NE	45541c

  (654) 0x455440 ADD	X17, X2, #8

  (654) 0x455444 LDR	X8, [X18, X2]

  (654) 0x455448 LDR	X14, [X23, X17]

  (654) 0x45544c ADD	X4, X8, X14

  (654) 0x455450 CMP	X8, X4

  (654) 0x455454 B.GE	4555d0

  (654) 0x455458 LDR	X24, [SP, #144]

  (654) 0x45545c UBFM	X2, X8, #61, #60

  (654) 0x455460 LDUR	X24, [X24, #504]

  (654) 0x455464 ADD	X14, X24, X4,LSL #3

  (654) 0x455468 ADD	X4, X24, X8,LSL #3

  (654) 0x45546c SUB	X8, X14, X4

  (654) 0x455470 SUB	X8, X8, #8

  (654) 0x455474 UBFM	X8, X8, #3, #63

  (654) 0x455478 ADD	X8, X8, #1

  (654) 0x45547c ANDS	X8, X8, #0x3

  (654) 0x455480 B.EQ	455520

  (654) 0x455484 CMP	X8, #1

  (654) 0x455488 B.EQ	4554ec

  (654) 0x45548c CMP	X8, #2

  (654) 0x455490 B.EQ	4554c0

  (654) 0x455494 LDR	X24, [X24, X2]

  (654) 0x455498 UBFM	X2, X24, #61, #60

  (654) 0x45549c LDR	X8, [X20, X2]

  (654) 0x4554a0 CMP	X0, X8

  (654) 0x4554a4 B.EQ	4554bc

  (654) 0x4554a8 LDR	X24, [X23, X1]

  (654) 0x4554ac ADD	X6, X6, #1

  (654) 0x4554b0 ADD	X8, X24, #1

  (654) 0x4554b4 STR	X8, [X23, X1]

  (654) 0x4554b8 STR	X0, [X20, X2]

  (654) 0x4554bc ADD	X4, X4, #8

  (654) 0x4554c0 LDR	X2, [X4]

  (654) 0x4554c4 UBFM	X8, X2, #61, #60

  (654) 0x4554c8 LDR	X24, [X20, X8]

  (654) 0x4554cc CMP	X0, X24

  (654) 0x4554d0 B.EQ	4554e8

  (654) 0x4554d4 LDR	X2, [X23, X1]

  (654) 0x4554d8 ADD	X6, X6, #1

  (654) 0x4554dc ADD	X24, X2, #1

  (654) 0x4554e0 STR	X24, [X23, X1]

  (654) 0x4554e4 STR	X0, [X20, X8]

  (654) 0x4554e8 ADD	X4, X4, #8

  (654) 0x4554ec LDR	X8, [X4]

  (654) 0x4554f0 UBFM	X2, X8, #61, #60

  (654) 0x4554f4 LDR	X24, [X20, X2]

  (654) 0x4554f8 CMP	X0, X24

  (654) 0x4554fc B.EQ	455514

  (654) 0x455500 LDR	X8, [X23, X1]

  (654) 0x455504 ADD	X6, X6, #1

  (654) 0x455508 ADD	X24, X8, #1

  (654) 0x45550c STR	X24, [X23, X1]

  (654) 0x455510 STR	X0, [X20, X2]

  (654) 0x455514 ADD	X4, X4, #8

  (654) 0x455518 CMP	X14, X4

  (654) 0x45551c B.EQ	4555d0

    (656) 0x455520 LDR	X2, [X4]

    (656) 0x455524 ADD	X8, X4, #8

    (656) 0x455528 UBFM	X2, X2, #61, #60

    (656) 0x45552c LDR	X24, [X20, X2]

    (656) 0x455530 CMP	X0, X24

    (656) 0x455534 B.EQ	45554c

    (656) 0x455538 LDR	X24, [X23, X1]

    (656) 0x45553c ADD	X6, X6, #1

    (656) 0x455540 ADD	X24, X24, #1

    (656) 0x455544 STR	X24, [X23, X1]

    (656) 0x455548 STR	X0, [X20, X2]

    (656) 0x45554c LDR	X4, [X4, #8]

    (656) 0x455550 UBFM	X2, X4, #61, #60

    (656) 0x455554 LDR	X24, [X20, X2]

    (656) 0x455558 CMP	X0, X24

    (656) 0x45555c B.EQ	455574

    (656) 0x455560 LDR	X4, [X23, X1]

    (656) 0x455564 ADD	X6, X6, #1

    (656) 0x455568 ADD	X24, X4, #1

    (656) 0x45556c STR	X24, [X23, X1]

    (656) 0x455570 STR	X0, [X20, X2]

    (656) 0x455574 LDR	X2, [X8, #8]

    (656) 0x455578 ADD	X4, X8, #24

    (656) 0x45557c UBFM	X2, X2, #61, #60

    (656) 0x455580 LDR	X24, [X20, X2]

    (656) 0x455584 CMP	X0, X24

    (656) 0x455588 B.EQ	4555a0

    (656) 0x45558c LDR	X24, [X23, X1]

    (656) 0x455590 ADD	X6, X6, #1

    (656) 0x455594 ADD	X24, X24, #1

    (656) 0x455598 STR	X24, [X23, X1]

    (656) 0x45559c STR	X0, [X20, X2]

    (656) 0x4555a0 LDR	X8, [X8, #16]

    (656) 0x4555a4 UBFM	X2, X8, #61, #60

    (656) 0x4555a8 LDR	X24, [X20, X2]

    (656) 0x4555ac CMP	X0, X24

    (656) 0x4555b0 B.EQ	4555c8

    (656) 0x4555b4 LDR	X8, [X23, X1]

    (656) 0x4555b8 ADD	X6, X6, #1

    (656) 0x4555bc ADD	X24, X8, #1

    (656) 0x4555c0 STR	X24, [X23, X1]

    (656) 0x4555c4 STR	X0, [X20, X2]

    (656) 0x4555c8 CMP	X14, X4

    (656) 0x4555cc B.NE	455520

  (654) 0x4555d0 LDR	X14, [SP, #96]

  (654) 0x4555d4 LDR	X17, [X21, X17]

  (654) 0x4555d8 LDR	X4, [X16, X14]

  (654) 0x4555dc ADD	X2, X4, X17

  (654) 0x4555e0 CMP	X4, X2

  (654) 0x4555e4 B.GE	45575c

  (654) 0x4555e8 LDUR	X17, [X30, #504]

  (654) 0x4555ec UBFM	X24, X4, #61, #60

  (654) 0x4555f0 ADD	X8, X17, X2,LSL #3

  (654) 0x4555f4 ADD	X2, X17, X4,LSL #3

  (654) 0x4555f8 SUB	X14, X8, X2

  (654) 0x4555fc SUB	X4, X14, #8

  (654) 0x455600 UBFM	X14, X4, #3, #63

  (654) 0x455604 ADD	X4, X14, #1

  (654) 0x455608 ANDS	X14, X4, #0x3

  (654) 0x45560c B.EQ	4556ac

  (654) 0x455610 CMP	X14, #1

  (654) 0x455614 B.EQ	455678

  (654) 0x455618 CMP	X14, #2

  (654) 0x45561c B.EQ	45564c

  (654) 0x455620 LDR	X24, [X17, X24]

  (654) 0x455624 UBFM	X17, X24, #61, #60

  (654) 0x455628 LDR	X4, [X19, X17]

  (654) 0x45562c CMP	X0, X4

  (654) 0x455630 B.EQ	455648

  (654) 0x455634 LDR	X14, [X21, X1]

  (654) 0x455638 ADD	X5, X5, #1

  (654) 0x45563c ADD	X24, X14, #1

  (654) 0x455640 STR	X24, [X21, X1]

  (654) 0x455644 STR	X0, [X19, X17]

  (654) 0x455648 ADD	X2, X2, #8

  (654) 0x45564c LDR	X17, [X2]

  (654) 0x455650 UBFM	X4, X17, #61, #60

  (654) 0x455654 LDR	X14, [X19, X4]

  (654) 0x455658 CMP	X0, X14

  (654) 0x45565c B.EQ	455674

  (654) 0x455660 LDR	X24, [X21, X1]

  (654) 0x455664 ADD	X5, X5, #1

  (654) 0x455668 ADD	X17, X24, #1

  (654) 0x45566c STR	X17, [X21, X1]

  (654) 0x455670 STR	X0, [X19, X4]

  (654) 0x455674 ADD	X2, X2, #8

  (654) 0x455678 LDR	X4, [X2]

  (654) 0x45567c UBFM	X24, X4, #61, #60

  (654) 0x455680 LDR	X14, [X19, X24]

  (654) 0x455684 CMP	X0, X14

  (654) 0x455688 B.EQ	4556a0

  (654) 0x45568c LDR	X17, [X21, X1]

  (654) 0x455690 ADD	X5, X5, #1

  (654) 0x455694 ADD	X4, X17, #1

  (654) 0x455698 STR	X4, [X21, X1]

  (654) 0x45569c STR	X0, [X19, X24]

  (654) 0x4556a0 ADD	X2, X2, #8

  (654) 0x4556a4 CMP	X2, X8

  (654) 0x4556a8 B.EQ	45575c

    (655) 0x4556ac LDR	X14, [X2]

    (655) 0x4556b0 ADD	X24, X2, #8

    (655) 0x4556b4 UBFM	X4, X14, #61, #60

    (655) 0x4556b8 LDR	X17, [X19, X4]

    (655) 0x4556bc CMP	X0, X17

    (655) 0x4556c0 B.EQ	4556d8

    (655) 0x4556c4 LDR	X14, [X21, X1]

    (655) 0x4556c8 ADD	X5, X5, #1

    (655) 0x4556cc ADD	X17, X14, #1

    (655) 0x4556d0 STR	X17, [X21, X1]

    (655) 0x4556d4 STR	X0, [X19, X4]

    (655) 0x4556d8 LDR	X2, [X2, #8]

    (655) 0x4556dc UBFM	X14, X2, #61, #60

    (655) 0x4556e0 LDR	X4, [X19, X14]

    (655) 0x4556e4 CMP	X0, X4

    (655) 0x4556e8 B.EQ	455700

    (655) 0x4556ec LDR	X17, [X21, X1]

    (655) 0x4556f0 ADD	X5, X5, #1

    (655) 0x4556f4 ADD	X2, X17, #1

    (655) 0x4556f8 STR	X2, [X21, X1]

    (655) 0x4556fc STR	X0, [X19, X14]

    (655) 0x455700 LDR	X14, [X24, #8]

    (655) 0x455704 ADD	X2, X24, #24

    (655) 0x455708 UBFM	X4, X14, #61, #60

    (655) 0x45570c LDR	X17, [X19, X4]

    (655) 0x455710 CMP	X0, X17

    (655) 0x455714 B.EQ	45572c

    (655) 0x455718 LDR	X14, [X21, X1]

    (655) 0x45571c ADD	X5, X5, #1

    (655) 0x455720 ADD	X17, X14, #1

    (655) 0x455724 STR	X17, [X21, X1]

    (655) 0x455728 STR	X0, [X19, X4]

    (655) 0x45572c LDR	X24, [X24, #16]

    (655) 0x455730 UBFM	X4, X24, #61, #60

    (655) 0x455734 LDR	X14, [X19, X4]

    (655) 0x455738 CMP	X0, X14

    (655) 0x45573c B.EQ	455754

    (655) 0x455740 LDR	X17, [X21, X1]

    (655) 0x455744 ADD	X5, X5, #1

    (655) 0x455748 ADD	X24, X17, #1

    (655) 0x45574c STR	X24, [X21, X1]

    (655) 0x455750 STR	X0, [X19, X4]

    (655) 0x455754 CMP	X2, X8

    (655) 0x455758 B.NE	4556ac

  (654) 0x45575c LDR	X8, [X9]

  (654) 0x455760 ADD	X3, X3, #1

  (654) 0x455764 CMP	X3, X8

  (654) 0x455768 B.LT	455428

(651) 0x45576c LDR	X9, [SP, #128]

(651) 0x455770 ORR	X24, XZR, X28

(651) 0x455774 LDR	X3, [X11, X10]

(651) 0x455778 ADD	X10, X11, X1

(651) 0x45577c LDR	X4, [X11, X1]

(651) 0x455780 CMP	X3, X4

(651) 0x455784 B.GE	4558c0

(651) 0x455788 LDP	X14, X28, [SP, #112]

(651) 0x45578c ORR	X2, XZR, X10

(651) 0x455790 B	4557a0

  (652) 0x455794 ADD	X3, X3, #1

  (652) 0x455798 CMP	X3, X4

  (652) 0x45579c B.GE	4558c0

  (652) 0x4557a0 LDR	X17, [X26, X3,LSL #3]

  (652) 0x4557a4 UBFM	X8, X17, #61, #60

  (652) 0x4557a8 LDR	X10, [X24, X8]

  (652) 0x4557ac CMP	X10, X7

  (652) 0x4557b0 B.NE	455794

  (652) 0x4557b4 ADD	X17, X14, X8

  (652) 0x4557b8 LDR	X8, [X13, X8]

  (652) 0x4557bc LDR	X10, [X17, #8]

  (652) 0x4557c0 ADD	X10, X8, X10

  (652) 0x4557c4 CMP	X8, X10

  (652) 0x4557c8 B.GE	455794

  (652) 0x4557cc LDR	X17, [X28, X22]

  (652) 0x4557d0 UBFM	X4, X8, #61, #60

  (652) 0x4557d4 STR	X4, [SP, #96]

  (652) 0x4557d8 ADD	X10, X17, X10,LSL #3

  (652) 0x4557dc ADD	X4, X17, X8,LSL #3

  (652) 0x4557e0 SUB	X8, X10, X4

  (652) 0x4557e4 SUB	X8, X8, #8

  (652) 0x4557e8 UBFM	X8, X8, #3, #63

  (652) 0x4557ec ADD	X8, X8, #1

  (652) 0x4557f0 ANDS	X8, X8, #0x3

  (652) 0x4557f4 B.EQ	455afc

  (652) 0x4557f8 CMP	X8, #1

  (652) 0x4557fc B.EQ	45586c

  (652) 0x455800 CMP	X8, #2

  (652) 0x455804 B.EQ	45583c

  (652) 0x455808 LDR	X8, [SP, #96]

  (652) 0x45580c LDR	X17, [X17, X8]

  (652) 0x455810 TBNZ	X17, #63, 455c1c

  (652) 0x455814 UBFM	X8, X17, #61, #60

  (652) 0x455818 LDR	X17, [X19, X8]

  (652) 0x45581c CMP	X0, X17

  (652) 0x455820 B.EQ	455838

  (652) 0x455824 LDR	X17, [X21, X1]

  (652) 0x455828 ADD	X5, X5, #1

  (652) 0x45582c ADD	X17, X17, #1

  (652) 0x455830 STR	X17, [X21, X1]

  (652) 0x455834 STR	X0, [X19, X8]

  (652) 0x455838 ADD	X4, X4, #8

  (652) 0x45583c LDR	X8, [X4]

  (652) 0x455840 TBNZ	X8, #63, 455bf0

  (652) 0x455844 UBFM	X8, X8, #61, #60

  (652) 0x455848 LDR	X17, [X19, X8]

  (652) 0x45584c CMP	X0, X17

  (652) 0x455850 B.EQ	455868

  (652) 0x455854 LDR	X17, [X21, X1]

  (652) 0x455858 ADD	X5, X5, #1

  (652) 0x45585c ADD	X17, X17, #1

  (652) 0x455860 STR	X17, [X21, X1]

  (652) 0x455864 STR	X0, [X19, X8]

  (652) 0x455868 ADD	X4, X4, #8

  (652) 0x45586c LDR	X8, [X4]

  (652) 0x455870 TBNZ	X8, #63, 455bc4

  (652) 0x455874 UBFM	X8, X8, #61, #60

  (652) 0x455878 LDR	X17, [X19, X8]

  (652) 0x45587c CMP	X0, X17

  (652) 0x455880 B.EQ	455898

  (652) 0x455884 LDR	X17, [X21, X1]

  (652) 0x455888 ADD	X5, X5, #1

  (652) 0x45588c ADD	X17, X17, #1

  (652) 0x455890 STR	X17, [X21, X1]

  (652) 0x455894 STR	X0, [X19, X8]

  (652) 0x455898 ADD	X4, X4, #8

  (652) 0x45589c CMP	X4, X10

  (652) 0x4558a0 B.NE	455afc

  (652) 0x4558a4 LDR	X4, [X2]

  (652) 0x4558a8 ADD	X3, X3, #1

  (652) 0x4558ac CMP	X3, X4

  (652) 0x4558b0 B.LT	4557a0

(651) 0x4558b4 HINT	#0

(651) 0x4558b8 HINT	#0

(651) 0x4558bc HINT	#0

(651) 0x4558c0 ADD	X15, X15, #1

(651) 0x4558c4 CMP	X9, X15

(651) 0x4558c8 B.GT	4553e0

0x4558cc LDR	X3, [SP, #272]

0x4558d0 LDP	X13, X14, [SP, #224]

0x4558d4 LDP	X4, X8, [SP, #240]

0x4558d8 LDP	X10, X9, [SP, #256]

0x4558dc STP	X8, X10, [SP, #224]

0x4558e0 LDR	X17, [SP, #152]

0x4558e4 STP	X18, X11, [SP, #240]

0x4558e8 STP	X12, X9, [SP, #256]

0x4558ec STR	X3, [SP, #272]

0x4558f0 CBNZ	X17, 455c48

0x4558f4 LDR	X11, [SP, #280]

0x4558f8 ORR	X18, XZR, X13

0x4558fc ORR	X28, XZR, X14

0x455900 STR	X14, [SP, #128]

0x455904 STR	X11, [X4]

0x455908 STR	X5, [X18], #504

0x45590c STR	X6, [X28], #504

0x455910 STR	X18, [SP, #96]

0x455914 STP	X4, X13, [SP, #144]

0x455918 BL	4102a0

0x45591c LDP	X4, X6, [SP, #144]

0x455920 MOVZ	X7, #1

0x455924 LDP	X8, X10, [SP, #224]

0x455928 LDP	X15, X13, [SP, #240]

0x45592c LDP	X12, X9, [SP, #256]

0x455930 LDR	X2, [X4]

0x455934 LDR	X0, [SP, #96]

0x455938 LDR	X1, [SP, #128]

0x45593c LDR	X3, [SP, #272]

0x455940 CMP	X2, X7

0x455944 B.LE	455978

(650) 0x455948 LDR	X30, [X6, X7,LSL #3]

(650) 0x45594c LDR	X5, [X0, X7,LSL #3]

(650) 0x455950 ADD	X16, X30, X5

(650) 0x455954 STR	X16, [X6, X7,LSL #3]

(650) 0x455958 LDR	X17, [X1, X7,LSL #3]

(650) 0x45595c LDR	X14, [X28, X7,LSL #3]

(650) 0x455960 ADD	X18, X17, X14

(650) 0x455964 STR	X18, [X1, X7,LSL #3]

(650) 0x455968 ADD	X7, X7, #1

(650) 0x45596c LDR	X11, [X4]

(650) 0x455970 CMP	X11, X7

(650) 0x455974 B.GT	455948

0x455978 STR	X6, [SP, #96]

0x45597c STR	X1, [SP, #128]

0x455980 STP	X4, X8, [SP, #144]

0x455984 STP	X10, X15, [SP, #224]

0x455988 STP	X13, X12, [SP, #240]

0x45598c STP	X9, X3, [SP, #256]

0x455990 BL	4102a0

0x455994 LDR	X13, [SP, #96]

0x455998 LDP	X7, X8, [SP, #144]

0x45599c LDP	X10, X18, [SP, #224]

0x4559a0 LDP	X11, X12, [SP, #240]

0x4559a4 LDP	X9, X15, [SP, #256]

0x4559a8 LDR	X14, [SP, #128]

0x4559ac MOVZ	X1, #8

0x4559b0 STR	X8, [SP, #96]

0x4559b4 LDR	X28, [X7]

0x4559b8 STR	X10, [SP, #128]

0x4559bc LDR	X6, [X15, #120]

0x4559c0 STR	X15, [SP, #240]

0x4559c4 LDR	X3, [X15, #176]

0x4559c8 UBFM	X0, X28, #61, #60

0x4559cc SUB	X4, X0, #8

0x4559d0 LDR	X0, [X14, X4]

0x4559d4 LDR	X28, [X13, X4]

0x4559d8 ADD	X30, X6, X0

0x4559dc ADD	X2, X3, X28

0x4559e0 STR	X30, [X15, #120]

0x4559e4 STR	X2, [X15, #176]

0x4559e8 STP	X18, X11, [SP, #144]

0x4559ec STP	X12, X9, [SP, #224]

0x4559f0 BL	524ea8

0x4559f4 LDR	X13, [SP, #128]

0x4559f8 LDP	X14, X7, [SP, #144]

0x4559fc LDP	X8, X10, [SP, #224]

0x455a00 STR	X0, [X13, X22]

0x455a04 LDR	X5, [SP, #96]

0x455a08 CBNZ	X28, 4566c8

0x455a0c LDR	X1, [SP, #240]

0x455a10 LDR	X16, [X1, #168]

0x455a14 LDR	X17, [X16]

0x455a18 CMP	X17, #1

0x455a1c B.LE	45670c

0x455a20 STR	XZR, [X5, X22]

0x455a24 BL	4102a0

0x455a28 LDR	X8, [SP, #96]

0x455a2c LDP	X15, X11, [SP, #144]

0x455a30 LDP	X12, X9, [SP, #224]

0x455a34 LDR	X10, [SP, #128]

0x455a38 MOVZ	X2, #0

0x455a3c MOVZ	X4, #0

0x455a40 B	455e80

    (653) 0x455a44 UBFM	X8, X8, #61, #60

    (653) 0x455a48 LDR	X17, [X19, X8]

    (653) 0x455a4c CMP	X0, X17

    (653) 0x455a50 B.EQ	455a68

    (653) 0x455a54 LDR	X17, [X21, X1]

    (653) 0x455a58 ADD	X5, X5, #1

    (653) 0x455a5c ADD	X17, X17, #1

    (653) 0x455a60 STR	X17, [X21, X1]

    (653) 0x455a64 STR	X0, [X19, X8]

    (653) 0x455a68 LDR	X8, [X4, #8]

    (653) 0x455a6c ADD	X4, X4, #8

    (653) 0x455a70 TBNZ	X8, #63, 455b38

    (653) 0x455a74 UBFM	X8, X8, #61, #60

    (653) 0x455a78 LDR	X17, [X19, X8]

    (653) 0x455a7c CMP	X0, X17

    (653) 0x455a80 B.EQ	455a98

    (653) 0x455a84 LDR	X17, [X21, X1]

    (653) 0x455a88 ADD	X5, X5, #1

    (653) 0x455a8c ADD	X17, X17, #1

    (653) 0x455a90 STR	X17, [X21, X1]

    (653) 0x455a94 STR	X0, [X19, X8]

    (653) 0x455a98 LDR	X8, [X4, #8]

    (653) 0x455a9c TBNZ	X8, #63, 455b68

    (653) 0x455aa0 UBFM	X8, X8, #61, #60

    (653) 0x455aa4 LDR	X17, [X19, X8]

    (653) 0x455aa8 CMP	X0, X17

    (653) 0x455aac B.EQ	455ac4

    (653) 0x455ab0 LDR	X17, [X21, X1]

    (653) 0x455ab4 ADD	X5, X5, #1

    (653) 0x455ab8 ADD	X17, X17, #1

    (653) 0x455abc STR	X17, [X21, X1]

    (653) 0x455ac0 STR	X0, [X19, X8]

    (653) 0x455ac4 LDR	X8, [X4, #16]

    (653) 0x455ac8 TBNZ	X8, #63, 455b98

    (653) 0x455acc UBFM	X8, X8, #61, #60

    (653) 0x455ad0 LDR	X17, [X19, X8]

    (653) 0x455ad4 CMP	X0, X17

    (653) 0x455ad8 B.EQ	455af0

    (653) 0x455adc LDR	X17, [X21, X1]

    (653) 0x455ae0 ADD	X5, X5, #1

    (653) 0x455ae4 ADD	X17, X17, #1

    (653) 0x455ae8 STR	X17, [X21, X1]

    (653) 0x455aec STR	X0, [X19, X8]

    (653) 0x455af0 ADD	X4, X4, #24

    (653) 0x455af4 CMP	X4, X10

    (653) 0x455af8 B.EQ	4558a4

    (653) 0x455afc LDR	X8, [X4]

    (653) 0x455b00 TBZ	X8, #63, 455a44

    (653) 0x455b04 ORN	X8, XZR, X8

    (653) 0x455b08 UBFM	X8, X8, #61, #60

    (653) 0x455b0c LDR	X17, [X20, X8]

    (653) 0x455b10 CMP	X0, X17

    (653) 0x455b14 B.EQ	455a68

    (653) 0x455b18 LDR	X17, [X23, X1]

    (653) 0x455b1c ADD	X6, X6, #1

    (653) 0x455b20 ADD	X4, X4, #8

    (653) 0x455b24 ADD	X17, X17, #1

    (653) 0x455b28 STR	X17, [X23, X1]

    (653) 0x455b2c STR	X0, [X20, X8]

    (653) 0x455b30 LDR	X8, [X4]

    (653) 0x455b34 TBZ	X8, #63, 455a74

    (653) 0x455b38 ORN	X8, XZR, X8

    (653) 0x455b3c UBFM	X8, X8, #61, #60

    (653) 0x455b40 LDR	X17, [X20, X8]

    (653) 0x455b44 CMP	X0, X17

    (653) 0x455b48 B.EQ	455a98

    (653) 0x455b4c LDR	X17, [X23, X1]

    (653) 0x455b50 ADD	X6, X6, #1

    (653) 0x455b54 ADD	X17, X17, #1

    (653) 0x455b58 STR	X17, [X23, X1]

    (653) 0x455b5c STR	X0, [X20, X8]

    (653) 0x455b60 LDR	X8, [X4, #8]

    (653) 0x455b64 TBZ	X8, #63, 455aa0

    (653) 0x455b68 ORN	X8, XZR, X8

    (653) 0x455b6c UBFM	X8, X8, #61, #60

    (653) 0x455b70 LDR	X17, [X20, X8]

    (653) 0x455b74 CMP	X0, X17

    (653) 0x455b78 B.EQ	455ac4

    (653) 0x455b7c LDR	X17, [X23, X1]

    (653) 0x455b80 ADD	X6, X6, #1

    (653) 0x455b84 ADD	X17, X17, #1

    (653) 0x455b88 STR	X17, [X23, X1]

    (653) 0x455b8c STR	X0, [X20, X8]

    (653) 0x455b90 LDR	X8, [X4, #16]

    (653) 0x455b94 TBZ	X8, #63, 455acc

    (653) 0x455b98 ORN	X8, XZR, X8

    (653) 0x455b9c UBFM	X8, X8, #61, #60

    (653) 0x455ba0 LDR	X17, [X20, X8]

    (653) 0x455ba4 CMP	X0, X17

    (653) 0x455ba8 B.EQ	455af0

    (653) 0x455bac LDR	X17, [X23, X1]

    (653) 0x455bb0 ADD	X6, X6, #1

    (653) 0x455bb4 ADD	X17, X17, #1

    (653) 0x455bb8 STR	X17, [X23, X1]

    (653) 0x455bbc STR	X0, [X20, X8]

    (653) 0x455bc0 B	455af0

  (652) 0x455bc4 ORN	X8, XZR, X8

  (652) 0x455bc8 UBFM	X8, X8, #61, #60

  (652) 0x455bcc LDR	X17, [X20, X8]

  (652) 0x455bd0 CMP	X0, X17

  (652) 0x455bd4 B.EQ	455898

  (652) 0x455bd8 LDR	X17, [X23, X1]

  (652) 0x455bdc ADD	X6, X6, #1

  (652) 0x455be0 ADD	X17, X17, #1

  (652) 0x455be4 STR	X17, [X23, X1]

  (652) 0x455be8 STR	X0, [X20, X8]

  (652) 0x455bec B	455898

  (652) 0x455bf0 ORN	X8, XZR, X8

  (652) 0x455bf4 UBFM	X8, X8, #61, #60

  (652) 0x455bf8 LDR	X17, [X20, X8]

  (652) 0x455bfc CMP	X0, X17

  (652) 0x455c00 B.EQ	455868

  (652) 0x455c04 LDR	X17, [X23, X1]

  (652) 0x455c08 ADD	X6, X6, #1

  (652) 0x455c0c ADD	X17, X17, #1

  (652) 0x455c10 STR	X17, [X23, X1]

  (652) 0x455c14 STR	X0, [X20, X8]

  (652) 0x455c18 B	455868

  (652) 0x455c1c ORN	X8, XZR, X17

  (652) 0x455c20 UBFM	X8, X8, #61, #60

  (652) 0x455c24 LDR	X17, [X20, X8]

  (652) 0x455c28 CMP	X0, X17

  (652) 0x455c2c B.EQ	455838

  (652) 0x455c30 LDR	X17, [X23, X1]

  (652) 0x455c34 ADD	X6, X6, #1

  (652) 0x455c38 ADD	X17, X17, #1

  (652) 0x455c3c STR	X17, [X23, X1]

  (652) 0x455c40 STR	X0, [X20, X8]

  (652) 0x455c44 B	455838

0x455c48 UBFM	X28, X17, #61, #60

0x455c4c STR	X14, [SP, #96]

0x455c50 STR	X13, [SP, #128]

0x455c54 STR	X5, [X13, X28]

0x455c58 STR	X6, [X14, X28]

0x455c5c STR	X4, [SP, #144]

0x455c60 BL	4102a0

0x455c64 BL	4102a0

0x455c68 LDP	X7, X6, [SP, #144]

0x455c6c LDP	X8, X10, [SP, #224]

0x455c70 LDP	X18, X11, [SP, #240]

0x455c74 LDP	X12, X9, [SP, #256]

0x455c78 LDR	X14, [SP, #96]

0x455c7c LDR	X13, [SP, #128]

0x455c80 LDR	X15, [SP, #272]

0x455c84 CMP	X6, #0

0x455c88 B.LE	4559ac

0x455c8c SUB	X28, X28, #8

0x455c90 LDR	X5, [SP, #168]

0x455c94 ADD	X3, X14, X28

0x455c98 ADD	X2, X13, X28

0x455c9c LDR	X0, [SP, #184]

0x455ca0 CMP	X0, X5

0x455ca4 B.LE	456704

0x455ca8 LDR	X16, [SP, #104]

0x455cac ORN	X1, XZR, X9

0x455cb0 ADD	X0, X9, #1

0x455cb4 LDR	X7, [X3]

0x455cb8 LDR	X30, [SP, #136]

0x455cbc LDR	X4, [X16, X9,LSL #3]

0x455cc0 LDR	X15, [SP, #176]

0x455cc4 ADD	X6, X18, X4,LSL #3

0x455cc8 ADD	X16, X30, X4,LSL #3

0x455ccc LDR	X5, [X6]

0x455cd0 ADD	X17, X1, X15

0x455cd4 AND	X1, X17, #0x3

0x455cd8 ADD	X7, X5, X7

0x455cdc STR	X7, [X6]

0x455ce0 LDR	X30, [X2]

0x455ce4 LDR	X4, [X16]

0x455ce8 ADD	X17, X4, X30

0x455cec STR	X17, [X16]

0x455cf0 CMP	X15, X0

0x455cf4 B.LE	455e4c

0x455cf8 CBZ	X1, 45667c

0x455cfc CMP	X1, #1

0x455d00 B.EQ	455d44

0x455d04 CMP	X1, #2

0x455d08 B.NE	45668c

0x455d0c LDR	X16, [SP, #104]

0x455d10 LDR	X6, [X3]

0x455d14 LDR	X7, [SP, #136]

0x455d18 LDR	X30, [X16, X0,LSL #3]

0x455d1c ADD	X0, X0, #1

0x455d20 ADD	X5, X18, X30,LSL #3

0x455d24 ADD	X17, X7, X30,LSL #3

0x455d28 LDR	X4, [X5]

0x455d2c ADD	X15, X4, X6

0x455d30 STR	X15, [X5]

0x455d34 LDR	X1, [X17]

0x455d38 LDR	X6, [X2]

0x455d3c ADD	X16, X1, X6

0x455d40 STR	X16, [X17]

0x455d44 LDR	X30, [SP, #104]

0x455d48 LDR	X7, [X3]

0x455d4c LDR	X17, [SP, #136]

0x455d50 LDR	X4, [X30, X0,LSL #3]

0x455d54 ADD	X0, X0, #1

0x455d58 ADD	X5, X18, X4,LSL #3

0x455d5c ADD	X15, X17, X4,LSL #3

0x455d60 LDR	X17, [SP, #176]

0x455d64 LDR	X1, [X5]

0x455d68 ADD	X6, X1, X7

0x455d6c STR	X6, [X5]

0x455d70 LDR	X16, [X15]

0x455d74 LDR	X7, [X2]

0x455d78 ADD	X30, X16, X7

0x455d7c STR	X30, [X15]

0x455d80 CMP	X17, X0

0x455d84 B.LE	455e4c

0x455d88 LDR	X5, [SP, #104]

0x455d8c ORR	X7, XZR, X17

0x455d90 LDR	X1, [SP, #136]

(649) 0x455d94 ADD	X17, X0, #1

(649) 0x455d98 ADD	X15, X0, #3

(649) 0x455d9c LDR	X4, [X5, X0,LSL #3]

(649) 0x455da0 ADD	X16, X17, #1

(649) 0x455da4 ADD	X0, X0, #4

(649) 0x455da8 LDR	X30, [X3]

(649) 0x455dac UBFM	X4, X4, #61, #60

(649) 0x455db0 LDR	X6, [X18, X4]

(649) 0x455db4 ADD	X6, X6, X30

(649) 0x455db8 STR	X6, [X18, X4]

(649) 0x455dbc LDR	X6, [X1, X4]

(649) 0x455dc0 LDR	X30, [X2]

(649) 0x455dc4 ADD	X6, X6, X30

(649) 0x455dc8 STR	X6, [X1, X4]

(649) 0x455dcc LDR	X17, [X5, X17,LSL #3]

(649) 0x455dd0 LDR	X6, [X3]

(649) 0x455dd4 UBFM	X4, X17, #61, #60

(649) 0x455dd8 LDR	X30, [X18, X4]

(649) 0x455ddc ADD	X17, X30, X6

(649) 0x455de0 STR	X17, [X18, X4]

(649) 0x455de4 LDR	X30, [X1, X4]

(649) 0x455de8 LDR	X6, [X2]

(649) 0x455dec ADD	X17, X30, X6

(649) 0x455df0 STR	X17, [X1, X4]

(649) 0x455df4 LDR	X16, [X5, X16,LSL #3]

(649) 0x455df8 LDR	X6, [X3]

(649) 0x455dfc UBFM	X4, X16, #61, #60

(649) 0x455e00 LDR	X30, [X18, X4]

(649) 0x455e04 ADD	X17, X30, X6

(649) 0x455e08 STR	X17, [X18, X4]

(649) 0x455e0c LDR	X30, [X1, X4]

(649) 0x455e10 LDR	X16, [X2]

(649) 0x455e14 ADD	X6, X30, X16

(649) 0x455e18 STR	X6, [X1, X4]

(649) 0x455e1c LDR	X15, [X5, X15,LSL #3]

(649) 0x455e20 LDR	X30, [X3]

(649) 0x455e24 UBFM	X4, X15, #61, #60

(649) 0x455e28 LDR	X17, [X18, X4]

(649) 0x455e2c ADD	X16, X17, X30

(649) 0x455e30 STR	X16, [X18, X4]

(649) 0x455e34 LDR	X6, [X1, X4]

(649) 0x455e38 LDR	X15, [X2]

(649) 0x455e3c ADD	X17, X6, X15

(649) 0x455e40 STR	X17, [X1, X4]

(649) 0x455e44 CMP	X7, X0

(649) 0x455e48 B.GT	455d94

0x455e4c STR	X13, [SP, #96]

0x455e50 STR	X14, [SP, #128]

0x455e54 STP	X8, X10, [SP, #144]

0x455e58 STP	X18, X11, [SP, #224]

0x455e5c STP	X12, X9, [SP, #240]

0x455e60 BL	4102a0

0x455e64 LDR	X13, [SP, #96]

0x455e68 LDP	X8, X10, [SP, #144]

0x455e6c LDP	X15, X11, [SP, #224]

0x455e70 LDP	X12, X9, [SP, #240]

0x455e74 LDR	X14, [SP, #128]

0x455e78 LDR	X2, [X13, X28]

0x455e7c LDR	X4, [X14, X28]

0x455e80 LDP	X0, X6, [SP, #160]

0x455e84 ADD	X3, X10, X22

0x455e88 ADD	X28, X8, X22

0x455e8c STR	X3, [SP, #160]

0x455e90 LDR	X30, [SP, #184]

0x455e94 SUB	X7, X0, #1

0x455e98 CMP	X30, X6

0x455e9c B.LE	45638c

0x455ea0 LDR	X30, [SP, #176]

0x455ea4 ORR	X18, XZR, X21

0x455ea8 STR	X15, [SP, #152]

0x455eac LDR	X17, [SP, #208]

0x455eb0 STR	X28, [SP, #168]

0x455eb4 HINT	#0

0x455eb8 HINT	#0

0x455ebc HINT	#0

(643) 0x455ec0 LDR	X21, [SP, #104]

(643) 0x455ec4 LDR	X6, [X21, X9,LSL #3]

(643) 0x455ec8 UBFM	X15, X6, #61, #60

(643) 0x455ecc ORN	X0, XZR, X6

(643) 0x455ed0 ADD	X14, X15, #8

(643) 0x455ed4 LDR	X3, [X12, X15]

(643) 0x455ed8 ADD	X5, X12, X14

(643) 0x455edc LDR	X13, [X12, X14]

(643) 0x455ee0 CMP	X3, X13

(643) 0x455ee4 B.GE	456248

(643) 0x455ee8 ORR	X28, XZR, X24

(643) 0x455eec STR	X6, [SP, #128]

(643) 0x455ef0 ORR	X6, XZR, X5

(643) 0x455ef4 B	455f04

  (646) 0x455ef8 ADD	X3, X3, #1

  (646) 0x455efc CMP	X3, X13

  (646) 0x455f00 B.GE	456240

  (646) 0x455f04 LDR	X24, [X27, X3,LSL #3]

  (646) 0x455f08 UBFM	X1, X24, #61, #60

  (646) 0x455f0c LDR	X16, [X25, X1]

  (646) 0x455f10 CMP	X16, X7

  (646) 0x455f14 B.NE	455ef8

  (646) 0x455f18 LDR	X21, [SP, #152]

  (646) 0x455f1c ADD	X16, X1, #8

  (646) 0x455f20 LDR	X13, [X23, X16]

  (646) 0x455f24 LDR	X5, [X21, X1]

  (646) 0x455f28 ADD	X13, X5, X13

  (646) 0x455f2c CMP	X5, X13

  (646) 0x455f30 B.GE	4560b8

  (646) 0x455f34 LDR	X24, [SP, #160]

  (646) 0x455f38 UBFM	X21, X5, #61, #60

  (646) 0x455f3c STR	X21, [SP, #144]

  (646) 0x455f40 LDUR	X24, [X24, #504]

  (646) 0x455f44 ADD	X13, X24, X13,LSL #3

  (646) 0x455f48 ADD	X5, X24, X5,LSL #3

  (646) 0x455f4c SUB	X21, X13, X5

  (646) 0x455f50 STR	X13, [SP, #96]

  (646) 0x455f54 SUB	X21, X21, #8

  (646) 0x455f58 UBFM	X21, X21, #3, #63

  (646) 0x455f5c ADD	X21, X21, #1

  (646) 0x455f60 ANDS	X21, X21, #0x3

  (646) 0x455f64 B.EQ	456000

  (646) 0x455f68 CMP	X21, #1

  (646) 0x455f6c B.EQ	455fcc

  (646) 0x455f70 CMP	X21, #2

  (646) 0x455f74 B.EQ	455fa4

  (646) 0x455f78 LDR	X13, [SP, #144]

  (646) 0x455f7c LDR	X24, [X24, X13]

  (646) 0x455f80 UBFM	X21, X24, #61, #60

  (646) 0x455f84 LDR	X13, [X20, X21]

  (646) 0x455f88 CMP	X13, X0

  (646) 0x455f8c B.EQ	455fa0

  (646) 0x455f90 LDR	X13, [X10, X22]

  (646) 0x455f94 STR	X24, [X13, X4,LSL #3]

  (646) 0x455f98 ADD	X4, X4, #1

  (646) 0x455f9c STR	X0, [X20, X21]

  (646) 0x455fa0 ADD	X5, X5, #8

  (646) 0x455fa4 LDR	X24, [X5]

  (646) 0x455fa8 UBFM	X21, X24, #61, #60

  (646) 0x455fac LDR	X13, [X20, X21]

  (646) 0x455fb0 CMP	X13, X0

  (646) 0x455fb4 B.EQ	455fc8

  (646) 0x455fb8 LDR	X13, [X10, X22]

  (646) 0x455fbc STR	X24, [X13, X4,LSL #3]

  (646) 0x455fc0 ADD	X4, X4, #1

  (646) 0x455fc4 STR	X0, [X20, X21]

  (646) 0x455fc8 ADD	X5, X5, #8

  (646) 0x455fcc LDR	X24, [X5]

  (646) 0x455fd0 UBFM	X21, X24, #61, #60

  (646) 0x455fd4 LDR	X13, [X20, X21]

  (646) 0x455fd8 CMP	X13, X0

  (646) 0x455fdc B.EQ	455ff0

  (646) 0x455fe0 LDR	X13, [X10, X22]

  (646) 0x455fe4 STR	X24, [X13, X4,LSL #3]

  (646) 0x455fe8 ADD	X4, X4, #1

  (646) 0x455fec STR	X0, [X20, X21]

  (646) 0x455ff0 LDR	X13, [SP, #96]

  (646) 0x455ff4 ADD	X5, X5, #8

  (646) 0x455ff8 CMP	X13, X5

  (646) 0x455ffc B.EQ	4560b8

  (646) 0x456000 ORR	X24, XZR, X2

  (646) 0x456004 STR	X1, [SP, #96]

  (646) 0x456008 STR	X19, [SP, #144]

    (648) 0x45600c LDR	X21, [X5]

    (648) 0x456010 ADD	X2, X5, #8

    (648) 0x456014 UBFM	X19, X21, #61, #60

    (648) 0x456018 LDR	X1, [X20, X19]

    (648) 0x45601c CMP	X1, X0

    (648) 0x456020 B.EQ	456034

    (648) 0x456024 LDR	X1, [X10, X22]

    (648) 0x456028 STR	X21, [X1, X4,LSL #3]

    (648) 0x45602c ADD	X4, X4, #1

    (648) 0x456030 STR	X0, [X20, X19]

    (648) 0x456034 LDR	X19, [X5, #8]

    (648) 0x456038 UBFM	X5, X19, #61, #60

    (648) 0x45603c LDR	X21, [X20, X5]

    (648) 0x456040 CMP	X21, X0

    (648) 0x456044 B.EQ	456058

    (648) 0x456048 LDR	X1, [X10, X22]

    (648) 0x45604c STR	X19, [X1, X4,LSL #3]

    (648) 0x456050 ADD	X4, X4, #1

    (648) 0x456054 STR	X0, [X20, X5]

    (648) 0x456058 LDR	X21, [X2, #8]

    (648) 0x45605c ADD	X5, X2, #24

    (648) 0x456060 UBFM	X19, X21, #61, #60

    (648) 0x456064 LDR	X1, [X20, X19]

    (648) 0x456068 CMP	X1, X0

    (648) 0x45606c B.EQ	456080

    (648) 0x456070 LDR	X1, [X10, X22]

    (648) 0x456074 STR	X21, [X1, X4,LSL #3]

    (648) 0x456078 ADD	X4, X4, #1

    (648) 0x45607c STR	X0, [X20, X19]

    (648) 0x456080 LDR	X19, [X2, #16]

    (648) 0x456084 UBFM	X2, X19, #61, #60

    (648) 0x456088 LDR	X21, [X20, X2]

    (648) 0x45608c CMP	X21, X0

    (648) 0x456090 B.EQ	4560a4

    (648) 0x456094 LDR	X1, [X10, X22]

    (648) 0x456098 STR	X19, [X1, X4,LSL #3]

    (648) 0x45609c ADD	X4, X4, #1

    (648) 0x4560a0 STR	X0, [X20, X2]

    (648) 0x4560a4 CMP	X13, X5

    (648) 0x4560a8 B.NE	45600c

  (646) 0x4560ac LDR	X1, [SP, #96]

  (646) 0x4560b0 ORR	X2, XZR, X24

  (646) 0x4560b4 LDR	X19, [SP, #144]

  (646) 0x4560b8 LDR	X13, [SP, #136]

  (646) 0x4560bc LDR	X16, [X18, X16]

  (646) 0x4560c0 LDR	X24, [X13, X1]

  (646) 0x4560c4 ADD	X5, X24, X16

  (646) 0x4560c8 CMP	X24, X5

  (646) 0x4560cc B.GE	45622c

  (646) 0x4560d0 LDR	X1, [SP, #168]

  (646) 0x4560d4 UBFM	X21, X24, #61, #60

  (646) 0x4560d8 LDUR	X16, [X1, #504]

  (646) 0x4560dc ADD	X1, X16, X24,LSL #3

  (646) 0x4560e0 ADD	X5, X16, X5,LSL #3

  (646) 0x4560e4 SUB	X13, X5, X1

  (646) 0x4560e8 SUB	X24, X13, #8

  (646) 0x4560ec UBFM	X13, X24, #3, #63

  (646) 0x4560f0 ADD	X24, X13, #1

  (646) 0x4560f4 ANDS	X13, X24, #0x3

  (646) 0x4560f8 B.EQ	45618c

  (646) 0x4560fc CMP	X13, #1

  (646) 0x456100 B.EQ	45615c

  (646) 0x456104 CMP	X13, #2

  (646) 0x456108 B.EQ	456134

  (646) 0x45610c LDR	X16, [X16, X21]

  (646) 0x456110 UBFM	X24, X16, #61, #60

  (646) 0x456114 LDR	X21, [X19, X24]

  (646) 0x456118 CMP	X21, X0

  (646) 0x45611c B.EQ	456130

  (646) 0x456120 LDR	X13, [X8, X22]

  (646) 0x456124 STR	X16, [X13, X2,LSL #3]

  (646) 0x456128 ADD	X2, X2, #1

  (646) 0x45612c STR	X0, [X19, X24]

  (646) 0x456130 ADD	X1, X1, #8

  (646) 0x456134 LDR	X16, [X1]

  (646) 0x456138 UBFM	X24, X16, #61, #60

  (646) 0x45613c LDR	X21, [X19, X24]

  (646) 0x456140 CMP	X21, X0

  (646) 0x456144 B.EQ	456158

  (646) 0x456148 LDR	X13, [X8, X22]

  (646) 0x45614c STR	X16, [X13, X2,LSL #3]

  (646) 0x456150 ADD	X2, X2, #1

  (646) 0x456154 STR	X0, [X19, X24]

  (646) 0x456158 ADD	X1, X1, #8

  (646) 0x45615c LDR	X16, [X1]

  (646) 0x456160 UBFM	X24, X16, #61, #60

  (646) 0x456164 LDR	X21, [X19, X24]

  (646) 0x456168 CMP	X21, X0

  (646) 0x45616c B.EQ	456180

  (646) 0x456170 LDR	X13, [X8, X22]

  (646) 0x456174 STR	X16, [X13, X2,LSL #3]

  (646) 0x456178 ADD	X2, X2, #1

  (646) 0x45617c STR	X0, [X19, X24]

  (646) 0x456180 ADD	X1, X1, #8

  (646) 0x456184 CMP	X1, X5

  (646) 0x456188 B.EQ	45622c

    (647) 0x45618c LDR	X21, [X1]

    (647) 0x456190 ADD	X13, X1, #8

    (647) 0x456194 UBFM	X16, X21, #61, #60

    (647) 0x456198 LDR	X24, [X19, X16]

    (647) 0x45619c CMP	X24, X0

    (647) 0x4561a0 B.EQ	4561b4

    (647) 0x4561a4 LDR	X24, [X8, X22]

    (647) 0x4561a8 STR	X21, [X24, X2,LSL #3]

    (647) 0x4561ac ADD	X2, X2, #1

    (647) 0x4561b0 STR	X0, [X19, X16]

    (647) 0x4561b4 LDR	X16, [X1, #8]

    (647) 0x4561b8 UBFM	X1, X16, #61, #60

    (647) 0x4561bc LDR	X21, [X19, X1]

    (647) 0x4561c0 CMP	X21, X0

    (647) 0x4561c4 B.EQ	4561d8

    (647) 0x4561c8 LDR	X24, [X8, X22]

    (647) 0x4561cc STR	X16, [X24, X2,LSL #3]

    (647) 0x4561d0 ADD	X2, X2, #1

    (647) 0x4561d4 STR	X0, [X19, X1]

    (647) 0x4561d8 LDR	X21, [X13, #8]

    (647) 0x4561dc ADD	X1, X13, #24

    (647) 0x4561e0 UBFM	X16, X21, #61, #60

    (647) 0x4561e4 LDR	X24, [X19, X16]

    (647) 0x4561e8 CMP	X24, X0

    (647) 0x4561ec B.EQ	456200

    (647) 0x4561f0 LDR	X24, [X8, X22]

    (647) 0x4561f4 STR	X21, [X24, X2,LSL #3]

    (647) 0x4561f8 ADD	X2, X2, #1

    (647) 0x4561fc STR	X0, [X19, X16]

    (647) 0x456200 LDR	X16, [X13, #16]

    (647) 0x456204 UBFM	X13, X16, #61, #60

    (647) 0x456208 LDR	X21, [X19, X13]

    (647) 0x45620c CMP	X21, X0

    (647) 0x456210 B.EQ	456224

    (647) 0x456214 LDR	X24, [X8, X22]

    (647) 0x456218 STR	X16, [X24, X2,LSL #3]

    (647) 0x45621c ADD	X2, X2, #1

    (647) 0x456220 STR	X0, [X19, X13]

    (647) 0x456224 CMP	X1, X5

    (647) 0x456228 B.NE	45618c

  (646) 0x45622c LDR	X13, [X6]

  (646) 0x456230 ADD	X3, X3, #1

  (646) 0x456234 CMP	X3, X13

  (646) 0x456238 B.LT	455f04

(643) 0x45623c HINT	#0

(643) 0x456240 LDR	X6, [SP, #128]

(643) 0x456244 ORR	X24, XZR, X28

(643) 0x456248 ORN	X6, XZR, X6

(643) 0x45624c LDR	X1, [X11, X15]

(643) 0x456250 ADD	X15, X11, X14

(643) 0x456254 LDR	X3, [X11, X14]

(643) 0x456258 CMP	X3, X1

(643) 0x45625c B.LE	456380

(643) 0x456260 LDP	X21, X28, [SP, #112]

(643) 0x456264 B	456274

  (644) 0x456268 ADD	X1, X1, #1

  (644) 0x45626c CMP	X1, X3

  (644) 0x456270 B.GE	456380

  (644) 0x456274 LDR	X0, [X26, X1,LSL #3]

  (644) 0x456278 UBFM	X14, X0, #61, #60

  (644) 0x45627c LDR	X5, [X24, X14]

  (644) 0x456280 CMP	X5, X7

  (644) 0x456284 B.NE	456268

  (644) 0x456288 ADD	X16, X21, X14

  (644) 0x45628c LDR	X0, [X17, X14]

  (644) 0x456290 LDR	X13, [X16, #8]

  (644) 0x456294 ADD	X5, X0, X13

  (644) 0x456298 CMP	X0, X5

  (644) 0x45629c B.GE	456268

  (644) 0x4562a0 LDR	X16, [X28, X22]

  (644) 0x4562a4 UBFM	X14, X0, #61, #60

  (644) 0x4562a8 ADD	X5, X16, X5,LSL #3

  (644) 0x4562ac ADD	X0, X16, X0,LSL #3

  (644) 0x4562b0 SUB	X3, X5, X0

  (644) 0x4562b4 SUB	X13, X3, #8

  (644) 0x4562b8 UBFM	X3, X13, #3, #63

  (644) 0x4562bc ADD	X13, X3, #1

  (644) 0x4562c0 ANDS	X3, X13, #0x3

  (644) 0x4562c4 B.EQ	456448

  (644) 0x4562c8 CMP	X3, #1

  (644) 0x4562cc B.EQ	456330

  (644) 0x4562d0 CMP	X3, #2

  (644) 0x4562d4 B.EQ	456304

  (644) 0x4562d8 LDR	X16, [X16, X14]

  (644) 0x4562dc TBNZ	X16, #63, 45658c

  (644) 0x4562e0 UBFM	X13, X16, #61, #60

  (644) 0x4562e4 LDR	X14, [X19, X13]

  (644) 0x4562e8 CMP	X14, X6

  (644) 0x4562ec B.EQ	456300

  (644) 0x4562f0 LDR	X3, [X8, X22]

  (644) 0x4562f4 STR	X16, [X3, X2,LSL #3]

  (644) 0x4562f8 ADD	X2, X2, #1

  (644) 0x4562fc STR	X6, [X19, X13]

  (644) 0x456300 ADD	X0, X0, #8

  (644) 0x456304 LDR	X3, [X0]

  (644) 0x456308 TBNZ	X3, #63, 456560

  (644) 0x45630c UBFM	X13, X3, #61, #60

  (644) 0x456310 LDR	X14, [X19, X13]

  (644) 0x456314 CMP	X14, X6

  (644) 0x456318 B.EQ	45632c

  (644) 0x45631c LDR	X16, [X8, X22]

  (644) 0x456320 STR	X3, [X16, X2,LSL #3]

  (644) 0x456324 ADD	X2, X2, #1

  (644) 0x456328 STR	X6, [X19, X13]

  (644) 0x45632c ADD	X0, X0, #8

  (644) 0x456330 LDR	X16, [X0]

  (644) 0x456334 TBNZ	X16, #63, 456534

  (644) 0x456338 UBFM	X13, X16, #61, #60

  (644) 0x45633c LDR	X14, [X19, X13]

  (644) 0x456340 CMP	X14, X6

  (644) 0x456344 B.EQ	456358

  (644) 0x456348 LDR	X3, [X8, X22]

  (644) 0x45634c STR	X16, [X3, X2,LSL #3]

  (644) 0x456350 ADD	X2, X2, #1

  (644) 0x456354 STR	X6, [X19, X13]

  (644) 0x456358 ADD	X0, X0, #8

  (644) 0x45635c CMP	X0, X5

  (644) 0x456360 B.NE	456448

  (644) 0x456364 LDR	X3, [X15]

  (644) 0x456368 ADD	X1, X1, #1

  (644) 0x45636c CMP	X1, X3

  (644) 0x456370 B.LT	456274

(643) 0x456374 HINT	#0

(643) 0x456378 HINT	#0

(643) 0x45637c HINT	#0

(643) 0x456380 ADD	X9, X9, #1

(643) 0x456384 CMP	X30, X9

(643) 0x456388 B.GT	455ec0

0x45638c ORR	X0, XZR, X20

0x456390 BL	524f40

0x456394 LDR	X27, [SP, #200]

0x456398 LDR	X23, [SP, #192]

0x45639c LDR	X26, [SP, #216]

0x4563a0 CMP	X27, #0

0x4563a4 CCMP	X23, X26, #4, #0

0x4563a8 B.NE	4565b8

0x4563ac LDP	X21, X22, [SP, #32]

0x4563b0 ORR	X0, XZR, X19

0x4563b4 LDP	X23, X24, [SP, #48]

0x4563b8 LDP	X19, X20, [SP, #16]

0x4563bc LDP	X25, X26, [SP, #64]

0x4563c0 LDP	X27, X28, [SP, #80]

0x4563c4 LDP	X29, X30, [SP], #288

0x4563c8 B	524f40

    (645) 0x4563cc UBFM	X13, X16, #61, #60

    (645) 0x4563d0 LDR	X14, [X19, X13]

    (645) 0x4563d4 CMP	X14, X6

    (645) 0x4563d8 B.EQ	4563ec

    (645) 0x4563dc LDR	X3, [X8, X22]

    (645) 0x4563e0 STR	X16, [X3, X2,LSL #3]

    (645) 0x4563e4 ADD	X2, X2, #1

    (645) 0x4563e8 STR	X6, [X19, X13]

    (645) 0x4563ec LDR	X3, [X0, #8]

    (645) 0x4563f0 TBNZ	X3, #63, 4564ac

    (645) 0x4563f4 UBFM	X13, X3, #61, #60

    (645) 0x4563f8 LDR	X14, [X19, X13]

    (645) 0x4563fc CMP	X14, X6

    (645) 0x456400 B.EQ	456414

    (645) 0x456404 LDR	X16, [X8, X22]

    (645) 0x456408 STR	X3, [X16, X2,LSL #3]

    (645) 0x45640c ADD	X2, X2, #1

    (645) 0x456410 STR	X6, [X19, X13]

    (645) 0x456414 LDR	X16, [X0, #16]

    (645) 0x456418 TBNZ	X16, #63, 4564dc

    (645) 0x45641c UBFM	X13, X16, #61, #60

    (645) 0x456420 LDR	X14, [X19, X13]

    (645) 0x456424 CMP	X14, X6

    (645) 0x456428 B.EQ	45643c

    (645) 0x45642c LDR	X3, [X8, X22]

    (645) 0x456430 STR	X16, [X3, X2,LSL #3]

    (645) 0x456434 ADD	X2, X2, #1

    (645) 0x456438 STR	X6, [X19, X13]

    (645) 0x45643c ADD	X0, X0, #24

    (645) 0x456440 CMP	X0, X5

    (645) 0x456444 B.EQ	456364

    (645) 0x456448 LDR	X3, [X0]

    (645) 0x45644c TBNZ	X3, #63, 456508

    (645) 0x456450 UBFM	X13, X3, #61, #60

    (645) 0x456454 LDR	X14, [X19, X13]

    (645) 0x456458 CMP	X14, X6

    (645) 0x45645c B.EQ	456470

    (645) 0x456460 LDR	X16, [X8, X22]

    (645) 0x456464 STR	X3, [X16, X2,LSL #3]

    (645) 0x456468 ADD	X2, X2, #1

    (645) 0x45646c STR	X6, [X19, X13]

    (645) 0x456470 LDR	X16, [X0, #8]

    (645) 0x456474 ADD	X0, X0, #8

    (645) 0x456478 TBZ	X16, #63, 4563cc

    (645) 0x45647c ORN	X13, XZR, X16

    (645) 0x456480 UBFM	X13, X13, #61, #60

    (645) 0x456484 LDR	X14, [X20, X13]

    (645) 0x456488 CMP	X14, X6

    (645) 0x45648c B.EQ	4563ec

    (645) 0x456490 LDR	X14, [X10, X22]

    (645) 0x456494 ORN	X16, XZR, X16

    (645) 0x456498 STR	X16, [X14, X4,LSL #3]

    (645) 0x45649c ADD	X4, X4, #1

    (645) 0x4564a0 STR	X6, [X20, X13]

    (645) 0x4564a4 LDR	X3, [X0, #8]

    (645) 0x4564a8 TBZ	X3, #63, 4563f4

    (645) 0x4564ac ORN	X13, XZR, X3

    (645) 0x4564b0 UBFM	X16, X13, #61, #60

    (645) 0x4564b4 LDR	X14, [X20, X16]

    (645) 0x4564b8 CMP	X14, X6

    (645) 0x4564bc B.EQ	456414

    (645) 0x4564c0 LDR	X13, [X10, X22]

    (645) 0x4564c4 ORN	X3, XZR, X3

    (645) 0x4564c8 STR	X3, [X13, X4,LSL #3]

    (645) 0x4564cc ADD	X4, X4, #1

    (645) 0x4564d0 STR	X6, [X20, X16]

    (645) 0x4564d4 LDR	X16, [X0, #16]

    (645) 0x4564d8 TBZ	X16, #63, 45641c

    (645) 0x4564dc ORN	X13, XZR, X16

    (645) 0x4564e0 UBFM	X13, X13, #61, #60

    (645) 0x4564e4 LDR	X14, [X20, X13]

    (645) 0x4564e8 CMP	X14, X6

    (645) 0x4564ec B.EQ	45643c

    (645) 0x4564f0 LDR	X14, [X10, X22]

    (645) 0x4564f4 ORN	X16, XZR, X16

    (645) 0x4564f8 STR	X16, [X14, X4,LSL #3]

    (645) 0x4564fc ADD	X4, X4, #1

    (645) 0x456500 STR	X6, [X20, X13]

    (645) 0x456504 B	45643c

    (645) 0x456508 ORN	X13, XZR, X3

    (645) 0x45650c UBFM	X16, X13, #61, #60

    (645) 0x456510 LDR	X14, [X20, X16]

    (645) 0x456514 CMP	X14, X6

    (645) 0x456518 B.EQ	456470

    (645) 0x45651c LDR	X13, [X10, X22]

    (645) 0x456520 ORN	X3, XZR, X3

    (645) 0x456524 STR	X3, [X13, X4,LSL #3]

    (645) 0x456528 ADD	X4, X4, #1

    (645) 0x45652c STR	X6, [X20, X16]

    (645) 0x456530 B	456470

  (644) 0x456534 ORN	X13, XZR, X16

  (644) 0x456538 UBFM	X13, X13, #61, #60

  (644) 0x45653c LDR	X14, [X20, X13]

  (644) 0x456540 CMP	X14, X6

  (644) 0x456544 B.EQ	456358

  (644) 0x456548 LDR	X14, [X10, X22]

  (644) 0x45654c ORN	X16, XZR, X16

  (644) 0x456550 STR	X16, [X14, X4,LSL #3]

  (644) 0x456554 ADD	X4, X4, #1

  (644) 0x456558 STR	X6, [X20, X13]

  (644) 0x45655c B	456358

  (644) 0x456560 ORN	X13, XZR, X3

  (644) 0x456564 UBFM	X16, X13, #61, #60

  (644) 0x456568 LDR	X14, [X20, X16]

  (644) 0x45656c CMP	X14, X6

  (644) 0x456570 B.EQ	45632c

  (644) 0x456574 LDR	X13, [X10, X22]

  (644) 0x456578 ORN	X3, XZR, X3

  (644) 0x45657c STR	X3, [X13, X4,LSL #3]

  (644) 0x456580 ADD	X4, X4, #1

  (644) 0x456584 STR	X6, [X20, X16]

  (644) 0x456588 B	45632c

  (644) 0x45658c ORN	X13, XZR, X16

  (644) 0x456590 UBFM	X13, X13, #61, #60

  (644) 0x456594 LDR	X14, [X20, X13]

  (644) 0x456598 CMP	X14, X6

  (644) 0x45659c B.EQ	456300

  (644) 0x4565a0 LDR	X14, [X10, X22]

  (644) 0x4565a4 ORN	X16, XZR, X16

  (644) 0x4565a8 STR	X16, [X14, X4,LSL #3]

  (644) 0x4565ac ADD	X4, X4, #1

  (644) 0x4565b0 STR	X6, [X20, X13]

  (644) 0x4565b4 B	456300

0x4565b8 LDP	X19, X20, [SP, #16]

0x4565bc LDP	X21, X22, [SP, #32]

0x4565c0 LDP	X23, X24, [SP, #48]

0x4565c4 LDP	X25, X26, [SP, #64]

0x4565c8 LDP	X27, X28, [SP, #80]

0x4565cc LDP	X29, X30, [SP], #288

0x4565d0 RET

0x4565d4 MOVZ	X1, #8

0x4565d8 ORR	X28, XZR, X0

0x4565dc STR	X13, [SP, #96]

0x4565e0 STR	X14, [SP, #128]

0x4565e4 STR	X4, [SP, #144]

0x4565e8 STP	X8, X10, [SP, #224]

0x4565ec STP	X18, X11, [SP, #240]

0x4565f0 STP	X12, X9, [SP, #256]

0x4565f4 STR	X3, [SP, #272]

0x4565f8 BL	524ea8

0x4565fc CMP	X28, #0

0x456600 LDR	X13, [SP, #96]

0x456604 ORR	X19, XZR, X0

0x456608 LDP	X8, X10, [SP, #224]

0x45660c LDP	X18, X11, [SP, #240]

0x456610 LDP	X12, X9, [SP, #256]

0x456614 LDR	X14, [SP, #128]

0x456618 LDR	X4, [SP, #144]

0x45661c LDR	X3, [SP, #272]

0x456620 B.LE	45538c

0x456624 UBFM	X2, X28, #61, #60

0x456628 MOVZ	W1, #255

0x45662c BL	410600

0x456630 LDR	X13, [SP, #96]

0x456634 LDP	X8, X10, [SP, #224]

0x456638 LDP	X18, X11, [SP, #240]

0x45663c LDP	X12, X9, [SP, #256]

0x456640 LDR	X14, [SP, #128]

0x456644 LDR	X4, [SP, #144]

0x456648 LDR	X3, [SP, #272]

0x45664c B	45538c

0x456650 ORR	X28, XZR, X30

0x456654 MOVZ	X1, #8

0x456658 STR	X13, [SP, #96]

0x45665c ORR	X0, XZR, X30

0x456660 STR	X14, [SP, #128]

0x456664 STR	X4, [SP, #144]

0x456668 STP	X8, X10, [SP, #224]

0x45666c STP	X18, X11, [SP, #240]

0x456670 STP	X12, X9, [SP, #256]

0x456674 STR	X3, [SP, #272]

0x456678 B	4565f8

0x45667c LDR	X5, [SP, #104]

0x456680 ORR	X7, XZR, X15

0x456684 LDR	X1, [SP, #136]

0x456688 B	455d94

0x45668c LDR	X1, [SP, #104]

0x456690 LDR	X15, [X3]

0x456694 LDR	X6, [SP, #136]

0x456698 LDR	X16, [X1, X0,LSL #3]

0x45669c ADD	X0, X0, #1

0x4566a0 ADD	X7, X18, X16,LSL #3

0x4566a4 ADD	X5, X6, X16,LSL #3

0x4566a8 LDR	X30, [X7]

0x4566ac ADD	X4, X30, X15

0x4566b0 STR	X4, [X7]

0x4566b4 LDR	X17, [X2]

0x4566b8 LDR	X15, [X5]

0x4566bc ADD	X1, X15, X17

0x4566c0 STR	X1, [X5]

0x4566c4 B	455d0c

0x4566c8 MOVZ	X1, #8

0x4566cc ORR	X0, XZR, X28

0x4566d0 STR	X5, [SP, #96]

0x4566d4 STR	X13, [SP, #128]

0x4566d8 STP	X14, X7, [SP, #144]

0x4566dc STP	X8, X10, [SP, #224]

0x4566e0 BL	524ea8

0x4566e4 LDR	X18, [SP, #96]

0x4566e8 STR	X0, [X18, X22]

0x4566ec BL	4102a0

0x4566f0 LDR	X8, [SP, #96]

0x4566f4 LDP	X15, X11, [SP, #144]

0x4566f8 LDP	X12, X9, [SP, #224]

0x4566fc LDR	X10, [SP, #128]

0x456700 B	455a38

0x456704 BL	4102a0

0x456708 B	45638c

0x45670c STR	X5, [SP, #96]

0x456710 STR	X13, [SP, #128]

0x456714 STP	X14, X7, [SP, #144]

0x456718 STP	X8, X10, [SP, #224]

0x45671c B	455a24

Coverage (%)	Name	Source Location	Module
►98.50+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.50+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:891	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_multi_interp.c:891-1134
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:891,900-927,939-970,976-999,1008-1034,1040-1125,1132-1134.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 34% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 91.17 to 27.67 cycles (3.30x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_CAlloc: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:916
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1048
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:921
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1050
hypre_Free: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1132
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:900
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:901
unknown: 10 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:918
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1013
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1024
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1013
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1024
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:923
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	417
nb uops	412
loop length	1668
used w registers	1
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	207

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	51.50 cycles
front end	51.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	22.50	22.50	28.00	28.00	28.00	28.00	0.00	0.00	0.00	0.00	91.17	90.83	91.00	54.50	54.50
cycles	22.50	22.50	28.00	28.00	28.00	28.00	0.00	0.00	0.00	0.00	91.17	90.83	91.00	54.50	54.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	51.50
Dispatch	91.17
DIV/SQRT	5.00-20.00
Overall L1	91.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	34%
load	42%
store	33%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 91.17 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 45520c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #736]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X3, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X1, X18, [X3, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X8, [X3, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X26, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X12, X27, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X21, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X10, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X11, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X2, [X3, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X3, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X3, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X12, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [X3, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X20, X7, [X3, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X14, X13, [X3, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X28, [X3, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X24, [X3, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X14, X7, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [X3, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X6, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X15, [X3, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X13, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [X3, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X22, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UBFM X22, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X16, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 527b40 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 527b20 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X11, X20, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
LDR X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X12, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X0, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X0, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X18, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X1, X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X18, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
MUL X8, X18, X11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X2, X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSEL X4, X2, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, X4, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X3, X14, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X4, X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X18, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X11, X12, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X13, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B.LE 45536c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X4, X8, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X18, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X11, X12, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X3, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410600 <@plt_start@+0x5e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X4, X8, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X18, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X11, X12, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X3, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X0, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X30, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456650 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1444>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X0, 4565d4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x13c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X10, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X15, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X7, X16, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MOVZ X5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X8, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X17, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4558dc <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x6d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X30, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X13, X14, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X13, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X10, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X4, X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
LDR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X13, X14, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X4, X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X17, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X18, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBNZ X17, 455c48 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xa3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X18, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X28, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X11, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [X18], #504	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [X28], #504	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X18, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X4, X13, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X4, X6, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MOVZ X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X15, X13, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X2, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 455978 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x76c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X6, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X4, X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X15, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X13, X12, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X3, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X7, X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X18, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X11, X12, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X15, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X28, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [X15, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X15, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X15, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X0, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X14, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [X13, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X30, X6, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X3, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X30, [X15, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X2, [X15, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X18, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X9, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X14, X7, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X0, [X13, X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X28, 4566c8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x14bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X1, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45670c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1500>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X5, X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X15, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X10, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 455e80 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xc74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X28, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X14, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [X13, X28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [X14, X28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X7, X6, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X18, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4559ac <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X28, X28, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X14, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X13, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 456704 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x14f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORN X1, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X7, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X16, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X18, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X30, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X17, X1, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X1, X17, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X5, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X7, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X17, X4, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X17, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X15, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 455e4c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xc40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X1, 45667c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 455d44 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xb38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45668c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X18, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X17, X7, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X4, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X4, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X15, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X16, X1, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X16, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X30, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X18, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X17, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X17, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X1, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X30, X16, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X30, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 455e4c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xc40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X7, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X8, X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X11, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X8, X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X15, X11, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X13, X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X14, X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X0, X6, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X3, X10, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X28, X8, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X3, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X7, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X30, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45638c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X18, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X15, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X28, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X27, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X26, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X23, X26, #4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.NE 4565b8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x13ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #288	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
B 524f40 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #288	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X28, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X18, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B.LE 45538c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410600 <@plt_start@+0x5e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X18, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 45538c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X28, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X0, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 4565f8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x13ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X7, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 455d94 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xb88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X18, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X6, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X30, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X4, X30, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X4, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X15, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X1, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 455d0c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xb00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X14, X7, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X18, X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X15, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X10, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 455a38 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x82c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 45638c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X14, X7, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 455a24 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x818>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_multi_interp.c:891-1134
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_CAlloc: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:916
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1048
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:921
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1050
hypre_Free: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1132
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:900
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:901
unknown: 10 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:918
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1013
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1024
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1013
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1024
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:923
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	417
nb uops	412
loop length	1668
used w registers	1
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	207

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	51.50 cycles
front end	51.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	22.50	22.50	28.00	28.00	28.00	28.00	0.00	0.00	0.00	0.00	91.17	90.83	91.00	54.50	54.50
cycles	22.50	22.50	28.00	28.00	28.00	28.00	0.00	0.00	0.00	0.00	91.17	90.83	91.00	54.50	54.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	51.50
Dispatch	91.17
DIV/SQRT	5.00-20.00
Overall L1	91.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	34%
load	42%
store	33%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 91.17 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 45520c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #736]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X3, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X1, X18, [X3, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X8, [X3, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X26, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X12, X27, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X21, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X10, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X11, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X2, [X3, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X3, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X3, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X12, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [X3, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X20, X7, [X3, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X14, X13, [X3, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X28, [X3, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X24, [X3, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X14, X7, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [X3, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X6, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X15, [X3, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X13, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [X3, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X22, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UBFM X22, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X16, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 527b40 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 527b20 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X11, X20, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
LDR X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X12, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X0, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X0, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X18, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X1, X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X18, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
MUL X8, X18, X11	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X2, X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSEL X4, X2, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, X4, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X3, X14, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X4, X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X18, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X11, X12, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X13, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B.LE 45536c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X4, X8, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X18, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X11, X12, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X3, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410600 <@plt_start@+0x5e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X4, X8, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X18, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X11, X12, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X3, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X0, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X30, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 456650 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1444>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X0, 4565d4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x13c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X10, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X15, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X7, X16, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MOVZ X5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X8, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X17, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4558dc <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x6d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X30, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X13, X14, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X13, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X10, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X4, X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
LDR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X13, X14, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X4, X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X17, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X18, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBNZ X17, 455c48 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xa3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X18, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X28, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X11, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [X18], #504	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [X28], #504	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X18, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X4, X13, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X4, X6, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MOVZ X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X15, X13, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X2, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 455978 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x76c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X6, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X4, X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X15, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X13, X12, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X3, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X7, X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X18, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X11, X12, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X15, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X28, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [X15, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X15, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X15, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X0, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X14, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [X13, X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X30, X6, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X3, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X30, [X15, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X2, [X15, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X18, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X9, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X14, X7, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X0, [X13, X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X28, 4566c8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x14bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X1, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45670c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1500>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X5, X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X15, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X10, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 455e80 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xc74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X28, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X14, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [X13, X28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [X14, X28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X7, X6, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X18, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4559ac <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X28, X28, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X14, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X13, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 456704 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x14f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORN X1, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X7, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X16, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X18, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X30, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X17, X1, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X1, X17, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X5, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X7, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X17, X4, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X17, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X15, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 455e4c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xc40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X1, 45667c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 455d44 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xb38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45668c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X18, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X17, X7, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X4, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X4, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X15, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X16, X1, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X16, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X30, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X18, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X17, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X17, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X1, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X30, X16, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X30, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 455e4c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xc40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X7, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X8, X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X11, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X8, X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X15, X11, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X13, X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X14, X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X0, X6, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X3, X10, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X28, X8, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X3, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X7, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X30, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45638c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X18, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X15, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X28, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X27, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X26, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X23, X26, #4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.NE 4565b8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x13ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #288	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
B 524f40 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #288	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X28, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X18, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B.LE 45538c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410600 <@plt_start@+0x5e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X18, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 45538c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X28, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X0, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 4565f8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x13ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X7, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 455d94 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xb88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X18, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X6, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X30, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X4, X30, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X4, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X15, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X1, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 455d0c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xb00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X14, X7, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X18, X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X15, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X9, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X10, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 455a38 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x82c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4102a0 <@plt_start@+0x280>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 45638c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X5, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X14, X7, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 455a24 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x818>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass._omp_fn.5–	1.19	0.50
▼Loop 651 - par_multi_interp.c:939-999 - exec–	0.04	0.01
▼Loop 654 - par_multi_interp.c:944-970 - exec–	0.52	0.16
○Loop 656 - par_multi_interp.c:951-958 - exec	0.00	0.00
○Loop 655 - par_multi_interp.c:963-970 - exec	0.00	0.00
▼Loop 652 - par_multi_interp.c:976-999 - exec–	0.00	0.00
○Loop 653 - par_multi_interp.c:983-999 - exec	0.00	0.00
▼Loop 643 - par_multi_interp.c:1072-1125 - exec–	0.04	0.01
▼Loop 646 - par_multi_interp.c:1075-1099 - exec–	0.55	0.17
○Loop 648 - par_multi_interp.c:1082-1088 - exec	0.00	0.00
○Loop 647 - par_multi_interp.c:1093-1099 - exec	0.00	0.00
▼Loop 644 - par_multi_interp.c:1104-1125 - exec–	0.00	0.00
○Loop 645 - par_multi_interp.c:1111-1125 - exec	0.00	0.00
○Loop 649 - par_multi_interp.c:1030-1034 - exec	0.03	0.01
○Loop 650 - par_multi_interp.c:1017-1020 - exec	0.00	0.00

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