OV - exec - Function hypre_BoomerAMGBuildMultipass._omp

	Function: hypre_BoomerAMGBuildMultipass._omp_fn.10	Module: exec	Source: par_multi_interp.c:1737-1881 [...]	Coverage (incl. loops): 1.03% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1737 - 1881

--------------------------------------------------------------------------------

1737: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa,tmp_array,tmp_array_offd)

[...]

1746:              tmp_marker = NULL;

1747:              if (n_fine)

1748:              {    tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); }

1749:              tmp_marker_offd = NULL;

1750:              if (num_cols_offd)

1751:              {    tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); }

1752:              tmp_array = NULL;

1753:              if (n_coarse)

1754:              {    tmp_array = hypre_CTAlloc(HYPRE_Int,n_coarse); }

1755:              tmp_array_offd = NULL;

1756:              if (new_num_cols_offd > n_coarse_offd)

1757:              {    tmp_array_offd = hypre_CTAlloc(HYPRE_Int,new_num_cols_offd); }

1758:              else

1759:              {    tmp_array_offd = hypre_CTAlloc(HYPRE_Int,n_coarse_offd);}

1760:              for (i=0; i < n_fine; i++)

1761:              {    tmp_marker[i] = -1; }

1762:              for (i=0; i < num_cols_offd; i++)

1763:              {    tmp_marker_offd[i] = -1; }

1764:

1765:              /* Compute this thread's range of pass_length */

1766:              my_thread_num = hypre_GetThreadNum();

1767:              num_threads = hypre_NumActiveThreads();

1768:              thread_start = pass_pointer[pass] + (pass_length/num_threads)*my_thread_num;

1769:              if (my_thread_num == num_threads-1)

1770:              {  thread_stop = pass_pointer[pass] + pass_length; }

1771:              else

1772:              {  thread_stop = pass_pointer[pass] + (pass_length/num_threads)*(my_thread_num+1); }

1773:

1774:              for (i=thread_start; i < thread_stop; i++)

1775:              {

1776:                 i1 = pass_array[i];

1777:                 sum_C = 0;

1778:                 sum_N = 0;

1779:                 j_start = P_diag_start[i1];

1780:                 j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1781:                 cnt = P_diag_i[i1];

1782:                 for (j=j_start; j < j_end; j++)

1783:                 {

1784:                    k1 = P_diag_pass[pass][j];

1785:                tmp_array[k1] = cnt;

1786:                P_diag_data[cnt] = 0;

1787:                P_diag_j[cnt++] = k1;

1788:                 }

1789:                 j_start = P_offd_start[i1];

1790:                 j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1791:                 cnt_offd = P_offd_i[i1];

1792:                 for (j=j_start; j < j_end; j++)

1793:                 {

1794:                    k1 = P_offd_pass[pass][j];

1795:                tmp_array_offd[k1] = cnt_offd;

1796:                P_offd_data[cnt_offd] = 0;

1797:                P_offd_j[cnt_offd++] = k1;

1798:                 }

1799:                 for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1800:                 {

1801:                j1 = S_diag_j[j];

1802:                if (assigned[j1] == pass-1)

1803:                   tmp_marker[j1] = i1;

1804:                 }

1805:                 for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1806:                 {

1807:                j1 = S_offd_j[j];

1808:                if (assigned_offd[j1] == pass-1)

1809:                   tmp_marker_offd[j1] = i1;

1810:                 }

1811:                 for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1812:                 {

1813:                j1 = A_diag_j[j];

1814:                if (tmp_marker[j1] == i1)

1815:                {

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

1823:                       }

1824:                   for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++)

1825:                   {

1826:                  k1 = P_offd_j[k];

1827:                      alfa = A_diag_data[j]*P_offd_data[k];

1828:                      P_offd_data[tmp_array_offd[k1]] += alfa;

1829:                      sum_C += alfa;

1830:                      sum_N += alfa;

1831:                       }

1832:                    }

1833:                    else

1834:                    {

1835:                       if (CF_marker[j1] != -3 &&

1836:                 (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1837:                  sum_N += A_diag_data[j];

1838:                    }

1839:                 }

1840:                 for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1841:                 {

1842:                if (col_offd_S_to_A)

1843:                   j1 = map_A_to_S[A_offd_j[j]];

1844:                else

1845:                   j1 = A_offd_j[j];

1846:

1847:                if (j1 > -1 && tmp_marker_offd[j1] == i1)

1848:                {

1849:                   j_start = Pext_start[j1];

1850:                   j_end = j_start+Pext_i[j1+1];

1851:                   for (k=j_start; k < j_end; k++)

1852:                   {

1853:                  k1 = Pext_pass[pass][k];

1854:                      alfa = A_offd_data[j]*Pext_data[k];

1855:                  if (k1 < 0)

1856:                         P_diag_data[tmp_array[-k1-1]] += alfa;

1857:                  else

1858:                         P_offd_data[tmp_array_offd[k1]] += alfa;

1859:                      sum_C += alfa;

1860:                      sum_N += alfa;

1861:                       }

1862:                    }

1863:                    else

1864:                    {

1865:                       if (CF_marker_offd[j1] != -3 &&

1866:                 (num_functions == 1 || dof_func_offd[j1] == dof_func[i1]))

1867:                  sum_N += A_offd_data[j];

1868:                    }

1869:                 }

1870:                 diagonal = A_diag_data[A_diag_i[i1]];

1871:                 if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1872:

1873:                 for (j=P_diag_i[i1]; j < P_diag_i[i1+1]; j++)

1874:                P_diag_data[j] *= alfa;

1875:                 for (j=P_offd_i[i1]; j < P_offd_i[i1+1]; j++)

1876:                P_offd_data[j] *= alfa;

1877:              }

1878:              hypre_TFree(tmp_marker);

1879:              hypre_TFree(tmp_marker_offd);

1880:              hypre_TFree(tmp_array);

1881:              hypre_TFree(tmp_array_offd);

0x45830c STP	X29, X30, [SP, #640]!

0x458310 ADD	X29, SP, #0

0x458314 STP	X19, X20, [SP, #16]

0x458318 STP	X21, X22, [SP, #32]

0x45831c STP	X23, X24, [SP, #48]

0x458320 STP	X25, X26, [SP, #64]

0x458324 STP	X27, X28, [SP, #80]

0x458328 LDR	X3, [X0, #96]

0x45832c LDP	X1, X11, [X0, #80]

0x458330 LDP	X25, X19, [X0, #136]

0x458334 STR	X3, [SP, #224]

0x458338 LDR	X4, [X0, #112]

0x45833c STR	X1, [SP, #232]

0x458340 LDR	X5, [X0, #128]

0x458344 LDR	X7, [X0, #152]

0x458348 STR	X4, [SP, #104]

0x45834c LDR	X8, [X0, #168]

0x458350 STR	X5, [SP, #160]

0x458354 LDR	X9, [X0, #184]

0x458358 STR	X7, [SP, #120]

0x45835c LDR	X12, [X0, #192]

0x458360 STR	X8, [SP, #320]

0x458364 LDR	X10, [X0, #104]

0x458368 STR	X9, [SP, #296]

0x45836c LDR	X20, [X0, #120]

0x458370 LDR	X24, [X0, #160]

0x458374 LDR	X6, [X0, #176]

0x458378 LDR	X2, [X0, #272]

0x45837c STR	X12, [SP, #216]

0x458380 LDR	X8, [X0, #72]

0x458384 LDP	X7, X18, [X0]

0x458388 LDP	X22, X3, [X0, #280]

0x45838c LDP	X9, X28, [X0, #296]

0x458390 STR	X8, [SP, #304]

0x458394 LDR	X13, [X0, #200]

0x458398 LDR	X14, [X0, #208]

0x45839c LDR	X15, [X0, #216]

0x4583a0 STR	X13, [SP, #144]

0x4583a4 LDR	X16, [X0, #224]

0x4583a8 STR	X14, [SP, #208]

0x4583ac LDR	X17, [X0, #232]

0x4583b0 STR	X15, [SP, #200]

0x4583b4 LDR	X21, [X0, #240]

0x4583b8 STR	X16, [SP, #288]

0x4583bc LDR	X23, [X0, #248]

0x4583c0 STR	X17, [SP, #280]

0x4583c4 LDR	X26, [X0, #256]

0x4583c8 STR	X21, [SP, #328]

0x4583cc LDR	X30, [X0, #264]

0x4583d0 STR	X23, [SP, #312]

0x4583d4 LDR	X1, [X0, #312]

0x4583d8 STR	X26, [SP, #272]

0x4583dc LDR	X5, [X0, #328]

0x4583e0 STR	X30, [SP, #128]

0x4583e4 LDR	X27, [X0, #16]

0x4583e8 STR	X1, [SP, #264]

0x4583ec LDR	X4, [X0, #320]

0x4583f0 STR	X5, [SP, #112]

0x4583f4 LDP	X13, X21, [X0, #24]

0x4583f8 LDR	X14, [X0, #40]

0x4583fc STR	X13, [SP, #176]

0x458400 LDR	X12, [X0, #48]

0x458404 STR	X14, [SP, #248]

0x458408 LDP	X15, X0, [X0, #56]

0x45840c STR	X15, [SP, #168]

0x458410 STR	X0, [SP, #240]

0x458414 CBNZ	X2, 459720

0x458418 MOVZ	X26, #0

0x45841c LDR	X0, [SP, #104]

0x458420 CBNZ	X0, 4596d8

0x458424 MOVZ	X5, #0

0x458428 CBNZ	X22, 45968c

0x45842c MOVZ	X23, #0

0x458430 CMP	X4, X3

0x458434 B.LE	45966c

0x458438 ORR	X0, XZR, X4

0x45843c STR	X5, [SP, #136]

0x458440 STR	X9, [SP, #152]

0x458444 STP	X2, X6, [SP, #184]

0x458448 STR	X10, [SP, #256]

0x45844c STP	X11, X12, [SP, #336]

0x458450 STP	X18, X7, [SP, #352]

0x458454 MOVZ	X1, #8

0x458458 BL	524ea8

0x45845c LDP	X1, X14, [SP, #184]

0x458460 ORR	X22, XZR, X0

0x458464 LDP	X4, X9, [SP, #336]

0x458468 LDP	X3, X6, [SP, #352]

0x45846c LDR	X8, [SP, #136]

0x458470 LDR	X13, [SP, #152]

0x458474 LDR	X15, [SP, #256]

0x458478 CMP	X1, #0

0x45847c B.LE	4584c0

0x458480 UBFM	X2, X1, #61, #60

0x458484 ORR	X0, XZR, X26

0x458488 STR	X8, [SP, #136]

0x45848c MOVZ	W1, #255

0x458490 STR	X13, [SP, #152]

0x458494 STP	X14, X15, [SP, #184]

0x458498 STR	X4, [SP, #256]

0x45849c STP	X9, X3, [SP, #336]

0x4584a0 STR	X6, [SP, #352]

0x4584a4 BL	410600

0x4584a8 LDR	X8, [SP, #136]

0x4584ac LDP	X14, X15, [SP, #184]

0x4584b0 LDP	X9, X3, [SP, #336]

0x4584b4 LDR	X13, [SP, #152]

0x4584b8 LDR	X4, [SP, #256]

0x4584bc LDR	X6, [SP, #352]

0x4584c0 LDR	X16, [SP, #104]

0x4584c4 CMP	X16, #0

0x4584c8 B.LE	458508

0x4584cc ORR	X0, XZR, X8

0x4584d0 UBFM	X2, X16, #61, #60

0x4584d4 STR	X13, [SP, #136]

0x4584d8 MOVZ	W1, #255

0x4584dc STR	X14, [SP, #152]

0x4584e0 STP	X15, X4, [SP, #184]

0x4584e4 STR	X9, [SP, #256]

0x4584e8 STP	X3, X6, [SP, #336]

0x4584ec BL	410600

0x4584f0 LDR	X13, [SP, #136]

0x4584f4 ORR	X8, XZR, X0

0x4584f8 LDP	X15, X4, [SP, #184]

0x4584fc LDP	X3, X6, [SP, #336]

0x458500 LDR	X14, [SP, #152]

0x458504 LDR	X9, [SP, #256]

0x458508 STR	X8, [SP, #152]

0x45850c STP	X13, X14, [SP, #184]

0x458510 STP	X15, X4, [SP, #336]

0x458514 STP	X9, X3, [SP, #352]

0x458518 STR	X6, [SP, #368]

0x45851c BL	527b40

0x458520 STR	X0, [SP, #104]

0x458524 BL	527b20

0x458528 LDR	X10, [SP, #112]

0x45852c SUB	X7, X0, #1

0x458530 LDP	X2, X15, [SP, #144]

0x458534 SDIV	X5, X10, X0

0x458538 LDR	X11, [SP, #128]

0x45853c LDR	X8, [SP, #104]

0x458540 UBFM	X12, X11, #61, #60

0x458544 LDR	X18, [X2, X12]

0x458548 CMP	X8, X7

0x45854c STR	X12, [SP, #136]

0x458550 MUL	X1, X8, X5

0x458554 ADD	X13, X10, X18

0x458558 ADD	X14, X5, X1

0x45855c ADD	X4, X18, X1

0x458560 ADD	X9, X14, X18

0x458564 CSEL	X3, X13, X9, #0

0x458568 CMP	X3, X4

0x45856c B.LE	458f88

0x458570 SUB	X30, X25, #8

0x458574 SUB	X17, X24, #8

0x458578 LDR	X7, [SP, #368]

0x45857c SUB	X2, X11, #1

0x458580 LDP	X9, X6, [SP, #184]

0x458584 LDP	X10, X11, [SP, #336]

0x458588 LDP	X12, X18, [SP, #352]

0x45858c STP	X30, X17, [SP, #104]

0x458590 LDR	X30, [SP, #176]

0x458594 LDP	X16, X17, [SP, #160]

0x458598 STR	X4, [SP, #128]

0x45859c STR	X3, [SP, #256]

(679) 0x4585a0 LDR	X5, [SP, #128]

(679) 0x4585a4 LDR	X0, [SP, #216]

(679) 0x4585a8 LDR	X1, [SP, #208]

(679) 0x4585ac LDR	X3, [X0, X5,LSL #3]

(679) 0x4585b0 UBFM	X4, X3, #61, #60

(679) 0x4585b4 ADD	X8, X4, #8

(679) 0x4585b8 LDR	X14, [X1, X4]

(679) 0x4585bc LDR	X13, [X16, X8]

(679) 0x4585c0 LDR	X0, [X16, X4]

(679) 0x4585c4 ADD	X5, X14, X13

(679) 0x4585c8 SUB	X5, X5, X0

(679) 0x4585cc CMP	X14, X5

(679) 0x4585d0 B.GE	4587ac

(679) 0x4585d4 LDR	X13, [SP, #136]

(679) 0x4585d8 LDR	X1, [SP, #288]

(679) 0x4585dc LDR	X1, [X1, X13]

(679) 0x4585e0 SUB	X13, X0, X14

(679) 0x4585e4 ADD	X13, X13, X5

(679) 0x4585e8 SUB	X5, X13, X0

(679) 0x4585ec ANDS	X5, X5, #0x7

(679) 0x4585f0 STR	X1, [SP, #144]

(679) 0x4585f4 SUB	X1, XZR, X0,LSL #3

(679) 0x4585f8 ADD	X1, X1, X14,LSL #3

(679) 0x4585fc LDR	X14, [SP, #144]

(679) 0x458600 ADD	X1, X14, X1

(679) 0x458604 B.EQ	45962c

(679) 0x458608 CMP	X5, #1

(679) 0x45860c B.EQ	4586c8

(679) 0x458610 CMP	X5, #2

(679) 0x458614 B.EQ	4586b0

(679) 0x458618 CMP	X5, #3

(679) 0x45861c B.EQ	458698

(679) 0x458620 CMP	X5, #4

(679) 0x458624 B.EQ	458680

(679) 0x458628 CMP	X5, #5

(679) 0x45862c B.EQ	458668

(679) 0x458630 CMP	X5, #6

(679) 0x458634 B.EQ	458650

(679) 0x458638 LDR	X5, [X1, X0,LSL #3]

(679) 0x45863c LDR	X14, [SP, #104]

(679) 0x458640 STR	X0, [X23, X5,LSL #3]

(679) 0x458644 STR	XZR, [X20, X0,LSL #3]

(679) 0x458648 ADD	X0, X0, #1

(679) 0x45864c STR	X5, [X14, X0,LSL #3]

(679) 0x458650 LDR	X5, [X1, X0,LSL #3]

(679) 0x458654 LDR	X14, [SP, #104]

(679) 0x458658 STR	X0, [X23, X5,LSL #3]

(679) 0x45865c STR	XZR, [X20, X0,LSL #3]

(679) 0x458660 ADD	X0, X0, #1

(679) 0x458664 STR	X5, [X14, X0,LSL #3]

(679) 0x458668 LDR	X5, [X1, X0,LSL #3]

(679) 0x45866c LDR	X14, [SP, #104]

(679) 0x458670 STR	X0, [X23, X5,LSL #3]

(679) 0x458674 STR	XZR, [X20, X0,LSL #3]

(679) 0x458678 ADD	X0, X0, #1

(679) 0x45867c STR	X5, [X14, X0,LSL #3]

(679) 0x458680 LDR	X5, [X1, X0,LSL #3]

(679) 0x458684 LDR	X14, [SP, #104]

(679) 0x458688 STR	X0, [X23, X5,LSL #3]

(679) 0x45868c STR	XZR, [X20, X0,LSL #3]

(679) 0x458690 ADD	X0, X0, #1

(679) 0x458694 STR	X5, [X14, X0,LSL #3]

(679) 0x458698 LDR	X5, [X1, X0,LSL #3]

(679) 0x45869c LDR	X14, [SP, #104]

(679) 0x4586a0 STR	X0, [X23, X5,LSL #3]

(679) 0x4586a4 STR	XZR, [X20, X0,LSL #3]

(679) 0x4586a8 ADD	X0, X0, #1

(679) 0x4586ac STR	X5, [X14, X0,LSL #3]

(679) 0x4586b0 LDR	X5, [X1, X0,LSL #3]

(679) 0x4586b4 LDR	X14, [SP, #104]

(679) 0x4586b8 STR	X0, [X23, X5,LSL #3]

(679) 0x4586bc STR	XZR, [X20, X0,LSL #3]

(679) 0x4586c0 ADD	X0, X0, #1

(679) 0x4586c4 STR	X5, [X14, X0,LSL #3]

(679) 0x4586c8 LDR	X5, [X1, X0,LSL #3]

(679) 0x4586cc LDR	X14, [SP, #104]

(679) 0x4586d0 STR	X0, [X23, X5,LSL #3]

(679) 0x4586d4 STR	XZR, [X20, X0,LSL #3]

(679) 0x4586d8 ADD	X0, X0, #1

(679) 0x4586dc STR	X5, [X14, X0,LSL #3]

(679) 0x4586e0 CMP	X13, X0

(679) 0x4586e4 B.EQ	4587ac

(679) 0x4586e8 ORR	X5, XZR, X14

(679) 0x4586ec STP	X26, X15, [SP, #144]

(679) 0x4586f0 STP	X22, X28, [SP, #160]

(679) 0x4586f4 STP	X9, X6, [SP, #176]

  (690) 0x4586f8 ADD	X6, X0, #1

  (690) 0x4586fc ADD	X26, X0, #2

  (690) 0x458700 ADD	X22, X0, #3

  (690) 0x458704 ADD	X15, X0, #4

  (690) 0x458708 LDR	X28, [X1, X0,LSL #3]

  (690) 0x45870c ADD	X14, X0, #5

  (690) 0x458710 ADD	X9, X0, #6

  (690) 0x458714 STR	X0, [X23, X28,LSL #3]

  (690) 0x458718 STR	XZR, [X20, X0,LSL #3]

  (690) 0x45871c STR	X28, [X5, X6,LSL #3]

  (690) 0x458720 LDR	X28, [X1, X6,LSL #3]

  (690) 0x458724 STR	X6, [X23, X28,LSL #3]

  (690) 0x458728 STR	XZR, [X20, X6,LSL #3]

  (690) 0x45872c ADD	X6, X0, #7

  (690) 0x458730 ADD	X0, X0, #8

  (690) 0x458734 STR	X28, [X5, X26,LSL #3]

  (690) 0x458738 LDR	X28, [X1, X26,LSL #3]

  (690) 0x45873c STR	X26, [X23, X28,LSL #3]

  (690) 0x458740 STR	XZR, [X20, X26,LSL #3]

  (690) 0x458744 STR	X28, [X5, X22,LSL #3]

  (690) 0x458748 LDR	X26, [X1, X22,LSL #3]

  (690) 0x45874c STR	X22, [X23, X26,LSL #3]

  (690) 0x458750 STR	XZR, [X20, X22,LSL #3]

  (690) 0x458754 STR	X26, [X5, X15,LSL #3]

  (690) 0x458758 LDR	X22, [X1, X15,LSL #3]

  (690) 0x45875c STR	X15, [X23, X22,LSL #3]

  (690) 0x458760 STR	XZR, [X20, X15,LSL #3]

  (690) 0x458764 STR	X22, [X5, X14,LSL #3]

  (690) 0x458768 LDR	X15, [X1, X14,LSL #3]

  (690) 0x45876c STR	X14, [X23, X15,LSL #3]

  (690) 0x458770 STR	XZR, [X20, X14,LSL #3]

  (690) 0x458774 STR	X15, [X5, X9,LSL #3]

  (690) 0x458778 LDR	X14, [X1, X9,LSL #3]

  (690) 0x45877c STR	X9, [X23, X14,LSL #3]

  (690) 0x458780 STR	XZR, [X20, X9,LSL #3]

  (690) 0x458784 STR	X14, [X5, X6,LSL #3]

  (690) 0x458788 LDR	X9, [X1, X6,LSL #3]

  (690) 0x45878c STR	X6, [X23, X9,LSL #3]

  (690) 0x458790 STR	XZR, [X20, X6,LSL #3]

  (690) 0x458794 STR	X9, [X5, X0,LSL #3]

  (690) 0x458798 CMP	X13, X0

  (690) 0x45879c B.NE	4586f8

(679) 0x4587a0 LDP	X26, X15, [SP, #144]

(679) 0x4587a4 LDP	X22, X28, [SP, #160]

(679) 0x4587a8 LDP	X9, X6, [SP, #176]

(679) 0x4587ac LDR	X13, [SP, #120]

(679) 0x4587b0 LDR	X0, [SP, #200]

(679) 0x4587b4 LDR	X5, [X13, X8]

(679) 0x4587b8 LDR	X1, [X0, X4]

(679) 0x4587bc LDR	X0, [X13, X4]

(679) 0x4587c0 ADD	X14, X1, X5

(679) 0x4587c4 SUB	X5, X14, X0

(679) 0x4587c8 CMP	X1, X5

(679) 0x4587cc B.GE	4589a0

(679) 0x4587d0 LDR	X14, [SP, #136]

(679) 0x4587d4 LDR	X13, [SP, #280]

(679) 0x4587d8 LDR	X14, [X13, X14]

(679) 0x4587dc SUB	X13, X0, X1

(679) 0x4587e0 UBFM	X1, X1, #61, #60

(679) 0x4587e4 ADD	X13, X13, X5

(679) 0x4587e8 SUB	X1, X1, X0,LSL #3

(679) 0x4587ec SUB	X5, X13, X0

(679) 0x4587f0 ANDS	X5, X5, #0x7

(679) 0x4587f4 ADD	X1, X14, X1

(679) 0x4587f8 B.EQ	459618

(679) 0x4587fc CMP	X5, #1

(679) 0x458800 B.EQ	4588bc

(679) 0x458804 CMP	X5, #2

(679) 0x458808 B.EQ	4588a4

(679) 0x45880c CMP	X5, #3

(679) 0x458810 B.EQ	45888c

(679) 0x458814 CMP	X5, #4

(679) 0x458818 B.EQ	458874

(679) 0x45881c CMP	X5, #5

(679) 0x458820 B.EQ	45885c

(679) 0x458824 CMP	X5, #6

(679) 0x458828 B.EQ	458844

(679) 0x45882c LDR	X5, [X1, X0,LSL #3]

(679) 0x458830 LDR	X14, [SP, #112]

(679) 0x458834 STR	X0, [X22, X5,LSL #3]

(679) 0x458838 STR	XZR, [X19, X0,LSL #3]

(679) 0x45883c ADD	X0, X0, #1

(679) 0x458840 STR	X5, [X14, X0,LSL #3]

(679) 0x458844 LDR	X5, [X1, X0,LSL #3]

(679) 0x458848 LDR	X14, [SP, #112]

(679) 0x45884c STR	X0, [X22, X5,LSL #3]

(679) 0x458850 STR	XZR, [X19, X0,LSL #3]

(679) 0x458854 ADD	X0, X0, #1

(679) 0x458858 STR	X5, [X14, X0,LSL #3]

(679) 0x45885c LDR	X5, [X1, X0,LSL #3]

(679) 0x458860 LDR	X14, [SP, #112]

(679) 0x458864 STR	X0, [X22, X5,LSL #3]

(679) 0x458868 STR	XZR, [X19, X0,LSL #3]

(679) 0x45886c ADD	X0, X0, #1

(679) 0x458870 STR	X5, [X14, X0,LSL #3]

(679) 0x458874 LDR	X5, [X1, X0,LSL #3]

(679) 0x458878 LDR	X14, [SP, #112]

(679) 0x45887c STR	X0, [X22, X5,LSL #3]

(679) 0x458880 STR	XZR, [X19, X0,LSL #3]

(679) 0x458884 ADD	X0, X0, #1

(679) 0x458888 STR	X5, [X14, X0,LSL #3]

(679) 0x45888c LDR	X5, [X1, X0,LSL #3]

(679) 0x458890 LDR	X14, [SP, #112]

(679) 0x458894 STR	X0, [X22, X5,LSL #3]

(679) 0x458898 STR	XZR, [X19, X0,LSL #3]

(679) 0x45889c ADD	X0, X0, #1

(679) 0x4588a0 STR	X5, [X14, X0,LSL #3]

(679) 0x4588a4 LDR	X5, [X1, X0,LSL #3]

(679) 0x4588a8 LDR	X14, [SP, #112]

(679) 0x4588ac STR	X0, [X22, X5,LSL #3]

(679) 0x4588b0 STR	XZR, [X19, X0,LSL #3]

(679) 0x4588b4 ADD	X0, X0, #1

(679) 0x4588b8 STR	X5, [X14, X0,LSL #3]

(679) 0x4588bc LDR	X5, [X1, X0,LSL #3]

(679) 0x4588c0 LDR	X14, [SP, #112]

(679) 0x4588c4 STR	X0, [X22, X5,LSL #3]

(679) 0x4588c8 STR	XZR, [X19, X0,LSL #3]

(679) 0x4588cc ADD	X0, X0, #1

(679) 0x4588d0 STR	X5, [X14, X0,LSL #3]

(679) 0x4588d4 CMP	X0, X13

(679) 0x4588d8 B.EQ	4589a0

(679) 0x4588dc ORR	X5, XZR, X14

(679) 0x4588e0 STP	X26, X15, [SP, #144]

(679) 0x4588e4 STP	X23, X28, [SP, #160]

(679) 0x4588e8 STP	X9, X6, [SP, #176]

  (689) 0x4588ec ADD	X6, X0, #1

  (689) 0x4588f0 ADD	X26, X0, #2

  (689) 0x4588f4 ADD	X23, X0, #3

  (689) 0x4588f8 ADD	X15, X0, #4

  (689) 0x4588fc LDR	X28, [X1, X0,LSL #3]

  (689) 0x458900 ADD	X14, X0, #5

  (689) 0x458904 ADD	X9, X0, #6

  (689) 0x458908 STR	X0, [X22, X28,LSL #3]

  (689) 0x45890c STR	XZR, [X19, X0,LSL #3]

  (689) 0x458910 STR	X28, [X5, X6,LSL #3]

  (689) 0x458914 LDR	X28, [X1, X6,LSL #3]

  (689) 0x458918 STR	X6, [X22, X28,LSL #3]

  (689) 0x45891c STR	XZR, [X19, X6,LSL #3]

  (689) 0x458920 ADD	X6, X0, #7

  (689) 0x458924 ADD	X0, X0, #8

  (689) 0x458928 STR	X28, [X5, X26,LSL #3]

  (689) 0x45892c LDR	X28, [X1, X26,LSL #3]

  (689) 0x458930 STR	X26, [X22, X28,LSL #3]

  (689) 0x458934 STR	XZR, [X19, X26,LSL #3]

  (689) 0x458938 STR	X28, [X5, X23,LSL #3]

  (689) 0x45893c LDR	X26, [X1, X23,LSL #3]

  (689) 0x458940 STR	X23, [X22, X26,LSL #3]

  (689) 0x458944 STR	XZR, [X19, X23,LSL #3]

  (689) 0x458948 STR	X26, [X5, X15,LSL #3]

  (689) 0x45894c LDR	X23, [X1, X15,LSL #3]

  (689) 0x458950 STR	X15, [X22, X23,LSL #3]

  (689) 0x458954 STR	XZR, [X19, X15,LSL #3]

  (689) 0x458958 STR	X23, [X5, X14,LSL #3]

  (689) 0x45895c LDR	X15, [X1, X14,LSL #3]

  (689) 0x458960 STR	X14, [X22, X15,LSL #3]

  (689) 0x458964 STR	XZR, [X19, X14,LSL #3]

  (689) 0x458968 STR	X15, [X5, X9,LSL #3]

  (689) 0x45896c LDR	X14, [X1, X9,LSL #3]

  (689) 0x458970 STR	X9, [X22, X14,LSL #3]

  (689) 0x458974 STR	XZR, [X19, X9,LSL #3]

  (689) 0x458978 STR	X14, [X5, X6,LSL #3]

  (689) 0x45897c LDR	X9, [X1, X6,LSL #3]

  (689) 0x458980 STR	X6, [X22, X9,LSL #3]

  (689) 0x458984 STR	XZR, [X19, X6,LSL #3]

  (689) 0x458988 STR	X9, [X5, X0,LSL #3]

  (689) 0x45898c CMP	X0, X13

  (689) 0x458990 B.NE	4588ec

(679) 0x458994 LDP	X26, X15, [SP, #144]

(679) 0x458998 LDP	X23, X28, [SP, #160]

(679) 0x45899c LDP	X9, X6, [SP, #176]

(679) 0x4589a0 LDR	X0, [SP, #232]

(679) 0x4589a4 LDR	X1, [X0, X4]

(679) 0x4589a8 ADD	X14, X0, X8

(679) 0x4589ac LDR	X13, [X0, X8]

(679) 0x4589b0 CMP	X1, X13

(679) 0x4589b4 B.GE	4589e0

(679) 0x4589b8 HINT	#0

(679) 0x4589bc HINT	#0

  (688) 0x4589c0 LDR	X5, [X11, X1,LSL #3]

  (688) 0x4589c4 UBFM	X0, X5, #61, #60

  (688) 0x4589c8 LDR	X5, [X9, X0]

  (688) 0x4589cc CMP	X2, X5

  (688) 0x4589d0 B.EQ	458fc4

  (688) 0x4589d4 ADD	X1, X1, #1

  (688) 0x4589d8 CMP	X1, X13

  (688) 0x4589dc B.LT	4589c0

(679) 0x4589e0 LDR	X0, [SP, #224]

(679) 0x4589e4 LDR	X1, [X0, X4]

(679) 0x4589e8 ADD	X14, X0, X8

(679) 0x4589ec LDR	X13, [X0, X8]

(679) 0x4589f0 CMP	X1, X13

(679) 0x4589f4 B.GE	458a20

(679) 0x4589f8 HINT	#0

(679) 0x4589fc HINT	#0

  (687) 0x458a00 LDR	X5, [X10, X1,LSL #3]

  (687) 0x458a04 UBFM	X0, X5, #61, #60

  (687) 0x458a08 LDR	X5, [X28, X0]

  (687) 0x458a0c CMP	X2, X5

  (687) 0x458a10 B.EQ	458fdc

  (687) 0x458a14 ADD	X1, X1, #1

  (687) 0x458a18 CMP	X1, X13

  (687) 0x458a1c B.LT	458a00

(679) 0x458a20 LDR	X14, [SP, #248]

(679) 0x458a24 MOVI	D18, #0

(679) 0x458a28 FMOV	D29, D18

(679) 0x458a2c LDR	X1, [X14, X4]

(679) 0x458a30 LDR	X14, [X14, X8]

(679) 0x458a34 ADD	X0, X1, #1

(679) 0x458a38 CMP	X0, X14

(679) 0x458a3c B.GE	458ac4

(679) 0x458a40 STP	X15, X28, [SP, #144]

(679) 0x458a44 ORR	X15, XZR, X10

(679) 0x458a48 ORR	X10, XZR, X17

(679) 0x458a4c STR	X9, [SP, #160]

(679) 0x458a50 ORR	X9, XZR, X6

(679) 0x458a54 B	458a74

  (684) 0x458a58 LDR	X13, [X27, X5]

  (684) 0x458a5c LDR	X17, [X27, X4]

  (684) 0x458a60 CMP	X17, X13

  (684) 0x458a64 B.EQ	458a9c

  (684) 0x458a68 ADD	X0, X0, #1

  (684) 0x458a6c CMP	X0, X14

  (684) 0x458a70 B.EQ	458ab0

  (684) 0x458a74 LDR	X17, [X12, X0,LSL #3]

  (684) 0x458a78 UBFM	X5, X17, #61, #60

  (684) 0x458a7c LDR	X28, [X26, X5]

  (684) 0x458a80 CMP	X3, X28

  (684) 0x458a84 B.EQ	458ff4

  (684) 0x458a88 LDR	X6, [X7, X5]

  (684) 0x458a8c CMN	X6, #3

  (684) 0x458a90 B.EQ	458a68

  (684) 0x458a94 CMP	X18, #1

  (684) 0x458a98 B.NE	458a58

  (684) 0x458a9c LDR	D28, [X21, X0,LSL #3]

  (684) 0x458aa0 ADD	X0, X0, #1

  (684) 0x458aa4 FADD	D18, D18, D28

  (684) 0x458aa8 CMP	X0, X14

  (684) 0x458aac B.NE	458a74

(679) 0x458ab0 ORR	X6, XZR, X9

(679) 0x458ab4 LDR	X9, [SP, #160]

(679) 0x458ab8 ORR	X17, XZR, X10

(679) 0x458abc ORR	X10, XZR, X15

(679) 0x458ac0 LDP	X15, X28, [SP, #144]

(679) 0x458ac4 LDR	X5, [SP, #240]

(679) 0x458ac8 LDR	X0, [X5, X4]

(679) 0x458acc LDR	X5, [X5, X8]

(679) 0x458ad0 CMP	X0, X5

(679) 0x458ad4 B.GE	458b64

(679) 0x458ad8 LDR	X13, [SP, #304]

(679) 0x458adc STP	X26, X28, [SP, #144]

(679) 0x458ae0 STP	X9, X24, [SP, #160]

(679) 0x458ae4 STP	X25, X1, [SP, #176]

(679) 0x458ae8 LDR	X1, [SP, #296]

(679) 0x458aec LDP	X24, X25, [SP, #264]

(679) 0x458af0 B	458b10

  (682) 0x458af4 LDR	X28, [X1, X9]

  (682) 0x458af8 LDR	X9, [X27, X4]

  (682) 0x458afc CMP	X28, X9

  (682) 0x458b00 B.EQ	458b44

  (682) 0x458b04 ADD	X0, X0, #1

  (682) 0x458b08 CMP	X0, X5

  (682) 0x458b0c B.EQ	458b58

  (682) 0x458b10 LDR	X28, [X13, X0,LSL #3]

  (682) 0x458b14 CBZ	X30, 458b1c

  (682) 0x458b18 LDR	X28, [X25, X28,LSL #3]

  (682) 0x458b1c UBFM	X9, X28, #61, #60

  (682) 0x458b20 TBNZ	X28, #63, 458b30

  (682) 0x458b24 LDR	X26, [X15, X9]

  (682) 0x458b28 CMP	X3, X26

  (682) 0x458b2c B.EQ	459330

  (682) 0x458b30 LDR	X14, [X6, X9]

  (682) 0x458b34 CMN	X14, #3

  (682) 0x458b38 B.EQ	458b04

  (682) 0x458b3c CMP	X18, #1

  (682) 0x458b40 B.NE	458af4

  (682) 0x458b44 LDR	D5, [X17, X0,LSL #3]

  (682) 0x458b48 ADD	X0, X0, #1

  (682) 0x458b4c FADD	D18, D18, D5

  (682) 0x458b50 CMP	X0, X5

  (682) 0x458b54 B.NE	458b10

(679) 0x458b58 LDP	X26, X28, [SP, #144]

(679) 0x458b5c LDP	X9, X24, [SP, #160]

(679) 0x458b60 LDP	X25, X1, [SP, #176]

(679) 0x458b64 LDR	D20, [X21, X1,LSL #3]

(679) 0x458b68 FMUL	D22, D29, D20

(679) 0x458b6c FCMP	D22, #0

(679) 0x458b70 B.EQ	458b7c

(679) 0x458b74 FNEG	D18, D18

(679) 0x458b78 FDIV	D31, D18, D22

(679) 0x458b7c LDR	X3, [X16, X4]

(679) 0x458b80 LDR	X14, [X16, X8]

(679) 0x458b84 CMP	X3, X14

(679) 0x458b88 B.GE	458d78

(679) 0x458b8c SUB	X1, X14, X3

(679) 0x458b90 SUB	X5, X1, #1

(679) 0x458b94 CMP	X5, #2

(679) 0x458b98 B.LS	459640

(679) 0x458b9c UBFM	X5, X1, #2, #63

(679) 0x458ba0 ADD	X0, X20, X3,LSL #3

(679) 0x458ba4 DUP	V23.2D, V31.D[0]

(679) 0x458ba8 UBFM	X13, X5, #59, #58

(679) 0x458bac UBFM	X14, X3, #61, #60

(679) 0x458bb0 SUB	X13, X13, #32

(679) 0x458bb4 ADD	X5, X0, X5,LSL #5

(679) 0x458bb8 UBFM	X13, X13, #5, #63

(679) 0x458bbc ADD	X13, X13, #1

(679) 0x458bc0 ANDS	X13, X13, #0x7

(679) 0x458bc4 B.EQ	458c94

(679) 0x458bc8 CMP	X13, #1

(679) 0x458bcc B.EQ	458c78

(679) 0x458bd0 CMP	X13, #2

(679) 0x458bd4 B.EQ	458c64

(679) 0x458bd8 CMP	X13, #3

(679) 0x458bdc B.EQ	458c50

(679) 0x458be0 CMP	X13, #4

(679) 0x458be4 B.EQ	458c3c

(679) 0x458be8 CMP	X13, #5

(679) 0x458bec B.EQ	458c28

(679) 0x458bf0 CMP	X13, #6

(679) 0x458bf4 B.EQ	458c14

(679) 0x458bf8 LDR	Q26, [X20, X14]

(679) 0x458bfc ADD	X0, X0, #32

(679) 0x458c00 LDUR	Q0, [X0, #496]

(679) 0x458c04 FMUL	V30.2D, V26.2D, V23.2D

(679) 0x458c08 FMUL	V1.2D, V0.2D, V23.2D

(679) 0x458c0c STR	Q30, [X20, X14]

(679) 0x458c10 STUR	Q1, [X0, #496]

(679) 0x458c14 LDP	Q27, Q28, [X0]

(679) 0x458c18 ADD	X0, X0, #32

(679) 0x458c1c FMUL	V2.2D, V27.2D, V23.2D

(679) 0x458c20 FMUL	V7.2D, V28.2D, V23.2D

(679) 0x458c24 STP	Q2, Q7, [X0, #2016]

(679) 0x458c28 LDP	Q25, Q24, [X0]

(679) 0x458c2c ADD	X0, X0, #32

(679) 0x458c30 FMUL	V3.2D, V25.2D, V23.2D

(679) 0x458c34 FMUL	V5.2D, V24.2D, V23.2D

(679) 0x458c38 STP	Q3, Q5, [X0, #2016]

(679) 0x458c3c LDP	Q4, Q6, [X0]

(679) 0x458c40 ADD	X0, X0, #32

(679) 0x458c44 FMUL	V17.2D, V4.2D, V23.2D

(679) 0x458c48 FMUL	V16.2D, V6.2D, V23.2D

(679) 0x458c4c STP	Q17, Q16, [X0, #2016]

(679) 0x458c50 LDP	Q19, Q21, [X0]

(679) 0x458c54 ADD	X0, X0, #32

(679) 0x458c58 FMUL	V29.2D, V19.2D, V23.2D

(679) 0x458c5c FMUL	V20.2D, V21.2D, V23.2D

(679) 0x458c60 STP	Q29, Q20, [X0, #2016]

(679) 0x458c64 LDP	Q22, Q18, [X0]

(679) 0x458c68 ADD	X0, X0, #32

(679) 0x458c6c FMUL	V26.2D, V22.2D, V23.2D

(679) 0x458c70 FMUL	V30.2D, V18.2D, V23.2D

(679) 0x458c74 STP	Q26, Q30, [X0, #2016]

(679) 0x458c78 LDP	Q0, Q1, [X0]

(679) 0x458c7c ADD	X0, X0, #32

(679) 0x458c80 FMUL	V27.2D, V0.2D, V23.2D

(679) 0x458c84 FMUL	V28.2D, V1.2D, V23.2D

(679) 0x458c88 STP	Q27, Q28, [X0, #2016]

(679) 0x458c8c CMP	X5, X0

(679) 0x458c90 B.EQ	458d3c

(679) 0x458c94 STP	X26, X15, [SP, #144]

(679) 0x458c98 STP	X23, X22, [SP, #160]

  (681) 0x458c9c ORR	X22, XZR, X0

  (681) 0x458ca0 LDP	Q2, Q7, [X0]

  (681) 0x458ca4 LDP	Q25, Q24, [X0, #32]

  (681) 0x458ca8 LDP	Q3, Q5, [X0, #64]

  (681) 0x458cac LDP	Q29, Q20, [X0, #96]

  (681) 0x458cb0 LDP	Q22, Q18, [X0, #128]

  (681) 0x458cb4 FMUL	V4.2D, V2.2D, V23.2D

  (681) 0x458cb8 LDP	Q30, Q0, [X0, #160]

  (681) 0x458cbc FMUL	V6.2D, V7.2D, V23.2D

  (681) 0x458cc0 LDP	Q1, Q26, [X0, #192]

  (681) 0x458cc4 FMUL	V16.2D, V25.2D, V23.2D

  (681) 0x458cc8 LDP	Q27, Q28, [X0, #224]

  (681) 0x458ccc ADD	X0, X0, #256

  (681) 0x458cd0 FMUL	V19.2D, V24.2D, V23.2D

  (681) 0x458cd4 FMUL	V17.2D, V3.2D, V23.2D

  (681) 0x458cd8 FMUL	V21.2D, V5.2D, V23.2D

  (681) 0x458cdc FMUL	V7.2D, V29.2D, V23.2D

  (681) 0x458ce0 FMUL	V25.2D, V20.2D, V23.2D

  (681) 0x458ce4 FMUL	V5.2D, V22.2D, V23.2D

  (681) 0x458ce8 FMUL	V3.2D, V30.2D, V23.2D

  (681) 0x458cec STUR	Q17, [X0, #320]

  (681) 0x458cf0 FMUL	V2.2D, V1.2D, V23.2D

  (681) 0x458cf4 STUR	Q21, [X0, #336]

  (681) 0x458cf8 STP	Q4, Q6, [X0, #1792]

  (681) 0x458cfc FMUL	V6.2D, V18.2D, V23.2D

  (681) 0x458d00 FMUL	V4.2D, V0.2D, V23.2D

  (681) 0x458d04 STP	Q16, Q19, [X0, #1824]

  (681) 0x458d08 FMUL	V16.2D, V26.2D, V23.2D

  (681) 0x458d0c FMUL	V19.2D, V27.2D, V23.2D

  (681) 0x458d10 FMUL	V24.2D, V28.2D, V23.2D

  (681) 0x458d14 STP	Q7, Q25, [X0, #1888]

  (681) 0x458d18 STP	Q5, Q6, [X0, #1920]

  (681) 0x458d1c STP	Q3, Q4, [X0, #1952]

  (681) 0x458d20 STP	Q2, Q16, [X0, #1984]

  (681) 0x458d24 STUR	Q19, [X0, #480]

  (681) 0x458d28 STR	Q24, [X22, #240]

  (681) 0x458d2c CMP	X5, X0

  (681) 0x458d30 B.NE	458c9c

(679) 0x458d34 LDP	X26, X15, [SP, #144]

(679) 0x458d38 LDP	X23, X22, [SP, #160]

(679) 0x458d3c AND	X13, X1, #0x0

(679) 0x458d40 ANDS	XZR, X1, #0x3

(679) 0x458d44 B.EQ	458d78

(679) 0x458d48 ADD	X3, X13, X3

(679) 0x458d4c SUB	X14, X1, X13

(679) 0x458d50 DUP	Z23.D, Z31.D[0]

(679) 0x458d54 WHILELO	P7.D, XZR, X14

(679) 0x458d58 ADD	X1, X20, X3,LSL #3

(679) 0x458d5c LD1D	{Z17.D}, P7/Z, [X20, X3,LSL #3]

(679) 0x458d60 MOVPRFX	Z21, Z23

(679) 0x458d64 FMUL	Z21.D, P7/M, Z21.D, Z17.D

(679) 0x458d68 ST1D	{Z21.D}, P7, [X1, MUL VL]

(679) 0x458d6c CNTD	X5, ALL

(679) 0x458d70 WHILELO	P0.D, X5, X14

(679) 0x458d74 B.NE	4595cc

(679) 0x458d78 LDR	X13, [SP, #120]

(679) 0x458d7c LDR	X3, [X13, X4]

(679) 0x458d80 LDR	X4, [X13, X8]

(679) 0x458d84 CMP	X3, X4

(679) 0x458d88 B.GE	458f70

(679) 0x458d8c SUB	X14, X4, X3

(679) 0x458d90 SUB	X8, X14, #1

(679) 0x458d94 CMP	X8, #2

(679) 0x458d98 B.LS	459648

(679) 0x458d9c UBFM	X1, X14, #2, #63

(679) 0x458da0 ADD	X0, X19, X3,LSL #3

(679) 0x458da4 DUP	V30.2D, V31.D[0]

(679) 0x458da8 UBFM	X5, X1, #59, #58

(679) 0x458dac UBFM	X13, X3, #61, #60

(679) 0x458db0 SUB	X8, X5, #32

(679) 0x458db4 ADD	X4, X0, X1,LSL #5

(679) 0x458db8 UBFM	X1, X8, #5, #63

(679) 0x458dbc ADD	X5, X1, #1

(679) 0x458dc0 ANDS	X8, X5, #0x7

(679) 0x458dc4 B.EQ	458e94

(679) 0x458dc8 CMP	X8, #1

(679) 0x458dcc B.EQ	458e78

(679) 0x458dd0 CMP	X8, #2

(679) 0x458dd4 B.EQ	458e64

(679) 0x458dd8 CMP	X8, #3

(679) 0x458ddc B.EQ	458e50

(679) 0x458de0 CMP	X8, #4

(679) 0x458de4 B.EQ	458e3c

(679) 0x458de8 CMP	X8, #5

(679) 0x458dec B.EQ	458e28

(679) 0x458df0 CMP	X8, #6

(679) 0x458df4 B.EQ	458e14

(679) 0x458df8 LDR	Q20, [X19, X13]

(679) 0x458dfc ADD	X0, X0, #32

(679) 0x458e00 LDUR	Q18, [X0, #496]

(679) 0x458e04 FMUL	V22.2D, V20.2D, V30.2D

(679) 0x458e08 FMUL	V0.2D, V18.2D, V30.2D

(679) 0x458e0c STR	Q22, [X19, X13]

(679) 0x458e10 STUR	Q0, [X0, #496]

(679) 0x458e14 LDP	Q1, Q26, [X0]

(679) 0x458e18 ADD	X0, X0, #32

(679) 0x458e1c FMUL	V27.2D, V1.2D, V30.2D

(679) 0x458e20 FMUL	V28.2D, V26.2D, V30.2D

(679) 0x458e24 STP	Q27, Q28, [X0, #2016]

(679) 0x458e28 LDP	Q7, Q25, [X0]

(679) 0x458e2c ADD	X0, X0, #32

(679) 0x458e30 FMUL	V5.2D, V7.2D, V30.2D

(679) 0x458e34 FMUL	V6.2D, V25.2D, V30.2D

(679) 0x458e38 STP	Q5, Q6, [X0, #2016]

(679) 0x458e3c LDP	Q3, Q4, [X0]

(679) 0x458e40 ADD	X0, X0, #32

(679) 0x458e44 FMUL	V2.2D, V3.2D, V30.2D

(679) 0x458e48 FMUL	V16.2D, V4.2D, V30.2D

(679) 0x458e4c STP	Q2, Q16, [X0, #2016]

(679) 0x458e50 LDP	Q19, Q24, [X0]

(679) 0x458e54 ADD	X0, X0, #32

(679) 0x458e58 FMUL	V23.2D, V19.2D, V30.2D

(679) 0x458e5c FMUL	V17.2D, V24.2D, V30.2D

(679) 0x458e60 STP	Q23, Q17, [X0, #2016]

(679) 0x458e64 LDP	Q21, Q29, [X0]

(679) 0x458e68 ADD	X0, X0, #32

(679) 0x458e6c FMUL	V20.2D, V21.2D, V30.2D

(679) 0x458e70 FMUL	V22.2D, V29.2D, V30.2D

(679) 0x458e74 STP	Q20, Q22, [X0, #2016]

(679) 0x458e78 LDP	Q18, Q0, [X0]

(679) 0x458e7c ADD	X0, X0, #32

(679) 0x458e80 FMUL	V1.2D, V18.2D, V30.2D

(679) 0x458e84 FMUL	V26.2D, V0.2D, V30.2D

(679) 0x458e88 STP	Q1, Q26, [X0, #2016]

(679) 0x458e8c CMP	X4, X0

(679) 0x458e90 B.EQ	458f34

(679) 0x458e94 STP	X26, X15, [SP, #144]

  (680) 0x458e98 ORR	X15, XZR, X0

  (680) 0x458e9c LDP	Q27, Q28, [X0]

  (680) 0x458ea0 LDP	Q7, Q25, [X0, #32]

  (680) 0x458ea4 LDP	Q5, Q6, [X0, #64]

  (680) 0x458ea8 LDP	Q23, Q21, [X0, #96]

  (680) 0x458eac LDP	Q29, Q20, [X0, #128]

  (680) 0x458eb0 FMUL	V3.2D, V27.2D, V30.2D

  (680) 0x458eb4 LDP	Q22, Q0, [X0, #160]

  (680) 0x458eb8 FMUL	V4.2D, V28.2D, V30.2D

  (680) 0x458ebc LDP	Q26, Q27, [X0, #192]

  (680) 0x458ec0 FMUL	V2.2D, V7.2D, V30.2D

  (680) 0x458ec4 LDP	Q1, Q28, [X0, #224]

  (680) 0x458ec8 ADD	X0, X0, #256

  (680) 0x458ecc FMUL	V16.2D, V25.2D, V30.2D

  (680) 0x458ed0 FMUL	V19.2D, V5.2D, V30.2D

  (680) 0x458ed4 FMUL	V24.2D, V6.2D, V30.2D

  (680) 0x458ed8 FMUL	V17.2D, V23.2D, V30.2D

  (680) 0x458edc FMUL	V18.2D, V21.2D, V30.2D

  (680) 0x458ee0 FMUL	V7.2D, V29.2D, V30.2D

  (680) 0x458ee4 FMUL	V25.2D, V20.2D, V30.2D

  (680) 0x458ee8 STUR	Q19, [X0, #320]

  (680) 0x458eec FMUL	V5.2D, V22.2D, V30.2D

  (680) 0x458ef0 STUR	Q24, [X0, #336]

  (680) 0x458ef4 FMUL	V6.2D, V0.2D, V30.2D

  (680) 0x458ef8 STP	Q3, Q4, [X0, #1792]

  (680) 0x458efc FMUL	V3.2D, V26.2D, V30.2D

  (680) 0x458f00 FMUL	V4.2D, V27.2D, V30.2D

  (680) 0x458f04 STP	Q2, Q16, [X0, #1824]

  (680) 0x458f08 FMUL	V16.2D, V1.2D, V30.2D

  (680) 0x458f0c FMUL	V2.2D, V28.2D, V30.2D

  (680) 0x458f10 STP	Q17, Q18, [X0, #1888]

  (680) 0x458f14 STP	Q7, Q25, [X0, #1920]

  (680) 0x458f18 STP	Q5, Q6, [X0, #1952]

  (680) 0x458f1c STP	Q3, Q4, [X0, #1984]

  (680) 0x458f20 STUR	Q16, [X0, #480]

  (680) 0x458f24 STR	Q2, [X15, #240]

  (680) 0x458f28 CMP	X4, X0

  (680) 0x458f2c B.NE	458e98

(679) 0x458f30 LDP	X26, X15, [SP, #144]

(679) 0x458f34 AND	X0, X14, #0x0

(679) 0x458f38 ANDS	XZR, X14, #0x3

(679) 0x458f3c B.EQ	458f70

(679) 0x458f40 ADD	X3, X3, X0

(679) 0x458f44 SUB	X14, X14, X0

(679) 0x458f48 DUP	Z30.D, Z31.D[0]

(679) 0x458f4c WHILELO	P1.D, XZR, X14

(679) 0x458f50 ADD	X13, X19, X3,LSL #3

(679) 0x458f54 LD1D	{Z19.D}, P1/Z, [X19, X3,LSL #3]

(679) 0x458f58 MOVPRFX	Z24, Z30

(679) 0x458f5c FMUL	Z24.D, P1/M, Z24.D, Z19.D

(679) 0x458f60 ST1D	{Z24.D}, P1, [X13, MUL VL]

(679) 0x458f64 CNTD	X4, ALL

(679) 0x458f68 WHILELO	P2.D, X4, X14

(679) 0x458f6c B.NE	4595b8

(679) 0x458f70 LDR	X5, [SP, #128]

(679) 0x458f74 LDR	X1, [SP, #256]

(679) 0x458f78 ADD	X8, X5, #1

(679) 0x458f7c STR	X8, [SP, #128]

(679) 0x458f80 CMP	X1, X8

(679) 0x458f84 B.NE	4585a0

0x458f88 ORR	X0, XZR, X26

0x458f8c STR	X15, [SP, #104]

0x458f90 BL	524f40

0x458f94 LDR	X0, [SP, #104]

0x458f98 BL	524f40

0x458f9c ORR	X0, XZR, X23

0x458fa0 BL	524f40

0x458fa4 ORR	X0, XZR, X22

0x458fa8 LDP	X19, X20, [SP, #16]

0x458fac LDP	X21, X22, [SP, #32]

0x458fb0 LDP	X23, X24, [SP, #48]

0x458fb4 LDP	X25, X26, [SP, #64]

0x458fb8 LDP	X27, X28, [SP, #80]

0x458fbc LDP	X29, X30, [SP], #384

0x458fc0 B	524f40

  (688) 0x458fc4 STR	X3, [X26, X0]

  (688) 0x458fc8 ADD	X1, X1, #1

  (688) 0x458fcc LDR	X13, [X14]

  (688) 0x458fd0 CMP	X13, X1

  (688) 0x458fd4 B.GT	4589c0

(679) 0x458fd8 B	4589e0

  (687) 0x458fdc STR	X3, [X15, X0]

  (687) 0x458fe0 ADD	X1, X1, #1

  (687) 0x458fe4 LDR	X13, [X14]

  (687) 0x458fe8 CMP	X13, X1

  (687) 0x458fec B.GT	458a00

(679) 0x458ff0 B	458a20

  (684) 0x458ff4 ADD	X13, X5, #8

  (684) 0x458ff8 LDR	X6, [X16, X5]

  (684) 0x458ffc LDR	X17, [X16, X13]

  (684) 0x459000 CMP	X6, X17

  (684) 0x459004 B.GE	459194

  (684) 0x459008 SUB	X28, X17, X6

  (684) 0x45900c ANDS	X28, X28, #0x3

  (684) 0x459010 B.EQ	4590bc

  (684) 0x459014 CMP	X28, #1

  (684) 0x459018 B.EQ	459084

  (684) 0x45901c CMP	X28, #2

  (684) 0x459020 B.EQ	459054

  (684) 0x459024 LDR	X28, [X25, X6,LSL #3]

  (684) 0x459028 LDR	D27, [X20, X6,LSL #3]

  (684) 0x45902c ADD	X6, X6, #1

  (684) 0x459030 LDR	D0, [X21, X0,LSL #3]

  (684) 0x459034 LDR	X28, [X23, X28,LSL #3]

  (684) 0x459038 FMUL	D1, D0, D27

  (684) 0x45903c UBFM	X28, X28, #61, #60

  (684) 0x459040 LDR	D7, [X20, X28]

  (684) 0x459044 FADD	D29, D29, D1

  (684) 0x459048 FADD	D18, D18, D1

  (684) 0x45904c FADD	D2, D7, D1

  (684) 0x459050 STR	D2, [X20, X28]

  (684) 0x459054 LDR	X28, [X25, X6,LSL #3]

  (684) 0x459058 LDR	D24, [X20, X6,LSL #3]

  (684) 0x45905c ADD	X6, X6, #1

  (684) 0x459060 LDR	D25, [X21, X0,LSL #3]

  (684) 0x459064 LDR	X28, [X23, X28,LSL #3]

  (684) 0x459068 FMUL	D3, D25, D24

  (684) 0x45906c UBFM	X28, X28, #61, #60

  (684) 0x459070 LDR	D5, [X20, X28]

  (684) 0x459074 FADD	D29, D29, D3

  (684) 0x459078 FADD	D18, D18, D3

  (684) 0x45907c FADD	D4, D5, D3

  (684) 0x459080 STR	D4, [X20, X28]

  (684) 0x459084 LDR	X28, [X25, X6,LSL #3]

  (684) 0x459088 LDR	D16, [X20, X6,LSL #3]

  (684) 0x45908c ADD	X6, X6, #1

  (684) 0x459090 LDR	D6, [X21, X0,LSL #3]

  (684) 0x459094 LDR	X28, [X23, X28,LSL #3]

  (684) 0x459098 FMUL	D31, D6, D16

  (684) 0x45909c UBFM	X28, X28, #61, #60

  (684) 0x4590a0 LDR	D17, [X20, X28]

  (684) 0x4590a4 FADD	D29, D29, D31

  (684) 0x4590a8 FADD	D18, D18, D31

  (684) 0x4590ac FADD	D19, D17, D31

  (684) 0x4590b0 STR	D19, [X20, X28]

  (684) 0x4590b4 CMP	X6, X17

  (684) 0x4590b8 B.EQ	459194

  (684) 0x4590bc STP	X26, X22, [SP, #168]

  (684) 0x4590c0 STP	X9, X24, [SP, #184]

    (686) 0x4590c4 ADD	X22, X6, #1

    (686) 0x4590c8 ADD	X26, X6, #3

    (686) 0x4590cc ADD	X28, X22, #1

    (686) 0x4590d0 LDR	X24, [X25, X6,LSL #3]

    (686) 0x4590d4 LDR	D21, [X21, X0,LSL #3]

    (686) 0x4590d8 LDR	D20, [X20, X6,LSL #3]

    (686) 0x4590dc ADD	X6, X6, #4

    (686) 0x4590e0 LDR	X9, [X23, X24,LSL #3]

    (686) 0x4590e4 LDR	X24, [X25, X22,LSL #3]

    (686) 0x4590e8 FMUL	D22, D21, D20

    (686) 0x4590ec UBFM	X9, X9, #61, #60

    (686) 0x4590f0 LDR	D23, [X20, X9]

    (686) 0x4590f4 LDR	X24, [X23, X24,LSL #3]

    (686) 0x4590f8 FADD	D26, D29, D22

    (686) 0x4590fc FADD	D30, D18, D22

    (686) 0x459100 FADD	D31, D23, D22

    (686) 0x459104 UBFM	X24, X24, #61, #60

    (686) 0x459108 STR	D31, [X20, X9]

    (686) 0x45910c LDR	D0, [X20, X22,LSL #3]

    (686) 0x459110 LDR	D28, [X21, X0,LSL #3]

    (686) 0x459114 LDR	D27, [X20, X24]

    (686) 0x459118 LDR	X22, [X25, X28,LSL #3]

    (686) 0x45911c FMUL	D1, D28, D0

    (686) 0x459120 LDR	X9, [X25, X26,LSL #3]

    (686) 0x459124 LDR	X22, [X23, X22,LSL #3]

    (686) 0x459128 LDR	X9, [X23, X9,LSL #3]

    (686) 0x45912c FADD	D7, D27, D1

    (686) 0x459130 FADD	D2, D26, D1

    (686) 0x459134 FADD	D25, D30, D1

    (686) 0x459138 UBFM	X22, X22, #61, #60

    (686) 0x45913c UBFM	X9, X9, #61, #60

    (686) 0x459140 STR	D7, [X20, X24]

    (686) 0x459144 LDR	D24, [X21, X0,LSL #3]

    (686) 0x459148 LDR	D3, [X20, X28,LSL #3]

    (686) 0x45914c LDR	D5, [X20, X22]

    (686) 0x459150 FMUL	D4, D24, D3

    (686) 0x459154 FADD	D6, D5, D4

    (686) 0x459158 FADD	D17, D2, D4

    (686) 0x45915c FADD	D18, D25, D4

    (686) 0x459160 STR	D6, [X20, X22]

    (686) 0x459164 LDR	D29, [X20, X26,LSL #3]

    (686) 0x459168 LDR	D16, [X21, X0,LSL #3]

    (686) 0x45916c LDR	D19, [X20, X9]

    (686) 0x459170 FMUL	D31, D16, D29

    (686) 0x459174 FADD	D21, D19, D31

    (686) 0x459178 FADD	D29, D17, D31

    (686) 0x45917c FADD	D18, D18, D31

    (686) 0x459180 STR	D21, [X20, X9]

    (686) 0x459184 CMP	X6, X17

    (686) 0x459188 B.NE	4590c4

  (684) 0x45918c LDP	X26, X22, [SP, #168]

  (684) 0x459190 LDP	X9, X24, [SP, #184]

  (684) 0x459194 LDR	X17, [SP, #120]

  (684) 0x459198 LDR	X5, [X17, X5]

  (684) 0x45919c LDR	X28, [X17, X13]

  (684) 0x4591a0 CMP	X5, X28

  (684) 0x4591a4 B.GE	458a68

  (684) 0x4591a8 SUB	X13, X28, X5

  (684) 0x4591ac ANDS	X6, X13, #0x3

  (684) 0x4591b0 B.EQ	45925c

  (684) 0x4591b4 CMP	X6, #1

  (684) 0x4591b8 B.EQ	459224

  (684) 0x4591bc CMP	X6, #2

  (684) 0x4591c0 B.EQ	4591f4

  (684) 0x4591c4 LDR	X17, [X24, X5,LSL #3]

  (684) 0x4591c8 LDR	D22, [X19, X5,LSL #3]

  (684) 0x4591cc ADD	X5, X5, #1

  (684) 0x4591d0 LDR	D20, [X21, X0,LSL #3]

  (684) 0x4591d4 LDR	X13, [X22, X17,LSL #3]

  (684) 0x4591d8 FMUL	D23, D20, D22

  (684) 0x4591dc UBFM	X6, X13, #61, #60

  (684) 0x4591e0 LDR	D26, [X19, X6]

  (684) 0x4591e4 FADD	D29, D29, D23

  (684) 0x4591e8 FADD	D18, D18, D23

  (684) 0x4591ec FADD	D30, D26, D23

  (684) 0x4591f0 STR	D30, [X19, X6]

  (684) 0x4591f4 LDR	X17, [X24, X5,LSL #3]

  (684) 0x4591f8 LDR	D28, [X19, X5,LSL #3]

  (684) 0x4591fc ADD	X5, X5, #1

  (684) 0x459200 LDR	D31, [X21, X0,LSL #3]

  (684) 0x459204 LDR	X13, [X22, X17,LSL #3]

  (684) 0x459208 FMUL	D0, D31, D28

  (684) 0x45920c UBFM	X6, X13, #61, #60

  (684) 0x459210 LDR	D27, [X19, X6]

  (684) 0x459214 FADD	D29, D29, D0

  (684) 0x459218 FADD	D18, D18, D0

  (684) 0x45921c FADD	D1, D27, D0

  (684) 0x459220 STR	D1, [X19, X6]

  (684) 0x459224 LDR	X17, [X24, X5,LSL #3]

  (684) 0x459228 LDR	D2, [X19, X5,LSL #3]

  (684) 0x45922c ADD	X5, X5, #1

  (684) 0x459230 LDR	D7, [X21, X0,LSL #3]

  (684) 0x459234 LDR	X13, [X22, X17,LSL #3]

  (684) 0x459238 FMUL	D31, D7, D2

  (684) 0x45923c UBFM	X6, X13, #61, #60

  (684) 0x459240 LDR	D25, [X19, X6]

  (684) 0x459244 FADD	D29, D29, D31

  (684) 0x459248 FADD	D18, D18, D31

  (684) 0x45924c FADD	D24, D25, D31

  (684) 0x459250 STR	D24, [X19, X6]

  (684) 0x459254 CMP	X5, X28

  (684) 0x459258 B.EQ	458a68

  (684) 0x45925c STP	X26, X23, [SP, #168]

    (685) 0x459260 ADD	X13, X5, #1

    (685) 0x459264 ADD	X23, X5, #3

    (685) 0x459268 LDR	X26, [X24, X5,LSL #3]

    (685) 0x45926c LDR	D3, [X21, X0,LSL #3]

    (685) 0x459270 LDR	D5, [X19, X5,LSL #3]

    (685) 0x459274 ADD	X5, X5, #4

    (685) 0x459278 LDR	X17, [X22, X26,LSL #3]

    (685) 0x45927c ADD	X26, X13, #1

    (685) 0x459280 FMUL	D4, D3, D5

    (685) 0x459284 UBFM	X6, X17, #61, #60

    (685) 0x459288 LDR	X17, [X24, X13,LSL #3]

    (685) 0x45928c LDR	D6, [X19, X6]

    (685) 0x459290 LDR	X17, [X22, X17,LSL #3]

    (685) 0x459294 FADD	D17, D29, D4

    (685) 0x459298 FADD	D18, D18, D4

    (685) 0x45929c FADD	D16, D6, D4

    (685) 0x4592a0 UBFM	X17, X17, #61, #60

    (685) 0x4592a4 STR	D16, [X19, X6]

    (685) 0x4592a8 LDR	D29, [X21, X0,LSL #3]

    (685) 0x4592ac LDR	D19, [X19, X13,LSL #3]

    (685) 0x4592b0 LDR	D21, [X19, X17]

    (685) 0x4592b4 LDR	X13, [X24, X26,LSL #3]

    (685) 0x4592b8 FMUL	D20, D29, D19

    (685) 0x4592bc LDR	X6, [X24, X23,LSL #3]

    (685) 0x4592c0 LDR	X13, [X22, X13,LSL #3]

    (685) 0x4592c4 LDR	X6, [X22, X6,LSL #3]

    (685) 0x4592c8 FADD	D22, D21, D20

    (685) 0x4592cc FADD	D26, D18, D20

    (685) 0x4592d0 FADD	D23, D17, D20

    (685) 0x4592d4 UBFM	X13, X13, #61, #60

    (685) 0x4592d8 UBFM	X6, X6, #61, #60

    (685) 0x4592dc STR	D22, [X19, X17]

    (685) 0x4592e0 LDR	D31, [X19, X26,LSL #3]

    (685) 0x4592e4 LDR	D30, [X21, X0,LSL #3]

    (685) 0x4592e8 LDR	D28, [X19, X13]

    (685) 0x4592ec FMUL	D0, D30, D31

    (685) 0x4592f0 FADD	D27, D28, D0

    (685) 0x4592f4 FADD	D1, D23, D0

    (685) 0x4592f8 FADD	D2, D26, D0

    (685) 0x4592fc STR	D27, [X19, X13]

    (685) 0x459300 LDR	D7, [X21, X0,LSL #3]

    (685) 0x459304 LDR	D25, [X19, X23,LSL #3]

    (685) 0x459308 LDR	D24, [X19, X6]

    (685) 0x45930c FMUL	D31, D7, D25

    (685) 0x459310 FADD	D3, D24, D31

    (685) 0x459314 FADD	D29, D1, D31

    (685) 0x459318 FADD	D18, D2, D31

    (685) 0x45931c STR	D3, [X19, X6]

    (685) 0x459320 CMP	X5, X28

    (685) 0x459324 B.NE	459260

  (684) 0x459328 LDP	X26, X23, [SP, #168]

  (684) 0x45932c B	458a68

  (682) 0x459330 LDP	X14, X26, [SP, #312]

  (682) 0x459334 ADD	X28, X14, X9

  (682) 0x459338 LDR	X9, [X26, X9]

  (682) 0x45933c LDR	X14, [X28, #8]

  (682) 0x459340 ADD	X26, X9, X14

  (682) 0x459344 CMP	X9, X26

  (682) 0x459348 B.GE	458b04

  (682) 0x45934c LDR	X28, [SP, #136]

  (682) 0x459350 LDR	X14, [SP, #328]

  (682) 0x459354 LDR	X14, [X14, X28]

  (682) 0x459358 SUB	X28, X26, X9

  (682) 0x45935c ANDS	X28, X28, #0x3

  (682) 0x459360 B.EQ	4594e0

  (682) 0x459364 CMP	X28, #1

  (682) 0x459368 B.EQ	4593dc

  (682) 0x45936c CMP	X28, #2

  (682) 0x459370 B.EQ	4593a8

  (682) 0x459374 LDR	D4, [X17, X0,LSL #3]

  (682) 0x459378 LDR	D6, [X24, X9,LSL #3]

  (682) 0x45937c LDR	X28, [X14, X9,LSL #3]

  (682) 0x459380 FMUL	D17, D4, D6

  (682) 0x459384 TBNZ	X28, #63, 459650

  (682) 0x459388 LDR	X28, [X22, X28,LSL #3]

  (682) 0x45938c UBFM	X28, X28, #61, #60

  (682) 0x459390 LDR	D16, [X19, X28]

  (682) 0x459394 FADD	D19, D16, D17

  (682) 0x459398 STR	D19, [X19, X28]

  (682) 0x45939c FADD	D29, D29, D17

  (682) 0x4593a0 FADD	D18, D18, D17

  (682) 0x4593a4 ADD	X9, X9, #1

  (682) 0x4593a8 LDR	D22, [X17, X0,LSL #3]

  (682) 0x4593ac LDR	D23, [X24, X9,LSL #3]

  (682) 0x4593b0 LDR	X28, [X14, X9,LSL #3]

  (682) 0x4593b4 FMUL	D26, D22, D23

  (682) 0x4593b8 TBNZ	X28, #63, 4595fc

  (682) 0x4593bc LDR	X28, [X22, X28,LSL #3]

  (682) 0x4593c0 UBFM	X28, X28, #61, #60

  (682) 0x4593c4 LDR	D30, [X19, X28]

  (682) 0x4593c8 FADD	D31, D30, D26

  (682) 0x4593cc STR	D31, [X19, X28]

  (682) 0x4593d0 FADD	D29, D29, D26

  (682) 0x4593d4 FADD	D18, D18, D26

  (682) 0x4593d8 ADD	X9, X9, #1

  (682) 0x4593dc LDR	D27, [X17, X0,LSL #3]

  (682) 0x4593e0 LDR	D1, [X24, X9,LSL #3]

  (682) 0x4593e4 LDR	X28, [X14, X9,LSL #3]

  (682) 0x4593e8 FMUL	D31, D27, D1

  (682) 0x4593ec TBNZ	X28, #63, 4595e0

  (682) 0x4593f0 LDR	X28, [X22, X28,LSL #3]

  (682) 0x4593f4 UBFM	X28, X28, #61, #60

  (682) 0x4593f8 LDR	D2, [X19, X28]

  (682) 0x4593fc FADD	D7, D2, D31

  (682) 0x459400 STR	D7, [X19, X28]

  (682) 0x459404 ADD	X9, X9, #1

  (682) 0x459408 FADD	D29, D29, D31

  (682) 0x45940c FADD	D18, D18, D31

  (682) 0x459410 CMP	X26, X9

  (682) 0x459414 B.NE	4594e0

  (682) 0x459418 B	458b04

    (683) 0x45941c LDR	X28, [X22, X28,LSL #3]

    (683) 0x459420 ADD	X9, X9, #1

    (683) 0x459424 FADD	D29, D29, D4

    (683) 0x459428 FADD	D18, D18, D4

    (683) 0x45942c UBFM	X28, X28, #61, #60

    (683) 0x459430 LDR	D6, [X19, X28]

    (683) 0x459434 FADD	D17, D6, D4

    (683) 0x459438 STR	D17, [X19, X28]

    (683) 0x45943c LDR	D21, [X17, X0,LSL #3]

    (683) 0x459440 LDR	D20, [X24, X9,LSL #3]

    (683) 0x459444 LDR	X28, [X14, X9,LSL #3]

    (683) 0x459448 FMUL	D22, D21, D20

    (683) 0x45944c TBNZ	X28, #63, 45952c

    (683) 0x459450 LDR	X28, [X22, X28,LSL #3]

    (683) 0x459454 FADD	D1, D29, D22

    (683) 0x459458 FADD	D27, D18, D22

    (683) 0x45945c UBFM	X28, X28, #61, #60

    (683) 0x459460 LDR	D23, [X19, X28]

    (683) 0x459464 FADD	D26, D23, D22

    (683) 0x459468 STR	D26, [X19, X28]

    (683) 0x45946c ADD	X28, X9, #1

    (683) 0x459470 LDR	D0, [X17, X0,LSL #3]

    (683) 0x459474 LDR	D28, [X24, X28,LSL #3]

    (683) 0x459478 LDR	X28, [X14, X28,LSL #3]

    (683) 0x45947c FMUL	D7, D0, D28

    (683) 0x459480 TBNZ	X28, #63, 459564

    (683) 0x459484 LDR	X28, [X22, X28,LSL #3]

    (683) 0x459488 FADD	D4, D1, D7

    (683) 0x45948c FADD	D6, D27, D7

    (683) 0x459490 UBFM	X28, X28, #61, #60

    (683) 0x459494 LDR	D2, [X19, X28]

    (683) 0x459498 FADD	D25, D2, D7

    (683) 0x45949c STR	D25, [X19, X28]

    (683) 0x4594a0 ADD	X28, X9, #2

    (683) 0x4594a4 LDR	D5, [X17, X0,LSL #3]

    (683) 0x4594a8 LDR	D17, [X24, X28,LSL #3]

    (683) 0x4594ac LDR	X28, [X14, X28,LSL #3]

    (683) 0x4594b0 FMUL	D31, D5, D17

    (683) 0x4594b4 TBNZ	X28, #63, 45959c

    (683) 0x4594b8 LDR	X28, [X22, X28,LSL #3]

    (683) 0x4594bc UBFM	X28, X28, #61, #60

    (683) 0x4594c0 LDR	D16, [X19, X28]

    (683) 0x4594c4 FADD	D19, D16, D31

    (683) 0x4594c8 STR	D19, [X19, X28]

    (683) 0x4594cc ADD	X9, X9, #3

    (683) 0x4594d0 FADD	D29, D4, D31

    (683) 0x4594d4 FADD	D18, D6, D31

    (683) 0x4594d8 CMP	X26, X9

    (683) 0x4594dc B.EQ	458b04

    (683) 0x4594e0 LDR	D3, [X17, X0,LSL #3]

    (683) 0x4594e4 LDR	D5, [X24, X9,LSL #3]

    (683) 0x4594e8 LDR	X28, [X14, X9,LSL #3]

    (683) 0x4594ec FMUL	D4, D3, D5

    (683) 0x4594f0 TBZ	X28, #63, 45941c

    (683) 0x4594f4 ORN	X28, XZR, X28

    (683) 0x4594f8 ADD	X9, X9, #1

    (683) 0x4594fc FADD	D29, D29, D4

    (683) 0x459500 LDR	X28, [X23, X28,LSL #3]

    (683) 0x459504 FADD	D18, D18, D4

    (683) 0x459508 UBFM	X28, X28, #61, #60

    (683) 0x45950c LDR	D16, [X20, X28]

    (683) 0x459510 FADD	D19, D16, D4

    (683) 0x459514 STR	D19, [X20, X28]

    (683) 0x459518 LDR	D21, [X17, X0,LSL #3]

    (683) 0x45951c LDR	D20, [X24, X9,LSL #3]

    (683) 0x459520 LDR	X28, [X14, X9,LSL #3]

    (683) 0x459524 FMUL	D22, D21, D20

    (683) 0x459528 TBZ	X28, #63, 459450

    (683) 0x45952c ORN	X28, XZR, X28

    (683) 0x459530 FADD	D1, D29, D22

    (683) 0x459534 FADD	D27, D18, D22

    (683) 0x459538 LDR	X28, [X23, X28,LSL #3]

    (683) 0x45953c UBFM	X28, X28, #61, #60

    (683) 0x459540 LDR	D30, [X20, X28]

    (683) 0x459544 FADD	D31, D30, D22

    (683) 0x459548 STR	D31, [X20, X28]

    (683) 0x45954c ADD	X28, X9, #1

    (683) 0x459550 LDR	D0, [X17, X0,LSL #3]

    (683) 0x459554 LDR	D28, [X24, X28,LSL #3]

    (683) 0x459558 LDR	X28, [X14, X28,LSL #3]

    (683) 0x45955c FMUL	D7, D0, D28

    (683) 0x459560 TBZ	X28, #63, 459484

    (683) 0x459564 ORN	X28, XZR, X28

    (683) 0x459568 FADD	D4, D1, D7

    (683) 0x45956c FADD	D6, D27, D7

    (683) 0x459570 LDR	X28, [X23, X28,LSL #3]

    (683) 0x459574 UBFM	X28, X28, #61, #60

    (683) 0x459578 LDR	D24, [X20, X28]

    (683) 0x45957c FADD	D3, D24, D7

    (683) 0x459580 STR	D3, [X20, X28]

    (683) 0x459584 ADD	X28, X9, #2

    (683) 0x459588 LDR	D5, [X17, X0,LSL #3]

    (683) 0x45958c LDR	D17, [X24, X28,LSL #3]

    (683) 0x459590 LDR	X28, [X14, X28,LSL #3]

    (683) 0x459594 FMUL	D31, D5, D17

    (683) 0x459598 TBZ	X28, #63, 4594b8

    (683) 0x45959c ORN	X28, XZR, X28

    (683) 0x4595a0 LDR	X28, [X23, X28,LSL #3]

    (683) 0x4595a4 UBFM	X28, X28, #61, #60

    (683) 0x4595a8 LDR	D21, [X20, X28]

    (683) 0x4595ac FADD	D29, D21, D31

    (683) 0x4595b0 STR	D29, [X20, X28]

    (683) 0x4595b4 B	4594cc

(679) 0x4595b8 LD1D	{Z23.D}, P2/Z, [X13, #1, MUL VL]

(679) 0x4595bc INCB	X13, ALL

(679) 0x4595c0 FMUL	Z30.D, P2/M, Z30.D, Z23.D

(679) 0x4595c4 ST1D	{Z30.D}, P2, [X13, MUL VL]

(679) 0x4595c8 B	458f70

(679) 0x4595cc LD1D	{Z29.D}, P0/Z, [X1, #1, MUL VL]

(679) 0x4595d0 INCB	X1, ALL

(679) 0x4595d4 FMUL	Z23.D, P0/M, Z23.D, Z29.D

(679) 0x4595d8 ST1D	{Z23.D}, P0, [X1, MUL VL]

(679) 0x4595dc B	458d78

  (682) 0x4595e0 ORN	X28, XZR, X28

  (682) 0x4595e4 LDR	X28, [X23, X28,LSL #3]

  (682) 0x4595e8 UBFM	X28, X28, #61, #60

  (682) 0x4595ec LDR	D25, [X20, X28]

  (682) 0x4595f0 FADD	D24, D25, D31

  (682) 0x4595f4 STR	D24, [X20, X28]

  (682) 0x4595f8 B	459404

  (682) 0x4595fc ORN	X28, XZR, X28

  (682) 0x459600 LDR	X28, [X23, X28,LSL #3]

  (682) 0x459604 UBFM	X28, X28, #61, #60

  (682) 0x459608 LDR	D28, [X20, X28]

  (682) 0x45960c FADD	D0, D28, D26

  (682) 0x459610 STR	D0, [X20, X28]

  (682) 0x459614 B	4593d0

(679) 0x459618 LDR	X5, [SP, #112]

(679) 0x45961c STP	X26, X15, [SP, #144]

(679) 0x459620 STP	X23, X28, [SP, #160]

(679) 0x459624 STP	X9, X6, [SP, #176]

(679) 0x459628 B	4588ec

(679) 0x45962c LDR	X5, [SP, #104]

(679) 0x459630 STP	X26, X15, [SP, #144]

(679) 0x459634 STP	X22, X28, [SP, #160]

(679) 0x459638 STP	X9, X6, [SP, #176]

(679) 0x45963c B	4586f8

(679) 0x459640 MOVZ	X13, #0

(679) 0x459644 B	458d48

(679) 0x459648 MOVZ	X0, #0

(679) 0x45964c B	458f40

  (682) 0x459650 ORN	X28, XZR, X28

  (682) 0x459654 LDR	X28, [X23, X28,LSL #3]

  (682) 0x459658 UBFM	X28, X28, #61, #60

  (682) 0x45965c LDR	D21, [X20, X28]

  (682) 0x459660 FADD	D20, D21, D17

  (682) 0x459664 STR	D20, [X20, X28]

  (682) 0x459668 B	45939c

0x45966c ORR	X0, XZR, X3

0x459670 STR	X5, [SP, #136]

0x459674 STR	X9, [SP, #152]

0x459678 STP	X2, X6, [SP, #184]

0x45967c STR	X10, [SP, #256]

0x459680 STP	X11, X12, [SP, #336]

0x459684 STP	X18, X7, [SP, #352]

0x459688 B	458454

0x45968c ORR	X0, XZR, X22

0x459690 MOVZ	X1, #8

0x459694 STR	X5, [SP, #136]

0x459698 STR	X4, [SP, #152]

0x45969c STP	X9, X3, [SP, #184]

0x4596a0 STR	X2, [SP, #256]

0x4596a4 STP	X6, X10, [SP, #336]

0x4596a8 STP	X11, X12, [SP, #352]

0x4596ac STP	X18, X7, [SP, #368]

0x4596b0 BL	524ea8

0x4596b4 LDR	X5, [SP, #136]

0x4596b8 ORR	X23, XZR, X0

0x4596bc LDP	X9, X3, [SP, #184]

0x4596c0 LDP	X6, X10, [SP, #336]

0x4596c4 LDP	X11, X12, [SP, #352]

0x4596c8 LDP	X18, X7, [SP, #368]

0x4596cc LDR	X4, [SP, #152]

0x4596d0 LDR	X2, [SP, #256]

0x4596d4 B	458430

0x4596d8 MOVZ	X1, #8

0x4596dc STR	X4, [SP, #136]

0x4596e0 STR	X9, [SP, #152]

0x4596e4 STP	X3, X2, [SP, #184]

0x4596e8 STR	X6, [SP, #256]

0x4596ec STP	X10, X11, [SP, #336]

0x4596f0 STP	X12, X18, [SP, #352]

0x4596f4 STR	X7, [SP, #368]

0x4596f8 BL	524ea8

0x4596fc LDR	X4, [SP, #136]

0x459700 ORR	X5, XZR, X0

0x459704 LDP	X3, X2, [SP, #184]

0x459708 LDP	X10, X11, [SP, #336]

0x45970c LDP	X12, X18, [SP, #352]

0x459710 LDR	X9, [SP, #152]

0x459714 LDR	X6, [SP, #256]

0x459718 LDR	X7, [SP, #368]

0x45971c B	458428

0x459720 ORR	X0, XZR, X2

0x459724 MOVZ	X1, #8

0x459728 STR	X2, [SP, #136]

0x45972c STR	X4, [SP, #152]

0x459730 STP	X9, X3, [SP, #184]

0x459734 STR	X6, [SP, #256]

0x459738 STP	X10, X11, [SP, #336]

0x45973c STP	X12, X18, [SP, #352]

0x459740 STR	X7, [SP, #368]

0x459744 BL	524ea8

0x459748 LDR	X2, [SP, #136]

0x45974c ORR	X26, XZR, X0

0x459750 LDP	X9, X3, [SP, #184]

0x459754 LDP	X10, X11, [SP, #336]

0x459758 LDP	X12, X18, [SP, #352]

0x45975c LDR	X4, [SP, #152]

0x459760 LDR	X6, [SP, #256]

0x459764 LDR	X7, [SP, #368]

0x459768 B	45841c

Coverage (%)	Name	Source Location	Module
►98.71+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.29+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:1884	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_multi_interp.c:1737-1881
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1737,1746-1881.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 32% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 59.50 to 18.54 cycles (3.21x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_CAlloc: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1757
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1754
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1751
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1748
hypre_Free: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1878
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1879
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1880
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1766
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1767
unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1761
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1763

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	244
nb uops	244
loop length	976
used w registers	1
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	142

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	30.50 cycles
front end	30.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	11.50	11.50	13.75	13.75	13.75	13.75	0.00	0.00	0.00	0.00	59.50	59.17	59.33	42.50	42.50
cycles	11.50	11.50	13.75	13.75	13.75	13.75	0.00	0.00	0.00	0.00	59.50	59.17	59.33	42.50	42.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	30.50
Dispatch	59.50
DIV/SQRT	5.00-20.00
Overall L1	59.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	32%
load	33%
store	33%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 59.50 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 45830c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #640]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X3, [X0, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X1, X11, [X0, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X19, [X0, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X3, [SP, #224]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X0, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X1, [SP, #232]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X0, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X7, [X0, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X4, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X0, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X5, [SP, #160]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [X0, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X7, [SP, #120]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [X0, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [X0, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X9, [SP, #296]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [X0, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X24, [X0, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X6, [X0, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X2, [X0, #272]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X12, [SP, #216]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X0, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X7, X18, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X3, [X0, #280]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X28, [X0, #296]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X8, [SP, #304]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [X0, #200]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X14, [X0, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [X0, #216]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X13, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [X0, #224]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X14, [SP, #208]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X0, #232]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X15, [SP, #200]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [X0, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X16, [SP, #288]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X23, [X0, #248]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X17, [SP, #280]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X26, [X0, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X21, [SP, #328]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [X0, #264]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X23, [SP, #312]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [X0, #312]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X26, [SP, #272]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X0, #328]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X30, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X27, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X1, [SP, #264]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X0, #320]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X5, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X13, X21, [X0, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X14, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X13, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X14, [SP, #248]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X15, X0, [X0, #56]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X15, [SP, #168]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBNZ X2, 459720 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1414>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X0, 4596d8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x13cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CBNZ X22, 45968c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X23, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X4, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45966c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X5, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X9, [SP, #152]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X2, X6, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X11, X12, [SP, #336]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X7, [SP, #352]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP X1, X14, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X4, X9, [SP, #336]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X3, X6, [SP, #352]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X8, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4584c0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
STR X13, [SP, #152]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X14, X15, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X9, X3, [SP, #336]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X6, [SP, #352]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410600 <@plt_start@+0x5e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X14, X15, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X3, [SP, #336]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X13, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X4, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X6, [SP, #352]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 458508 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
UBFM X2, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
STR X14, [SP, #152]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X15, X4, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X3, X6, [SP, #336]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410600 <@plt_start@+0x5e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X8, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X15, X4, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X3, X6, [SP, #336]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X14, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X9, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #152]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X13, X14, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X15, X4, [SP, #336]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X3, [SP, #352]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X6, [SP, #368]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 527b40 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 527b20 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X7, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X2, X15, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
SDIV X5, X10, X0	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
LDR X11, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X12, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X18, [X2, X12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
STR X12, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X1, X8, X5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X13, X10, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X5, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X18, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X9, X14, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CSEL X3, X13, X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X3, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 458f88 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X30, X25, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X17, X24, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X7, [SP, #368]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X2, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDP X9, X6, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X10, X11, [SP, #336]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X18, [SP, #352]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X30, X17, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X30, [SP, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X16, X17, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X4, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X3, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X0, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X15, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #384	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 524f40 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X5, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X9, [SP, #152]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X2, X6, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X11, X12, [SP, #336]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X7, [SP, #352]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 458454 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X5, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #152]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X9, X3, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X2, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X6, X10, [SP, #336]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X11, X12, [SP, #352]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X7, [SP, #368]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X9, X3, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X6, X10, [SP, #336]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X12, [SP, #352]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X18, X7, [SP, #368]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X4, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X2, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 458430 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X4, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X9, [SP, #152]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X3, X2, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X6, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X10, X11, [SP, #336]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X18, [SP, #352]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X7, [SP, #368]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X5, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X3, X2, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X11, [SP, #336]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X18, [SP, #352]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X9, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X6, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X7, [SP, #368]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 458428 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X2, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #152]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X9, X3, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X6, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X10, X11, [SP, #336]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X18, [SP, #352]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X7, [SP, #368]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X9, X3, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X10, X11, [SP, #336]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X18, [SP, #352]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X4, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X6, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X7, [SP, #368]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 45841c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_multi_interp.c:1737-1881
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1737,1746-1881.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_CAlloc: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1757
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1754
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1751
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1748
hypre_Free: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1878
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1879
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1880
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1766
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1767
unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1761
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1763

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	244
nb uops	244
loop length	976
used w registers	1
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	142

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	30.50 cycles
front end	30.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	11.50	11.50	13.75	13.75	13.75	13.75	0.00	0.00	0.00	0.00	59.50	59.17	59.33	42.50	42.50
cycles	11.50	11.50	13.75	13.75	13.75	13.75	0.00	0.00	0.00	0.00	59.50	59.17	59.33	42.50	42.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	30.50
Dispatch	59.50
DIV/SQRT	5.00-20.00
Overall L1	59.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	32%
load	33%
store	33%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 59.50 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 45830c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #640]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X3, [X0, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X1, X11, [X0, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X19, [X0, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X3, [SP, #224]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X0, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X1, [SP, #232]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X0, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X7, [X0, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X4, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X0, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X5, [SP, #160]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [X0, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X7, [SP, #120]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [X0, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [X0, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X9, [SP, #296]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [X0, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X24, [X0, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X6, [X0, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X2, [X0, #272]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X12, [SP, #216]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [X0, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X7, X18, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X3, [X0, #280]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X28, [X0, #296]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X8, [SP, #304]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [X0, #200]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X14, [X0, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [X0, #216]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X13, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [X0, #224]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X14, [SP, #208]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X0, #232]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X15, [SP, #200]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [X0, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X16, [SP, #288]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X23, [X0, #248]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X17, [SP, #280]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X26, [X0, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X21, [SP, #328]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [X0, #264]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X23, [SP, #312]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [X0, #312]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X26, [SP, #272]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X0, #328]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X30, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X27, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X1, [SP, #264]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X0, #320]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X5, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X13, X21, [X0, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X14, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X13, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X14, [SP, #248]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X15, X0, [X0, #56]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X15, [SP, #168]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBNZ X2, 459720 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1414>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X0, 4596d8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x13cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CBNZ X22, 45968c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X23, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X4, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45966c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X5, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X9, [SP, #152]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X2, X6, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X11, X12, [SP, #336]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X7, [SP, #352]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP X1, X14, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X4, X9, [SP, #336]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X3, X6, [SP, #352]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X8, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4584c0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
STR X13, [SP, #152]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X14, X15, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X9, X3, [SP, #336]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X6, [SP, #352]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410600 <@plt_start@+0x5e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X14, X15, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X3, [SP, #336]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X13, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X4, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X6, [SP, #352]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 458508 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
UBFM X2, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
STR X14, [SP, #152]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X15, X4, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X3, X6, [SP, #336]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410600 <@plt_start@+0x5e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X8, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X15, X4, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X3, X6, [SP, #336]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X14, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X9, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X8, [SP, #152]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X13, X14, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X15, X4, [SP, #336]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X3, [SP, #352]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X6, [SP, #368]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 527b40 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 527b20 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X7, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X2, X15, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
SDIV X5, X10, X0	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
LDR X11, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X12, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X18, [X2, X12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
STR X12, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL X1, X8, X5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X13, X10, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X5, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X18, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X9, X14, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CSEL X3, X13, X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X3, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 458f88 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X30, X25, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X17, X24, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X7, [SP, #368]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X2, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDP X9, X6, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X10, X11, [SP, #336]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X18, [SP, #352]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X30, X17, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X30, [SP, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X16, X17, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X4, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X3, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X0, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X15, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #384	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 524f40 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X5, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X9, [SP, #152]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X2, X6, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X11, X12, [SP, #336]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X7, [SP, #352]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 458454 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X5, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #152]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X9, X3, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X2, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X6, X10, [SP, #336]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X11, X12, [SP, #352]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X7, [SP, #368]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X9, X3, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X6, X10, [SP, #336]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X12, [SP, #352]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X18, X7, [SP, #368]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X4, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X2, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 458430 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X4, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X9, [SP, #152]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X3, X2, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X6, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X10, X11, [SP, #336]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X18, [SP, #352]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X7, [SP, #368]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X5, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X3, X2, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X10, X11, [SP, #336]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X18, [SP, #352]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X9, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X6, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X7, [SP, #368]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 458428 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X2, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #152]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X9, X3, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X6, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X10, X11, [SP, #336]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X18, [SP, #352]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X7, [SP, #368]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X9, X3, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X10, X11, [SP, #336]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X12, X18, [SP, #352]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X4, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X6, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X7, [SP, #368]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 45841c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass._omp_fn.10–	1.03	0.43
▼Loop 679 - par_multi_interp.c:1774-1876 - exec–	0.15	0.05
▼Loop 684 - par_multi_interp.c:1811-1837 - exec–	0.59	0.18
○Loop 686 - par_multi_interp.c:1816-1822 - exec	0.00	0.00
○Loop 685 - par_multi_interp.c:1824-1830 - exec	0.00	0.00
○Loop 688 - par_multi_interp.c:1799-1803 - exec	0.29	0.09
○Loop 690 - par_multi_interp.c:1782-1787 - exec	0.00	0.00
○Loop 680 - par_multi_interp.c:1875-1876 - exec	0.00	0.00
○Loop 689 - par_multi_interp.c:1792-1797 - exec	0.00	0.00
○Loop 687 - par_multi_interp.c:1805-1809 - exec	0.00	0.00
▼Loop 682 - par_multi_interp.c:1840-1867 - exec–	0.00	0.00
○Loop 683 - par_multi_interp.c:1851-1860 - exec	0.00	0.00
○Loop 681 - par_multi_interp.c:1873-1874 - exec	0.00	0.00

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ASM code

Vectorization

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CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code