OV - exec - Function hypre_BoomerAMGBuildMultipass._omp

	Function: hypre_BoomerAMGBuildMultipass._omp_fn.9	Module: exec	Source: par_multi_interp.c:1575-1663 [...]	Coverage (incl. loops): 0.20% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1575 - 1663

--------------------------------------------------------------------------------

1575: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa)

[...]

1584:            tmp_marker = NULL;

1585:            if (n_fine)

1586:            {   tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); }

1587:            tmp_marker_offd = NULL;

1588:            if (num_cols_offd)

1589:            {   tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); }

1590:            for (i=0; i < n_fine; i++)

1591:            {   tmp_marker[i] = -1; }

1592:            for (i=0; i < num_cols_offd; i++)

1593:            {   tmp_marker_offd[i] = -1; }

1594:

1595:            /* Compute this thread's range of pass_length */

1596:            my_thread_num = hypre_GetThreadNum();

1597:            num_threads = hypre_NumActiveThreads();

1598:            thread_start = pass_pointer[1] + (pass_length/num_threads)*my_thread_num;

1599:            if (my_thread_num == num_threads-1)

1600:            {  thread_stop = pass_pointer[1] + pass_length; }

1601:            else

1602:            {  thread_stop = pass_pointer[1] + (pass_length/num_threads)*(my_thread_num+1); }

1603:

1604:            /* determine P for points of pass 1, i.e. neighbors of coarse points */

1605:            for (i=thread_start; i < thread_stop; i++)

1606:            {

1607:              i1 = pass_array[i];

1608:              sum_C = 0;

1609:              sum_N = 0;

1610:              j_start = P_diag_start[i1];

1611:              j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1612:              for (j=j_start; j < j_end; j++)

1613:              {

1614:                 k1 = P_diag_pass[1][j];

1615:                 tmp_marker[C_array[k1]] = i1;

1616:              }

1617:              cnt = P_diag_i[i1];

1618:              for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1619:              {

1620:                 j1 = A_diag_j[j];

1621:                 if (CF_marker[j1] != -3 &&

1622:                    (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1623:                    sum_N += A_diag_data[j];

1624:                 if (j1 != -1 && tmp_marker[j1] == i1)

1625:                 {

1626:                    P_diag_data[cnt] = A_diag_data[j];

1627:                    P_diag_j[cnt++] = fine_to_coarse[j1];

1628:                    sum_C += A_diag_data[j];

1629:                 }

1630:              }

1631:              j_start = P_offd_start[i1];

1632:              j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1633:              for (j=j_start; j < j_end; j++)

1634:              {

1635:                 k1 = P_offd_pass[1][j];

1636:                 tmp_marker_offd[C_array_offd[k1]] = i1;

1637:              }

1638:              cnt_offd = P_offd_i[i1];

1639:              for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1640:              {

1641:                 if (col_offd_S_to_A)

1642:                     j1 = map_A_to_S[A_offd_j[j]];

1643:                 else

1644:                     j1 = A_offd_j[j];

1645:                 if (CF_marker_offd[j1] != -3 &&

1646:                   (num_functions == 1 || dof_func[i1] == dof_func_offd[j1]))

1647:                     sum_N += A_offd_data[j];

1648:                 if (j1 != -1 && tmp_marker_offd[j1] == i1)

1649:                 {

1650:                    P_offd_data[cnt_offd] = A_offd_data[j];

1651:                    P_offd_j[cnt_offd++] = map_S_to_new[j1];

1652:                    sum_C += A_offd_data[j];

1653:                 }

1654:              }

1655:              diagonal = A_diag_data[A_diag_i[i1]];

1656:              if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1657:              for (j=P_diag_i[i1]; j < cnt; j++)

1658:                 P_diag_data[j] *= alfa;

1659:              for (j=P_offd_i[i1]; j < cnt_offd; j++)

1660:                 P_offd_data[j] *= alfa;

1661:           }

1662:           hypre_TFree(tmp_marker);

1663:           hypre_TFree(tmp_marker_offd);

0x45976c STP	X29, X30, [SP, #736]!

0x459770 ADD	X29, SP, #0

0x459774 STP	X19, X20, [SP, #16]

0x459778 STP	X21, X22, [SP, #32]

0x45977c STP	X23, X24, [SP, #48]

0x459780 STP	X25, X26, [SP, #64]

0x459784 STP	X27, X28, [SP, #80]

0x459788 LDR	X4, [X0, #64]

0x45978c LDP	X27, X1, [X0, #16]

0x459790 LDP	X26, X7, [X0]

0x459794 LDP	X28, X10, [X0, #32]

0x459798 LDP	X25, X8, [X0, #48]

0x45979c LDP	X24, X3, [X0, #72]

0x4597a0 LDP	X9, X11, [X0, #88]

0x4597a4 LDP	X15, X12, [X0, #112]

0x4597a8 STR	X4, [SP, #160]

0x4597ac LDR	X5, [X0, #104]

0x4597b0 STR	X1, [SP, #200]

0x4597b4 LDR	X6, [X0, #128]

0x4597b8 LDR	X23, [X0, #136]

0x4597bc STR	X5, [SP, #104]

0x4597c0 LDR	X2, [X0, #232]

0x4597c4 STR	X6, [SP, #96]

0x4597c8 LDP	X13, X22, [X0, #144]

0x4597cc LDP	X21, X14, [X0, #160]

0x4597d0 LDR	X16, [X0, #176]

0x4597d4 STR	X14, [SP, #152]

0x4597d8 LDR	X17, [X0, #184]

0x4597dc LDR	X18, [X0, #192]

0x4597e0 STR	X16, [SP, #120]

0x4597e4 LDR	X19, [X0, #200]

0x4597e8 STR	X17, [SP, #144]

0x4597ec LDR	X20, [X0, #208]

0x4597f0 STR	X18, [SP, #136]

0x4597f4 LDR	X30, [X0, #216]

0x4597f8 STR	X19, [SP, #192]

0x4597fc LDR	X4, [X0, #224]

0x459800 STR	X20, [SP, #184]

0x459804 STR	X30, [SP, #176]

0x459808 LDP	X1, X0, [X0, #240]

0x45980c STR	X0, [SP, #112]

0x459810 STR	X1, [SP, #168]

0x459814 CBNZ	X2, 45a324

0x459818 CBNZ	X3, 459cb8

0x45981c MOVZ	X19, #0

0x459820 MOVZ	X20, #0

0x459824 STP	X4, X13, [SP, #208]

0x459828 STP	X12, X15, [SP, #224]

0x45982c STP	X11, X9, [SP, #240]

0x459830 STP	X8, X10, [SP, #256]

0x459834 STR	X7, [SP, #272]

0x459838 BL	527b40

0x45983c STR	X0, [SP, #128]

0x459840 BL	527b20

0x459844 LDP	X4, X1, [SP, #112]

0x459848 SUB	X18, X0, #1

0x45984c LDP	X6, X13, [SP, #208]

0x459850 SDIV	X0, X4, X0

0x459854 LDP	X12, X15, [SP, #224]

0x459858 LDP	X11, X9, [SP, #240]

0x45985c LDP	X8, X10, [SP, #256]

0x459860 LDR	X5, [SP, #128]

0x459864 LDR	X2, [X1, #8]

0x459868 LDR	X7, [SP, #272]

0x45986c MUL	X14, X5, X0

0x459870 CMP	X5, X18

0x459874 ADD	X3, X4, X2

0x459878 ADD	X18, X2, X14

0x45987c ADD	X4, X0, X14

0x459880 ADD	X1, X4, X2

0x459884 CSEL	X0, X3, X1, #0

0x459888 CMP	X0, X18

0x45988c STR	X0, [SP, #128]

0x459890 B.LE	45a16c

0x459894 HINT	#0

0x459898 HINT	#0

0x45989c HINT	#0

(691) 0x4598a0 LDR	X16, [SP, #152]

(691) 0x4598a4 LDR	X30, [SP, #144]

(691) 0x4598a8 LDR	X3, [X16, X18,LSL #3]

(691) 0x4598ac UBFM	X5, X3, #61, #60

(691) 0x4598b0 ADD	X16, X5, #8

(691) 0x4598b4 LDR	X0, [X30, X5]

(691) 0x4598b8 LDR	X17, [X11, X16]

(691) 0x4598bc LDR	X2, [X11, X5]

(691) 0x4598c0 ADD	X14, X0, X17

(691) 0x4598c4 SUB	X1, X14, X2

(691) 0x4598c8 CMP	X0, X1

(691) 0x4598cc B.GE	459a00

(691) 0x4598d0 LDR	X2, [SP, #192]

(691) 0x4598d4 UBFM	X17, X0, #61, #60

(691) 0x4598d8 LDR	X4, [X2, #8]

(691) 0x4598dc ADD	X30, X4, X1,LSL #3

(691) 0x4598e0 ADD	X0, X4, X0,LSL #3

(691) 0x4598e4 SUB	X14, X30, X0

(691) 0x4598e8 SUB	X1, X14, #8

(691) 0x4598ec UBFM	X2, X1, #3, #63

(691) 0x4598f0 ADD	X14, X2, #1

(691) 0x4598f4 ANDS	X1, X14, #0x7

(691) 0x4598f8 B.EQ	45998c

(691) 0x4598fc CMP	X1, #1

(691) 0x459900 B.EQ	459978

(691) 0x459904 CMP	X1, #2

(691) 0x459908 B.EQ	45996c

(691) 0x45990c CMP	X1, #3

(691) 0x459910 B.EQ	459960

(691) 0x459914 CMP	X1, #4

(691) 0x459918 B.EQ	459954

(691) 0x45991c CMP	X1, #5

(691) 0x459920 B.EQ	459948

(691) 0x459924 CMP	X1, #6

(691) 0x459928 B.EQ	45993c

(691) 0x45992c LDR	X17, [X4, X17]

(691) 0x459930 ADD	X0, X0, #8

(691) 0x459934 LDR	X4, [X22, X17,LSL #3]

(691) 0x459938 STR	X3, [X20, X4,LSL #3]

(691) 0x45993c LDR	X2, [X0], #8

(691) 0x459940 LDR	X14, [X22, X2,LSL #3]

(691) 0x459944 STR	X3, [X20, X14,LSL #3]

(691) 0x459948 LDR	X1, [X0], #8

(691) 0x45994c LDR	X17, [X22, X1,LSL #3]

(691) 0x459950 STR	X3, [X20, X17,LSL #3]

(691) 0x459954 LDR	X4, [X0], #8

(691) 0x459958 LDR	X2, [X22, X4,LSL #3]

(691) 0x45995c STR	X3, [X20, X2,LSL #3]

(691) 0x459960 LDR	X14, [X0], #8

(691) 0x459964 LDR	X1, [X22, X14,LSL #3]

(691) 0x459968 STR	X3, [X20, X1,LSL #3]

(691) 0x45996c LDR	X17, [X0], #8

(691) 0x459970 LDR	X4, [X22, X17,LSL #3]

(691) 0x459974 STR	X3, [X20, X4,LSL #3]

(691) 0x459978 LDR	X2, [X0], #8

(691) 0x45997c LDR	X14, [X22, X2,LSL #3]

(691) 0x459980 STR	X3, [X20, X14,LSL #3]

(691) 0x459984 CMP	X0, X30

(691) 0x459988 B.EQ	4599fc

  (700) 0x45998c ORR	X1, XZR, X0

  (700) 0x459990 ADD	X0, X0, #64

  (700) 0x459994 LDR	X17, [X1], #8

  (700) 0x459998 LDR	X4, [X22, X17,LSL #3]

  (700) 0x45999c STR	X3, [X20, X4,LSL #3]

  (700) 0x4599a0 LDUR	X2, [X0, #456]

  (700) 0x4599a4 LDR	X14, [X22, X2,LSL #3]

  (700) 0x4599a8 STR	X3, [X20, X14,LSL #3]

  (700) 0x4599ac LDR	X1, [X1, #8]

  (700) 0x4599b0 LDR	X17, [X22, X1,LSL #3]

  (700) 0x4599b4 STR	X3, [X20, X17,LSL #3]

  (700) 0x4599b8 LDUR	X4, [X0, #472]

  (700) 0x4599bc LDR	X2, [X22, X4,LSL #3]

  (700) 0x4599c0 STR	X3, [X20, X2,LSL #3]

  (700) 0x4599c4 LDUR	X14, [X0, #480]

  (700) 0x4599c8 LDR	X1, [X22, X14,LSL #3]

  (700) 0x4599cc STR	X3, [X20, X1,LSL #3]

  (700) 0x4599d0 LDUR	X17, [X0, #488]

  (700) 0x4599d4 LDR	X4, [X22, X17,LSL #3]

  (700) 0x4599d8 STR	X3, [X20, X4,LSL #3]

  (700) 0x4599dc LDUR	X2, [X0, #496]

  (700) 0x4599e0 LDR	X14, [X22, X2,LSL #3]

  (700) 0x4599e4 STR	X3, [X20, X14,LSL #3]

  (700) 0x4599e8 LDUR	X1, [X0, #504]

  (700) 0x4599ec LDR	X17, [X22, X1,LSL #3]

  (700) 0x4599f0 STR	X3, [X20, X17,LSL #3]

  (700) 0x4599f4 CMP	X0, X30

  (700) 0x4599f8 B.NE	45998c

(691) 0x4599fc LDR	X2, [X11, X5]

(691) 0x459a00 MOVI	D4, #0

(691) 0x459a04 ADD	X30, X10, X16

(691) 0x459a08 LDR	X0, [X10, X5]

(691) 0x459a0c LDR	X14, [X10, X16]

(691) 0x459a10 FMOV	D29, D4

(691) 0x459a14 ADD	X0, X0, #1

(691) 0x459a18 CMP	X0, X14

(691) 0x459a1c B.GE	459ab8

(691) 0x459a20 CMP	X7, #1

(691) 0x459a24 B.EQ	45a194

(691) 0x459a28 ORR	X17, XZR, X19

(691) 0x459a2c LDR	X19, [SP, #168]

(691) 0x459a30 STP	X6, X7, [SP, #112]

(691) 0x459a34 HINT	#0

(691) 0x459a38 HINT	#0

(691) 0x459a3c HINT	#0

  (699) 0x459a40 LDR	X4, [X25, X0,LSL #3]

  (699) 0x459a44 UBFM	X1, X4, #61, #60

  (699) 0x459a48 LDR	X7, [X26, X1]

  (699) 0x459a4c CMN	X7, #3

  (699) 0x459a50 B.EQ	459a6c

  (699) 0x459a54 LDR	X6, [X27, X5]

  (699) 0x459a58 LDR	X7, [X27, X1]

  (699) 0x459a5c CMP	X6, X7

  (699) 0x459a60 B.NE	459a6c

  (699) 0x459a64 LDR	D23, [X28, X0,LSL #3]

  (699) 0x459a68 FADD	D4, D4, D23

  (699) 0x459a6c CMN	X4, #1

  (699) 0x459a70 B.EQ	459aa4

  (699) 0x459a74 LDR	X4, [X20, X1]

  (699) 0x459a78 CMP	X3, X4

  (699) 0x459a7c B.NE	459aa4

  (699) 0x459a80 LDR	D19, [X28, X0,LSL #3]

  (699) 0x459a84 UBFM	X14, X2, #61, #60

  (699) 0x459a88 ADD	X2, X2, #1

  (699) 0x459a8c LDR	X1, [X19, X1]

  (699) 0x459a90 LDR	X6, [SP, #104]

  (699) 0x459a94 FADD	D29, D29, D19

  (699) 0x459a98 STR	D19, [X9, X14]

  (699) 0x459a9c STR	X1, [X6, X14]

  (699) 0x459aa0 LDR	X14, [X30]

  (699) 0x459aa4 ADD	X0, X0, #1

  (699) 0x459aa8 CMP	X0, X14

  (699) 0x459aac B.LT	459a40

(691) 0x459ab0 LDP	X6, X7, [SP, #112]

(691) 0x459ab4 ORR	X19, XZR, X17

(691) 0x459ab8 LDR	X0, [SP, #136]

(691) 0x459abc LDR	X30, [X12, X16]

(691) 0x459ac0 LDR	X1, [X12, X5]

(691) 0x459ac4 LDR	X0, [X0, X5]

(691) 0x459ac8 ADD	X17, X0, X30

(691) 0x459acc SUB	X4, X17, X1

(691) 0x459ad0 CMP	X0, X4

(691) 0x459ad4 B.GE	459c08

(691) 0x459ad8 LDR	X14, [SP, #184]

(691) 0x459adc UBFM	X30, X0, #61, #60

(691) 0x459ae0 LDR	X17, [X14, #8]

(691) 0x459ae4 ADD	X4, X17, X4,LSL #3

(691) 0x459ae8 ADD	X0, X17, X0,LSL #3

(691) 0x459aec SUB	X1, X4, X0

(691) 0x459af0 SUB	X14, X1, #8

(691) 0x459af4 UBFM	X1, X14, #3, #63

(691) 0x459af8 ADD	X14, X1, #1

(691) 0x459afc ANDS	X1, X14, #0x7

(691) 0x459b00 B.EQ	459b94

(691) 0x459b04 CMP	X1, #1

(691) 0x459b08 B.EQ	459b80

(691) 0x459b0c CMP	X1, #2

(691) 0x459b10 B.EQ	459b74

(691) 0x459b14 CMP	X1, #3

(691) 0x459b18 B.EQ	459b68

(691) 0x459b1c CMP	X1, #4

(691) 0x459b20 B.EQ	459b5c

(691) 0x459b24 CMP	X1, #5

(691) 0x459b28 B.EQ	459b50

(691) 0x459b2c CMP	X1, #6

(691) 0x459b30 B.EQ	459b44

(691) 0x459b34 LDR	X30, [X17, X30]

(691) 0x459b38 ADD	X0, X0, #8

(691) 0x459b3c LDR	X17, [X21, X30,LSL #3]

(691) 0x459b40 STR	X3, [X19, X17,LSL #3]

(691) 0x459b44 LDR	X14, [X0], #8

(691) 0x459b48 LDR	X1, [X21, X14,LSL #3]

(691) 0x459b4c STR	X3, [X19, X1,LSL #3]

(691) 0x459b50 LDR	X30, [X0], #8

(691) 0x459b54 LDR	X17, [X21, X30,LSL #3]

(691) 0x459b58 STR	X3, [X19, X17,LSL #3]

(691) 0x459b5c LDR	X14, [X0], #8

(691) 0x459b60 LDR	X1, [X21, X14,LSL #3]

(691) 0x459b64 STR	X3, [X19, X1,LSL #3]

(691) 0x459b68 LDR	X30, [X0], #8

(691) 0x459b6c LDR	X17, [X21, X30,LSL #3]

(691) 0x459b70 STR	X3, [X19, X17,LSL #3]

(691) 0x459b74 LDR	X14, [X0], #8

(691) 0x459b78 LDR	X1, [X21, X14,LSL #3]

(691) 0x459b7c STR	X3, [X19, X1,LSL #3]

(691) 0x459b80 LDR	X30, [X0], #8

(691) 0x459b84 LDR	X17, [X21, X30,LSL #3]

(691) 0x459b88 STR	X3, [X19, X17,LSL #3]

(691) 0x459b8c CMP	X4, X0

(691) 0x459b90 B.EQ	459c04

  (697) 0x459b94 ORR	X1, XZR, X0

  (697) 0x459b98 ADD	X0, X0, #64

  (697) 0x459b9c LDR	X14, [X1], #8

  (697) 0x459ba0 LDR	X30, [X21, X14,LSL #3]

  (697) 0x459ba4 STR	X3, [X19, X30,LSL #3]

  (697) 0x459ba8 LDUR	X17, [X0, #456]

  (697) 0x459bac LDR	X14, [X21, X17,LSL #3]

  (697) 0x459bb0 STR	X3, [X19, X14,LSL #3]

  (697) 0x459bb4 LDR	X1, [X1, #8]

  (697) 0x459bb8 LDR	X30, [X21, X1,LSL #3]

  (697) 0x459bbc STR	X3, [X19, X30,LSL #3]

  (697) 0x459bc0 LDUR	X17, [X0, #472]

  (697) 0x459bc4 LDR	X14, [X21, X17,LSL #3]

  (697) 0x459bc8 STR	X3, [X19, X14,LSL #3]

  (697) 0x459bcc LDUR	X1, [X0, #480]

  (697) 0x459bd0 LDR	X30, [X21, X1,LSL #3]

  (697) 0x459bd4 STR	X3, [X19, X30,LSL #3]

  (697) 0x459bd8 LDUR	X17, [X0, #488]

  (697) 0x459bdc LDR	X14, [X21, X17,LSL #3]

  (697) 0x459be0 STR	X3, [X19, X14,LSL #3]

  (697) 0x459be4 LDUR	X1, [X0, #496]

  (697) 0x459be8 LDR	X30, [X21, X1,LSL #3]

  (697) 0x459bec STR	X3, [X19, X30,LSL #3]

  (697) 0x459bf0 LDUR	X17, [X0, #504]

  (697) 0x459bf4 LDR	X14, [X21, X17,LSL #3]

  (697) 0x459bf8 STR	X3, [X19, X14,LSL #3]

  (697) 0x459bfc CMP	X4, X0

  (697) 0x459c00 B.NE	459b94

(691) 0x459c04 LDR	X1, [X12, X5]

(691) 0x459c08 LDR	X4, [SP, #160]

(691) 0x459c0c LDR	X0, [X4, X5]

(691) 0x459c10 ADD	X17, X4, X16

(691) 0x459c14 LDR	X16, [X4, X16]

(691) 0x459c18 CMP	X0, X16

(691) 0x459c1c B.GE	45a29c

(691) 0x459c20 LDR	X30, [SP, #200]

(691) 0x459c24 CBZ	X30, 45a208

(691) 0x459c28 ORR	X30, XZR, X21

(691) 0x459c2c LDR	X21, [SP, #176]

(691) 0x459c30 STP	X9, X2, [SP, #112]

(691) 0x459c34 B	459c8c

  (696) 0x459c38 LDR	X2, [X27, X5]

  (696) 0x459c3c LDR	X9, [X13, X4]

  (696) 0x459c40 CMP	X2, X9

  (696) 0x459c44 B.EQ	459cac

  (696) 0x459c48 CMN	X14, #1

  (696) 0x459c4c B.EQ	459c80

  (696) 0x459c50 LDR	X14, [X19, X4]

  (696) 0x459c54 CMP	X3, X14

  (696) 0x459c58 B.NE	459c80

  (696) 0x459c5c LDR	D6, [X8, X0,LSL #3]

  (696) 0x459c60 UBFM	X16, X1, #61, #60

  (696) 0x459c64 ADD	X1, X1, #1

  (696) 0x459c68 LDR	X4, [X21, X4]

  (696) 0x459c6c LDR	X2, [SP, #96]

  (696) 0x459c70 FADD	D29, D29, D6

  (696) 0x459c74 STR	D6, [X15, X16]

  (696) 0x459c78 STR	X4, [X2, X16]

  (696) 0x459c7c LDR	X16, [X17]

  (696) 0x459c80 ADD	X0, X0, #1

  (696) 0x459c84 CMP	X0, X16

  (696) 0x459c88 B.GE	459d40

  (696) 0x459c8c LDR	X9, [X24, X0,LSL #3]

  (696) 0x459c90 LDR	X14, [X6, X9,LSL #3]

  (696) 0x459c94 UBFM	X4, X14, #61, #60

  (696) 0x459c98 LDR	X2, [X23, X4]

  (696) 0x459c9c CMN	X2, #3

  (696) 0x459ca0 B.EQ	459c48

  (696) 0x459ca4 CMP	X7, #1

  (696) 0x459ca8 B.NE	459c38

  (696) 0x459cac LDR	D7, [X8, X0,LSL #3]

  (696) 0x459cb0 FADD	D4, D4, D7

  (696) 0x459cb4 B	459c48

0x459cb8 MOVZ	X1, #8

0x459cbc ORR	X0, XZR, X3

0x459cc0 STR	X3, [SP, #128]

0x459cc4 STP	X4, X13, [SP, #208]

0x459cc8 MOVZ	X20, #0

0x459ccc STP	X12, X15, [SP, #224]

0x459cd0 STP	X11, X9, [SP, #240]

0x459cd4 STP	X8, X10, [SP, #256]

0x459cd8 STR	X7, [SP, #272]

0x459cdc BL	524ea8

0x459ce0 LDR	X5, [SP, #128]

0x459ce4 ORR	X19, XZR, X0

0x459ce8 LDP	X4, X13, [SP, #208]

0x459cec LDP	X12, X15, [SP, #224]

0x459cf0 LDP	X11, X9, [SP, #240]

0x459cf4 LDP	X8, X10, [SP, #256]

0x459cf8 LDR	X7, [SP, #272]

0x459cfc CMP	X5, #0

0x459d00 B.LE	459824

0x459d04 UBFM	X2, X5, #61, #60

0x459d08 MOVZ	W1, #255

0x459d0c STR	X4, [SP, #128]

0x459d10 ORR	X0, XZR, X19

0x459d14 STP	X13, X12, [SP, #208]

0x459d18 STP	X15, X11, [SP, #224]

0x459d1c STP	X9, X8, [SP, #240]

0x459d20 STP	X10, X7, [SP, #256]

0x459d24 BL	410600

0x459d28 LDR	X4, [SP, #128]

0x459d2c LDP	X13, X12, [SP, #208]

0x459d30 LDP	X15, X11, [SP, #224]

0x459d34 LDP	X9, X8, [SP, #240]

0x459d38 LDP	X10, X7, [SP, #256]

0x459d3c B	459824

(691) 0x459d40 LDP	X9, X2, [SP, #112]

(691) 0x459d44 ORR	X21, XZR, X30

(691) 0x459d48 LDR	X17, [X12, X5]

(691) 0x459d4c LDR	X3, [X10, X5]

(691) 0x459d50 LDR	D5, [X28, X3,LSL #3]

(691) 0x459d54 FMUL	D0, D29, D5

(691) 0x459d58 FCMP	D0, #0

(691) 0x459d5c B.EQ	459d68

(691) 0x459d60 FNEG	D1, D4

(691) 0x459d64 FDIV	D31, D1, D0

(691) 0x459d68 LDR	X4, [X11, X5]

(691) 0x459d6c CMP	X4, X2

(691) 0x459d70 B.GE	459f68

(691) 0x459d74 SUB	X2, X2, X4

(691) 0x459d78 SUB	X5, X2, #1

(691) 0x459d7c CMP	X5, #2

(691) 0x459d80 B.LS	45a314

(691) 0x459d84 UBFM	X30, X2, #2, #63

(691) 0x459d88 ADD	X0, X9, X4,LSL #3

(691) 0x459d8c DUP	V25.2D, V31.D[0]

(691) 0x459d90 UBFM	X14, X30, #59, #58

(691) 0x459d94 UBFM	X16, X4, #61, #60

(691) 0x459d98 SUB	X3, X14, #32

(691) 0x459d9c ADD	X5, X0, X30,LSL #5

(691) 0x459da0 UBFM	X30, X3, #5, #63

(691) 0x459da4 ADD	X14, X30, #1

(691) 0x459da8 ANDS	X3, X14, #0x7

(691) 0x459dac B.EQ	459e7c

(691) 0x459db0 CMP	X3, #1

(691) 0x459db4 B.EQ	459e60

(691) 0x459db8 CMP	X3, #2

(691) 0x459dbc B.EQ	459e4c

(691) 0x459dc0 CMP	X3, #3

(691) 0x459dc4 B.EQ	459e38

(691) 0x459dc8 CMP	X3, #4

(691) 0x459dcc B.EQ	459e24

(691) 0x459dd0 CMP	X3, #5

(691) 0x459dd4 B.EQ	459e10

(691) 0x459dd8 CMP	X3, #6

(691) 0x459ddc B.EQ	459dfc

(691) 0x459de0 LDR	Q2, [X9, X16]

(691) 0x459de4 ADD	X0, X0, #32

(691) 0x459de8 LDUR	Q3, [X0, #496]

(691) 0x459dec FMUL	V24.2D, V2.2D, V25.2D

(691) 0x459df0 FMUL	V26.2D, V3.2D, V25.2D

(691) 0x459df4 STR	Q24, [X9, X16]

(691) 0x459df8 STUR	Q26, [X0, #496]

(691) 0x459dfc LDP	Q27, Q28, [X0]

(691) 0x459e00 ADD	X0, X0, #32

(691) 0x459e04 FMUL	V30.2D, V27.2D, V25.2D

(691) 0x459e08 FMUL	V22.2D, V28.2D, V25.2D

(691) 0x459e0c STP	Q30, Q22, [X0, #2016]

(691) 0x459e10 LDP	Q4, Q21, [X0]

(691) 0x459e14 ADD	X0, X0, #32

(691) 0x459e18 FMUL	V29.2D, V4.2D, V25.2D

(691) 0x459e1c FMUL	V23.2D, V21.2D, V25.2D

(691) 0x459e20 STP	Q29, Q23, [X0, #2016]

(691) 0x459e24 LDP	Q19, Q7, [X0]

(691) 0x459e28 ADD	X0, X0, #32

(691) 0x459e2c FMUL	V6.2D, V19.2D, V25.2D

(691) 0x459e30 FMUL	V17.2D, V7.2D, V25.2D

(691) 0x459e34 STP	Q6, Q17, [X0, #2016]

(691) 0x459e38 LDP	Q16, Q20, [X0]

(691) 0x459e3c ADD	X0, X0, #32

(691) 0x459e40 FMUL	V18.2D, V16.2D, V25.2D

(691) 0x459e44 FMUL	V5.2D, V20.2D, V25.2D

(691) 0x459e48 STP	Q18, Q5, [X0, #2016]

(691) 0x459e4c LDP	Q0, Q1, [X0]

(691) 0x459e50 ADD	X0, X0, #32

(691) 0x459e54 FMUL	V2.2D, V0.2D, V25.2D

(691) 0x459e58 FMUL	V24.2D, V1.2D, V25.2D

(691) 0x459e5c STP	Q2, Q24, [X0, #2016]

(691) 0x459e60 LDP	Q3, Q26, [X0]

(691) 0x459e64 ADD	X0, X0, #32

(691) 0x459e68 FMUL	V27.2D, V3.2D, V25.2D

(691) 0x459e6c FMUL	V28.2D, V26.2D, V25.2D

(691) 0x459e70 STP	Q27, Q28, [X0, #2016]

(691) 0x459e74 CMP	X5, X0

(691) 0x459e78 B.EQ	459f1c

(691) 0x459e7c STP	X19, X6, [SP, #112]

  (693) 0x459e80 ORR	X19, XZR, X0

  (693) 0x459e84 LDP	Q30, Q22, [X0]

  (693) 0x459e88 LDP	Q4, Q21, [X0, #32]

  (693) 0x459e8c LDP	Q29, Q23, [X0, #64]

  (693) 0x459e90 LDP	Q18, Q5, [X0, #96]

  (693) 0x459e94 LDP	Q1, Q2, [X0, #128]

  (693) 0x459e98 FMUL	V19.2D, V30.2D, V25.2D

  (693) 0x459e9c LDP	Q27, Q28, [X0, #160]

  (693) 0x459ea0 FMUL	V17.2D, V22.2D, V25.2D

  (693) 0x459ea4 LDP	Q0, Q26, [X0, #192]

  (693) 0x459ea8 FMUL	V7.2D, V4.2D, V25.2D

  (693) 0x459eac LDP	Q30, Q24, [X0, #224]

  (693) 0x459eb0 ADD	X0, X0, #256

  (693) 0x459eb4 FMUL	V16.2D, V21.2D, V25.2D

  (693) 0x459eb8 FMUL	V20.2D, V29.2D, V25.2D

  (693) 0x459ebc FMUL	V6.2D, V23.2D, V25.2D

  (693) 0x459ec0 FMUL	V3.2D, V18.2D, V25.2D

  (693) 0x459ec4 FMUL	V22.2D, V5.2D, V25.2D

  (693) 0x459ec8 FMUL	V4.2D, V1.2D, V25.2D

  (693) 0x459ecc FMUL	V21.2D, V2.2D, V25.2D

  (693) 0x459ed0 STUR	Q20, [X0, #320]

  (693) 0x459ed4 FMUL	V29.2D, V27.2D, V25.2D

  (693) 0x459ed8 STUR	Q6, [X0, #336]

  (693) 0x459edc FMUL	V23.2D, V30.2D, V25.2D

  (693) 0x459ee0 STP	Q19, Q17, [X0, #1792]

  (693) 0x459ee4 FMUL	V19.2D, V28.2D, V25.2D

  (693) 0x459ee8 FMUL	V17.2D, V0.2D, V25.2D

  (693) 0x459eec STP	Q7, Q16, [X0, #1824]

  (693) 0x459ef0 FMUL	V7.2D, V26.2D, V25.2D

  (693) 0x459ef4 STUR	Q23, [X0, #480]

  (693) 0x459ef8 FMUL	V16.2D, V24.2D, V25.2D

  (693) 0x459efc STP	Q3, Q22, [X0, #1888]

  (693) 0x459f00 STP	Q4, Q21, [X0, #1920]

  (693) 0x459f04 STP	Q29, Q19, [X0, #1952]

  (693) 0x459f08 STP	Q17, Q7, [X0, #1984]

  (693) 0x459f0c STR	Q16, [X19, #240]

  (693) 0x459f10 CMP	X5, X0

  (693) 0x459f14 B.NE	459e80

(691) 0x459f18 LDP	X19, X6, [SP, #112]

(691) 0x459f1c AND	X0, X2, #0x0

(691) 0x459f20 ANDS	XZR, X2, #0x3

(691) 0x459f24 B.EQ	459f68

(691) 0x459f28 ADD	X4, X4, X0

(691) 0x459f2c SUB	X16, X2, X0

(691) 0x459f30 DUP	Z25.D, Z31.D[0]

(691) 0x459f34 WHILELO	P7.D, XZR, X16

(691) 0x459f38 ADD	X2, X9, X4,LSL #3

(691) 0x459f3c LD1D	{Z20.D}, P7/Z, [X9, X4,LSL #3]

(691) 0x459f40 MOVPRFX	Z6, Z25

(691) 0x459f44 FMUL	Z6.D, P7/M, Z6.D, Z20.D

(691) 0x459f48 ST1D	{Z6.D}, P7, [X2, MUL VL]

(691) 0x459f4c CNTD	X5, ALL

(691) 0x459f50 WHILELO	P0.D, X5, X16

(691) 0x459f54 B.EQ	459f68

(691) 0x459f58 LD1D	{Z18.D}, P0/Z, [X2, #1, MUL VL]

(691) 0x459f5c INCB	X2, ALL

(691) 0x459f60 FMUL	Z25.D, P0/M, Z25.D, Z18.D

(691) 0x459f64 ST1D	{Z25.D}, P0, [X2, MUL VL]

(691) 0x459f68 CMP	X1, X17

(691) 0x459f6c B.LE	45a15c

(691) 0x459f70 SUB	X1, X1, X17

(691) 0x459f74 SUB	X30, X1, #1

(691) 0x459f78 CMP	X30, #2

(691) 0x459f7c B.LS	45a31c

(691) 0x459f80 UBFM	X4, X1, #2, #63

(691) 0x459f84 ADD	X0, X15, X17,LSL #3

(691) 0x459f88 DUP	V30.2D, V31.D[0]

(691) 0x459f8c UBFM	X3, X4, #59, #58

(691) 0x459f90 UBFM	X16, X17, #61, #60

(691) 0x459f94 SUB	X5, X3, #32

(691) 0x459f98 ADD	X2, X0, X4,LSL #5

(691) 0x459f9c UBFM	X30, X5, #5, #63

(691) 0x459fa0 ADD	X14, X30, #1

(691) 0x459fa4 ANDS	X4, X14, #0x7

(691) 0x459fa8 B.EQ	45a078

(691) 0x459fac CMP	X4, #1

(691) 0x459fb0 B.EQ	45a05c

(691) 0x459fb4 CMP	X4, #2

(691) 0x459fb8 B.EQ	45a048

(691) 0x459fbc CMP	X4, #3

(691) 0x459fc0 B.EQ	45a034

(691) 0x459fc4 CMP	X4, #4

(691) 0x459fc8 B.EQ	45a020

(691) 0x459fcc CMP	X4, #5

(691) 0x459fd0 B.EQ	45a00c

(691) 0x459fd4 CMP	X4, #6

(691) 0x459fd8 B.EQ	459ff8

(691) 0x459fdc LDR	Q5, [X15, X16]

(691) 0x459fe0 ADD	X0, X0, #32

(691) 0x459fe4 LDUR	Q2, [X0, #496]

(691) 0x459fe8 FMUL	V1.2D, V5.2D, V30.2D

(691) 0x459fec FMUL	V27.2D, V2.2D, V30.2D

(691) 0x459ff0 STR	Q1, [X15, X16]

(691) 0x459ff4 STUR	Q27, [X0, #496]

(691) 0x459ff8 LDP	Q28, Q0, [X0]

(691) 0x459ffc ADD	X0, X0, #32

(691) 0x45a000 FMUL	V26.2D, V28.2D, V30.2D

(691) 0x45a004 FMUL	V24.2D, V0.2D, V30.2D

(691) 0x45a008 STP	Q26, Q24, [X0, #2016]

(691) 0x45a00c LDP	Q3, Q22, [X0]

(691) 0x45a010 ADD	X0, X0, #32

(691) 0x45a014 FMUL	V4.2D, V3.2D, V30.2D

(691) 0x45a018 FMUL	V21.2D, V22.2D, V30.2D

(691) 0x45a01c STP	Q4, Q21, [X0, #2016]

(691) 0x45a020 LDP	Q29, Q19, [X0]

(691) 0x45a024 ADD	X0, X0, #32

(691) 0x45a028 FMUL	V17.2D, V29.2D, V30.2D

(691) 0x45a02c FMUL	V7.2D, V19.2D, V30.2D

(691) 0x45a030 STP	Q17, Q7, [X0, #2016]

(691) 0x45a034 LDP	Q23, Q16, [X0]

(691) 0x45a038 ADD	X0, X0, #32

(691) 0x45a03c FMUL	V25.2D, V23.2D, V30.2D

(691) 0x45a040 FMUL	V20.2D, V16.2D, V30.2D

(691) 0x45a044 STP	Q25, Q20, [X0, #2016]

(691) 0x45a048 LDP	Q6, Q18, [X0]

(691) 0x45a04c ADD	X0, X0, #32

(691) 0x45a050 FMUL	V5.2D, V6.2D, V30.2D

(691) 0x45a054 FMUL	V1.2D, V18.2D, V30.2D

(691) 0x45a058 STP	Q5, Q1, [X0, #2016]

(691) 0x45a05c LDP	Q2, Q27, [X0]

(691) 0x45a060 ADD	X0, X0, #32

(691) 0x45a064 FMUL	V0.2D, V2.2D, V30.2D

(691) 0x45a068 FMUL	V28.2D, V27.2D, V30.2D

(691) 0x45a06c STP	Q0, Q28, [X0, #2016]

(691) 0x45a070 CMP	X0, X2

(691) 0x45a074 B.EQ	45a110

  (692) 0x45a078 LDP	Q26, Q24, [X0]

  (692) 0x45a07c ORR	X16, XZR, X0

  (692) 0x45a080 LDP	Q3, Q22, [X0, #32]

  (692) 0x45a084 LDP	Q4, Q29, [X0, #64]

  (692) 0x45a088 LDP	Q25, Q20, [X0, #96]

  (692) 0x45a08c LDP	Q27, Q0, [X0, #128]

  (692) 0x45a090 FMUL	V17.2D, V26.2D, V30.2D

  (692) 0x45a094 LDP	Q5, Q6, [X0, #160]

  (692) 0x45a098 FMUL	V7.2D, V24.2D, V30.2D

  (692) 0x45a09c LDP	Q28, Q26, [X0, #192]

  (692) 0x45a0a0 FMUL	V21.2D, V3.2D, V30.2D

  (692) 0x45a0a4 LDP	Q1, Q2, [X0, #224]

  (692) 0x45a0a8 ADD	X0, X0, #256

  (692) 0x45a0ac FMUL	V23.2D, V22.2D, V30.2D

  (692) 0x45a0b0 FMUL	V19.2D, V4.2D, V30.2D

  (692) 0x45a0b4 FMUL	V16.2D, V29.2D, V30.2D

  (692) 0x45a0b8 FMUL	V24.2D, V25.2D, V30.2D

  (692) 0x45a0bc FMUL	V18.2D, V20.2D, V30.2D

  (692) 0x45a0c0 FMUL	V22.2D, V27.2D, V30.2D

  (692) 0x45a0c4 FMUL	V29.2D, V0.2D, V30.2D

  (692) 0x45a0c8 STUR	Q19, [X0, #320]

  (692) 0x45a0cc FMUL	V3.2D, V28.2D, V30.2D

  (692) 0x45a0d0 STUR	Q16, [X0, #336]

  (692) 0x45a0d4 FMUL	V4.2D, V26.2D, V30.2D

  (692) 0x45a0d8 STP	Q17, Q7, [X0, #1792]

  (692) 0x45a0dc FMUL	V17.2D, V5.2D, V30.2D

  (692) 0x45a0e0 FMUL	V7.2D, V6.2D, V30.2D

  (692) 0x45a0e4 STP	Q21, Q23, [X0, #1824]

  (692) 0x45a0e8 FMUL	V21.2D, V1.2D, V30.2D

  (692) 0x45a0ec FMUL	V23.2D, V2.2D, V30.2D

  (692) 0x45a0f0 STP	Q24, Q18, [X0, #1888]

  (692) 0x45a0f4 STP	Q22, Q29, [X0, #1920]

  (692) 0x45a0f8 STP	Q17, Q7, [X0, #1952]

  (692) 0x45a0fc STP	Q3, Q4, [X0, #1984]

  (692) 0x45a100 STUR	Q21, [X0, #480]

  (692) 0x45a104 STR	Q23, [X16, #240]

  (692) 0x45a108 CMP	X0, X2

  (692) 0x45a10c B.NE	45a078

(691) 0x45a110 AND	X14, X1, #0x0

(691) 0x45a114 ANDS	XZR, X1, #0x3

(691) 0x45a118 B.EQ	45a15c

(691) 0x45a11c ADD	X17, X14, X17

(691) 0x45a120 SUB	X5, X1, X14

(691) 0x45a124 DUP	Z30.D, Z31.D[0]

(691) 0x45a128 WHILELO	P1.D, XZR, X5

(691) 0x45a12c ADD	X1, X15, X17,LSL #3

(691) 0x45a130 LD1D	{Z19.D}, P1/Z, [X15, X17,LSL #3]

(691) 0x45a134 MOVPRFX	Z16, Z30

(691) 0x45a138 FMUL	Z16.D, P1/M, Z16.D, Z19.D

(691) 0x45a13c ST1D	{Z16.D}, P1, [X1, MUL VL]

(691) 0x45a140 CNTD	X2, ALL

(691) 0x45a144 WHILELO	P2.D, X2, X5

(691) 0x45a148 B.EQ	45a15c

(691) 0x45a14c LD1D	{Z25.D}, P2/Z, [X1, #1, MUL VL]

(691) 0x45a150 INCB	X1, ALL

(691) 0x45a154 FMUL	Z30.D, P2/M, Z30.D, Z25.D

(691) 0x45a158 ST1D	{Z30.D}, P2, [X1, MUL VL]

(691) 0x45a15c LDR	X30, [SP, #128]

(691) 0x45a160 ADD	X18, X18, #1

(691) 0x45a164 CMP	X30, X18

(691) 0x45a168 B.NE	4598a0

0x45a16c ORR	X0, XZR, X20

0x45a170 BL	524f40

0x45a174 ORR	X0, XZR, X19

0x45a178 LDP	X21, X22, [SP, #32]

0x45a17c LDP	X19, X20, [SP, #16]

0x45a180 LDP	X23, X24, [SP, #48]

0x45a184 LDP	X25, X26, [SP, #64]

0x45a188 LDP	X27, X28, [SP, #80]

0x45a18c LDP	X29, X30, [SP], #288

0x45a190 B	524f40

(691) 0x45a194 LDR	X17, [SP, #168]

(691) 0x45a198 STR	X5, [SP, #112]

(691) 0x45a19c HINT	#0

  (698) 0x45a1a0 LDR	X1, [X25, X0,LSL #3]

  (698) 0x45a1a4 UBFM	X4, X1, #61, #60

  (698) 0x45a1a8 LDR	X5, [X26, X4]

  (698) 0x45a1ac CMN	X5, #3

  (698) 0x45a1b0 B.EQ	45a1bc

  (698) 0x45a1b4 LDR	D22, [X28, X0,LSL #3]

  (698) 0x45a1b8 FADD	D4, D4, D22

  (698) 0x45a1bc CMN	X1, #1

  (698) 0x45a1c0 B.EQ	45a1f4

  (698) 0x45a1c4 LDR	X1, [X20, X4]

  (698) 0x45a1c8 CMP	X3, X1

  (698) 0x45a1cc B.NE	45a1f4

  (698) 0x45a1d0 LDR	D21, [X28, X0,LSL #3]

  (698) 0x45a1d4 UBFM	X14, X2, #61, #60

  (698) 0x45a1d8 ADD	X2, X2, #1

  (698) 0x45a1dc LDR	X4, [X17, X4]

  (698) 0x45a1e0 LDR	X5, [SP, #104]

  (698) 0x45a1e4 FADD	D29, D29, D21

  (698) 0x45a1e8 STR	D21, [X9, X14]

  (698) 0x45a1ec STR	X4, [X5, X14]

  (698) 0x45a1f0 LDR	X14, [X30]

  (698) 0x45a1f4 ADD	X0, X0, #1

  (698) 0x45a1f8 CMP	X0, X14

  (698) 0x45a1fc B.LT	45a1a0

(691) 0x45a200 LDR	X5, [SP, #112]

(691) 0x45a204 B	459ab8

(691) 0x45a208 CMP	X7, #1

(691) 0x45a20c B.EQ	45a2a4

(691) 0x45a210 LDR	X30, [SP, #176]

(691) 0x45a214 ORR	X14, XZR, X6

(691) 0x45a218 STP	X7, X2, [SP, #112]

(691) 0x45a21c HINT	#0

  (695) 0x45a220 LDR	X6, [X24, X0,LSL #3]

  (695) 0x45a224 UBFM	X4, X6, #61, #60

  (695) 0x45a228 LDR	X7, [X23, X4]

  (695) 0x45a22c CMN	X7, #3

  (695) 0x45a230 B.EQ	45a24c

  (695) 0x45a234 LDR	X2, [X13, X4]

  (695) 0x45a238 LDR	X7, [X27, X5]

  (695) 0x45a23c CMP	X2, X7

  (695) 0x45a240 B.NE	45a24c

  (695) 0x45a244 LDR	D20, [X8, X0,LSL #3]

  (695) 0x45a248 FADD	D4, D4, D20

  (695) 0x45a24c CMN	X6, #1

  (695) 0x45a250 B.EQ	45a284

  (695) 0x45a254 LDR	X6, [X19, X4]

  (695) 0x45a258 CMP	X3, X6

  (695) 0x45a25c B.NE	45a284

  (695) 0x45a260 LDR	D18, [X8, X0,LSL #3]

  (695) 0x45a264 UBFM	X16, X1, #61, #60

  (695) 0x45a268 ADD	X1, X1, #1

  (695) 0x45a26c LDR	X4, [X30, X4]

  (695) 0x45a270 LDR	X2, [SP, #96]

  (695) 0x45a274 FADD	D29, D29, D18

  (695) 0x45a278 STR	D18, [X15, X16]

  (695) 0x45a27c STR	X4, [X2, X16]

  (695) 0x45a280 LDR	X16, [X17]

  (695) 0x45a284 ADD	X0, X0, #1

  (695) 0x45a288 CMP	X16, X0

  (695) 0x45a28c B.GT	45a220

(691) 0x45a290 LDP	X7, X2, [SP, #112]

(691) 0x45a294 ORR	X6, XZR, X14

(691) 0x45a298 B	459d48

(691) 0x45a29c ORR	X17, XZR, X1

(691) 0x45a2a0 B	459d4c

(691) 0x45a2a4 LDR	X30, [SP, #176]

(691) 0x45a2a8 STR	X2, [SP, #112]

  (694) 0x45a2ac LDR	X4, [X24, X0,LSL #3]

  (694) 0x45a2b0 UBFM	X14, X4, #61, #60

  (694) 0x45a2b4 LDR	X2, [X23, X14]

  (694) 0x45a2b8 CMN	X2, #3

  (694) 0x45a2bc B.EQ	45a2c8

  (694) 0x45a2c0 LDR	D17, [X8, X0,LSL #3]

  (694) 0x45a2c4 FADD	D4, D4, D17

  (694) 0x45a2c8 CMN	X4, #1

  (694) 0x45a2cc B.EQ	45a300

  (694) 0x45a2d0 LDR	X4, [X19, X14]

  (694) 0x45a2d4 CMP	X3, X4

  (694) 0x45a2d8 B.NE	45a300

  (694) 0x45a2dc LDR	D16, [X8, X0,LSL #3]

  (694) 0x45a2e0 UBFM	X16, X1, #61, #60

  (694) 0x45a2e4 ADD	X1, X1, #1

  (694) 0x45a2e8 LDR	X14, [X30, X14]

  (694) 0x45a2ec LDR	X2, [SP, #96]

  (694) 0x45a2f0 FADD	D29, D29, D16

  (694) 0x45a2f4 STR	D16, [X15, X16]

  (694) 0x45a2f8 STR	X14, [X2, X16]

  (694) 0x45a2fc LDR	X16, [X17]

  (694) 0x45a300 ADD	X0, X0, #1

  (694) 0x45a304 CMP	X16, X0

  (694) 0x45a308 B.GT	45a2ac

(691) 0x45a30c LDR	X2, [SP, #112]

(691) 0x45a310 B	459d48

(691) 0x45a314 MOVZ	X0, #0

(691) 0x45a318 B	459f28

(691) 0x45a31c MOVZ	X14, #0

(691) 0x45a320 B	45a11c

0x45a324 ORR	X0, XZR, X2

0x45a328 MOVZ	X1, #8

0x45a32c STR	X2, [SP, #128]

0x45a330 STP	X4, X13, [SP, #208]

0x45a334 STP	X12, X15, [SP, #224]

0x45a338 STP	X11, X9, [SP, #240]

0x45a33c STP	X3, X8, [SP, #256]

0x45a340 STP	X10, X7, [SP, #272]

0x45a344 BL	524ea8

0x45a348 LDP	X3, X8, [SP, #256]

0x45a34c ORR	X20, XZR, X0

0x45a350 LDP	X4, X13, [SP, #208]

0x45a354 LDP	X12, X15, [SP, #224]

0x45a358 LDP	X11, X9, [SP, #240]

0x45a35c LDP	X10, X7, [SP, #272]

0x45a360 LDR	X2, [SP, #128]

0x45a364 CBNZ	X3, 45a39c

0x45a368 MOVZ	X19, #0

0x45a36c CMP	X2, #0

0x45a370 B.LE	459824

0x45a374 UBFM	X2, X2, #61, #60

0x45a378 MOVZ	W1, #255

0x45a37c STR	X4, [SP, #128]

0x45a380 MOVZ	X19, #0

0x45a384 STP	X13, X12, [SP, #208]

0x45a388 STP	X15, X11, [SP, #224]

0x45a38c STP	X9, X8, [SP, #240]

0x45a390 STP	X10, X7, [SP, #256]

0x45a394 BL	410600

0x45a398 B	459d28

0x45a39c MOVZ	X1, #8

0x45a3a0 ORR	X0, XZR, X3

0x45a3a4 STR	X3, [SP, #128]

0x45a3a8 STP	X2, X4, [SP, #208]

0x45a3ac STP	X13, X12, [SP, #224]

0x45a3b0 STP	X15, X11, [SP, #240]

0x45a3b4 STP	X9, X8, [SP, #256]

0x45a3b8 STP	X10, X7, [SP, #272]

0x45a3bc BL	524ea8

0x45a3c0 LDP	X6, X4, [SP, #208]

0x45a3c4 ORR	X19, XZR, X0

0x45a3c8 LDP	X13, X12, [SP, #224]

0x45a3cc LDP	X15, X11, [SP, #240]

0x45a3d0 LDP	X9, X8, [SP, #256]

0x45a3d4 LDP	X10, X7, [SP, #272]

0x45a3d8 LDR	X5, [SP, #128]

0x45a3dc CMP	X6, #0

0x45a3e0 B.LE	459cfc

0x45a3e4 UBFM	X2, X6, #61, #60

0x45a3e8 MOVZ	W1, #255

0x45a3ec STR	X4, [SP, #128]

0x45a3f0 ORR	X0, XZR, X20

0x45a3f4 STP	X13, X12, [SP, #208]

0x45a3f8 STP	X15, X11, [SP, #224]

0x45a3fc STP	X9, X5, [SP, #240]

0x45a400 STP	X8, X10, [SP, #256]

0x45a404 STR	X7, [SP, #272]

0x45a408 BL	410600

0x45a40c LDR	X4, [SP, #128]

0x45a410 LDP	X13, X12, [SP, #208]

0x45a414 LDP	X15, X11, [SP, #224]

0x45a418 LDP	X9, X5, [SP, #240]

0x45a41c LDP	X8, X10, [SP, #256]

0x45a420 LDR	X7, [SP, #272]

0x45a424 B	459cfc

Coverage (%)	Name	Source Location	Module
►98.99+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.01+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:1666	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_multi_interp.c:1575-1663
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1575,1584-1663.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 38% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 41.67 to 16.58 cycles (2.51x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_CAlloc: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1589
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1586
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1589
hypre_Free: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1662
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1596
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1597
unknown: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1593
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1591
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1591

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	186
nb uops	183
loop length	744
used w registers	1
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	102

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	22.88 cycles
front end	22.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	10.00	10.00	12.00	12.00	12.00	12.00	0.00	0.00	0.00	0.00	41.67	41.67	41.67	30.00	30.00
cycles	10.00	10.00	12.00	12.00	12.00	12.00	0.00	0.00	0.00	0.00	41.67	41.67	41.67	30.00	30.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	22.88
Dispatch	41.67
DIV/SQRT	5.00-20.00
Overall L1	41.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	38%
load	41%
store	40%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 41.67 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 45976c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #736]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X4, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X27, X1, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X7, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X10, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X8, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X3, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X11, [X0, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X15, X12, [X0, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X4, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X0, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X1, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [X0, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [X0, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X5, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X0, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X6, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X13, X22, [X0, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X14, [X0, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X16, [X0, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X14, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X0, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X0, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X16, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X19, [X0, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X17, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [X0, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X18, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [X0, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X0, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X20, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X1, X0, [X0, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X0, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X1, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBNZ X2, 45a324 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xbb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ X3, 459cb8 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x54c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X4, X13, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X15, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X11, X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X10, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X7, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 527b40 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 527b20 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X4, X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
SUB X18, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X6, X13, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
SDIV X0, X4, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
LDP X12, X15, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X8, X10, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X5, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X2, [X1, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X7, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MUL X14, X5, X0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
CMP X5, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X3, X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X18, X2, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSEL X0, X3, X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR X0, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LE 45a16c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xa00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X3, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X4, X13, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X12, X15, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X11, X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X10, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X7, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X4, X13, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X12, X15, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X8, X10, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X7, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 459824 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X4, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X13, X12, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X15, X11, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X7, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410600 <@plt_start@+0x5e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X13, X12, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X15, X11, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X10, X7, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 459824 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #288	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 524f40 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X2, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X4, X13, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X15, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X11, X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X3, X8, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X7, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X3, X8, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X4, X13, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X12, X15, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X10, X7, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X2, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBNZ X3, 45a39c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xc30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 459824 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X2, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X4, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X13, X12, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X15, X11, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X7, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410600 <@plt_start@+0x5e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 459d28 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X3, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X2, X4, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X13, X12, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X15, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X8, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X7, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X6, X4, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X13, X12, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X15, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X8, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X10, X7, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X5, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 459cfc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x590>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X4, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X13, X12, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X15, X11, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X5, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X10, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X7, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410600 <@plt_start@+0x5e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X13, X12, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X15, X11, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X5, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X8, X10, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X7, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 459cfc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x590>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_multi_interp.c:1575-1663
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1575,1584-1663.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_CAlloc: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1589
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1586
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1589
hypre_Free: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1662
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1596
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1597
unknown: 3 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1593
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1591
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1591

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	186
nb uops	183
loop length	744
used w registers	1
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	102

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	22.88 cycles
front end	22.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	10.00	10.00	12.00	12.00	12.00	12.00	0.00	0.00	0.00	0.00	41.67	41.67	41.67	30.00	30.00
cycles	10.00	10.00	12.00	12.00	12.00	12.00	0.00	0.00	0.00	0.00	41.67	41.67	41.67	30.00	30.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	22.88
Dispatch	41.67
DIV/SQRT	5.00-20.00
Overall L1	41.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	38%
load	41%
store	40%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 41.67 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 45976c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #736]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X4, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X27, X1, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X7, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X10, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X8, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X24, X3, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X11, [X0, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X15, X12, [X0, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STR X4, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X0, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X1, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [X0, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [X0, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X5, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X0, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X6, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X13, X22, [X0, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X14, [X0, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X16, [X0, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X14, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X0, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X0, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X16, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X19, [X0, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X17, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [X0, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X18, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [X0, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X0, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X20, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X1, X0, [X0, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X0, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X1, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBNZ X2, 45a324 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xbb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ X3, 459cb8 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x54c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X4, X13, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X15, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X11, X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X10, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X7, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 527b40 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 527b20 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X4, X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
SUB X18, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X6, X13, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
SDIV X0, X4, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
LDP X12, X15, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X8, X10, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X5, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X2, [X1, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X7, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MUL X14, X5, X0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
CMP X5, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X3, X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X18, X2, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSEL X0, X3, X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR X0, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LE 45a16c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xa00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X3, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X4, X13, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X12, X15, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X11, X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X10, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X7, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X4, X13, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X12, X15, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X8, X10, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X7, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 459824 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X4, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X13, X12, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X15, X11, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X7, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410600 <@plt_start@+0x5e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X13, X12, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X15, X11, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X10, X7, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 459824 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #288	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 524f40 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X2, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X4, X13, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X15, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X11, X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X3, X8, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X7, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X3, X8, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X4, X13, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X12, X15, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X10, X7, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X2, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CBNZ X3, 45a39c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xc30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 459824 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X2, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X4, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X13, X12, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X15, X11, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X7, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410600 <@plt_start@+0x5e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 459d28 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X3, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X2, X4, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X13, X12, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X15, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X8, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X7, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X6, X4, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X13, X12, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X15, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X8, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X10, X7, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X5, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 459cfc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x590>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X4, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X13, X12, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X15, X11, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X5, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X10, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X7, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410600 <@plt_start@+0x5e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X13, X12, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X15, X11, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X5, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X8, X10, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X7, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 459cfc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x590>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass._omp_fn.9–	0.20	0.08
▼Loop 691 - par_multi_interp.c:1593-1660 - exec–	0.05	0.02
○Loop 698 - par_multi_interp.c:1618-1628 - exec	0.15	0.05
○Loop 693 - par_multi_interp.c:1657-1658 - exec	0.00	0.00
○Loop 694 - par_multi_interp.c:1639-1652 - exec	0.00	0.00
○Loop 695 - par_multi_interp.c:1639-1652 - exec	0.00	0.00
○Loop 697 - par_multi_interp.c:1633-1636 - exec	0.00	0.00
○Loop 699 - par_multi_interp.c:1618-1628 - exec	0.00	0.00
○Loop 692 - par_multi_interp.c:1659-1660 - exec	0.00	0.00
○Loop 696 - par_multi_interp.c:1639-1652 - exec	0.00	0.00
○Loop 700 - par_multi_interp.c:1612-1615 - exec	0.00	0.00

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