OV - exec - Function hypre_BoomerAMGBuildMultipass

	Function: hypre_BoomerAMGBuildMultipass	Module: exec	Source: par_multi_interp.c:41-2061 [...]	Coverage (incl. loops): 0.22% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 41 - 2061

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41: {

42: #ifdef HYPRE_PROFILE

43:    hypre_profile_times[HYPRE_TIMER_ID_MULTIPASS_INTERP] -= hypre_MPI_Wtime();

44: #endif

45:

46:    MPI_Comm	           comm = hypre_ParCSRMatrixComm(A);

47:    hypre_ParCSRCommPkg    *comm_pkg = hypre_ParCSRMatrixCommPkg(S);

48:    hypre_ParCSRCommHandle *comm_handle;

49:    hypre_ParCSRCommPkg    *tmp_comm_pkg;

50:

51:    hypre_CSRMatrix *A_diag = hypre_ParCSRMatrixDiag(A);

52:    HYPRE_Real      *A_diag_data = hypre_CSRMatrixData(A_diag);

53:    HYPRE_Int             *A_diag_i = hypre_CSRMatrixI(A_diag);

54:    HYPRE_Int             *A_diag_j = hypre_CSRMatrixJ(A_diag);

55:

56:    hypre_CSRMatrix *A_offd = hypre_ParCSRMatrixOffd(A);

57:    HYPRE_Real      *A_offd_data = NULL;

58:    HYPRE_Int             *A_offd_i = hypre_CSRMatrixI(A_offd);

59:    HYPRE_Int             *A_offd_j = NULL;

60:    HYPRE_Int		   *col_map_offd_A = hypre_ParCSRMatrixColMapOffd(A);

61:    HYPRE_Int		    num_cols_offd_A = hypre_CSRMatrixNumCols(A_offd);

62:

63:    hypre_CSRMatrix *S_diag = hypre_ParCSRMatrixDiag(S);

64:    HYPRE_Int             *S_diag_i = hypre_CSRMatrixI(S_diag);

65:    HYPRE_Int             *S_diag_j = hypre_CSRMatrixJ(S_diag);

66:

67:    hypre_CSRMatrix *S_offd = hypre_ParCSRMatrixOffd(S);

68:    HYPRE_Int             *S_offd_i = hypre_CSRMatrixI(S_offd);

69:    HYPRE_Int             *S_offd_j = NULL;

70:    HYPRE_Int		   *col_map_offd_S = hypre_ParCSRMatrixColMapOffd(S);

71:    HYPRE_Int		    num_cols_offd_S = hypre_CSRMatrixNumCols(S_offd);

[...]

83:    HYPRE_Real      *P_offd_data = NULL;

84:    HYPRE_Int             *P_offd_i; /*at first counter of nonzero cols for each row,

85: 				finally will be pointer to start of row */

86:    HYPRE_Int             *P_offd_j = NULL;

87:

88:    HYPRE_Int              num_sends = 0;

89:    HYPRE_Int             *int_buf_data = NULL;

90:    HYPRE_Int             *send_map_start;

91:    HYPRE_Int             *send_map_elmt;

92:    HYPRE_Int             *send_procs;

93:    HYPRE_Int              num_recvs = 0;

94:    HYPRE_Int             *recv_vec_start;

95:    HYPRE_Int             *recv_procs;

96:    HYPRE_Int             *new_recv_vec_start = NULL;

97:    HYPRE_Int            **Pext_send_map_start = NULL;

98:    HYPRE_Int            **Pext_recv_vec_start = NULL;

99:    HYPRE_Int             *Pext_start = NULL;

100:    HYPRE_Int             *P_ncols = NULL;

101:

102:    HYPRE_Int             *CF_marker_offd = NULL;

103:    HYPRE_Int             *dof_func_offd = NULL;

104:    HYPRE_Int             *P_marker;

105:    HYPRE_Int             *P_marker_offd = NULL;

106:    HYPRE_Int             *C_array;

107:    HYPRE_Int             *C_array_offd = NULL;

108:    HYPRE_Int             *pass_array = NULL; /* contains points ordered according to pass */

[...]

114:    HYPRE_Int            **P_offd_pass = NULL;

115:    HYPRE_Int            **Pext_pass = NULL;

116:    HYPRE_Int            **new_elmts = NULL; /* new neighbors generated in each pass */

117:    HYPRE_Int             *new_counter = NULL; /* contains no. of new neighbors for

118: 					each pass */

119:    HYPRE_Int             *loc = NULL; /* contains locations for new neighbor

120: 			connections in int_o_buffer to avoid searching */

121:    HYPRE_Int             *Pext_i = NULL; /*contains P_diag_i and P_offd_i info for nonzero

122: 				cols of off proc neighbors */

123:    HYPRE_Int             *Pext_send_buffer = NULL; /* used to collect global nonzero

124: 				col ids in P_diag for send_map_elmts */

125:

126:    HYPRE_Int             *map_S_to_new = NULL;

127:    /*HYPRE_Int             *map_A_to_new = NULL;*/

128:    HYPRE_Int             *map_A_to_S = NULL;

129:    HYPRE_Int             *new_col_map_offd = NULL;

130:    HYPRE_Int             *col_map_offd_P = NULL;

131:    HYPRE_Int             *permute = NULL;

[...]

146:    HYPRE_Int             *fine_to_coarse = NULL;

147:    HYPRE_Int             *fine_to_coarse_offd = NULL;

148:

149:    HYPRE_Int             *assigned = NULL;

150:    HYPRE_Int             *assigned_offd = NULL;

[...]

185:    HYPRE_Int              local_index = -1;

186:    HYPRE_Int              new_num_cols_offd = 0;

[...]

194:    HYPRE_Int * max_num_threads = hypre_CTAlloc(HYPRE_Int, 1);

[...]

202:    max_num_threads[0] = hypre_NumThreads();

203:    cnt_nz_per_thread = hypre_CTAlloc(HYPRE_Int, max_num_threads[0]);

204:    cnt_nz_offd_per_thread = hypre_CTAlloc(HYPRE_Int, max_num_threads[0]);

205:    for(i=0; i < max_num_threads[0]; i++)

206:    {

207:        cnt_nz_offd_per_thread[i] = 0;

208:        cnt_nz_per_thread[i] = 0;

[...]

216:    hypre_MPI_Comm_size(comm,&num_procs);

217:    hypre_MPI_Comm_rank(comm,&my_id);

218:

219: #ifdef HYPRE_NO_GLOBAL_PARTITION

220:    my_first_cpt = num_cpts_global[0];

221:    /*   total_global_cpts = 0; */

222:     if (my_id == (num_procs -1)) total_global_cpts = num_cpts_global[1];

223:     hypre_MPI_Bcast(&total_global_cpts, 1, HYPRE_MPI_INT, num_procs-1, comm);

[...]

229:    if (!comm_pkg)

230:    {

231:       comm_pkg = hypre_ParCSRMatrixCommPkg(A);

232:       if (!comm_pkg)

233:       {

234:           hypre_MatvecCommPkgCreate(A);

235:

236:           comm_pkg = hypre_ParCSRMatrixCommPkg(A);

237:       }

238:       col_offd_S_to_A = NULL;

239:    }

240:

241:    if (col_offd_S_to_A)

[...]

252:    if (num_cols_offd_A)

253:    {

254:       A_offd_data = hypre_CSRMatrixData(A_offd);

255:       A_offd_j    = hypre_CSRMatrixJ(A_offd);

256:    }

257:

258:    if (num_cols_offd)

259:       S_offd_j    = hypre_CSRMatrixJ(S_offd);

260:

261:    n_fine = hypre_CSRMatrixNumRows(A_diag);

[...]

267:    if (n_fine) fine_to_coarse = hypre_CTAlloc(HYPRE_Int, n_fine);

268:

269:    n_coarse = 0;

270:    n_SF = 0;

271: #ifdef HYPRE_USING_OPENMP

272: #pragma omp parallel for private(i) reduction(+:n_coarse,n_SF ) HYPRE_SMP_SCHEDULE

[...]

278:    pass_array_size = n_fine-n_coarse-n_SF;

279:    if (pass_array_size) pass_array = hypre_CTAlloc(HYPRE_Int, pass_array_size);

280:    pass_pointer = hypre_CTAlloc(HYPRE_Int, max_num_passes+1);

281:    if (n_fine) assigned = hypre_CTAlloc(HYPRE_Int, n_fine);

282:    P_diag_i = hypre_CTAlloc(HYPRE_Int, n_fine+1);

283:    P_offd_i = hypre_CTAlloc(HYPRE_Int, n_fine+1);

284:    if (n_coarse) C_array = hypre_CTAlloc(HYPRE_Int, n_coarse);

285:

286:    if (num_cols_offd)

287:    {

288:       CF_marker_offd = hypre_CTAlloc(HYPRE_Int, num_cols_offd);

289:       if (num_functions > 1) dof_func_offd = hypre_CTAlloc(HYPRE_Int, num_cols_offd);

290:    }

291:

292:    if (num_procs > 1)

293:    {

294:       num_sends = hypre_ParCSRCommPkgNumSends(comm_pkg);

295:       send_procs = hypre_ParCSRCommPkgSendProcs(comm_pkg);

296:       send_map_start = hypre_ParCSRCommPkgSendMapStarts(comm_pkg);

297:       send_map_elmt = hypre_ParCSRCommPkgSendMapElmts(comm_pkg);

298:       num_recvs = hypre_ParCSRCommPkgNumRecvs(comm_pkg);

299:       recv_procs = hypre_ParCSRCommPkgRecvProcs(comm_pkg);

300:       recv_vec_start = hypre_ParCSRCommPkgRecvVecStarts(comm_pkg);

301:       if (send_map_start[num_sends])

302:          int_buf_data = hypre_CTAlloc(HYPRE_Int, send_map_start[num_sends]);

303:    }

304:

305:

306:    index = 0;

307:    for (i=0; i < num_sends; i++)

308:    {

309:       start = send_map_start[i];

310:       for (j = start; j < send_map_start[i+1]; j++)

311:          int_buf_data[index++] = CF_marker[send_map_elmt[j]];

312:    }

313:    if (num_procs > 1)

314:    {

315:       comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data,

316: 	 CF_marker_offd);

317:       hypre_ParCSRCommHandleDestroy(comm_handle);

318:    }

319:

320:    if (num_functions > 1)

321:    {

322:       index = 0;

323:       for (i=0; i < num_sends; i++)

324:       {

325:          start = send_map_start[i];

326:          for (j = start; j < send_map_start[i+1]; j++)

327: 	    int_buf_data[index++] = dof_func[send_map_elmt[j]];

328:       }

329:       if (num_procs > 1)

330:       {

331:          comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data,

332: 	    dof_func_offd);

333:          hypre_ParCSRCommHandleDestroy(comm_handle);

[...]

340: #pragma omp parallel for private(i) reduction(+:n_coarse_offd,n_SF_offd) HYPRE_SMP_SCHEDULE

[...]

346:    if (num_cols_offd)

347:    {

348:       assigned_offd = hypre_CTAlloc(HYPRE_Int, num_cols_offd);

349:       map_S_to_new = hypre_CTAlloc(HYPRE_Int, num_cols_offd);

350:       fine_to_coarse_offd = hypre_CTAlloc(HYPRE_Int, num_cols_offd);

351:       new_col_map_offd = hypre_CTAlloc(HYPRE_Int, n_coarse_offd);

[...]

381:    cnt = 0;

382:    p_cnt = pass_array_size-1;

383:    P_diag_i[0] = 0;

384:    P_offd_i[0] = 0;

385:    for (i = 0; i < n_fine; i++)

386:    {

387:       if (CF_marker[i] == 1)

388:       {

389:          fine_to_coarse[i] = cnt; /* this C point is assigned index

390:                                      coarse_counter on coarse grid,

391:                                      and in column of P */

392:          C_array[cnt++] = i;

393:          assigned[i] = 0;

394:          P_diag_i[i+1] = 1; /* one element in row i1 of P */

395:          P_offd_i[i+1] = 0;

396:       }

397:       else if (CF_marker[i] == -1)

398:       {

399:          pass_array[p_cnt--] = i;

400:          P_diag_i[i+1] = 0;

401:          P_offd_i[i+1] = 0;

402:          assigned[i] = -1;

403:          fine_to_coarse[i] = -1;

404:       }

405:       else

406:       {

407:          P_diag_i[i+1] = 0;

408:          P_offd_i[i+1] = 0;

409:          assigned[i] = -1;

410:          fine_to_coarse[i] = -1;

411:       }

412:    }

413:

414:    index = 0;

415:    for (i=0; i < num_sends; i++)

416:    {

417:       start = send_map_start[i];

418:       for (j = start; j < send_map_start[i+1]; j++)

419:       {

420:          int_buf_data[index] = fine_to_coarse[send_map_elmt[j]];

421:          if (int_buf_data[index] > -1)

422:             int_buf_data[index] += my_first_cpt;

423:          index++;

424:       }

425:    }

426:    if (num_procs > 1)

427:    {

428:       comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data,

429:          fine_to_coarse_offd);

430:       hypre_ParCSRCommHandleDestroy(comm_handle);

431:    }

432:

433:    new_recv_vec_start = hypre_CTAlloc(HYPRE_Int,num_recvs+1);

434:

435:    if (n_coarse_offd)

436:       C_array_offd = hypre_CTAlloc(HYPRE_Int,n_coarse_offd);

437:

438:    cnt = 0;

439:    new_recv_vec_start[0] = 0;

440:    for (j = 0; j < num_recvs; j++)

441:    {

442:       for (i = recv_vec_start[j]; i < recv_vec_start[j+1]; i++)

443:       {

444:          if (CF_marker_offd[i] == 1)

445:          {

446:             map_S_to_new[i] = cnt;

447:             C_array_offd[cnt] = i;

448:             new_col_map_offd[cnt++] = fine_to_coarse_offd[i];

449:             assigned_offd[i] = 0;

450:          }

451:          else

452:          {

453:             assigned_offd[i] = -1;

454:             map_S_to_new[i] = -1;

455:          }

456:       }

457:       new_recv_vec_start[j+1] = cnt;

458:    }

459:

460:    cnt = 0;

461:    hypre_TFree(fine_to_coarse_offd);

462:

463:    if (col_offd_S_to_A)

464:    {

465:       map_A_to_S = hypre_CTAlloc(HYPRE_Int,num_cols_offd_A);

466:       for (i=0; i < num_cols_offd_A; i++)

467:       {

468:         if (cnt < num_cols_offd && col_map_offd_A[i] == col_map_offd[cnt])

469:            map_A_to_S[i] = cnt++;

[...]

479:    pass_pointer[0] = 0;

480:    pass_pointer[1] = 0;

481:    total_nz = n_coarse;  /* accumulates total number of nonzeros in P_diag */

482:    total_nz_offd = 0; /* accumulates total number of nonzeros in P_offd */

483:

484:    cnt = 0;

485:    cnt_offd = 0;

486:    cnt_nz = 0;

487:    cnt_nz_offd = 0;

488:    for (i = pass_array_size-1; i > cnt-1; i--)

489:    {

490:      i1 = pass_array[i];

491:      for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

492:      {

493:         j1 = S_diag_j[j];

494:         if (CF_marker[j1] == 1)

495:         {

496:            P_diag_i[i1+1]++;

497:            cnt_nz++;

498:            assigned[i1] = 1;

499:         }

500:      }

501:      for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

502:      {

503:         j1 = S_offd_j[j];

504:         if (CF_marker_offd[j1] == 1)

505:         {

506:            P_offd_i[i1+1]++;

507:            cnt_nz_offd++;

508:            assigned[i1] = 1;

509:         }

510:      }

511:      if (assigned[i1] == 1)

512:      {

513:         pass_array[i++] = pass_array[cnt];

514:         pass_array[cnt++] = i1;

515:      }

516:    }

517:

518:    pass_pointer[2] = cnt;

[...]

525:    index = 0;

526:    for (i=0; i < num_sends; i++)

527:    {

528:       start = send_map_start[i];

529:       for (j = start; j < send_map_start[i+1]; j++)

530:       {    int_buf_data[index++] = assigned[send_map_elmt[j]]; }

531:    }

532:    if (num_procs > 1)

533:    {

534:       comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data,

535:                      assigned_offd);

536:       hypre_ParCSRCommHandleDestroy(comm_handle);

[...]

544:    pass = 2;

545:    local_pass_array_size = pass_array_size - cnt;

546:    hypre_MPI_Allreduce(&local_pass_array_size, &global_pass_array_size, 1, HYPRE_MPI_INT,

547:                        hypre_MPI_SUM, comm);

548:    while (global_pass_array_size && pass < max_num_passes)

549:    {

550:       for (i = pass_array_size-1; i > cnt-1; i--)

551:       {

552:          i1 = pass_array[i];

553:          no_break = 1;

554:          for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

555:          {

556:             j1 = S_diag_j[j];

557:             if (assigned[j1] == pass-1)

[...]

568:             for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

569:             {

570:                j1 = S_offd_j[j];

571:                if (assigned_offd[j1] == pass-1)

572:                {

573:                   pass_array[i++] = pass_array[cnt];

574:                   pass_array[cnt++] = i1;

575:                   assigned[i1] = pass;

576:                   break;

[...]

583:       pass++;

584:       pass_pointer[pass] = cnt;

585:

586:       local_pass_array_size = pass_array_size - cnt;

587:       hypre_MPI_Allreduce(&local_pass_array_size, &global_pass_array_size, 1, HYPRE_MPI_INT,

588:                           hypre_MPI_SUM, comm);

589:       index = 0;

590:       for (i=0; i < num_sends; i++)

591:       {

592:          start = send_map_start[i];

593:          for (j = start; j < send_map_start[i+1]; j++)

594:          {   int_buf_data[index++] = assigned[send_map_elmt[j]]; }

595:       }

596:       if (num_procs > 1)

597:       {

598:          comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data,

599:                        assigned_offd);

600:          hypre_ParCSRCommHandleDestroy(comm_handle);

601:       }

602:    }

603:

604:    hypre_TFree(int_buf_data);

605:

606:    num_passes = pass;

607:

608:    P_diag_pass = hypre_CTAlloc(HYPRE_Int*,num_passes); /* P_diag_pass[i] will contain

609:                                  all column numbers for points of pass i */

610:

611:    P_diag_pass[1] = hypre_CTAlloc(HYPRE_Int,cnt_nz);

612:

613:    P_diag_start = hypre_CTAlloc(HYPRE_Int, n_fine); /* P_diag_start[i] contains

614:            pointer to begin of column numbers in P_pass for point i,

615:            P_diag_i[i+1] contains number of columns for point i */

616:

617:    P_offd_start = hypre_CTAlloc(HYPRE_Int, n_fine);

618:

619:    if (num_procs > 1)

620:    {

621:       P_offd_pass = hypre_CTAlloc(HYPRE_Int*,num_passes);

622:

623:       if (cnt_nz_offd)

624:          P_offd_pass[1] = hypre_CTAlloc(HYPRE_Int,cnt_nz_offd);

625:       else

626:          P_offd_pass[1] = NULL;

627:

628:       new_elmts = hypre_CTAlloc(HYPRE_Int*,num_passes);

629:

630:       new_counter = hypre_CTAlloc(HYPRE_Int, num_passes+1);

631:

632:       new_counter[0] = 0;

633:       new_counter[1] = n_coarse_offd;

634:       new_num_cols_offd = n_coarse_offd;

635:

636:       new_elmts[0] = new_col_map_offd;

[...]

643:    cnt_nz = 0;

644:    cnt_nz_offd = 0;

645:    /* JBS: Possible candidate for threading */

646:    for (i=pass_pointer[1]; i < pass_pointer[2]; i++)

647:    {

648:       i1 = pass_array[i];

649:       P_diag_start[i1] = cnt_nz;

650:       P_offd_start[i1] = cnt_nz_offd;

651:       for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

652:       {

653:          j1 = S_diag_j[j];

654:          if (CF_marker[j1] == 1)

655:          {   P_diag_pass[1][cnt_nz++] = fine_to_coarse[j1]; }

656:       }

657:       for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

658:       {

659:          j1 = S_offd_j[j];

660:          if (CF_marker_offd[j1] == 1)

661:          {   P_offd_pass[1][cnt_nz_offd++] = map_S_to_new[j1]; }

662:       }

663:    }

664:

665:

666:    total_nz += cnt_nz;

667:    total_nz_offd += cnt_nz_offd;

668:

669:    if (num_procs > 1)

670:    {

671:       tmp_comm_pkg = hypre_CTAlloc(hypre_ParCSRCommPkg,1);

672:       Pext_send_map_start = hypre_CTAlloc(HYPRE_Int*,num_passes);

673:       Pext_recv_vec_start = hypre_CTAlloc(HYPRE_Int*,num_passes);

674:       Pext_pass = hypre_CTAlloc(HYPRE_Int*,num_passes);

675:       Pext_i = hypre_CTAlloc(HYPRE_Int, num_cols_offd+1);

676:       if (num_cols_offd) Pext_start = hypre_CTAlloc(HYPRE_Int, num_cols_offd);

677:       if (send_map_start[num_sends])

678:          P_ncols = hypre_CTAlloc(HYPRE_Int,send_map_start[num_sends]);

679: #ifdef HYPRE_USING_OPENMP

680: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

681: #endif

682:       for (i=0; i < num_cols_offd+1; i++)

683:       {   Pext_i[i] = 0; }

684: #ifdef HYPRE_USING_OPENMP

685: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

[...]

691:    old_Pext_send_size = 0;

692:    old_Pext_recv_size = 0;

693:    for (pass=2; pass < num_passes; pass++)

694:    {

695:

696:       if (num_procs > 1)

697:       {

698:          Pext_send_map_start[pass] = hypre_CTAlloc(HYPRE_Int, num_sends+1);

699:          Pext_recv_vec_start[pass] = hypre_CTAlloc(HYPRE_Int, num_recvs+1);

700:          Pext_send_size = 0;

701:          Pext_send_map_start[pass][0] = 0;

702:

703:          for (i=0; i < num_sends; i++)

704:          {

705: #ifdef HYPRE_USING_OPENMP

706: #pragma omp parallel for private(j,j1) reduction(+:Pext_send_size) HYPRE_SMP_SCHEDULE

[...]

717:             Pext_send_map_start[pass][i+1] = Pext_send_size;

718:          }

719:

720:          comm_handle = hypre_ParCSRCommHandleCreate (11, comm_pkg,

721:                                               P_ncols, &Pext_i[1]);

722:          hypre_ParCSRCommHandleDestroy(comm_handle);

723:

724:          if (Pext_send_size > old_Pext_send_size)

725:          {

726:             hypre_TFree(Pext_send_buffer);

727:             Pext_send_buffer = hypre_CTAlloc(HYPRE_Int, Pext_send_size);

728:          }

729:          old_Pext_send_size = Pext_send_size;

730:       }

731:

732:       cnt_offd = 0;

733:       for (i=0; i < num_sends; i++)

734:       {

735:          for (j=send_map_start[i]; j < send_map_start[i+1]; j++)

736:          {

737:             j1 = send_map_elmt[j];

738:             if (assigned[j1] == pass-1)

739:             {

740:                j_start = P_diag_start[j1];

741:                j_end = j_start+P_diag_i[j1+1];

742:                for (k=j_start; k < j_end; k++)

743:                {

744:                 Pext_send_buffer[cnt_offd++] = my_first_cpt

745:                     +P_diag_pass[pass-1][k];

746:                }

747:                j_start = P_offd_start[j1];

748:                j_end = j_start+P_offd_i[j1+1];

749:                for (k=j_start; k < j_end; k++)

750:                {

751:                  k1 = P_offd_pass[pass-1][k];

752:                  k3 = 0;

753:                  while (k3 < pass-1)

754:                  {

755:                     if (k1 < new_counter[k3+1])

756:                     {

757:                        k2 = k1-new_counter[k3];

758:                        Pext_send_buffer[cnt_offd++] = new_elmts[k3][k2];

759:                        break;

[...]

768:       if (num_procs > 1)

769:       {

770:          Pext_recv_size = 0;

771:          Pext_recv_vec_start[pass][0] = 0;

772:          cnt_offd = 0;

773:          for (i=0; i < num_recvs; i++)

774:          {

775:             for (j=recv_vec_start[i]; j<recv_vec_start[i+1]; j++)

776:             {

777:                if (assigned_offd[j] == pass-1)

778:                {

779:                   Pext_start[j] = cnt_offd;

780:                   cnt_offd += Pext_i[j+1];

781:                }

782:             }

783:             Pext_recv_size = cnt_offd;

784:             Pext_recv_vec_start[pass][i+1] = Pext_recv_size;

785:          }

786:

787:          hypre_ParCSRCommPkgComm(tmp_comm_pkg) = comm;

788:          hypre_ParCSRCommPkgNumSends(tmp_comm_pkg) = num_sends;

789:          hypre_ParCSRCommPkgSendProcs(tmp_comm_pkg) = send_procs;

790:          hypre_ParCSRCommPkgSendMapStarts(tmp_comm_pkg) =

791:             Pext_send_map_start[pass];

792:          hypre_ParCSRCommPkgNumRecvs(tmp_comm_pkg) = num_recvs;

793:          hypre_ParCSRCommPkgRecvProcs(tmp_comm_pkg) = recv_procs;

794:          hypre_ParCSRCommPkgRecvVecStarts(tmp_comm_pkg) =

795:             Pext_recv_vec_start[pass];

796:

797:          if (Pext_recv_size)

798:          {

799:             Pext_pass[pass] = hypre_CTAlloc(HYPRE_Int, Pext_recv_size);

800:             new_elmts[pass-1] = hypre_CTAlloc(HYPRE_Int,Pext_recv_size);

801:          }

802:          else

803:          {

804:             Pext_pass[pass] = NULL;

805:             new_elmts[pass-1] = NULL;

806:          }

807:

808:          comm_handle = hypre_ParCSRCommHandleCreate (11, tmp_comm_pkg,

809:             Pext_send_buffer, Pext_pass[pass]);

810:          hypre_ParCSRCommHandleDestroy(comm_handle);

811:

812:          if (Pext_recv_size > old_Pext_recv_size)

813:          {

814:             hypre_TFree(loc);

815:             loc = hypre_CTAlloc(HYPRE_Int,Pext_recv_size);

816:          }

817:          old_Pext_recv_size = Pext_recv_size;

818:       }

819:

820:       cnt_new = 0;

821:       cnt_offd = 0;

822:       /* JBS: Possible candidate for threading */

823:       for (i=0; i < num_recvs; i++)

824:       {

825:          for (j=recv_vec_start[i]; j < recv_vec_start[i+1]; j++)

826:          {

827:             if (assigned_offd[j] == pass-1)

828:             {

829:                for (j1 = cnt_offd; j1 < cnt_offd+Pext_i[j+1]; j1++)

830:                {

831:                   k1 = Pext_pass[pass][j1];

832:                   k2 = k1 - my_first_cpt;

833:                   if (k2 > -1 && k2 < n_coarse)

834:                   {  Pext_pass[pass][j1] = -k2-1; }

835:                   else

836:                   {

837:                      not_found = 1;

838:                      k3 = 0;

839:                      while (k3 < pass-1 && not_found)

840:                      {

841:                         k2 = hypre_BinarySearch(new_elmts[k3], k1,

842:                                 (new_counter[k3+1]-new_counter[k3]));

843:                         if (k2 > -1)

844:                         {

845:                             Pext_pass[pass][j1] = k2 + new_counter[k3];

846:                             not_found = 0;

847:                         }

848:                         else

849:                         {

850:                             k3++;

851:                         }

852:                      }

853:                      if (not_found)

854:                      {

855:                          new_elmts[pass-1][cnt_new] = Pext_pass[pass][j1];

856:                          loc[cnt_new++] = j1;

857:                      }

858:                   }

859:                }

860:                cnt_offd += Pext_i[j+1];

861:             }

862:          }

863:       }

864:

865:       if (cnt_new)

866:       {

867:          hypre_qsort2i(new_elmts[pass-1],loc,0,cnt_new-1);

868:          cnt = 0;

869:          local_index = new_counter[pass-1];

870:          Pext_pass[pass][loc[0]] = local_index;

871:

872:          for (i=1; i < cnt_new; i++)

873:          {

874:             if (new_elmts[pass-1][i] > new_elmts[pass-1][cnt])

875:             {

876:                new_elmts[pass-1][++cnt] = new_elmts[pass-1][i];

877:                local_index++;

878:             }

879:             Pext_pass[pass][loc[i]] = local_index;

880:          }

881:          new_counter[pass] = local_index+1;

882:       }

883:       else if (num_procs > 1)

884:          new_counter[pass] = new_counter[pass-1];

885:

886:       if (new_num_cols_offd < local_index+1)

887:       {    new_num_cols_offd = local_index+1; }

888:

889:       pass_length = pass_pointer[pass+1] - pass_pointer[pass];

890:       #ifdef HYPRE_USING_OPENMP

891:       #pragma omp parallel private(i,my_thread_num,num_threads,thread_start,thread_stop,cnt_nz,cnt_nz_offd,i1,j,j1,j_start,j_end,k1,k,P_marker,P_marker_offd)

[...]

1140:    hypre_TFree(loc);

1141:    hypre_TFree(P_ncols);

1142:    hypre_TFree(Pext_send_buffer);

1143:    hypre_TFree(new_recv_vec_start);

1144:    hypre_TFree(cnt_nz_per_thread);

1145:    hypre_TFree(cnt_nz_offd_per_thread);

1146:    hypre_TFree(max_num_threads);

1147:

1148:    P_diag_j = hypre_CTAlloc(HYPRE_Int,total_nz);

1149:    P_diag_data = hypre_CTAlloc(HYPRE_Real,total_nz);

1150:

1151:

1152:    if (total_nz_offd)

1153:    {

1154:       P_offd_j = hypre_CTAlloc(HYPRE_Int,total_nz_offd);

1155:       P_offd_data = hypre_CTAlloc(HYPRE_Real,total_nz_offd);

1156:    }

1157:

1158:    for (i=0; i < n_fine; i++)

1159:    {

1160:       P_diag_i[i+1] += P_diag_i[i];

1161:       P_offd_i[i+1] += P_offd_i[i];

[...]

1167: #pragma omp parallel for private(i,i1) HYPRE_SMP_SCHEDULE

[...]

1177:    if (weight_option) /*if this is set, weights are separated into

1178:                         negative and positive offdiagonals and accumulated

1179:                         accordingly */

1180:    {

1181:

1182:        pass_length = pass_pointer[2]-pass_pointer[1];

1183: #ifdef HYPRE_USING_OPENMP

1184: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,P_marker,P_marker_offd,i,i1,sum_C_pos,sum_C_neg,sum_N_pos,sum_N_neg,j_start,j_end,j,k1,cnt,j1,cnt_offd,diagonal,alfa,beta)

[...]

1304:       if (n_coarse) hypre_TFree(C_array);

1305:       hypre_TFree(C_array_offd);

1306:       hypre_TFree(P_diag_pass[1]);

1307:       if (num_procs > 1) hypre_TFree(P_offd_pass[1]);

1308:

1309:

1310:       for (pass = 2; pass < num_passes; pass++)

1311:       {

1312:

1313:          if (num_procs > 1)

1314:          {

1315:             Pext_send_size = Pext_send_map_start[pass][num_sends];

1316:             if (Pext_send_size > old_Pext_send_size)

1317:             {

1318:                hypre_TFree(Pext_send_data);

1319:                Pext_send_data = hypre_CTAlloc(HYPRE_Real, Pext_send_size);

1320:             }

1321:             old_Pext_send_size = Pext_send_size;

1322:

1323:             cnt_offd = 0;

1324:             for (i=0; i < num_sends; i++)

1325:             {

1326:                for (j=send_map_start[i]; j < send_map_start[i+1]; j++)

1327:                {

1328:                   j1 = send_map_elmt[j];

1329:                   if (assigned[j1] == pass-1)

1330:                   {

1331:                      j_start = P_diag_i[j1];

1332:                      j_end = P_diag_i[j1+1];

1333:                      for (k=j_start; k < j_end; k++)

1334:                      {   Pext_send_data[cnt_offd++] = P_diag_data[k]; }

1335:                      j_start = P_offd_i[j1];

1336:                      j_end = P_offd_i[j1+1];

1337:                      for (k=j_start; k < j_end; k++)

1338:                      {  Pext_send_data[cnt_offd++] = P_offd_data[k]; }

1339:                   }

1340:                }

1341:             }

1342:

1343:             hypre_ParCSRCommPkgNumSends(tmp_comm_pkg) = num_sends;

1344:             hypre_ParCSRCommPkgSendMapStarts(tmp_comm_pkg) =

1345:                 Pext_send_map_start[pass];

1346:             hypre_ParCSRCommPkgNumRecvs(tmp_comm_pkg) = num_recvs;

1347:             hypre_ParCSRCommPkgRecvVecStarts(tmp_comm_pkg) =

1348:                 Pext_recv_vec_start[pass];

1349:

1350:             Pext_recv_size = Pext_recv_vec_start[pass][num_recvs];

1351:

1352:             if (Pext_recv_size > old_Pext_recv_size)

1353:             {

1354:                hypre_TFree(Pext_data);

1355:                Pext_data = hypre_CTAlloc(HYPRE_Real, Pext_recv_size);

1356:             }

1357:             old_Pext_recv_size = Pext_recv_size;

1358:

1359:             comm_handle = hypre_ParCSRCommHandleCreate (1, tmp_comm_pkg,

1360:                 Pext_send_data, Pext_data);

1361:             hypre_ParCSRCommHandleDestroy(comm_handle);

1362:

1363:             hypre_TFree(Pext_send_map_start[pass]);

1364:             hypre_TFree(Pext_recv_vec_start[pass]);

1365:          }

1366:

1367:          pass_length = pass_pointer[pass+1]-pass_pointer[pass];

1368: #ifdef HYPRE_USING_OPENMP

1369: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,P_marker,P_marker_offd,i,i1,sum_C_neg,sum_C_pos,sum_N_neg,sum_N_pos,j_start,j_end,cnt,j,k1,cnt_offd,j1,k,alfa,beta,diagonal,C_array,C_array_offd)

[...]

1562:          hypre_TFree(P_diag_pass[pass]);

1563:          if (num_procs > 1)

1564:          {

1565:             hypre_TFree(P_offd_pass[pass]);

1566:             hypre_TFree(Pext_pass[pass]);

[...]

1575: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa)

[...]

1669:       if (n_coarse) hypre_TFree(C_array);

1670:       hypre_TFree(C_array_offd);

1671:       hypre_TFree(P_diag_pass[1]);

1672:       if (num_procs > 1) hypre_TFree(P_offd_pass[1]);

1673:

1674:       for (pass = 2; pass < num_passes; pass++)

1675:       {

1676:

1677:          if (num_procs > 1)

1678:          {

1679:             Pext_send_size = Pext_send_map_start[pass][num_sends];

1680:             if (Pext_send_size > old_Pext_send_size)

1681:             {

1682:                hypre_TFree(Pext_send_data);

1683:                Pext_send_data = hypre_CTAlloc(HYPRE_Real, Pext_send_size);

1684:             }

1685:             old_Pext_send_size = Pext_send_size;

1686:

1687:             cnt_offd = 0;

1688:             for (i=0; i < num_sends; i++)

1689:             {

1690:                for (j=send_map_start[i]; j < send_map_start[i+1]; j++)

1691:                {

1692:                   j1 = send_map_elmt[j];

1693:                   if (assigned[j1] == pass-1)

1694:                   {

1695:                      j_start = P_diag_i[j1];

1696:                      j_end = P_diag_i[j1+1];

1697:                      for (k=j_start; k < j_end; k++)

1698:                      {

1699:                         Pext_send_data[cnt_offd++] = P_diag_data[k];

1700:                      }

1701:                      j_start = P_offd_i[j1];

1702:                      j_end = P_offd_i[j1+1];

1703:                      for (k=j_start; k < j_end; k++)

1704:                      {

1705:                         Pext_send_data[cnt_offd++] = P_offd_data[k];

[...]

1711:             hypre_ParCSRCommPkgNumSends(tmp_comm_pkg) = num_sends;

1712:             hypre_ParCSRCommPkgSendMapStarts(tmp_comm_pkg) =

1713:                 Pext_send_map_start[pass];

1714:             hypre_ParCSRCommPkgNumRecvs(tmp_comm_pkg) = num_recvs;

1715:             hypre_ParCSRCommPkgRecvVecStarts(tmp_comm_pkg) =

1716:                 Pext_recv_vec_start[pass];

1717:

1718:             Pext_recv_size = Pext_recv_vec_start[pass][num_recvs];

1719:

1720:             if (Pext_recv_size > old_Pext_recv_size)

1721:             {

1722:                hypre_TFree(Pext_data);

1723:                Pext_data = hypre_CTAlloc(HYPRE_Real, Pext_recv_size);

1724:             }

1725:             old_Pext_recv_size = Pext_recv_size;

1726:

1727:             comm_handle = hypre_ParCSRCommHandleCreate (1, tmp_comm_pkg,

1728:                 Pext_send_data, Pext_data);

1729:             hypre_ParCSRCommHandleDestroy(comm_handle);

1730:

1731:             hypre_TFree(Pext_send_map_start[pass]);

1732:             hypre_TFree(Pext_recv_vec_start[pass]);

1733:          }

1734:

1735:          pass_length = pass_pointer[pass+1]-pass_pointer[pass];

1736: #ifdef HYPRE_USING_OPENMP

1737: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa,tmp_array,tmp_array_offd)

[...]

1884:          hypre_TFree(P_diag_pass[pass]);

1885:          if (num_procs > 1)

1886:          {

1887:             hypre_TFree(P_offd_pass[pass]);

1888:             hypre_TFree(Pext_pass[pass]);

1889:          }

1890:       }

1891:    }

1892:

1893:    hypre_TFree(CF_marker_offd);

1894:    hypre_TFree(Pext_send_map_start);

1895:    hypre_TFree(Pext_recv_vec_start);

1896:    hypre_TFree(dof_func_offd);

1897:    hypre_TFree(Pext_send_data);

1898:    hypre_TFree(Pext_data);

1899:    hypre_TFree(P_diag_pass);

1900:    hypre_TFree(P_offd_pass);

1901:    hypre_TFree(Pext_pass);

1902:    hypre_TFree(P_diag_start);

1903:    hypre_TFree(P_offd_start);

1904:    hypre_TFree(Pext_start);

1905:    hypre_TFree(Pext_i);

1906:    hypre_TFree(fine_to_coarse);

1907:    hypre_TFree(assigned);

1908:    hypre_TFree(assigned_offd);

1909:    hypre_TFree(pass_pointer);

1910:    hypre_TFree(pass_array);

1911:    hypre_TFree(map_S_to_new);

1912:    hypre_TFree(map_A_to_S);

1913:    if (num_procs > 1) hypre_TFree(tmp_comm_pkg);

1914:

1915:     P = hypre_ParCSRMatrixCreate(comm,

[...]

1921:                                 P_diag_i[n_fine],

1922:                                 P_offd_i[n_fine]);

1923:    P_diag = hypre_ParCSRMatrixDiag(P);

1924:    hypre_CSRMatrixData(P_diag) = P_diag_data;

1925:    hypre_CSRMatrixI(P_diag) = P_diag_i;

1926:    hypre_CSRMatrixJ(P_diag) = P_diag_j;

1927:    P_offd = hypre_ParCSRMatrixOffd(P);

1928:    hypre_CSRMatrixData(P_offd) = P_offd_data;

1929:    hypre_CSRMatrixI(P_offd) = P_offd_i;

1930:    hypre_CSRMatrixJ(P_offd) = P_offd_j;

1931:    hypre_ParCSRMatrixOwnsRowStarts(P) = 0;

1932:

1933:    /* Compress P, removing coefficients smaller than trunc_factor * Max

1934:       and/or keep yat most <P_max_elmts> per row absolutely maximal coefficients */

1935:

1936:    if (trunc_factor != 0.0 || P_max_elmts != 0)

1937:    {

1938:       hypre_BoomerAMGInterpTruncation(P, trunc_factor, P_max_elmts);

[...]

1944:       P_offd_j = hypre_CSRMatrixJ(P_offd);

1945:    }

1946:    P_offd_size = P_offd_i[n_fine];

1947:

1948:    num_cols_offd_P = 0;

1949:    if (P_offd_size)

1950:    {

1951:       if (new_num_cols_offd > num_cols_offd)

1952:       {   P_marker_offd = hypre_CTAlloc(HYPRE_Int,new_num_cols_offd); }

1953:       else

1954:       {   P_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); }

1955: #ifdef HYPRE_USING_OPENMP

1956: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

1957: #endif

1958:       for (i=0; i < new_num_cols_offd; i++)

1959:       {   P_marker_offd[i] = 0; }

1960:

1961:       num_cols_offd_P = 0;

1962:       for (i=0; i < P_offd_size; i++)

1963:       {

1964:          index = P_offd_j[i];

1965:          if (!P_marker_offd[index])

1966:          {

1967:             num_cols_offd_P++;

1968:             P_marker_offd[index] = 1;

1969:          }

1970:       }

1971:

1972:       col_map_offd_P = hypre_CTAlloc(HYPRE_Int,num_cols_offd_P);

1973:       permute = hypre_CTAlloc(HYPRE_Int, new_counter[num_passes-1]);

1974:

1975: #ifdef HYPRE_USING_OPENMP

1976: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

1977: #endif

1978:       for (i=0; i < new_counter[num_passes-1]; i++)

1979:          permute[i] = -1;

1980:

1981:       cnt = 0;

1982:       for (i=0; i < num_passes-1; i++)

1983:       {

1984:          for (j=new_counter[i]; j < new_counter[i+1]; j++)

1985:          {

1986:             if (P_marker_offd[j])

1987:             {

1988:                col_map_offd_P[cnt] = new_elmts[i][j-new_counter[i]];

1989:                permute[j] = col_map_offd_P[cnt++];

1990:             }

1991:          }

1992:       }

1993:

1994:       hypre_qsort0(col_map_offd_P,0,num_cols_offd_P-1);

1995:

1996: #ifdef HYPRE_USING_OPENMP

1997: #pragma omp parallel for private(i,k1) HYPRE_SMP_SCHEDULE

[...]

2007: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

2008: #endif

2009:       for (i=0; i < P_offd_size; i++)

2010:       {   P_offd_j[i] = permute[P_offd_j[i]]; }

2011:

2012:       hypre_TFree(P_marker_offd);

2013:    }

2014:    if (num_procs > 1)

2015:    {

2016:       for (i=0; i < num_passes-1; i++)

2017:          hypre_TFree(new_elmts[i]);

2018:    }

2019:    hypre_TFree(permute);

2020:    hypre_TFree(new_elmts);

2021:    hypre_TFree(new_counter);

2022:

2023:    if (num_cols_offd_P)

2024:    {

2025:         hypre_ParCSRMatrixColMapOffd(P) = col_map_offd_P;

2026:         hypre_CSRMatrixNumCols(P_offd) = num_cols_offd_P;

2027:    }

2028:

2029:    if (n_SF)

2030:    {

2031: #ifdef HYPRE_USING_OPENMP

2032: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

[...]

2038:    if (num_procs > 1)

2039:    {

2040:         hypre_MatvecCommPkgCreate(P);

2041:    }

2042:

2043:    *P_ptr = P;

[...]

2061: }

0x45adc0 SUB	SP, SP, #1168

0x45adc4 ORR	X8, XZR, X1

0x45adc8 ORR	X9, XZR, X0

0x45adcc MOVZ	X1, #8

0x45add0 STP	X29, X30, [SP]

0x45add4 ADD	X29, SP, #0

0x45add8 STP	X19, X20, [SP, #16]

0x45addc STP	X21, X22, [SP, #32]

0x45ade0 STP	X23, X24, [SP, #48]

0x45ade4 STP	X25, X26, [SP, #64]

0x45ade8 STP	X27, X28, [SP, #80]

0x45adec LDP	X20, X24, [X0, #56]

0x45adf0 LDP	X6, X22, [X2, #56]

0x45adf4 STR	X4, [SP, #432]

0x45adf8 LDR	X4, [X24]

0x45adfc STR	X3, [SP, #688]

0x45ae00 LDR	X3, [X20]

0x45ae04 STR	D15, [SP, #96]

0x45ae08 FMOV	D15, D0

0x45ae0c LDR	X10, [X22]

0x45ae10 STR	X8, [SP, #320]

0x45ae14 LDR	X11, [X9]

0x45ae18 STR	X5, [SP, #584]

0x45ae1c LDR	X12, [X20, #8]

0x45ae20 STR	X3, [SP, #600]

0x45ae24 STR	X4, [SP, #616]

0x45ae28 STR	X0, [SP, #680]

0x45ae2c MOVZ	X0, #1

0x45ae30 STR	X7, [SP, #728]

0x45ae34 LDP	X5, X7, [X6]

0x45ae38 STR	X11, [SP, #400]

0x45ae3c STR	X10, [SP, #480]

0x45ae40 STR	X5, [SP, #536]

0x45ae44 STR	X12, [SP, #608]

0x45ae48 STR	X7, [SP, #120]

0x45ae4c LDR	X13, [X22, #24]

0x45ae50 LDR	X14, [X20, #48]

0x45ae54 LDR	X19, [X2, #88]

0x45ae58 STR	X13, [SP, #184]

0x45ae5c LDR	X2, [X2, #112]

0x45ae60 STR	X14, [SP, #592]

0x45ae64 LDR	X23, [X24, #24]

0x45ae68 LDR	X21, [X9, #88]

0x45ae6c STR	X2, [SP, #344]

0x45ae70 BL	524ea8

0x45ae74 ORR	X26, XZR, X0

0x45ae78 STR	X0, [SP, #640]

0x45ae7c BL	527b00

0x45ae80 MOVZ	X1, #8

0x45ae84 STR	X0, [X26]

0x45ae88 BL	524ea8

0x45ae8c ORR	X15, XZR, X0

0x45ae90 LDR	X0, [X26]

0x45ae94 MOVZ	X1, #8

0x45ae98 STR	X15, [SP, #648]

0x45ae9c BL	524ea8

0x45aea0 LDR	X1, [X26]

0x45aea4 STR	X0, [SP, #656]

0x45aea8 LDR	X18, [SP, #120]

0x45aeac CMP	X1, #0

0x45aeb0 B.LE	45aedc

0x45aeb4 LDR	X16, [SP, #640]

0x45aeb8 MOVZ	X27, #0

(780) 0x45aebc LDR	X0, [SP, #656]

(780) 0x45aec0 LDR	X17, [SP, #648]

(780) 0x45aec4 STR	XZR, [X0, X27,LSL #3]

(780) 0x45aec8 STR	XZR, [X17, X27,LSL #3]

(780) 0x45aecc ADD	X27, X27, #1

(780) 0x45aed0 LDR	X28, [X16]

(780) 0x45aed4 CMP	X28, X27

(780) 0x45aed8 B.GT	45aebc

0x45aedc LDR	X26, [SP, #400]

0x45aee0 ADD	X1, SP, #816

0x45aee4 STR	X18, [SP, #120]

0x45aee8 ORR	X0, XZR, X26

0x45aeec BL	526dc0

0x45aef0 ADD	X1, SP, #808

0x45aef4 ORR	X0, XZR, X26

0x45aef8 BL	526df0

0x45aefc LDR	X8, [SP, #688]

0x45af00 LDR	X3, [SP, #816]

0x45af04 LDR	X6, [SP, #808]

0x45af08 LDR	X4, [X8]

0x45af0c SUB	X3, X3, #1

0x45af10 LDR	X9, [SP, #120]

0x45af14 CMP	X3, X6

0x45af18 STR	X4, [SP, #144]

0x45af1c B.NE	45af2c

0x45af20 LDR	X30, [SP, #688]

0x45af24 LDR	X5, [X30, #8]

0x45af28 STR	X5, [SP, #824]

0x45af2c ADRP	X7,

0x45af30 LDR	X4, [SP, #400]

0x45af34 MOVZ	X1, #1

0x45af38 ADD	X10, X7, #1288

0x45af3c ADD	X0, SP, #824

0x45af40 STR	X9, [SP, #120]

0x45af44 ORR	X2, XZR, X10

0x45af48 STR	X10, [SP, #160]

0x45af4c BL	5274a8

0x45af50 LDR	X11, [SP, #344]

0x45af54 LDR	X18, [SP, #120]

0x45af58 CBZ	X11, 45b8ac

0x45af5c LDR	X12, [SP, #1176]

0x45af60 CBZ	X12, 45b8bc

0x45af64 CBZ	X23, 45f530

0x45af68 LDR	X2, [X24, #8]

0x45af6c LDR	X24, [X24, #48]

0x45af70 STR	X2, [SP, #448]

0x45af74 STR	X24, [SP, #440]

0x45af78 LDR	X13, [SP, #184]

0x45af7c STR	XZR, [SP, #392]

0x45af80 CBZ	X13, 45af8c

0x45af84 LDR	X22, [X22, #8]

0x45af88 STR	X22, [SP, #392]

0x45af8c LDR	X0, [X20, #16]

0x45af90 STR	X18, [SP, #136]

0x45af94 STR	X0, [SP, #312]

0x45af98 CBNZ	X0, 45b8e4

0x45af9c LDR	X28, [SP, #320]

0x45afa0 ADD	X1, SP, #832

0x45afa4 ADD	X26, SP, #832

0x45afa8 ADRP	X17, 45afa8

0x45afac MOVZ	W3, #0

0x45afb0 STR	X1, [SP, #296]

0x45afb4 ADD	X0, X17, #2720

0x45afb8 MOVZ	W2, #0

0x45afbc STP	XZR, XZR, [X26, #16]

0x45afc0 STP	X28, XZR, [X26]

0x45afc4 BL	4103b0

0x45afc8 LDR	X6, [SP, #856]

0x45afcc LDR	X8, [SP, #848]

0x45afd0 LDR	X9, [SP, #136]

0x45afd4 SUB	X3, XZR, X6

0x45afd8 STR	X6, [SP, #128]

0x45afdc SUBS	X0, X3, X8

0x45afe0 STR	X8, [SP, #720]

0x45afe4 STR	X0, [SP, #120]

0x45afe8 B.NE	45f4fc

0x45afec MOVZ	X1, #8

0x45aff0 MOVZ	X0, #11

0x45aff4 STR	X9, [SP, #136]

0x45aff8 BL	524ea8

0x45affc LDR	X5, [SP, #136]

0x45b000 MOVZ	X22, #0

0x45b004 STR	XZR, [SP, #232]

0x45b008 STR	X0, [SP, #256]

0x45b00c STR	XZR, [SP, #272]

0x45b010 LDR	X30, [SP, #312]

0x45b014 MOVZ	X1, #8

0x45b018 STR	X5, [SP, #136]

0x45b01c ADD	X0, X30, #1

0x45b020 ORR	X20, XZR, X0

0x45b024 STR	X0, [SP, #760]

0x45b028 BL	524ea8

0x45b02c ORR	X28, XZR, X0

0x45b030 MOVZ	X1, #8

0x45b034 ORR	X0, XZR, X20

0x45b038 STR	X28, [SP, #240]

0x45b03c BL	524ea8

0x45b040 STR	X0, [SP, #248]

0x45b044 LDR	X0, [SP, #128]

0x45b048 LDR	X6, [SP, #136]

0x45b04c CBNZ	X0, 45f4c4

0x45b050 LDR	X0, [SP, #184]

0x45b054 CBNZ	X0, 45f47c

0x45b058 LDR	X16, [SP, #816]

0x45b05c STR	XZR, [SP, #352]

0x45b060 STR	XZR, [SP, #424]

0x45b064 CMP	X16, #1

0x45b068 B.LE	45f574

0x45b06c LDR	X4, [SP, #344]

0x45b070 LDR	X11, [X4, #40]

0x45b074 LDP	X5, X3, [X4, #8]

0x45b078 LDP	X7, X25, [X4, #24]

0x45b07c UBFM	X24, X5, #61, #60

0x45b080 STR	X5, [SP, #152]

0x45b084 STR	X11, [SP, #176]

0x45b088 STR	X7, [SP, #288]

0x45b08c STR	X3, [SP, #704]

0x45b090 LDP	X12, X2, [X4, #48]

0x45b094 LDR	X0, [X7, X24]

0x45b098 STR	X2, [SP, #664]

0x45b09c STR	X12, [SP, #712]

0x45b0a0 CBNZ	X0, 45f628

0x45b0a4 LDR	X13, [SP, #176]

0x45b0a8 MOVZ	X20, #0

0x45b0ac LDR	X27, [SP, #152]

0x45b0b0 ADD	X14, X13, #1

0x45b0b4 STR	X14, [SP, #552]

0x45b0b8 CMP	X27, #0

0x45b0bc B.LE	45b144

0x45b0c0 LDR	X16, [SP, #288]

0x45b0c4 MOVZ	X27, #0

0x45b0c8 LDR	X26, [SP, #320]

0x45b0cc ADD	X1, X16, #8

0x45b0d0 ORR	X3, XZR, X1

0x45b0d4 ADD	X17, X1, X24

(720) 0x45b0d8 LDP	X0, X9, [X3, #1016]

(720) 0x45b0dc CMP	X0, X9

(720) 0x45b0e0 B.GE	45b12c

(720) 0x45b0e4 SUB	X8, XZR, X0,LSL #3

(720) 0x45b0e8 ORR	X7, XZR, X0

(720) 0x45b0ec ADD	X4, X8, X27,LSL #3

(720) 0x45b0f0 ADD	X10, X20, X4

(720) 0x45b0f4 HINT	#0

(720) 0x45b0f8 HINT	#0

(720) 0x45b0fc HINT	#0

  (779) 0x45b100 LDR	X11, [X25, X0,LSL #3]

  (779) 0x45b104 ORR	X12, XZR, X0

  (779) 0x45b108 LDR	X2, [X26, X11,LSL #3]

  (779) 0x45b10c STR	X2, [X10, X0,LSL #3]

  (779) 0x45b110 ADD	X0, X0, #1

  (779) 0x45b114 LDR	X13, [X3]

  (779) 0x45b118 CMP	X13, X0

  (779) 0x45b11c B.GT	45b100

(720) 0x45b120 SUB	X14, X12, X7

(720) 0x45b124 ADD	X5, X27, #1

(720) 0x45b128 ADD	X27, X14, X5

(720) 0x45b12c ADD	X3, X3, #8

(720) 0x45b130 CMP	X3, X17

(720) 0x45b134 B.NE	45b0d8

0x45b138 LDR	X15, [SP, #816]

0x45b13c CMP	X15, #1

0x45b140 B.LE	45fa38

0x45b144 LDP	X1, X3, [SP, #344]

0x45b148 ORR	X2, XZR, X20

0x45b14c MOVZ	X0, #11

0x45b150 STR	X6, [SP, #136]

0x45b154 BL	4e0364

0x45b158 BL	4e0b6c

0x45b15c LDR	X28, [SP, #432]

0x45b160 LDR	X6, [SP, #136]

0x45b164 CMP	X28, #1

0x45b168 B.LE	45b20c

0x45b16c LDR	X16, [SP, #152]

0x45b170 LDR	X30, [SP, #288]

0x45b174 ADD	X1, X30, #8

0x45b178 CMP	X16, #0

0x45b17c B.LE	45b1e0

0x45b180 LDR	X26, [SP, #584]

0x45b184 MOVZ	X5, #0

0x45b188 ADD	X24, X1, X24

(721) 0x45b18c LDP	X2, X17, [X1, #1016]

(721) 0x45b190 CMP	X2, X17

(721) 0x45b194 B.GE	45b1d4

(721) 0x45b198 UBFM	X9, X5, #61, #60

(721) 0x45b19c ORR	X8, XZR, X2

(721) 0x45b1a0 SUB	X7, X9, X2,LSL #3

(721) 0x45b1a4 ADD	X10, X20, X7

  (778) 0x45b1a8 LDR	X11, [X25, X2,LSL #3]

  (778) 0x45b1ac ORR	X4, XZR, X2

  (778) 0x45b1b0 LDR	X12, [X26, X11,LSL #3]

  (778) 0x45b1b4 STR	X12, [X10, X2,LSL #3]

  (778) 0x45b1b8 ADD	X2, X2, #1

  (778) 0x45b1bc LDR	X0, [X1]

  (778) 0x45b1c0 CMP	X0, X2

  (778) 0x45b1c4 B.GT	45b1a8

(721) 0x45b1c8 ADD	X13, X5, #1

(721) 0x45b1cc SUB	X14, X4, X8

(721) 0x45b1d0 ADD	X5, X13, X14

(721) 0x45b1d4 ADD	X1, X1, #8

(721) 0x45b1d8 CMP	X1, X24

(721) 0x45b1dc B.NE	45b18c

0x45b1e0 LDR	X1, [SP, #816]

0x45b1e4 CMP	X1, #1

0x45b1e8 B.LE	45b20c

0x45b1ec LDR	X1, [SP, #344]

0x45b1f0 ORR	X2, XZR, X20

0x45b1f4 MOVZ	X0, #11

0x45b1f8 STR	X6, [SP, #136]

0x45b1fc LDR	X3, [SP, #424]

0x45b200 BL	4e0364

0x45b204 BL	4e0b6c

0x45b208 LDR	X6, [SP, #136]

0x45b20c ADD	X15, SP, #832

0x45b210 ADRP	X27,

0x45b214 STR	X6, [SP, #136]

0x45b218 LDR	X28, [SP, #184]

0x45b21c MOVZ	W3, #0

0x45b220 ADD	X0, X27, #1920

0x45b224 MOVZ	W2, #0

0x45b228 LDR	X18, [SP, #352]

0x45b22c STP	XZR, XZR, [X15, #16]

0x45b230 STP	X28, X18, [X15]

0x45b234 LDR	X1, [SP, #296]

0x45b238 BL	4103b0

0x45b23c LDR	X3, [SP, #856]

0x45b240 LDR	X6, [SP, #136]

0x45b244 STR	X3, [SP, #488]

0x45b248 CBNZ	X28, 45dfa0

0x45b24c MOVZ	X26, #0

0x45b250 MOVZ	X24, #0

0x45b254 STR	XZR, [SP, #136]

0x45b258 STR	XZR, [SP, #520]

0x45b25c LDR	X30, [SP, #240]

0x45b260 LDR	X17, [SP, #248]

0x45b264 LDR	X16, [SP, #120]

0x45b268 STR	XZR, [X30]

0x45b26c LDR	X8, [SP, #312]

0x45b270 STR	XZR, [X17]

0x45b274 SUB	X27, X16, #1

0x45b278 CMP	X8, #0

0x45b27c B.LE	45b4bc

0x45b280 LDP	X10, X11, [SP, #240]

0x45b284 ANDS	X7, X8, #0x3

0x45b288 ORR	X3, XZR, X27

0x45b28c MOVZ	X0, #0

0x45b290 MOVZ	X1, #0

0x45b294 MOVN	X13, #0

0x45b298 ADD	X2, X10, #8

0x45b29c ADD	X4, X11, #8

0x45b2a0 B.EQ	45b35c

0x45b2a4 CMP	X7, #1

0x45b2a8 B.EQ	45b320

0x45b2ac CMP	X7, #2

0x45b2b0 B.EQ	45b2f0

0x45b2b4 LDR	X12, [SP, #320]

0x45b2b8 LDR	X0, [X12]

0x45b2bc CMP	X0, #1

0x45b2c0 B.EQ	45fa10

0x45b2c4 CMN	X0, #1

0x45b2c8 B.NE	45b2d8

0x45b2cc LDR	X14, [SP, #272]

0x45b2d0 SUB	X3, X27, #1

0x45b2d4 STR	XZR, [X14, X27,LSL #3]

0x45b2d8 LDR	X5, [SP, #232]

0x45b2dc MOVZ	X0, #1

0x45b2e0 STR	XZR, [X2]

0x45b2e4 STR	XZR, [X4]

0x45b2e8 STR	X13, [X22]

0x45b2ec STR	X13, [X5]

0x45b2f0 LDR	X18, [SP, #320]

0x45b2f4 LDR	X15, [X18, X0,LSL #3]

0x45b2f8 CMP	X15, #1

0x45b2fc B.EQ	45f724

0x45b300 CMN	X15, #1

0x45b304 B.EQ	45f6fc

0x45b308 LDR	X9, [SP, #232]

0x45b30c STR	XZR, [X2, X0,LSL #3]

0x45b310 STR	XZR, [X4, X0,LSL #3]

0x45b314 STR	X13, [X22, X0,LSL #3]

0x45b318 STR	X13, [X9, X0,LSL #3]

0x45b31c ADD	X0, X0, #1

0x45b320 LDR	X7, [SP, #320]

0x45b324 LDR	X10, [X7, X0,LSL #3]

0x45b328 CMP	X10, #1

0x45b32c B.EQ	45f4d8

0x45b330 CMN	X10, #1

0x45b334 B.EQ	45f6d8

0x45b338 LDR	X11, [SP, #232]

0x45b33c STR	XZR, [X2, X0,LSL #3]

0x45b340 STR	XZR, [X4, X0,LSL #3]

0x45b344 STR	X13, [X22, X0,LSL #3]

0x45b348 STR	X13, [X11, X0,LSL #3]

0x45b34c LDR	X18, [SP, #312]

0x45b350 ADD	X0, X0, #1

0x45b354 CMP	X18, X0

0x45b358 B.EQ	45b4bc

0x45b35c LDR	X15, [SP, #232]

0x45b360 LDR	X30, [SP, #272]

0x45b364 LDR	X16, [SP, #320]

0x45b368 LDR	X17, [SP, #360]

0x45b36c B	45b410

(777) 0x45b370 CMN	X9, #1

(777) 0x45b374 B.EQ	45f460

(777) 0x45b378 STR	XZR, [X2, X0,LSL #3]

(777) 0x45b37c STR	XZR, [X4, X0,LSL #3]

(777) 0x45b380 STR	X13, [X22, X0,LSL #3]

(777) 0x45b384 STR	X13, [X15, X0,LSL #3]

(777) 0x45b388 ADD	X0, X0, #1

(777) 0x45b38c LDR	X8, [X16, X0,LSL #3]

(777) 0x45b390 CMP	X8, #1

(777) 0x45b394 B.EQ	45b444

(777) 0x45b398 CMN	X8, #1

(777) 0x45b39c B.EQ	45f444

(777) 0x45b3a0 STR	XZR, [X2, X0,LSL #3]

(777) 0x45b3a4 STR	XZR, [X4, X0,LSL #3]

(777) 0x45b3a8 STR	X13, [X22, X0,LSL #3]

(777) 0x45b3ac STR	X13, [X15, X0,LSL #3]

(777) 0x45b3b0 ADD	X7, X0, #1

(777) 0x45b3b4 LDR	X10, [X16, X7,LSL #3]

(777) 0x45b3b8 CMP	X10, #1

(777) 0x45b3bc B.EQ	45b46c

(777) 0x45b3c0 CMN	X10, #1

(777) 0x45b3c4 B.EQ	45f428

(777) 0x45b3c8 STR	XZR, [X2, X7,LSL #3]

(777) 0x45b3cc STR	XZR, [X4, X7,LSL #3]

(777) 0x45b3d0 STR	X13, [X22, X7,LSL #3]

(777) 0x45b3d4 STR	X13, [X15, X7,LSL #3]

(777) 0x45b3d8 ADD	X11, X0, #2

(777) 0x45b3dc LDR	X12, [X16, X11,LSL #3]

(777) 0x45b3e0 CMP	X12, #1

(777) 0x45b3e4 B.EQ	45b494

(777) 0x45b3e8 CMN	X12, #1

(777) 0x45b3ec B.EQ	45f40c

(777) 0x45b3f0 STR	XZR, [X2, X11,LSL #3]

(777) 0x45b3f4 STR	XZR, [X4, X11,LSL #3]

(777) 0x45b3f8 STR	X13, [X22, X11,LSL #3]

(777) 0x45b3fc STR	X13, [X15, X11,LSL #3]

(777) 0x45b400 LDR	X14, [SP, #312]

(777) 0x45b404 ADD	X0, X0, #3

(777) 0x45b408 CMP	X14, X0

(777) 0x45b40c B.EQ	45b4bc

(777) 0x45b410 LDR	X9, [X16, X0,LSL #3]

(777) 0x45b414 CMP	X9, #1

(777) 0x45b418 B.NE	45b370

(777) 0x45b41c STR	X1, [X15, X0,LSL #3]

(777) 0x45b420 STR	X0, [X17, X1,LSL #3]

(777) 0x45b424 ADD	X1, X1, #1

(777) 0x45b428 STR	XZR, [X22, X0,LSL #3]

(777) 0x45b42c STR	X9, [X2, X0,LSL #3]

(777) 0x45b430 STR	XZR, [X4, X0,LSL #3]

(777) 0x45b434 ADD	X0, X0, #1

(777) 0x45b438 LDR	X8, [X16, X0,LSL #3]

(777) 0x45b43c CMP	X8, #1

(777) 0x45b440 B.NE	45b398

(777) 0x45b444 STR	X1, [X15, X0,LSL #3]

(777) 0x45b448 ADD	X7, X0, #1

(777) 0x45b44c STR	X0, [X17, X1,LSL #3]

(777) 0x45b450 ADD	X1, X1, #1

(777) 0x45b454 STR	XZR, [X22, X0,LSL #3]

(777) 0x45b458 STR	X8, [X2, X0,LSL #3]

(777) 0x45b45c STR	XZR, [X4, X0,LSL #3]

(777) 0x45b460 LDR	X10, [X16, X7,LSL #3]

(777) 0x45b464 CMP	X10, #1

(777) 0x45b468 B.NE	45b3c0

(777) 0x45b46c STR	X1, [X15, X7,LSL #3]

(777) 0x45b470 ADD	X11, X0, #2

(777) 0x45b474 STR	X7, [X17, X1,LSL #3]

(777) 0x45b478 ADD	X1, X1, #1

(777) 0x45b47c STR	XZR, [X22, X7,LSL #3]

(777) 0x45b480 STR	X10, [X2, X7,LSL #3]

(777) 0x45b484 STR	XZR, [X4, X7,LSL #3]

(777) 0x45b488 LDR	X12, [X16, X11,LSL #3]

(777) 0x45b48c CMP	X12, #1

(777) 0x45b490 B.NE	45b3e8

(777) 0x45b494 LDR	X14, [SP, #312]

(777) 0x45b498 ADD	X0, X0, #3

(777) 0x45b49c STR	X1, [X15, X11,LSL #3]

(777) 0x45b4a0 STR	X11, [X17, X1,LSL #3]

(777) 0x45b4a4 ADD	X1, X1, #1

(777) 0x45b4a8 STR	XZR, [X22, X11,LSL #3]

(777) 0x45b4ac STR	X12, [X2, X11,LSL #3]

(777) 0x45b4b0 STR	XZR, [X4, X11,LSL #3]

(777) 0x45b4b4 CMP	X14, X0

(777) 0x45b4b8 B.NE	45b410

0x45b4bc LDR	X2, [SP, #288]

0x45b4c0 MOVZ	X11, #0

0x45b4c4 LDR	X13, [SP, #152]

0x45b4c8 ADD	X14, X2, #8

0x45b4cc ADD	X28, X14, X13,LSL #3

0x45b4d0 CMP	X13, #0

0x45b4d4 B.LE	45b538

0x45b4d8 LDR	X18, [SP, #144]

0x45b4dc LDR	X15, [SP, #232]

(775) 0x45b4e0 LDP	X4, X5, [X14, #1016]

(775) 0x45b4e4 CMP	X4, X5

(775) 0x45b4e8 B.GE	45b52c

(775) 0x45b4ec UBFM	X30, X4, #61, #60

(775) 0x45b4f0 SUB	X16, X4, X11

(775) 0x45b4f4 SUB	X17, X30, X11,LSL #3

(775) 0x45b4f8 ADD	X9, X25, X17

(775) 0x45b4fc HINT	#0

  (776) 0x45b500 LDR	X8, [X9, X11,LSL #3]

  (776) 0x45b504 LDR	X7, [X15, X8,LSL #3]

  (776) 0x45b508 STR	X7, [X20, X11,LSL #3]

  (776) 0x45b50c ADD	X10, X18, X7

  (776) 0x45b510 TBNZ	X7, #63, 45b97c

  (776) 0x45b514 STR	X10, [X20, X11,LSL #3]

  (776) 0x45b518 ADD	X11, X11, #1

  (776) 0x45b51c LDR	X1, [X14]

  (776) 0x45b520 ADD	X0, X16, X11

  (776) 0x45b524 CMP	X0, X1

  (776) 0x45b528 B.LT	45b500

(775) 0x45b52c ADD	X14, X14, #8

(775) 0x45b530 CMP	X14, X28

(775) 0x45b534 B.NE	45b4e0

0x45b538 LDR	X13, [SP, #816]

0x45b53c CMP	X13, #1

0x45b540 B.LE	45b564

0x45b544 LDR	X1, [SP, #344]

0x45b548 ORR	X3, XZR, X24

0x45b54c ORR	X2, XZR, X20

0x45b550 MOVZ	X0, #11

0x45b554 STR	X6, [SP, #168]

0x45b558 BL	4e0364

0x45b55c BL	4e0b6c

0x45b560 LDR	X6, [SP, #168]

0x45b564 MOVZ	X1, #8

0x45b568 STR	X6, [SP, #168]

0x45b56c LDR	X0, [SP, #552]

0x45b570 BL	524ea8

0x45b574 STR	XZR, [SP, #496]

0x45b578 STR	X0, [SP, #672]

0x45b57c LDR	X0, [SP, #488]

0x45b580 LDR	X28, [SP, #168]

0x45b584 CBNZ	X0, 45dff4

0x45b588 LDR	X2, [SP, #672]

0x45b58c LDR	X18, [SP, #176]

0x45b590 STR	XZR, [X2]

0x45b594 CMP	X18, #0

0x45b598 B.LE	45b618

0x45b59c LDR	X8, [SP, #664]

0x45b5a0 ADD	X15, X18, #1

0x45b5a4 MOVZ	X7, #0

0x45b5a8 MOVZ	X5, #8

0x45b5ac UBFM	X30, X15, #61, #60

0x45b5b0 LDR	X17, [SP, #136]

0x45b5b4 MOVN	X16, #0

0x45b5b8 LDR	X9, [SP, #352]

0x45b5bc SUB	X4, X8, #8

0x45b5c0 LDR	X12, [SP, #496]

0x45b5c4 LDR	X10, [SP, #520]

(773) 0x45b5c8 LDR	X0, [X4, X5]

(773) 0x45b5cc LDR	X11, [X8, X5]

(773) 0x45b5d0 CMP	X0, X11

(773) 0x45b5d4 B.GE	45b604

(773) 0x45b5d8 HINT	#0

(773) 0x45b5dc HINT	#0

  (774) 0x45b5e0 LDR	X3, [X9, X0,LSL #3]

  (774) 0x45b5e4 CMP	X3, #1

  (774) 0x45b5e8 B.EQ	45b9a0

  (774) 0x45b5ec STR	X16, [X26, X0,LSL #3]

  (774) 0x45b5f0 STR	X16, [X10, X0,LSL #3]

  (774) 0x45b5f4 ADD	X0, X0, #1

  (774) 0x45b5f8 LDR	X1, [X8, X5]

  (774) 0x45b5fc CMP	X0, X1

  (774) 0x45b600 B.LT	45b5e0

(773) 0x45b604 LDR	X2, [SP, #672]

(773) 0x45b608 STR	X7, [X2, X5]

(773) 0x45b60c ADD	X5, X5, #8

(773) 0x45b610 CMP	X5, X30

(773) 0x45b614 B.NE	45b5c8

0x45b618 ORR	X0, XZR, X24

0x45b61c STR	X28, [SP, #168]

0x45b620 BL	524f40

0x45b624 LDR	X24, [SP, #1176]

0x45b628 LDR	X6, [SP, #168]

0x45b62c CBZ	X24, 45c0e4

0x45b630 MOVZ	X1, #8

0x45b634 ORR	X0, XZR, X23

0x45b638 STR	X6, [SP, #168]

0x45b63c BL	524ea8

0x45b640 CMP	X23, #0

0x45b644 STR	X0, [SP, #264]

0x45b648 LDR	X6, [SP, #168]

0x45b64c B.LE	45b7dc

0x45b650 ANDS	X28, X23, #0x7

0x45b654 MOVZ	X1, #0

0x45b658 MOVZ	X0, #0

0x45b65c B.EQ	45f8a0

0x45b660 CMP	X28, #1

0x45b664 B.EQ	45f858

0x45b668 CMP	X28, #2

0x45b66c B.EQ	45b794

0x45b670 CMP	X28, #3

0x45b674 B.EQ	45b760

0x45b678 CMP	X28, #4

0x45b67c B.EQ	45b72c

0x45b680 CMP	X28, #5

0x45b684 B.EQ	45b6f8

0x45b688 CMP	X28, #6

0x45b68c B.EQ	45b6c4

0x45b690 LDR	X18, [SP, #184]

0x45b694 CMP	X18, #0

0x45b698 B.LE	45b7a0

0x45b69c LDR	X17, [X19]

0x45b6a0 MOVN	X15, #0

0x45b6a4 MOVZ	X30, #0

0x45b6a8 MOVZ	X1, #1

0x45b6ac LDR	X9, [X21]

0x45b6b0 LDR	X10, [SP, #264]

0x45b6b4 CMP	X9, X17

0x45b6b8 CSEL	X12, X15, X30, #1

0x45b6bc CSEL	X0, X0, X1, #1

0x45b6c0 STR	X12, [X10]

0x45b6c4 LDR	X8, [SP, #184]

0x45b6c8 CMP	X8, X0

0x45b6cc B.LE	45b7a0

0x45b6d0 LDR	X4, [X21, X1,LSL #3]

0x45b6d4 MOVN	X14, #0

0x45b6d8 LDR	X11, [X19, X0,LSL #3]

0x45b6dc CMP	X4, X11

0x45b6e0 B.NE	45b6ec

0x45b6e4 ORR	X14, XZR, X0

0x45b6e8 ADD	X0, X0, #1

0x45b6ec LDR	X3, [SP, #264]

0x45b6f0 STR	X14, [X3, X1,LSL #3]

0x45b6f4 ADD	X1, X1, #1

0x45b6f8 LDR	X7, [SP, #184]

0x45b6fc CMP	X7, X0

0x45b700 B.LE	45b7a0

0x45b704 LDR	X13, [X21, X1,LSL #3]

0x45b708 MOVN	X2, #0

0x45b70c LDR	X5, [X19, X0,LSL #3]

0x45b710 CMP	X13, X5

0x45b714 B.NE	45b720

0x45b718 ORR	X2, XZR, X0

0x45b71c ADD	X0, X0, #1

0x45b720 LDR	X24, [SP, #264]

0x45b724 STR	X2, [X24, X1,LSL #3]

0x45b728 ADD	X1, X1, #1

0x45b72c LDR	X28, [SP, #184]

0x45b730 CMP	X28, X0

0x45b734 B.LE	45b7a0

0x45b738 LDR	X18, [X21, X1,LSL #3]

0x45b73c MOVN	X30, #0

0x45b740 LDR	X15, [X19, X0,LSL #3]

0x45b744 CMP	X18, X15

0x45b748 B.NE	45b754

0x45b74c ORR	X30, XZR, X0

0x45b750 ADD	X0, X0, #1

0x45b754 LDR	X16, [SP, #264]

0x45b758 STR	X30, [X16, X1,LSL #3]

0x45b75c ADD	X1, X1, #1

0x45b760 LDR	X17, [SP, #184]

0x45b764 CMP	X17, X0

0x45b768 B.LE	45b7a0

0x45b76c LDR	X9, [X21, X1,LSL #3]

0x45b770 MOVN	X10, #0

0x45b774 LDR	X12, [X19, X0,LSL #3]

0x45b778 CMP	X9, X12

0x45b77c B.NE	45b788

0x45b780 ORR	X10, XZR, X0

0x45b784 ADD	X0, X0, #1

0x45b788 LDR	X8, [SP, #264]

0x45b78c STR	X10, [X8, X1,LSL #3]

0x45b790 ADD	X1, X1, #1

0x45b794 LDR	X4, [SP, #184]

0x45b798 CMP	X4, X0

0x45b79c B.GT	45f838

0x45b7a0 LDR	X0, [SP, #264]

0x45b7a4 MOVN	X21, #0

0x45b7a8 ADD	X19, X1, #1

0x45b7ac STR	X21, [X0, X1,LSL #3]

0x45b7b0 CMP	X23, X19

0x45b7b4 B.EQ	45b7dc

0x45b7b8 SUB	X23, X23, X19

0x45b7bc MOVZ	X15, #8

0x45b7c0 ADD	X0, X0, X19,LSL #3

0x45b7c4 UBFM	X18, X23, #61, #60

0x45b7c8 MOVZ	W1, #255

0x45b7cc CSEL	X2, X18, X15, #12

0x45b7d0 STR	X6, [SP, #168]

0x45b7d4 BL	410600

0x45b7d8 LDR	X6, [SP, #168]

0x45b7dc LDR	X9, [SP, #256]

0x45b7e0 STP	XZR, XZR, [X9]

0x45b7e4 TBNZ	X27, #63, 45c0f4

0x45b7e8 MOVZ	X28, #0

0x45b7ec MOVZ	X4, #0

0x45b7f0 LDR	X14, [SP, #272]

0x45b7f4 ORR	X7, XZR, X27

0x45b7f8 MOVZ	X23, #0

0x45b7fc LDP	X30, X13, [SP, #240]

0x45b800 UBFM	X8, X27, #61, #60

0x45b804 LDR	X12, [SP, #320]

0x45b808 LDR	X10, [SP, #352]

0x45b80c LDR	X5, [SP, #392]

0x45b810 LDR	X16, [SP, #480]

0x45b814 LDR	X15, [SP, #536]

(722) 0x45b818 ADD	X18, X14, X8

(722) 0x45b81c LDR	X17, [X14, X8]

(722) 0x45b820 UBFM	X19, X17, #61, #60

(722) 0x45b824 ADD	X2, X19, #8

(722) 0x45b828 LDR	X0, [X15, X19]

(722) 0x45b82c ADD	X11, X22, X19

(722) 0x45b830 ADD	X21, X15, X2

(722) 0x45b834 LDR	X3, [X15, X2]

(722) 0x45b838 CMP	X0, X3

(722) 0x45b83c B.GE	45b85c

  (771) 0x45b840 LDR	X1, [X6, X0,LSL #3]

  (771) 0x45b844 LDR	X9, [X12, X1,LSL #3]

  (771) 0x45b848 CMP	X9, #1

  (771) 0x45b84c B.EQ	45c0a0

  (771) 0x45b850 ADD	X0, X0, #1

  (771) 0x45b854 CMP	X0, X3

  (771) 0x45b858 B.LT	45b840

(722) 0x45b85c LDR	X9, [X16, X19]

(722) 0x45b860 ADD	X19, X16, X2

(722) 0x45b864 LDR	X3, [X16, X2]

(722) 0x45b868 CMP	X9, X3

(722) 0x45b86c B.GE	45b88c

  (770) 0x45b870 LDR	X21, [X5, X9,LSL #3]

  (770) 0x45b874 LDR	X1, [X10, X21,LSL #3]

  (770) 0x45b878 CMP	X1, #1

  (770) 0x45b87c B.EQ	45b9e4

  (770) 0x45b880 ADD	X9, X9, #1

  (770) 0x45b884 CMP	X9, X3

  (770) 0x45b888 B.LT	45b870

(722) 0x45b88c LDR	X2, [X11]

(722) 0x45b890 CMP	X2, #1

(722) 0x45b894 B.EQ	45ba08

(722) 0x45b898 SUB	X7, X7, #1

(722) 0x45b89c CMP	X23, X7

(722) 0x45b8a0 B.GT	45ba24

(722) 0x45b8a4 UBFM	X8, X7, #61, #60

(722) 0x45b8a8 B	45b818

0x45b8ac LDR	X19, [SP, #680]

0x45b8b0 LDR	X14, [X19, #112]

0x45b8b4 STR	X14, [SP, #344]

0x45b8b8 CBZ	X14, 45f664

0x45b8bc CBNZ	X23, 45f538

0x45b8c0 STP	XZR, XZR, [SP, #440]

0x45b8c4 ORR	X19, XZR, X21

0x45b8c8 LDR	X0, [X20, #16]

0x45b8cc STR	X18, [SP, #136]

0x45b8d0 STR	XZR, [SP, #184]

0x45b8d4 STR	XZR, [SP, #392]

0x45b8d8 STR	XZR, [SP, #1176]

0x45b8dc STR	X0, [SP, #312]

0x45b8e0 CBZ	X0, 45af9c

0x45b8e4 MOVZ	X1, #8

0x45b8e8 ORR	X24, XZR, X0

0x45b8ec BL	524ea8

0x45b8f0 LDR	X10, [SP, #320]

0x45b8f4 ADD	X1, SP, #832

0x45b8f8 ADD	X11, SP, #832

0x45b8fc ADRP	X12,

0x45b900 STR	X0, [SP, #232]

0x45b904 MOVZ	W2, #0

0x45b908 STR	X1, [SP, #296]

0x45b90c ADD	X0, X12, #2720

0x45b910 MOVZ	W3, #0

0x45b914 STP	XZR, XZR, [X11, #16]

0x45b918 STP	X10, X24, [X11]

0x45b91c BL	4103b0

0x45b920 LDR	X14, [SP, #856]

0x45b924 LDR	X13, [SP, #848]

0x45b928 LDR	X2, [SP, #136]

0x45b92c SUB	X27, X24, X14

0x45b930 STR	X14, [SP, #128]

0x45b934 SUBS	X0, X27, X13

0x45b938 STR	X13, [SP, #720]

0x45b93c STR	X0, [SP, #120]

0x45b940 B.NE	45f684

0x45b944 MOVZ	X1, #8

0x45b948 MOVZ	X0, #11

0x45b94c STR	X2, [SP, #136]

0x45b950 BL	524ea8

0x45b954 LDR	X18, [SP, #136]

0x45b958 STR	X0, [SP, #256]

0x45b95c STR	XZR, [SP, #272]

0x45b960 LDR	X0, [SP, #312]

0x45b964 MOVZ	X1, #8

0x45b968 STR	X18, [SP, #136]

0x45b96c BL	524ea8

0x45b970 LDR	X5, [SP, #136]

0x45b974 ORR	X22, XZR, X0

0x45b978 B	45b010

  (776) 0x45b97c LDR	X3, [X14]

  (776) 0x45b980 ADD	X11, X11, #1

  (776) 0x45b984 ADD	X12, X16, X11

  (776) 0x45b988 CMP	X12, X3

  (776) 0x45b98c B.LT	45b500

(775) 0x45b990 ADD	X14, X14, #8

(775) 0x45b994 CMP	X14, X28

(775) 0x45b998 B.NE	45b4e0

0x45b99c B	45b538

  (774) 0x45b9a0 UBFM	X14, X7, #61, #60

  (774) 0x45b9a4 STR	X7, [X10, X0,LSL #3]

  (774) 0x45b9a8 ADD	X7, X7, #1

  (774) 0x45b9ac STR	X0, [X12, X14]

  (774) 0x45b9b0 LDR	X13, [X24, X0,LSL #3]

  (774) 0x45b9b4 STR	X13, [X17, X14]

  (774) 0x45b9b8 STR	XZR, [X26, X0,LSL #3]

  (774) 0x45b9bc ADD	X0, X0, #1

  (774) 0x45b9c0 LDR	X6, [X8, X5]

  (774) 0x45b9c4 CMP	X6, X0

  (774) 0x45b9c8 B.GT	45b5e0

(773) 0x45b9cc LDR	X2, [SP, #672]

(773) 0x45b9d0 STR	X7, [X2, X5]

(773) 0x45b9d4 ADD	X5, X5, #8

(773) 0x45b9d8 CMP	X5, X30

(773) 0x45b9dc B.NE	45b5c8

0x45b9e0 B	45b618

  (770) 0x45b9e4 LDR	X0, [X13, X2]

  (770) 0x45b9e8 ADD	X9, X9, #1

  (770) 0x45b9ec ADD	X28, X28, #1

  (770) 0x45b9f0 ADD	X24, X0, #1

  (770) 0x45b9f4 STR	X24, [X13, X2]

  (770) 0x45b9f8 STR	X1, [X11]

  (770) 0x45b9fc LDR	X3, [X19]

  (770) 0x45ba00 CMP	X3, X9

  (770) 0x45ba04 B.GT	45b870

(722) 0x45ba08 UBFM	X11, X23, #61, #60

(722) 0x45ba0c ADD	X23, X23, #1

(722) 0x45ba10 LDR	X19, [X14, X11]

(722) 0x45ba14 STR	X19, [X18]

(722) 0x45ba18 STR	X17, [X14, X11]

(722) 0x45ba1c CMP	X23, X7

(722) 0x45ba20 B.LE	45b818

0x45ba24 LDR	X30, [SP, #120]

0x45ba28 STR	X4, [SP, #200]

0x45ba2c SUB	X24, X30, X23

0x45ba30 LDR	X14, [SP, #256]

0x45ba34 MOVZ	X3, #0

0x45ba38 LDR	X13, [SP, #288]

0x45ba3c LDR	X12, [SP, #152]

0x45ba40 STR	X23, [X14, #16]

0x45ba44 ADD	X4, X13, #8

0x45ba48 ADD	X10, X4, X12,LSL #3

0x45ba4c CMP	X12, #0

0x45ba50 B.LE	45baa8

(768) 0x45ba54 LDP	X7, X16, [X4, #1016]

(768) 0x45ba58 CMP	X7, X16

(768) 0x45ba5c B.GE	45ba9c

(768) 0x45ba60 SUB	X15, XZR, X7,LSL #3

(768) 0x45ba64 ORR	X17, XZR, X7

(768) 0x45ba68 ADD	X18, X15, X3,LSL #3

(768) 0x45ba6c ADD	X21, X20, X18

  (769) 0x45ba70 LDR	X1, [X25, X7,LSL #3]

  (769) 0x45ba74 ORR	X9, XZR, X7

  (769) 0x45ba78 LDR	X2, [X22, X1,LSL #3]

  (769) 0x45ba7c STR	X2, [X21, X7,LSL #3]

  (769) 0x45ba80 ADD	X7, X7, #1

  (769) 0x45ba84 LDR	X8, [X4]

  (769) 0x45ba88 CMP	X8, X7

  (769) 0x45ba8c B.GT	45ba70

(768) 0x45ba90 SUB	X0, X9, X17

(768) 0x45ba94 ADD	X5, X3, #1

(768) 0x45ba98 ADD	X3, X0, X5

(768) 0x45ba9c ADD	X4, X4, #8

(768) 0x45baa0 CMP	X4, X10

(768) 0x45baa4 B.NE	45ba54

0x45baa8 LDR	X11, [SP, #816]

0x45baac CMP	X11, #1

0x45bab0 B.LE	45bad4

0x45bab4 LDR	X1, [SP, #344]

0x45bab8 ORR	X3, XZR, X26

0x45babc ORR	X2, XZR, X20

0x45bac0 MOVZ	X0, #11

0x45bac4 STR	X6, [SP, #168]

0x45bac8 BL	4e0364

0x45bacc BL	4e0b6c

0x45bad0 LDR	X6, [SP, #168]

0x45bad4 ADRP	X19,

0x45bad8 ADD	X1, SP, #792

0x45badc STR	X6, [SP, #168]

0x45bae0 ADD	X30, X19, #1288

0x45bae4 LDR	X3, [SP, #160]

0x45bae8 MOVZ	X2, #1

0x45baec ORR	X4, XZR, X30

0x45baf0 ADD	X0, SP, #800

0x45baf4 STR	X24, [SP, #800]

0x45baf8 LDR	X5, [SP, #400]

0x45bafc STR	X30, [SP, #208]

0x45bb00 BL	5276d0

0x45bb04 LDR	X24, [SP, #152]

0x45bb08 MOVZ	X13, #1

0x45bb0c LDR	X10, [SP, #256]

0x45bb10 LDR	X14, [SP, #792]

0x45bb14 UBFM	X12, X24, #61, #60

0x45bb18 LDR	X21, [SP, #168]

0x45bb1c ADD	X15, X10, #16

0x45bb20 STR	X12, [SP, #192]

0x45bb24 STR	X15, [SP, #224]

0x45bb28 CBZ	X14, 45f824

0x45bb2c ORR	X24, XZR, X20

0x45bb30 ORR	X11, XZR, X27

0x45bb34 LDR	X27, [SP, #272]

0x45bb38 ORR	X20, XZR, X21

0x45bb3c STR	X28, [SP, #168]

0x45bb40 LDR	X21, [SP, #392]

0x45bb44 LDR	X28, [SP, #536]

(759) 0x45bb48 ORR	X30, XZR, X23

(759) 0x45bb4c ORR	X19, XZR, X13

(759) 0x45bb50 ORR	X4, XZR, X11

(759) 0x45bb54 ADD	X7, X13, #1

(759) 0x45bb58 CMP	X11, X23

(759) 0x45bb5c B.LT	45be90

(759) 0x45bb60 LDR	X8, [SP, #480]

  (765) 0x45bb64 ADD	X9, X27, X4,LSL #3

  (765) 0x45bb68 LDR	X5, [X27, X4,LSL #3]

  (765) 0x45bb6c UBFM	X2, X5, #61, #60

  (765) 0x45bb70 ADD	X6, X2, #8

  (765) 0x45bb74 LDR	X0, [X28, X2]

  (765) 0x45bb78 LDR	X3, [X28, X6]

  (765) 0x45bb7c CMP	X0, X3

  (765) 0x45bb80 B.GE	45bcfc

  (765) 0x45bb84 SUB	X16, X3, X0

  (765) 0x45bb88 ANDS	X17, X16, #0x7

  (765) 0x45bb8c B.EQ	45bc54

  (765) 0x45bb90 CMP	X17, #1

  (765) 0x45bb94 B.EQ	45bc38

  (765) 0x45bb98 CMP	X17, #2

  (765) 0x45bb9c B.EQ	45bc24

  (765) 0x45bba0 CMP	X17, #3

  (765) 0x45bba4 B.EQ	45bc10

  (765) 0x45bba8 CMP	X17, #4

  (765) 0x45bbac B.EQ	45bbfc

  (765) 0x45bbb0 CMP	X17, #5

  (765) 0x45bbb4 B.EQ	45bbe8

  (765) 0x45bbb8 CMP	X17, #6

  (765) 0x45bbbc B.EQ	45bbd4

  (765) 0x45bbc0 LDR	X18, [X20, X0,LSL #3]

  (765) 0x45bbc4 ADD	X0, X0, #1

  (765) 0x45bbc8 LDR	X1, [X22, X18,LSL #3]

  (765) 0x45bbcc CMP	X1, X19

  (765) 0x45bbd0 B.EQ	45c0c8

  (765) 0x45bbd4 LDR	X13, [X20, X0,LSL #3]

  (765) 0x45bbd8 ADD	X0, X0, #1

  (765) 0x45bbdc LDR	X14, [X22, X13,LSL #3]

  (765) 0x45bbe0 CMP	X14, X19

  (765) 0x45bbe4 B.EQ	45c0c8

  (765) 0x45bbe8 LDR	X12, [X20, X0,LSL #3]

  (765) 0x45bbec ADD	X0, X0, #1

  (765) 0x45bbf0 LDR	X10, [X22, X12,LSL #3]

  (765) 0x45bbf4 CMP	X10, X19

  (765) 0x45bbf8 B.EQ	45c0c8

  (765) 0x45bbfc LDR	X15, [X20, X0,LSL #3]

  (765) 0x45bc00 ADD	X0, X0, #1

  (765) 0x45bc04 LDR	X16, [X22, X15,LSL #3]

  (765) 0x45bc08 CMP	X16, X19

  (765) 0x45bc0c B.EQ	45c0c8

  (765) 0x45bc10 LDR	X17, [X20, X0,LSL #3]

  (765) 0x45bc14 ADD	X0, X0, #1

  (765) 0x45bc18 LDR	X18, [X22, X17,LSL #3]

  (765) 0x45bc1c CMP	X18, X19

  (765) 0x45bc20 B.EQ	45c0c8

  (765) 0x45bc24 LDR	X1, [X20, X0,LSL #3]

  (765) 0x45bc28 ADD	X0, X0, #1

  (765) 0x45bc2c LDR	X13, [X22, X1,LSL #3]

  (765) 0x45bc30 CMP	X13, X19

  (765) 0x45bc34 B.EQ	45c0c8

  (765) 0x45bc38 LDR	X14, [X20, X0,LSL #3]

  (765) 0x45bc3c LDR	X12, [X22, X14,LSL #3]

  (765) 0x45bc40 CMP	X12, X19

  (765) 0x45bc44 B.EQ	45c0c8

  (765) 0x45bc48 ADD	X0, X0, #1

  (765) 0x45bc4c CMP	X0, X3

  (765) 0x45bc50 B.EQ	45bcfc

    (767) 0x45bc54 LDR	X18, [X20, X0,LSL #3]

    (767) 0x45bc58 ADD	X10, X0, #1

    (767) 0x45bc5c ADD	X16, X0, #3

    (767) 0x45bc60 ADD	X15, X0, #4

    (767) 0x45bc64 ADD	X14, X0, #5

    (767) 0x45bc68 ADD	X13, X0, #6

    (767) 0x45bc6c ADD	X17, X0, #7

    (767) 0x45bc70 ADD	X12, X10, #1

    (767) 0x45bc74 ADD	X0, X0, #8

    (767) 0x45bc78 LDR	X1, [X22, X18,LSL #3]

    (767) 0x45bc7c CMP	X1, X19

    (767) 0x45bc80 B.EQ	45c0c8

    (767) 0x45bc84 LDR	X10, [X20, X10,LSL #3]

    (767) 0x45bc88 LDR	X18, [X22, X10,LSL #3]

    (767) 0x45bc8c CMP	X18, X19

    (767) 0x45bc90 B.EQ	45c0c8

    (767) 0x45bc94 LDR	X12, [X20, X12,LSL #3]

    (767) 0x45bc98 LDR	X1, [X22, X12,LSL #3]

    (767) 0x45bc9c CMP	X1, X19

    (767) 0x45bca0 B.EQ	45c0c8

    (767) 0x45bca4 LDR	X16, [X20, X16,LSL #3]

    (767) 0x45bca8 LDR	X10, [X22, X16,LSL #3]

    (767) 0x45bcac CMP	X10, X19

    (767) 0x45bcb0 B.EQ	45c0c8

    (767) 0x45bcb4 LDR	X15, [X20, X15,LSL #3]

    (767) 0x45bcb8 LDR	X18, [X22, X15,LSL #3]

    (767) 0x45bcbc CMP	X18, X19

    (767) 0x45bcc0 B.EQ	45c0c8

    (767) 0x45bcc4 LDR	X14, [X20, X14,LSL #3]

    (767) 0x45bcc8 LDR	X12, [X22, X14,LSL #3]

    (767) 0x45bccc CMP	X12, X19

    (767) 0x45bcd0 B.EQ	45c0c8

    (767) 0x45bcd4 LDR	X13, [X20, X13,LSL #3]

    (767) 0x45bcd8 LDR	X1, [X22, X13,LSL #3]

    (767) 0x45bcdc CMP	X1, X19

    (767) 0x45bce0 B.EQ	45c0c8

    (767) 0x45bce4 LDR	X17, [X20, X17,LSL #3]

    (767) 0x45bce8 LDR	X16, [X22, X17,LSL #3]

    (767) 0x45bcec CMP	X16, X19

    (767) 0x45bcf0 B.EQ	45c0c8

    (767) 0x45bcf4 CMP	X0, X3

    (767) 0x45bcf8 B.NE	45bc54

  (765) 0x45bcfc LDR	X3, [X8, X6]

  (765) 0x45bd00 LDR	X0, [X8, X2]

  (765) 0x45bd04 CMP	X0, X3

  (765) 0x45bd08 B.GE	45be84

  (765) 0x45bd0c SUB	X6, X3, X0

  (765) 0x45bd10 ANDS	X10, X6, #0x7

  (765) 0x45bd14 B.EQ	45bddc

  (765) 0x45bd18 CMP	X10, #1

  (765) 0x45bd1c B.EQ	45bdc0

  (765) 0x45bd20 CMP	X10, #2

  (765) 0x45bd24 B.EQ	45bdac

  (765) 0x45bd28 CMP	X10, #3

  (765) 0x45bd2c B.EQ	45bd98

  (765) 0x45bd30 CMP	X10, #4

  (765) 0x45bd34 B.EQ	45bd84

  (765) 0x45bd38 CMP	X10, #5

  (765) 0x45bd3c B.EQ	45bd70

  (765) 0x45bd40 CMP	X10, #6

  (765) 0x45bd44 B.EQ	45bd5c

  (765) 0x45bd48 LDR	X15, [X21, X0,LSL #3]

  (765) 0x45bd4c ADD	X0, X0, #1

  (765) 0x45bd50 LDR	X18, [X26, X15,LSL #3]

  (765) 0x45bd54 CMP	X18, X19

  (765) 0x45bd58 B.EQ	45c0c8

  (765) 0x45bd5c LDR	X14, [X21, X0,LSL #3]

  (765) 0x45bd60 ADD	X0, X0, #1

  (765) 0x45bd64 LDR	X12, [X26, X14,LSL #3]

  (765) 0x45bd68 CMP	X12, X19

  (765) 0x45bd6c B.EQ	45c0c8

  (765) 0x45bd70 LDR	X13, [X21, X0,LSL #3]

  (765) 0x45bd74 ADD	X0, X0, #1

  (765) 0x45bd78 LDR	X1, [X26, X13,LSL #3]

  (765) 0x45bd7c CMP	X1, X19

  (765) 0x45bd80 B.EQ	45c0c8

  (765) 0x45bd84 LDR	X17, [X21, X0,LSL #3]

  (765) 0x45bd88 ADD	X0, X0, #1

  (765) 0x45bd8c LDR	X16, [X26, X17,LSL #3]

  (765) 0x45bd90 CMP	X16, X19

  (765) 0x45bd94 B.EQ	45c0c8

  (765) 0x45bd98 LDR	X6, [X21, X0,LSL #3]

  (765) 0x45bd9c ADD	X0, X0, #1

  (765) 0x45bda0 LDR	X10, [X26, X6,LSL #3]

  (765) 0x45bda4 CMP	X10, X19

  (765) 0x45bda8 B.EQ	45c0c8

  (765) 0x45bdac LDR	X15, [X21, X0,LSL #3]

  (765) 0x45bdb0 ADD	X0, X0, #1

  (765) 0x45bdb4 LDR	X18, [X26, X15,LSL #3]

  (765) 0x45bdb8 CMP	X18, X19

  (765) 0x45bdbc B.EQ	45c0c8

  (765) 0x45bdc0 LDR	X14, [X21, X0,LSL #3]

  (765) 0x45bdc4 LDR	X12, [X26, X14,LSL #3]

  (765) 0x45bdc8 CMP	X12, X19

  (765) 0x45bdcc B.EQ	45c0c8

  (765) 0x45bdd0 ADD	X0, X0, #1

  (765) 0x45bdd4 CMP	X0, X3

  (765) 0x45bdd8 B.EQ	45be84

    (766) 0x45bddc LDR	X17, [X21, X0,LSL #3]

    (766) 0x45bde0 ADD	X1, X0, #1

    (766) 0x45bde4 ADD	X10, X0, #3

    (766) 0x45bde8 ADD	X15, X0, #4

    (766) 0x45bdec ADD	X18, X0, #5

    (766) 0x45bdf0 ADD	X6, X0, #6

    (766) 0x45bdf4 ADD	X13, X0, #7

    (766) 0x45bdf8 ADD	X16, X1, #1

    (766) 0x45bdfc ADD	X0, X0, #8

    (766) 0x45be00 LDR	X14, [X26, X17,LSL #3]

    (766) 0x45be04 CMP	X14, X19

    (766) 0x45be08 B.EQ	45c0c8

    (766) 0x45be0c LDR	X12, [X21, X1,LSL #3]

    (766) 0x45be10 LDR	X1, [X26, X12,LSL #3]

    (766) 0x45be14 CMP	X1, X19

    (766) 0x45be18 B.EQ	45c0c8

    (766) 0x45be1c LDR	X17, [X21, X16,LSL #3]

    (766) 0x45be20 LDR	X16, [X26, X17,LSL #3]

    (766) 0x45be24 CMP	X16, X19

    (766) 0x45be28 B.EQ	45c0c8

    (766) 0x45be2c LDR	X10, [X21, X10,LSL #3]

    (766) 0x45be30 LDR	X14, [X26, X10,LSL #3]

    (766) 0x45be34 CMP	X14, X19

    (766) 0x45be38 B.EQ	45c0c8

    (766) 0x45be3c LDR	X15, [X21, X15,LSL #3]

    (766) 0x45be40 LDR	X12, [X26, X15,LSL #3]

    (766) 0x45be44 CMP	X12, X19

    (766) 0x45be48 B.EQ	45c0c8

    (766) 0x45be4c LDR	X18, [X21, X18,LSL #3]

    (766) 0x45be50 LDR	X1, [X26, X18,LSL #3]

    (766) 0x45be54 CMP	X1, X19

    (766) 0x45be58 B.EQ	45c0c8

    (766) 0x45be5c LDR	X6, [X21, X6,LSL #3]

    (766) 0x45be60 LDR	X17, [X26, X6,LSL #3]

    (766) 0x45be64 CMP	X17, X19

    (766) 0x45be68 B.EQ	45c0c8

    (766) 0x45be6c LDR	X13, [X21, X13,LSL #3]

    (766) 0x45be70 LDR	X16, [X26, X13,LSL #3]

    (766) 0x45be74 CMP	X16, X19

    (766) 0x45be78 B.EQ	45c0c8

    (766) 0x45be7c CMP	X0, X3

    (766) 0x45be80 B.NE	45bddc

  (765) 0x45be84 SUB	X4, X4, #1

  (765) 0x45be88 CMP	X23, X4

  (765) 0x45be8c B.LE	45bb64

(759) 0x45be90 LDR	X9, [SP, #120]

(759) 0x45be94 ADD	X8, X19, #2

(759) 0x45be98 MOVZ	X2, #1

(759) 0x45be9c ADD	X1, SP, #792

(759) 0x45bea0 ADD	X0, SP, #800

(759) 0x45bea4 STR	X11, [SP, #304]

(759) 0x45bea8 LDR	X10, [SP, #224]

(759) 0x45beac STR	X8, [SP, #280]

(759) 0x45beb0 LDR	X3, [SP, #160]

(759) 0x45beb4 SUB	X14, X9, X23

(759) 0x45beb8 STR	X7, [SP, #376]

(759) 0x45bebc LDR	X4, [SP, #208]

(759) 0x45bec0 STR	X23, [X10, X19,LSL #3]

(759) 0x45bec4 LDR	X5, [SP, #400]

(759) 0x45bec8 STR	X14, [SP, #216]

(759) 0x45becc STP	X8, X30, [SP, #328]

(759) 0x45bed0 STR	X14, [SP, #800]

(759) 0x45bed4 BL	5276d0

(759) 0x45bed8 LDR	X4, [SP, #288]

(759) 0x45bedc MOVZ	X5, #0

(759) 0x45bee0 LDR	X2, [SP, #152]

(759) 0x45bee4 LDR	X7, [SP, #192]

(759) 0x45bee8 ADD	X3, X4, #8

(759) 0x45beec LDR	X11, [SP, #304]

(759) 0x45bef0 LDR	X10, [SP, #336]

(759) 0x45bef4 ADD	X15, X3, X7

(759) 0x45bef8 LDR	X13, [SP, #376]

(759) 0x45befc CMP	X2, #0

(759) 0x45bf00 B.LE	45bf58

  (763) 0x45bf04 LDP	X0, X30, [X3, #1016]

  (763) 0x45bf08 CMP	X0, X30

  (763) 0x45bf0c B.GE	45bf4c

  (763) 0x45bf10 SUB	X12, XZR, X0,LSL #3

  (763) 0x45bf14 ORR	X18, XZR, X0

  (763) 0x45bf18 ADD	X1, X12, X5,LSL #3

  (763) 0x45bf1c ADD	X6, X24, X1

    (764) 0x45bf20 LDR	X17, [X25, X0,LSL #3]

    (764) 0x45bf24 ORR	X16, XZR, X0

    (764) 0x45bf28 LDR	X8, [X22, X17,LSL #3]

    (764) 0x45bf2c STR	X8, [X6, X0,LSL #3]

    (764) 0x45bf30 ADD	X0, X0, #1

    (764) 0x45bf34 LDR	X9, [X3]

    (764) 0x45bf38 CMP	X9, X0

    (764) 0x45bf3c B.GT	45bf20

  (763) 0x45bf40 ADD	X5, X5, #1

  (763) 0x45bf44 SUB	X14, X16, X18

  (763) 0x45bf48 ADD	X5, X5, X14

  (763) 0x45bf4c ADD	X3, X3, #8

  (763) 0x45bf50 CMP	X15, X3

  (763) 0x45bf54 B.NE	45bf04

(759) 0x45bf58 LDR	X4, [SP, #816]

(759) 0x45bf5c CMP	X4, #1

(759) 0x45bf60 B.LE	45bf94

(759) 0x45bf64 LDR	X1, [SP, #344]

(759) 0x45bf68 ORR	X3, XZR, X26

(759) 0x45bf6c ORR	X2, XZR, X24

(759) 0x45bf70 MOVZ	X0, #11

(759) 0x45bf74 STR	X11, [SP, #304]

(759) 0x45bf78 STR	X10, [SP, #336]

(759) 0x45bf7c STR	X13, [SP, #376]

(759) 0x45bf80 BL	4e0364

(759) 0x45bf84 BL	4e0b6c

(759) 0x45bf88 LDR	X11, [SP, #304]

(759) 0x45bf8c LDR	X10, [SP, #336]

(759) 0x45bf90 LDR	X13, [SP, #376]

(759) 0x45bf94 LDR	X7, [SP, #792]

(759) 0x45bf98 CBZ	X7, 45f5c0

(759) 0x45bf9c CMP	X19, #8

(759) 0x45bfa0 B.EQ	45c108

(759) 0x45bfa4 CMP	X11, X10

(759) 0x45bfa8 B.GE	45bb48

0x45bfac LDR	X28, [SP, #168]

0x45bfb0 ORR	X27, XZR, X23

0x45bfb4 ORR	X23, XZR, X20

0x45bfb8 ORR	X20, XZR, X24

0x45bfbc LDR	X19, [SP, #328]

(760) 0x45bfc0 LDP	X4, X13, [SP, #208]

(760) 0x45bfc4 ADD	X19, X19, #1

(760) 0x45bfc8 MOVZ	X2, #1

(760) 0x45bfcc ADD	X1, SP, #792

(760) 0x45bfd0 ADD	X0, SP, #800

(760) 0x45bfd4 ORR	X24, XZR, X19

(760) 0x45bfd8 LDR	X15, [SP, #256]

(760) 0x45bfdc LDR	X3, [SP, #160]

(760) 0x45bfe0 LDR	X5, [SP, #400]

(760) 0x45bfe4 STR	X27, [X15, X19,LSL #3]

(760) 0x45bfe8 STR	X13, [SP, #800]

(760) 0x45bfec BL	5276d0

(760) 0x45bff0 LDR	X2, [SP, #152]

(760) 0x45bff4 CMP	X2, #0

(760) 0x45bff8 B.LE	45c064

(760) 0x45bffc LDR	X30, [SP, #288]

(760) 0x45c000 MOVZ	X11, #0

(760) 0x45c004 LDR	X12, [SP, #192]

(760) 0x45c008 ADD	X1, X30, #8

(760) 0x45c00c ADD	X18, X1, X12

  (761) 0x45c010 LDP	X0, X6, [X1, #1016]

  (761) 0x45c014 CMP	X6, X0

  (761) 0x45c018 B.LE	45c058

  (761) 0x45c01c SUB	X17, XZR, X0,LSL #3

  (761) 0x45c020 ORR	X16, XZR, X0

  (761) 0x45c024 ADD	X8, X17, X11,LSL #3

  (761) 0x45c028 ADD	X9, X20, X8

    (762) 0x45c02c LDR	X14, [X25, X0,LSL #3]

    (762) 0x45c030 ORR	X4, XZR, X0

    (762) 0x45c034 LDR	X3, [X22, X14,LSL #3]

    (762) 0x45c038 STR	X3, [X9, X0,LSL #3]

    (762) 0x45c03c ADD	X0, X0, #1

    (762) 0x45c040 LDR	X10, [X1]

    (762) 0x45c044 CMP	X10, X0

    (762) 0x45c048 B.GT	45c02c

  (761) 0x45c04c ADD	X5, X11, #1

  (761) 0x45c050 SUB	X7, X4, X16

  (761) 0x45c054 ADD	X11, X5, X7

  (761) 0x45c058 ADD	X1, X1, #8

  (761) 0x45c05c CMP	X1, X18

  (761) 0x45c060 B.NE	45c010

(760) 0x45c064 LDR	X21, [SP, #816]

(760) 0x45c068 CMP	X21, #1

(760) 0x45c06c B.LE	45c088

(760) 0x45c070 LDR	X1, [SP, #344]

(760) 0x45c074 ORR	X3, XZR, X26

(760) 0x45c078 ORR	X2, XZR, X20

(760) 0x45c07c MOVZ	X0, #11

(760) 0x45c080 BL	4e0364

(760) 0x45c084 BL	4e0b6c

(760) 0x45c088 LDR	X13, [SP, #792]

(760) 0x45c08c CBZ	X13, 45fa60

(760) 0x45c090 CMP	X19, #10

(760) 0x45c094 B.NE	45bfc0

0x45c098 ORR	X21, XZR, X23

0x45c09c B	45c114

  (771) 0x45c0a0 LDR	X3, [X30, X2]

  (771) 0x45c0a4 ADD	X0, X0, #1

  (771) 0x45c0a8 ADD	X4, X4, #1

  (771) 0x45c0ac ADD	X24, X3, #1

  (771) 0x45c0b0 STR	X24, [X30, X2]

  (771) 0x45c0b4 STR	X9, [X11]

  (771) 0x45c0b8 LDR	X3, [X21]

  (771) 0x45c0bc CMP	X3, X0

  (771) 0x45c0c0 B.GT	45b840

(722) 0x45c0c4 B	45b85c

  (765) 0x45c0c8 UBFM	X3, X23, #61, #60

  (765) 0x45c0cc ADD	X23, X23, #1

  (765) 0x45c0d0 LDR	X0, [X27, X3]

  (765) 0x45c0d4 STR	X0, [X9]

  (765) 0x45c0d8 STR	X5, [X27, X3]

  (765) 0x45c0dc STR	X7, [X22, X2]

  (765) 0x45c0e0 B	45be88

0x45c0e4 LDR	X9, [SP, #256]

0x45c0e8 STR	XZR, [SP, #264]

0x45c0ec STP	XZR, XZR, [X9]

0x45c0f0 TBZ	X27, #63, 45b7e8

0x45c0f4 MOVZ	X28, #0

0x45c0f8 MOVZ	X23, #0

0x45c0fc LDR	X24, [SP, #120]

0x45c100 STR	XZR, [SP, #200]

0x45c104 B	45ba30

0x45c108 LDR	X28, [SP, #168]

0x45c10c ORR	X21, XZR, X20

0x45c110 ORR	X20, XZR, X24

0x45c114 MOVZ	X24, #10

0x45c118 MOVZ	X23, #80

0x45c11c STR	X24, [SP, #328]

0x45c120 STR	X23, [SP, #632]

0x45c124 ORR	X0, XZR, X20

0x45c128 STR	X21, [SP, #120]

0x45c12c BL	524f40

0x45c130 MOVZ	X1, #8

0x45c134 ORR	X0, XZR, X24

0x45c138 BL	524ea8

0x45c13c ORR	X19, XZR, X0

0x45c140 LDR	X0, [SP, #200]

0x45c144 MOVZ	X1, #8

0x45c148 STR	X19, [SP, #200]

0x45c14c BL	524ea8

0x45c150 LDR	X20, [SP, #312]

0x45c154 ORR	X15, XZR, X0

0x45c158 MOVZ	X1, #8

0x45c15c STR	X15, [X19, #8]

0x45c160 ORR	X0, XZR, X20

0x45c164 BL	524ea8

0x45c168 ORR	X2, XZR, X0

0x45c16c MOVZ	X1, #8

0x45c170 ORR	X0, XZR, X20

0x45c174 STR	X2, [SP, #408]

0x45c178 BL	524ea8

0x45c17c LDR	X12, [SP, #816]

0x45c180 STR	X0, [SP, #416]

0x45c184 LDR	X6, [SP, #120]

0x45c188 CMP	X12, #1

0x45c18c B.GT	45e114

0x45c190 LDR	X30, [SP, #256]

0x45c194 MOVZ	X7, #0

0x45c198 STR	XZR, [SP, #192]

0x45c19c STR	XZR, [SP, #472]

0x45c1a0 STP	XZR, XZR, [SP, #504]

0x45c1a4 LDP	X5, X17, [X30, #8]

0x45c1a8 CMP	X5, X17

0x45c1ac B.GE	45e190

0x45c1b0 LDR	X13, [SP, #232]

0x45c1b4 MOVZ	X4, #0

0x45c1b8 LDP	X11, X27, [SP, #192]

0x45c1bc LDR	X23, [SP, #272]

0x45c1c0 LDR	X10, [SP, #320]

0x45c1c4 LDR	X18, [SP, #352]

0x45c1c8 LDR	X8, [SP, #392]

0x45c1cc LDR	X15, [SP, #480]

0x45c1d0 LDR	X12, [SP, #520]

0x45c1d4 LDR	X28, [SP, #536]

(723) 0x45c1d8 LDR	X3, [X23, X5,LSL #3]

(723) 0x45c1dc LDR	X1, [SP, #408]

(723) 0x45c1e0 LDR	X2, [SP, #416]

(723) 0x45c1e4 UBFM	X0, X3, #61, #60

(723) 0x45c1e8 ADD	X19, X0, #8

(723) 0x45c1ec STR	X4, [X1, X0]

(723) 0x45c1f0 ADD	X20, X28, X19

(723) 0x45c1f4 STR	X7, [X2, X0]

(723) 0x45c1f8 LDR	X17, [X28, X0]

(723) 0x45c1fc LDR	X2, [X28, X19]

(723) 0x45c200 CMP	X17, X2

(723) 0x45c204 B.GE	45c228

  (758) 0x45c208 LDR	X21, [X6, X17,LSL #3]

  (758) 0x45c20c UBFM	X9, X21, #61, #60

  (758) 0x45c210 LDR	X14, [X10, X9]

  (758) 0x45c214 CMP	X14, #1

  (758) 0x45c218 B.EQ	45d744

  (758) 0x45c21c ADD	X17, X17, #1

  (758) 0x45c220 CMP	X17, X2

  (758) 0x45c224 B.LT	45c208

(723) 0x45c228 LDR	X9, [X15, X0]

(723) 0x45c22c ADD	X20, X15, X19

(723) 0x45c230 LDR	X1, [X15, X19]

(723) 0x45c234 CMP	X9, X1

(723) 0x45c238 B.GE	45c260

(723) 0x45c23c HINT	#0

  (757) 0x45c240 LDR	X0, [X8, X9,LSL #3]

  (757) 0x45c244 UBFM	X19, X0, #61, #60

  (757) 0x45c248 LDR	X21, [X18, X19]

  (757) 0x45c24c CMP	X21, #1

  (757) 0x45c250 B.EQ	45d70c

  (757) 0x45c254 ADD	X9, X9, #1

  (757) 0x45c258 CMP	X9, X1

  (757) 0x45c25c B.LT	45c240

(723) 0x45c260 LDR	X3, [X30, #16]

(723) 0x45c264 ADD	X5, X5, #1

(723) 0x45c268 CMP	X3, X5

(723) 0x45c26c B.GT	45c1d8

0x45c270 LDR	X30, [SP, #128]

0x45c274 ADD	X11, X30, X4

0x45c278 STR	X11, [SP, #624]

0x45c27c LDR	X27, [SP, #816]

0x45c280 CMP	X27, #1

0x45c284 B.GT	45e008

0x45c288 LDR	X17, [SP, #328]

0x45c28c MOVZ	X24, #0

0x45c290 STR	XZR, [SP, #304]

0x45c294 STR	XZR, [SP, #336]

0x45c298 STR	XZR, [SP, #376]

0x45c29c STP	XZR, XZR, [SP, #456]

0x45c2a0 CMP	X17, #2

0x45c2a4 B.EQ	45e108

0x45c2a8 ADRP	X1,

0x45c2ac MOVZ	X5, #0

0x45c2b0 LDR	X3, [SP, #176]

0x45c2b4 MOVZ	X19, #1

0x45c2b8 MOVZ	X23, #2

0x45c2bc LDP	X21, X20, [SP, #504]

0x45c2c0 STR	X25, [SP, #560]

0x45c2c4 ORR	X25, XZR, X22

0x45c2c8 MOVN	X22, #0

0x45c2cc LDR	X27, [SP, #256]

0x45c2d0 ADD	X30, X3, #1

0x45c2d4 UBFM	X11, X30, #61, #60

0x45c2d8 STR	X24, [SP, #568]

0x45c2dc ADD	X24, X1, #524

0x45c2e0 LDR	X13, [SP, #464]

0x45c2e4 STR	X6, [SP, #736]

0x45c2e8 STR	XZR, [SP, #208]

0x45c2ec ADD	X6, X27, #8

0x45c2f0 STR	X5, [SP, #384]

0x45c2f4 STR	XZR, [SP, #528]

0x45c2f8 ADD	X27, X13, #8

0x45c2fc STR	XZR, [SP, #544]

0x45c300 STR	X22, [SP, #576]

0x45c304 STR	X7, [SP, #696]

0x45c308 STR	X11, [SP, #744]

0x45c30c STR	X6, [SP, #752]

0x45c310 STR	X24, [SP, #768]

(725) 0x45c314 LDR	X28, [SP, #816]

(725) 0x45c318 CMP	X28, #1

(725) 0x45c31c B.GT	45dac0

(725) 0x45c320 LDR	X10, [SP, #152]

(725) 0x45c324 CMP	X10, #0

(725) 0x45c328 B.LE	45c830

(725) 0x45c32c LDR	D31, [SP, #144]

(725) 0x45c330 ORR	X13, XZR, X23

(725) 0x45c334 MOVZ	X3, #0

(725) 0x45c338 LDP	X23, X24, [SP, #408]

(725) 0x45c33c MOVZ	X14, #0

(725) 0x45c340 CNTD	X22, ALL

(725) 0x45c344 STR	X26, [SP, #224]

(725) 0x45c348 LDR	X30, [SP, #288]

(725) 0x45c34c DUP	V0.2D, V31.D[0]

(725) 0x45c350 LDR	X17, [SP, #144]

(725) 0x45c354 LDR	X26, [SP, #240]

(725) 0x45c358 ADD	X15, X30, #8

(725) 0x45c35c LDR	X16, [SP, #248]

(725) 0x45c360 LDR	X18, [SP, #384]

(725) 0x45c364 LDR	X9, [SP, #560]

  (752) 0x45c368 LDR	X1, [X30, X14,LSL #3]

  (752) 0x45c36c LDR	X12, [X15, X14,LSL #3]

  (752) 0x45c370 CMP	X1, X12

  (752) 0x45c374 B.LT	45c388

  (752) 0x45c378 B	45c80c

    (753) 0x45c37c ADD	X1, X1, #1

    (753) 0x45c380 CMP	X1, X12

    (753) 0x45c384 B.GE	45c80c

    (753) 0x45c388 LDR	X28, [X9, X1,LSL #3]

    (753) 0x45c38c UBFM	X0, X28, #61, #60

    (753) 0x45c390 LDR	X10, [X25, X0]

    (753) 0x45c394 CMP	X10, X19

    (753) 0x45c398 B.NE	45c37c

    (753) 0x45c39c ADD	X12, X0, #8

    (753) 0x45c3a0 LDR	X4, [X23, X0]

    (753) 0x45c3a4 LDR	X10, [X26, X12]

    (753) 0x45c3a8 ADD	X8, X10, X4

    (753) 0x45c3ac CMP	X4, X8

    (753) 0x45c3b0 B.GE	45c670

    (753) 0x45c3b4 LDR	X7, [SP, #200]

    (753) 0x45c3b8 UBFM	X6, X3, #61, #60

    (753) 0x45c3bc ADD	X2, X4, #1

    (753) 0x45c3c0 ADD	X5, X18, X3,LSL #3

    (753) 0x45c3c4 UBFM	X28, X2, #61, #60

    (753) 0x45c3c8 STR	X6, [SP, #120]

    (753) 0x45c3cc LDR	X11, [X7, X19,LSL #3]

    (753) 0x45c3d0 ADD	X6, X11, X2,LSL #3

    (753) 0x45c3d4 SUB	X7, X5, X6

    (753) 0x45c3d8 CMP	X7, #16

    (753) 0x45c3dc B.LS	45d798

    (753) 0x45c3e0 SUB	X2, X10, #1

    (753) 0x45c3e4 CMP	X2, #2

    (753) 0x45c3e8 B.LS	45d984

    (753) 0x45c3ec UBFM	X6, X10, #2, #63

    (753) 0x45c3f0 SUB	X7, X28, #8

    (753) 0x45c3f4 UBFM	X8, X6, #59, #58

    (753) 0x45c3f8 ADD	X6, X11, X7

    (753) 0x45c3fc SUB	X28, X8, #32

    (753) 0x45c400 STR	X7, [SP, #136]

    (753) 0x45c404 MOVZ	X2, #0

    (753) 0x45c408 UBFM	X28, X28, #5, #63

    (753) 0x45c40c STR	X8, [SP, #120]

    (753) 0x45c410 ADD	X7, X5, #16

    (753) 0x45c414 ADD	X28, X28, #1

    (753) 0x45c418 ADD	X8, X6, #16

    (753) 0x45c41c ANDS	X28, X28, #0x7

    (753) 0x45c420 B.EQ	45c52c

    (753) 0x45c424 CMP	X28, #1

    (753) 0x45c428 B.EQ	45c504

    (753) 0x45c42c CMP	X28, #2

    (753) 0x45c430 B.EQ	45c4e8

    (753) 0x45c434 CMP	X28, #3

    (753) 0x45c438 B.EQ	45c4cc

    (753) 0x45c43c CMP	X28, #4

    (753) 0x45c440 B.EQ	45c4b0

    (753) 0x45c444 CMP	X28, #5

    (753) 0x45c448 B.EQ	45c494

    (753) 0x45c44c CMP	X28, #6

    (753) 0x45c450 B.EQ	45c478

    (753) 0x45c454 LDR	X2, [SP, #136]

    (753) 0x45c458 UBFM	X28, X3, #61, #60

    (753) 0x45c45c LDR	Q30, [X6, #16]

    (753) 0x45c460 LDR	Q29, [X11, X2]

    (753) 0x45c464 MOVZ	X2, #32

    (753) 0x45c468 ADD	V1.2D, V30.2D, V0.2D

    (753) 0x45c46c ADD	V2.2D, V29.2D, V0.2D

    (753) 0x45c470 STR	Q2, [X18, X28]

    (753) 0x45c474 STR	Q1, [X5, #16]

    (753) 0x45c478 LDR	Q3, [X6, X2]

    (753) 0x45c47c LDR	Q4, [X8, X2]

    (753) 0x45c480 ADD	V5.2D, V3.2D, V0.2D

    (753) 0x45c484 ADD	V6.2D, V4.2D, V0.2D

    (753) 0x45c488 STR	Q5, [X5, X2]

    (753) 0x45c48c STR	Q6, [X7, X2]

    (753) 0x45c490 ADD	X2, X2, #32

    (753) 0x45c494 LDR	Q7, [X6, X2]

    (753) 0x45c498 LDR	Q16, [X8, X2]

    (753) 0x45c49c ADD	V17.2D, V7.2D, V0.2D

    (753) 0x45c4a0 ADD	V18.2D, V16.2D, V0.2D

    (753) 0x45c4a4 STR	Q17, [X5, X2]

    (753) 0x45c4a8 STR	Q18, [X7, X2]

    (753) 0x45c4ac ADD	X2, X2, #32

    (753) 0x45c4b0 LDR	Q19, [X6, X2]

    (753) 0x45c4b4 LDR	Q20, [X8, X2]

    (753) 0x45c4b8 ADD	V21.2D, V19.2D, V0.2D

    (753) 0x45c4bc ADD	V22.2D, V20.2D, V0.2D

    (753) 0x45c4c0 STR	Q21, [X5, X2]

    (753) 0x45c4c4 STR	Q22, [X7, X2]

    (753) 0x45c4c8 ADD	X2, X2, #32

    (753) 0x45c4cc LDR	Q23, [X6, X2]

    (753) 0x45c4d0 LDR	Q24, [X8, X2]

    (753) 0x45c4d4 ADD	V25.2D, V23.2D, V0.2D

    (753) 0x45c4d8 ADD	V26.2D, V24.2D, V0.2D

    (753) 0x45c4dc STR	Q25, [X5, X2]

    (753) 0x45c4e0 STR	Q26, [X7, X2]

    (753) 0x45c4e4 ADD	X2, X2, #32

    (753) 0x45c4e8 LDR	Q27, [X6, X2]

    (753) 0x45c4ec LDR	Q28, [X8, X2]

    (753) 0x45c4f0 ADD	V31.2D, V27.2D, V0.2D

    (753) 0x45c4f4 ADD	V30.2D, V28.2D, V0.2D

    (753) 0x45c4f8 STR	Q31, [X5, X2]

    (753) 0x45c4fc STR	Q30, [X7, X2]

    (753) 0x45c500 ADD	X2, X2, #32

    (753) 0x45c504 LDR	Q1, [X6, X2]

    (753) 0x45c508 LDR	Q2, [X8, X2]

    (753) 0x45c50c LDR	X28, [SP, #120]

    (753) 0x45c510 ADD	V29.2D, V1.2D, V0.2D

    (753) 0x45c514 ADD	V3.2D, V2.2D, V0.2D

    (753) 0x45c518 STR	Q29, [X5, X2]

    (753) 0x45c51c STR	Q3, [X7, X2]

    (753) 0x45c520 ADD	X2, X2, #32

    (753) 0x45c524 CMP	X28, X2

    (753) 0x45c528 B.EQ	45c630

    (753) 0x45c52c STR	X9, [SP, #136]

    (753) 0x45c530 STP	X0, X12, [SP, #160]

    (753) 0x45c534 STR	X10, [SP, #216]

      (756) 0x45c538 LDR	Q4, [X6, X2]

      (756) 0x45c53c ADD	X0, X2, #32

      (756) 0x45c540 ADD	X28, X2, #64

      (756) 0x45c544 ADD	X12, X2, #96

      (756) 0x45c548 ADD	X10, X2, #128

      (756) 0x45c54c LDR	Q5, [X8, X2]

      (756) 0x45c550 ADD	X9, X2, #160

      (756) 0x45c554 ADD	V6.2D, V4.2D, V0.2D

      (756) 0x45c558 ADD	V7.2D, V5.2D, V0.2D

      (756) 0x45c55c STR	Q6, [X5, X2]

      (756) 0x45c560 STR	Q7, [X7, X2]

      (756) 0x45c564 LDR	Q16, [X6, X0]

      (756) 0x45c568 LDR	Q17, [X8, X0]

      (756) 0x45c56c ADD	V18.2D, V16.2D, V0.2D

      (756) 0x45c570 ADD	V19.2D, V17.2D, V0.2D

      (756) 0x45c574 STR	Q18, [X5, X0]

      (756) 0x45c578 STR	Q19, [X7, X0]

      (756) 0x45c57c ADD	X0, X2, #192

      (756) 0x45c580 LDR	Q20, [X6, X28]

      (756) 0x45c584 LDR	Q21, [X8, X28]

      (756) 0x45c588 ADD	V22.2D, V20.2D, V0.2D

      (756) 0x45c58c ADD	V23.2D, V21.2D, V0.2D

      (756) 0x45c590 STR	Q22, [X5, X28]

      (756) 0x45c594 STR	Q23, [X7, X28]

      (756) 0x45c598 ADD	X28, X2, #224

      (756) 0x45c59c ADD	X2, X2, #256

      (756) 0x45c5a0 LDR	Q24, [X6, X12]

      (756) 0x45c5a4 LDR	Q25, [X8, X12]

      (756) 0x45c5a8 ADD	V26.2D, V24.2D, V0.2D

      (756) 0x45c5ac ADD	V27.2D, V25.2D, V0.2D

      (756) 0x45c5b0 STR	Q26, [X5, X12]

      (756) 0x45c5b4 STR	Q27, [X7, X12]

      (756) 0x45c5b8 LDR	Q28, [X6, X10]

      (756) 0x45c5bc LDR	Q31, [X8, X10]

      (756) 0x45c5c0 ADD	V1.2D, V28.2D, V0.2D

      (756) 0x45c5c4 ADD	V30.2D, V31.2D, V0.2D

      (756) 0x45c5c8 STR	Q1, [X5, X10]

      (756) 0x45c5cc STR	Q30, [X7, X10]

      (756) 0x45c5d0 LDR	Q2, [X6, X9]

      (756) 0x45c5d4 LDR	Q3, [X8, X9]

      (756) 0x45c5d8 ADD	V29.2D, V2.2D, V0.2D

      (756) 0x45c5dc ADD	V4.2D, V3.2D, V0.2D

      (756) 0x45c5e0 STR	Q29, [X5, X9]

      (756) 0x45c5e4 STR	Q4, [X7, X9]

      (756) 0x45c5e8 LDR	Q5, [X6, X0]

      (756) 0x45c5ec LDR	Q6, [X8, X0]

      (756) 0x45c5f0 ADD	V7.2D, V5.2D, V0.2D

      (756) 0x45c5f4 ADD	V16.2D, V6.2D, V0.2D

      (756) 0x45c5f8 STR	Q7, [X5, X0]

      (756) 0x45c5fc STR	Q16, [X7, X0]

      (756) 0x45c600 LDR	Q17, [X6, X28]

      (756) 0x45c604 LDR	Q18, [X8, X28]

      (756) 0x45c608 ADD	V19.2D, V17.2D, V0.2D

      (756) 0x45c60c ADD	V20.2D, V18.2D, V0.2D

      (756) 0x45c610 STR	Q19, [X5, X28]

      (756) 0x45c614 STR	Q20, [X7, X28]

      (756) 0x45c618 LDR	X12, [SP, #120]

      (756) 0x45c61c CMP	X12, X2

      (756) 0x45c620 B.NE	45c538

    (753) 0x45c624 LDR	X9, [SP, #136]

    (753) 0x45c628 LDP	X0, X12, [SP, #160]

    (753) 0x45c62c LDR	X10, [SP, #216]

    (753) 0x45c630 AND	X8, X10, #0x0

    (753) 0x45c634 CMP	X8, X10

    (753) 0x45c638 B.EQ	45c66c

    (753) 0x45c63c ADD	X5, X8, X3

    (753) 0x45c640 ADD	X4, X8, X4

    (753) 0x45c644 DUP	Z21.D, X17

    (753) 0x45c648 SUB	X6, X10, X8

    (753) 0x45c64c ADD	X8, X18, X5,LSL #3

    (753) 0x45c650 WHILELO	P7.D, XZR, X6

    (753) 0x45c654 LD1D	{Z22.D}, P7/Z, [X11, X4,LSL #3]

    (753) 0x45c658 ADD	Z23.D, Z22.D, Z21.D

    (753) 0x45c65c ST1D	{Z23.D}, P7, [X8, MUL VL]

    (753) 0x45c660 ADD	X11, X11, X4,LSL #3

    (753) 0x45c664 WHILELO	P0.D, X22, X6

    (753) 0x45c668 B.NE	45d6c0

    (753) 0x45c66c ADD	X3, X10, X3

    (753) 0x45c670 LDR	X8, [X24, X0]

    (753) 0x45c674 LDR	X11, [X16, X12]

    (753) 0x45c678 ADD	X7, X8, X11

    (753) 0x45c67c CMP	X8, X7

    (753) 0x45c680 B.GE	45c7fc

    (753) 0x45c684 LDR	X4, [SP, #192]

    (753) 0x45c688 UBFM	X28, X8, #61, #60

    (753) 0x45c68c LDR	X6, [X4, X19,LSL #3]

    (753) 0x45c690 ADD	X12, X6, X7,LSL #3

    (753) 0x45c694 ADD	X2, X6, X8,LSL #3

    (753) 0x45c698 SUB	X5, X12, X2

    (753) 0x45c69c TBZ	W5, #3, 45c6b4

    (753) 0x45c6a0 LDR	X0, [X6, X28]

    (753) 0x45c6a4 LDR	X10, [X20, #8]

    (753) 0x45c6a8 CMP	X0, X10

    (753) 0x45c6ac B.GE	45c764

    (753) 0x45c6b0 B	45d694

      (754) 0x45c6b4 LDR	X7, [X2]

      (754) 0x45c6b8 LDR	X6, [X20, #8]

      (754) 0x45c6bc CMP	X7, X6

      (754) 0x45c6c0 B.LT	45d76c

      (754) 0x45c6c4 CMP	X19, #1

      (754) 0x45c6c8 B.EQ	45c750

      (754) 0x45c6cc LDR	X5, [X20, #16]

      (754) 0x45c6d0 CMP	X5, X7

      (754) 0x45c6d4 B.GT	45d91c

      (754) 0x45c6d8 CMP	X19, #2

      (754) 0x45c6dc B.EQ	45c750

      (754) 0x45c6e0 LDR	X10, [X20, #24]

      (754) 0x45c6e4 CMP	X10, X7

      (754) 0x45c6e8 B.GT	45d924

      (754) 0x45c6ec CMP	X19, #3

      (754) 0x45c6f0 B.EQ	45c750

      (754) 0x45c6f4 LDR	X8, [X20, #32]

      (754) 0x45c6f8 CMP	X7, X8

      (754) 0x45c6fc B.LT	45d93c

      (754) 0x45c700 CMP	X19, #4

      (754) 0x45c704 B.EQ	45c750

      (754) 0x45c708 LDR	X4, [X20, #40]

      (754) 0x45c70c CMP	X7, X4

      (754) 0x45c710 B.LT	45d944

      (754) 0x45c714 CMP	X19, #5

      (754) 0x45c718 B.EQ	45c750

      (754) 0x45c71c LDR	X11, [X20, #48]

      (754) 0x45c720 CMP	X7, X11

      (754) 0x45c724 B.LT	45d95c

      (754) 0x45c728 CMP	X19, #6

      (754) 0x45c72c B.EQ	45c750

      (754) 0x45c730 LDR	X0, [X20, #56]

      (754) 0x45c734 CMP	X7, X0

      (754) 0x45c738 B.LT	45d974

      (754) 0x45c73c CMP	X19, #8

      (754) 0x45c740 B.NE	45c750

      (754) 0x45c744 LDR	X28, [X20, #64]

      (754) 0x45c748 CMP	X28, X7

      (754) 0x45c74c B.GT	45d97c

      (754) 0x45c750 LDR	X0, [X2, #8]

      (754) 0x45c754 ADD	X2, X2, #8

      (754) 0x45c758 LDR	X11, [X20, #8]

      (754) 0x45c75c CMP	X0, X11

      (754) 0x45c760 B.LT	45d694

      (754) 0x45c764 CMP	X19, #1

      (754) 0x45c768 B.EQ	45c7f0

      (754) 0x45c76c LDR	X28, [X20, #16]

      (754) 0x45c770 CMP	X28, X0

      (754) 0x45c774 B.GT	45d790

      (754) 0x45c778 CMP	X19, #2

      (754) 0x45c77c B.EQ	45c7f0

      (754) 0x45c780 LDR	X6, [X20, #24]

      (754) 0x45c784 CMP	X6, X0

      (754) 0x45c788 B.GT	45d914

      (754) 0x45c78c CMP	X19, #3

      (754) 0x45c790 B.EQ	45c7f0

      (754) 0x45c794 LDR	X5, [X20, #32]

      (754) 0x45c798 CMP	X0, X5

      (754) 0x45c79c B.LT	45d92c

      (754) 0x45c7a0 CMP	X19, #4

      (754) 0x45c7a4 B.EQ	45c7f0

      (754) 0x45c7a8 LDR	X10, [X20, #40]

      (754) 0x45c7ac CMP	X0, X10

      (754) 0x45c7b0 B.LT	45d934

      (754) 0x45c7b4 CMP	X19, #5

      (754) 0x45c7b8 B.EQ	45c7f0

      (754) 0x45c7bc LDR	X8, [X20, #48]

      (754) 0x45c7c0 CMP	X0, X8

      (754) 0x45c7c4 B.LT	45d94c

      (754) 0x45c7c8 CMP	X19, #6

      (754) 0x45c7cc B.EQ	45c7f0

      (754) 0x45c7d0 LDR	X7, [X20, #56]

      (754) 0x45c7d4 CMP	X0, X7

      (754) 0x45c7d8 B.LT	45d964

      (754) 0x45c7dc CMP	X19, #8

      (754) 0x45c7e0 B.NE	45c7f0

      (754) 0x45c7e4 LDR	X4, [X20, #64]

      (754) 0x45c7e8 CMP	X4, X0

      (754) 0x45c7ec B.GT	45d96c

      (754) 0x45c7f0 ADD	X2, X2, #8

      (754) 0x45c7f4 CMP	X2, X12

      (754) 0x45c7f8 B.NE	45c6b4

    (753) 0x45c7fc LDR	X12, [X15, X14,LSL #3]

    (753) 0x45c800 ADD	X1, X1, #1

    (753) 0x45c804 CMP	X1, X12

    (753) 0x45c808 B.LT	45c388

  (752) 0x45c80c LDR	X6, [SP, #152]

  (752) 0x45c810 ADD	X14, X14, #1

  (752) 0x45c814 CMP	X6, X14

  (752) 0x45c818 B.GT	45c368

(725) 0x45c81c LDR	X26, [SP, #224]

(725) 0x45c820 ORR	X23, XZR, X13

(725) 0x45c824 LDR	X3, [SP, #816]

(725) 0x45c828 CMP	X3, #1

(725) 0x45c82c B.GT	45d99c

(725) 0x45c830 LDR	X22, [SP, #176]

(725) 0x45c834 CMP	X22, #0

(725) 0x45c838 B.LE	45c9f0

(725) 0x45c83c ORR	X15, XZR, X23

(725) 0x45c840 ORR	X23, XZR, X27

(725) 0x45c844 LDR	X27, [SP, #664]

(725) 0x45c848 MOVZ	X30, #0

(725) 0x45c84c MOVZ	X14, #0

(725) 0x45c850 STR	X25, [SP, #776]

(725) 0x45c854 LDR	X9, [SP, #568]

(725) 0x45c858 MOVZ	X6, #0

(725) 0x45c85c ORR	X17, XZR, X14

(725) 0x45c860 ORR	X25, XZR, X6

(725) 0x45c864 ORR	X22, XZR, X19

(725) 0x45c868 STP	X20, X30, [SP, #160]

(725) 0x45c86c ORR	X20, XZR, X26

(725) 0x45c870 ADD	X0, X27, #8

(725) 0x45c874 ORR	X28, XZR, X0

(725) 0x45c878 HINT	#0

(725) 0x45c87c HINT	#0

  (724) 0x45c880 LDP	X19, X27, [X28, #1016]

  (724) 0x45c884 CMP	X19, X27

  (724) 0x45c888 B.GE	45c9ac

  (724) 0x45c88c ORR	X24, XZR, X23

  (724) 0x45c890 ORR	X18, XZR, X19

  (724) 0x45c894 STR	X25, [SP, #280]

  (724) 0x45c898 ORR	X23, XZR, X9

  (724) 0x45c89c ORR	X3, XZR, X20

  (724) 0x45c8a0 ORR	X16, XZR, X15

  (724) 0x45c8a4 B	45c8b4

    (746) 0x45c8a8 ADD	X18, X18, #1

    (746) 0x45c8ac CMP	X18, X27

    (746) 0x45c8b0 B.GE	45c998

    (746) 0x45c8b4 LDR	X20, [X3, X18,LSL #3]

    (746) 0x45c8b8 CMP	X20, X22

    (746) 0x45c8bc B.NE	45c8a8

    (746) 0x45c8c0 LDR	X26, [X24, X18,LSL #3]

    (746) 0x45c8c4 ADD	X2, X17, X26

    (746) 0x45c8c8 CMP	X2, X17

    (746) 0x45c8cc B.LE	45d954

    (746) 0x45c8d0 LDR	X10, [X23, X16,LSL #3]

    (746) 0x45c8d4 ORR	X26, XZR, X17

    (746) 0x45c8d8 ORR	X27, XZR, X18

    (746) 0x45c8dc ORR	X25, XZR, X16

    (746) 0x45c8e0 STR	X22, [SP, #120]

    (746) 0x45c8e4 STR	X17, [SP, #136]

    (746) 0x45c8e8 STP	X3, X28, [SP, #216]

    (746) 0x45c8ec B	45c910

      (747) 0x45c8f0 ORN	X14, XZR, X18

      (747) 0x45c8f4 STR	X14, [X10, X20]

      (747) 0x45c8f8 LDR	X6, [X24, X27,LSL #3]

      (747) 0x45c8fc ADD	X26, X26, #1

      (747) 0x45c900 LDR	X2, [SP, #136]

      (747) 0x45c904 ADD	X17, X2, X6

      (747) 0x45c908 CMP	X17, X26

      (747) 0x45c90c B.LE	45c978

      (747) 0x45c910 UBFM	X20, X26, #61, #60

      (747) 0x45c914 LDR	X16, [SP, #144]

      (747) 0x45c918 LDR	X22, [X10, X20]

      (747) 0x45c91c LDR	X3, [SP, #128]

      (747) 0x45c920 SUBS	X18, X22, X16

      (747) 0x45c924 CCMP	X18, X3, #0, #5

      (747) 0x45c928 B.LT	45c8f0

      (747) 0x45c92c LDR	X28, [SP, #160]

      (747) 0x45c930 MOVZ	X19, #0

        (748) 0x45c934 LDP	X15, X9, [X28]

        (748) 0x45c938 ORR	X1, XZR, X22

        (748) 0x45c93c LDR	X0, [X21, X19,LSL #3]

        (748) 0x45c940 ADD	X19, X19, #1

        (748) 0x45c944 SUB	X2, X9, X15

        (748) 0x45c948 BL	5236a0

        (748) 0x45c94c TBNZ	X0, #63, 45d6d0

      (747) 0x45c950 LDR	X1, [X28]

      (747) 0x45c954 ADD	X26, X26, #1

      (747) 0x45c958 LDR	X10, [X23, X25,LSL #3]

      (747) 0x45c95c LDR	X2, [SP, #136]

      (747) 0x45c960 ADD	X30, X1, X0

      (747) 0x45c964 STR	X30, [X10, X20]

      (747) 0x45c968 LDR	X6, [X24, X27,LSL #3]

      (747) 0x45c96c ADD	X17, X2, X6

      (747) 0x45c970 CMP	X17, X26

      (747) 0x45c974 B.GT	45c910

    (746) 0x45c978 LDP	X3, X28, [SP, #216]

    (746) 0x45c97c ORR	X18, XZR, X27

    (746) 0x45c980 ORR	X16, XZR, X25

    (746) 0x45c984 ADD	X18, X18, #1

    (746) 0x45c988 LDR	X22, [SP, #120]

    (746) 0x45c98c LDR	X27, [X28]

    (746) 0x45c990 CMP	X18, X27

    (746) 0x45c994 B.LT	45c8b4

  (724) 0x45c998 LDR	X25, [SP, #280]

  (724) 0x45c99c ORR	X9, XZR, X23

  (724) 0x45c9a0 ORR	X15, XZR, X16

  (724) 0x45c9a4 ORR	X20, XZR, X3

  (724) 0x45c9a8 ORR	X23, XZR, X24

  (724) 0x45c9ac LDR	X19, [SP, #176]

  (724) 0x45c9b0 ADD	X25, X25, #1

  (724) 0x45c9b4 ADD	X28, X28, #8

  (724) 0x45c9b8 CMP	X19, X25

  (724) 0x45c9bc B.NE	45c880

(725) 0x45c9c0 ORR	X26, XZR, X20

(725) 0x45c9c4 LDP	X20, X5, [SP, #160]

(725) 0x45c9c8 ORR	X27, XZR, X23

(725) 0x45c9cc ORR	X19, XZR, X22

(725) 0x45c9d0 ORR	X23, XZR, X15

(725) 0x45c9d4 LDR	X25, [SP, #776]

(725) 0x45c9d8 CBNZ	X5, 45dee8

(725) 0x45c9dc LDR	X0, [SP, #816]

(725) 0x45c9e0 CMP	X0, #1

(725) 0x45c9e4 B.LE	45c9f0

(725) 0x45c9e8 LDR	X10, [X20, X19,LSL #3]

(725) 0x45c9ec STR	X10, [X20, X23,LSL #3]

(725) 0x45c9f0 LDR	X22, [SP, #256]

(725) 0x45c9f4 MOVZ	W3, #0

(725) 0x45c9f8 MOVZ	W2, #0

(725) 0x45c9fc ADD	X19, X19, #1

(725) 0x45ca00 LDR	X0, [SP, #752]

(725) 0x45ca04 LDR	X15, [SP, #200]

(725) 0x45ca08 LDR	X4, [SP, #240]

(725) 0x45ca0c LDR	X7, [SP, #248]

(725) 0x45ca10 LDR	X17, [SP, #272]

(725) 0x45ca14 LDR	X16, [SP, #392]

(725) 0x45ca18 LDR	X6, [SP, #408]

(725) 0x45ca1c LDR	X18, [SP, #416]

(725) 0x45ca20 LDR	X30, [SP, #456]

(725) 0x45ca24 LDR	X24, [SP, #472]

(725) 0x45ca28 LDR	X14, [SP, #480]

(725) 0x45ca2c LDR	X28, [SP, #536]

(725) 0x45ca30 LDR	X5, [SP, #576]

(725) 0x45ca34 LDR	X13, [SP, #736]

(725) 0x45ca38 LDR	X10, [X0, X23,LSL #3]

(725) 0x45ca3c CMP	X5, X24

(725) 0x45ca40 CSINC	X8, X24, X5, #11

(725) 0x45ca44 STR	X8, [SP, #472]

(725) 0x45ca48 LDR	X12, [X22, X23,LSL #3]

(725) 0x45ca4c STR	X28, [SP, #832]

(725) 0x45ca50 LDR	X9, [SP, #192]

(725) 0x45ca54 STR	X13, [SP, #840]

(725) 0x45ca58 STR	X14, [SP, #848]

(725) 0x45ca5c STR	X16, [SP, #856]

(725) 0x45ca60 SUB	X11, X10, X12

(725) 0x45ca64 ADD	X12, SP, #816

(725) 0x45ca68 STR	X4, [SP, #864]

(725) 0x45ca6c STR	X7, [SP, #872]

(725) 0x45ca70 STR	X30, [SP, #880]

(725) 0x45ca74 STR	X17, [SP, #888]

(725) 0x45ca78 STR	X22, [SP, #896]

(725) 0x45ca7c ADD	X22, SP, #984

(725) 0x45ca80 STR	X6, [SP, #904]

(725) 0x45ca84 STR	X18, [SP, #912]

(725) 0x45ca88 STR	X15, [SP, #920]

(725) 0x45ca8c LDR	X1, [SP, #296]

(725) 0x45ca90 STR	X9, [SP, #928]

(725) 0x45ca94 STR	X23, [SP, #960]

(725) 0x45ca98 ADD	X23, X23, #1

(725) 0x45ca9c STP	X25, X26, [X22]

(725) 0x45caa0 STP	X5, X8, [X22, #32]

(725) 0x45caa4 LDR	X0, [SP, #640]

(725) 0x45caa8 STR	X11, [SP, #1032]

(725) 0x45caac LDR	X28, [SP, #128]

(725) 0x45cab0 STR	X12, [SP, #1000]

(725) 0x45cab4 LDR	X10, [SP, #464]

(725) 0x45cab8 STR	X0, [SP, #1040]

(725) 0x45cabc LDR	X24, [SP, #488]

(725) 0x45cac0 STR	X28, [SP, #968]

(725) 0x45cac4 LDR	X5, [SP, #568]

(725) 0x45cac8 STR	X10, [SP, #944]

(725) 0x45cacc LDR	X11, [SP, #624]

(725) 0x45cad0 STR	X24, [SP, #976]

(725) 0x45cad4 LDR	X8, [SP, #648]

(725) 0x45cad8 STR	X5, [SP, #936]

(725) 0x45cadc LDR	X4, [SP, #656]

(725) 0x45cae0 STR	X11, [SP, #952]

(725) 0x45cae4 LDR	X7, [SP, #696]

(725) 0x45cae8 STR	X8, [SP, #1048]

(725) 0x45caec LDR	X0, [SP, #768]

(725) 0x45caf0 STR	X4, [SP, #1056]

(725) 0x45caf4 STR	X7, [SP, #1008]

(725) 0x45caf8 BL	4103b0

(725) 0x45cafc LDR	X3, [SP, #952]

(725) 0x45cb00 LDR	X2, [SP, #1008]

(725) 0x45cb04 LDR	X1, [SP, #328]

(725) 0x45cb08 STR	X3, [SP, #624]

(725) 0x45cb0c STR	X2, [SP, #696]

(725) 0x45cb10 CMP	X1, X23

(725) 0x45cb14 B.NE	45c314

0x45cb18 LDR	X16, [SP, #384]

0x45cb1c ORR	X22, XZR, X25

0x45cb20 LDR	X25, [SP, #560]

0x45cb24 LDR	X24, [SP, #568]

0x45cb28 LDR	X7, [SP, #696]

0x45cb2c LDR	X6, [SP, #736]

0x45cb30 STR	X16, [SP, #120]

0x45cb34 MOVZ	X28, #0

0x45cb38 LDR	X0, [SP, #208]

0x45cb3c STR	X6, [SP, #136]

0x45cb40 STR	X7, [SP, #160]

0x45cb44 BL	524f40

0x45cb48 LDR	X0, [SP, #376]

0x45cb4c BL	524f40

0x45cb50 LDR	X0, [SP, #120]

0x45cb54 BL	524f40

0x45cb58 LDR	X0, [SP, #672]

0x45cb5c BL	524f40

0x45cb60 LDR	X0, [SP, #648]

0x45cb64 BL	524f40

0x45cb68 LDR	X0, [SP, #656]

0x45cb6c BL	524f40

0x45cb70 LDR	X0, [SP, #640]

0x45cb74 BL	524f40

0x45cb78 LDR	X21, [SP, #624]

0x45cb7c MOVZ	X1, #8

0x45cb80 ORR	X0, XZR, X21

0x45cb84 BL	524ea8

0x45cb88 ORR	X27, XZR, X0

0x45cb8c MOVZ	X1, #8

0x45cb90 ORR	X0, XZR, X21

0x45cb94 STR	X27, [SP, #144]

0x45cb98 BL	524ea8

0x45cb9c LDR	X20, [SP, #160]

0x45cba0 ORR	X27, XZR, X0

0x45cba4 STR	XZR, [SP, #120]

0x45cba8 LDR	X6, [SP, #136]

0x45cbac CBNZ	X20, 45e210

0x45cbb0 LDR	X13, [SP, #312]

0x45cbb4 CMP	X13, #0

0x45cbb8 B.LE	45cd28

0x45cbbc LDR	X14, [SP, #760]

0x45cbc0 MOVZ	X0, #8

0x45cbc4 LDR	X30, [SP, #240]

0x45cbc8 LDR	X9, [SP, #248]

0x45cbcc UBFM	X7, X14, #61, #60

0x45cbd0 SUB	X17, X7, #16

0x45cbd4 UBFM	X16, X17, #3, #63

0x45cbd8 SUB	X3, X30, #8

0x45cbdc ADD	X18, X16, #1

0x45cbe0 ANDS	X15, X18, #0x3

0x45cbe4 SUB	X2, X9, #8

0x45cbe8 B.EQ	45f598

0x45cbec CMP	X15, #1

0x45cbf0 B.EQ	45cc54

0x45cbf4 CMP	X15, #2

0x45cbf8 B.EQ	45cc28

0x45cbfc LDR	X5, [SP, #240]

0x45cc00 MOVZ	X0, #16

0x45cc04 LDR	X23, [X3, #8]

0x45cc08 LDR	X11, [SP, #248]

0x45cc0c LDR	X10, [X5, #8]

0x45cc10 ADD	X8, X10, X23

0x45cc14 STR	X8, [X5, #8]

0x45cc18 LDR	X12, [X2, #8]

0x45cc1c LDR	X4, [X11, #8]

0x45cc20 ADD	X1, X4, X12

0x45cc24 STR	X1, [X11, #8]

0x45cc28 LDR	X20, [SP, #240]

0x45cc2c LDR	X21, [X3, X0]

0x45cc30 LDR	X14, [SP, #248]

0x45cc34 LDR	X19, [X20, X0]

0x45cc38 ADD	X13, X19, X21

0x45cc3c STR	X13, [X20, X0]

0x45cc40 LDR	X30, [X2, X0]

0x45cc44 LDR	X17, [X14, X0]

0x45cc48 ADD	X16, X17, X30

0x45cc4c STR	X16, [X14, X0]

0x45cc50 ADD	X0, X0, #8

0x45cc54 LDR	X15, [SP, #240]

0x45cc58 LDR	X18, [X3, X0]

0x45cc5c LDR	X5, [SP, #248]

0x45cc60 LDR	X9, [X15, X0]

0x45cc64 ADD	X23, X9, X18

0x45cc68 STR	X23, [X15, X0]

0x45cc6c LDR	X10, [X2, X0]

0x45cc70 LDR	X8, [X5, X0]

0x45cc74 ADD	X12, X8, X10

0x45cc78 STR	X12, [X5, X0]

0x45cc7c ADD	X0, X0, #8

0x45cc80 CMP	X7, X0

0x45cc84 B.EQ	45cd28

0x45cc88 LDR	X1, [SP, #240]

0x45cc8c ORR	X4, XZR, X5

(744) 0x45cc90 ADD	X20, X0, #8

(744) 0x45cc94 ADD	X13, X0, #16

(744) 0x45cc98 LDR	X21, [X1, X0]

(744) 0x45cc9c ADD	X19, X0, #24

(744) 0x45cca0 LDR	X11, [X3, X0]

(744) 0x45cca4 ADD	X30, X21, X11

(744) 0x45cca8 STR	X30, [X1, X0]

(744) 0x45ccac LDR	X14, [X4, X0]

(744) 0x45ccb0 LDR	X17, [X2, X0]

(744) 0x45ccb4 ADD	X16, X14, X17

(744) 0x45ccb8 STR	X16, [X4, X0]

(744) 0x45ccbc ADD	X0, X0, #32

(744) 0x45ccc0 LDR	X18, [X1, X20]

(744) 0x45ccc4 LDR	X15, [X3, X20]

(744) 0x45ccc8 ADD	X9, X18, X15

(744) 0x45cccc STR	X9, [X1, X20]

(744) 0x45ccd0 LDR	X23, [X4, X20]

(744) 0x45ccd4 LDR	X10, [X2, X20]

(744) 0x45ccd8 ADD	X5, X23, X10

(744) 0x45ccdc STR	X5, [X4, X20]

(744) 0x45cce0 LDR	X8, [X1, X13]

(744) 0x45cce4 LDR	X12, [X3, X13]

(744) 0x45cce8 ADD	X21, X8, X12

(744) 0x45ccec STR	X21, [X1, X13]

(744) 0x45ccf0 LDR	X20, [X4, X13]

(744) 0x45ccf4 LDR	X11, [X2, X13]

(744) 0x45ccf8 ADD	X30, X20, X11

(744) 0x45ccfc STR	X30, [X4, X13]

(744) 0x45cd00 LDR	X13, [X1, X19]

(744) 0x45cd04 LDR	X14, [X3, X19]

(744) 0x45cd08 ADD	X17, X13, X14

(744) 0x45cd0c STR	X17, [X1, X19]

(744) 0x45cd10 LDR	X16, [X4, X19]

(744) 0x45cd14 LDR	X18, [X2, X19]

(744) 0x45cd18 ADD	X15, X16, X18

(744) 0x45cd1c STR	X15, [X4, X19]

(744) 0x45cd20 CMP	X7, X0

(744) 0x45cd24 B.NE	45cc90

0x45cd28 LDR	X19, [SP, #128]

0x45cd2c ADRP	X0,

0x45cd30 MOVZ	W3, #0

0x45cd34 STR	X6, [SP, #136]

0x45cd38 MOVZ	W2, #0

0x45cd3c ADD	X0, X0, #3152

0x45cd40 LDR	X7, [SP, #144]

0x45cd44 STR	X27, [SP, #832]

0x45cd48 LDR	X9, [SP, #232]

0x45cd4c STR	X19, [SP, #864]

0x45cd50 LDR	X4, [SP, #240]

0x45cd54 STR	X7, [SP, #848]

0x45cd58 LDR	X6, [SP, #360]

0x45cd5c STR	X9, [SP, #872]

0x45cd60 LDR	X1, [SP, #296]

0x45cd64 STR	X4, [SP, #840]

0x45cd68 STR	X6, [SP, #856]

0x45cd6c BL	4103b0

0x45cd70 LDR	X2, [SP, #256]

0x45cd74 LDR	X5, [SP, #1168]

0x45cd78 LDR	X23, [SP, #136]

0x45cd7c LDP	X3, X1, [X2, #8]

0x45cd80 SUB	X10, X1, X3

0x45cd84 CBZ	X5, 45e264

0x45cd88 LDR	X16, [SP, #144]

0x45cd8c ADRP	X21,

0x45cd90 MOVZ	W2, #0

0x45cd94 ADD	X0, X21, #2372

0x45cd98 STR	X23, [SP, #136]

0x45cd9c MOVZ	W3, #0

0x45cda0 LDR	X8, [SP, #184]

0x45cda4 STR	X27, [SP, #920]

0x45cda8 LDR	X13, [SP, #240]

0x45cdac STR	X16, [SP, #936]

0x45cdb0 LDR	X9, [SP, #248]

0x45cdb4 STR	X8, [SP, #912]

0x45cdb8 LDR	X19, [SP, #320]

0x45cdbc STR	X13, [SP, #928]

0x45cdc0 LDR	X11, [SP, #432]

0x45cdc4 STR	X28, [SP, #944]

0x45cdc8 LDR	X12, [SP, #440]

0x45cdcc STR	X19, [SP, #832]

0x45cdd0 LDR	X17, [SP, #448]

0x45cdd4 STR	X11, [SP, #840]

0x45cdd8 LDR	X30, [SP, #584]

0x45cddc STR	X12, [SP, #888]

0x45cde0 LDR	X15, [SP, #592]

0x45cde4 STR	X17, [SP, #904]

0x45cde8 LDR	X7, [SP, #600]

0x45cdec STR	X30, [SP, #848]

0x45cdf0 LDR	X6, [SP, #608]

0x45cdf4 STR	X15, [SP, #864]

0x45cdf8 LDR	X5, [SP, #616]

0x45cdfc STR	X7, [SP, #872]

0x45ce00 LDR	X14, [SP, #1176]

0x45ce04 STR	X6, [SP, #880]

0x45ce08 LDR	X1, [SP, #296]

0x45ce0c STR	X5, [SP, #896]

0x45ce10 STR	X9, [SP, #952]

0x45ce14 STR	X14, [SP, #856]

0x45ce18 LDR	X18, [SP, #120]

0x45ce1c STR	X10, [SP, #1080]

0x45ce20 LDR	X15, [SP, #192]

0x45ce24 LDR	X14, [SP, #200]

0x45ce28 STR	X18, [SP, #960]

0x45ce2c LDR	X5, [SP, #232]

0x45ce30 STR	X15, [SP, #1040]

0x45ce34 LDR	X19, [SP, #256]

0x45ce38 STR	X14, [SP, #1032]

0x45ce3c LDR	X6, [SP, #264]

0x45ce40 STR	X5, [SP, #1072]

0x45ce44 LDR	X21, [SP, #272]

0x45ce48 STR	X19, [SP, #1008]

0x45ce4c LDR	X12, [SP, #312]

0x45ce50 STR	X6, [SP, #1056]

0x45ce54 LDR	X10, [SP, #352]

0x45ce58 STR	X21, [SP, #1000]

0x45ce5c LDR	X20, [SP, #360]

0x45ce60 STR	X12, [SP, #1064]

0x45ce64 LDR	X30, [SP, #408]

0x45ce68 STR	X10, [SP, #968]

0x45ce6c LDR	X11, [SP, #416]

0x45ce70 STR	X20, [SP, #984]

0x45ce74 LDR	X23, [SP, #424]

0x45ce78 STR	X30, [SP, #1016]

0x45ce7c LDR	X4, [SP, #496]

0x45ce80 STR	X11, [SP, #1024]

0x45ce84 LDR	X7, [SP, #520]

0x45ce88 STR	X23, [SP, #976]

0x45ce8c STR	X4, [SP, #992]

0x45ce90 STR	X7, [SP, #1048]

0x45ce94 BL	4103b0

0x45ce98 LDP	X2, X1, [SP, #128]

0x45ce9c CBNZ	X2, 45f7cc

0x45cea0 STR	X1, [SP, #136]

0x45cea4 LDR	X0, [SP, #496]

0x45cea8 BL	524f40

0x45ceac LDR	X23, [SP, #200]

0x45ceb0 LDR	X0, [X23, #8]

0x45ceb4 BL	524f40

0x45ceb8 LDR	X3, [SP, #816]

0x45cebc STR	XZR, [X23, #8]

0x45cec0 LDR	X13, [SP, #136]

0x45cec4 CMP	X3, #1

0x45cec8 B.LE	45cee0

0x45cecc LDR	X20, [SP, #192]

0x45ced0 LDR	X0, [X20, #8]

0x45ced4 BL	524f40

0x45ced8 LDR	X13, [SP, #136]

0x45cedc STR	XZR, [X20, #8]

0x45cee0 LDR	X17, [SP, #328]

0x45cee4 CMP	X17, #2

0x45cee8 B.EQ	45f7c0

0x45ceec LDR	X18, [SP, #152]

0x45cef0 ADRP	X9,

0x45cef4 MOVZ	X16, #0

0x45cef8 ADD	X10, X9, #1824

0x45cefc MOVZ	X19, #0

0x45cf00 STR	XZR, [SP, #136]

0x45cf04 LDR	X30, [SP, #176]

0x45cf08 MOVZ	X20, #1

0x45cf0c MOVZ	X23, #2

0x45cf10 STR	XZR, [SP, #160]

0x45cf14 LDR	X14, [SP, #256]

0x45cf18 UBFM	X4, X18, #61, #60

0x45cf1c STP	X16, X26, [SP, #208]

0x45cf20 UBFM	X11, X30, #61, #60

0x45cf24 LDR	X7, [SP, #288]

0x45cf28 ADD	X15, X14, #8

0x45cf2c LDP	X26, X21, [SP, #240]

0x45cf30 STR	X4, [SP, #280]

0x45cf34 ADD	X6, X7, #8

0x45cf38 STR	X11, [SP, #344]

0x45cf3c STR	X10, [SP, #360]

0x45cf40 STR	X6, [SP, #376]

0x45cf44 STR	X15, [SP, #384]

0x45cf48 STR	X13, [SP, #496]

0x45cf4c B	45d0f0

(737) 0x45cf50 LDR	X5, [SP, #256]

(737) 0x45cf54 ADD	X9, SP, #952

(737) 0x45cf58 MOVZ	W3, #0

(737) 0x45cf5c MOVZ	W2, #0

(737) 0x45cf60 LDR	X10, [SP, #384]

(737) 0x45cf64 LDR	X8, [SP, #480]

(737) 0x45cf68 LDR	X18, [SP, #144]

(737) 0x45cf6c LDR	X13, [X10, X23,LSL #3]

(737) 0x45cf70 LDR	X16, [X5, X23,LSL #3]

(737) 0x45cf74 STR	X8, [SP, #928]

(737) 0x45cf78 LDR	X1, [SP, #296]

(737) 0x45cf7c LDR	X0, [SP, #360]

(737) 0x45cf80 STP	X27, X26, [X9]

(737) 0x45cf84 SUB	X17, X13, X16

(737) 0x45cf88 STP	X18, X28, [X9, #16]

(737) 0x45cf8c LDR	X4, [SP, #120]

(737) 0x45cf90 STR	X5, [SP, #1032]

(737) 0x45cf94 LDR	X14, [SP, #184]

(737) 0x45cf98 STR	X21, [SP, #984]

(737) 0x45cf9c LDR	X5, [SP, #272]

(737) 0x45cfa0 STR	X4, [SP, #992]

(737) 0x45cfa4 LDR	X6, [SP, #352]

(737) 0x45cfa8 STR	X14, [SP, #944]

(737) 0x45cfac LDR	X30, [SP, #392]

(737) 0x45cfb0 STR	X5, [SP, #1024]

(737) 0x45cfb4 LDR	X11, [SP, #408]

(737) 0x45cfb8 STR	X6, [SP, #1008]

(737) 0x45cfbc LDR	X15, [SP, #416]

(737) 0x45cfc0 STR	X30, [SP, #936]

(737) 0x45cfc4 LDR	X12, [SP, #424]

(737) 0x45cfc8 STR	X11, [SP, #1040]

(737) 0x45cfcc LDR	X7, [SP, #456]

(737) 0x45cfd0 STR	X15, [SP, #1048]

(737) 0x45cfd4 STR	X24, [SP, #1072]

(737) 0x45cfd8 STR	X12, [SP, #1016]

(737) 0x45cfdc STR	X7, [SP, #1000]

(737) 0x45cfe0 STR	X23, [SP, #1096]

(737) 0x45cfe4 LDR	X30, [SP, #128]

(737) 0x45cfe8 LDP	X10, X8, [SP, #192]

(737) 0x45cfec STR	X17, [SP, #1160]

(737) 0x45cff0 LDR	X7, [SP, #136]

(737) 0x45cff4 STR	X8, [SP, #1056]

(737) 0x45cff8 LDR	X15, [SP, #216]

(737) 0x45cffc STR	X10, [SP, #1064]

(737) 0x45d000 LDR	X17, [SP, #264]

(737) 0x45d004 STR	X30, [SP, #1112]

(737) 0x45d008 LDR	X9, [SP, #312]

(737) 0x45d00c STR	X22, [SP, #1128]

(737) 0x45d010 LDR	X18, [SP, #320]

(737) 0x45d014 STR	X17, [SP, #1088]

(737) 0x45d018 LDR	X4, [SP, #432]

(737) 0x45d01c STR	X9, [SP, #1104]

(737) 0x45d020 LDR	X13, [SP, #464]

(737) 0x45d024 STR	X18, [SP, #832]

(737) 0x45d028 LDR	X6, [SP, #472]

(737) 0x45d02c STR	X4, [SP, #840]

(737) 0x45d030 LDR	X14, [SP, #488]

(737) 0x45d034 STR	X13, [SP, #1080]

(737) 0x45d038 LDR	X16, [SP, #496]

(737) 0x45d03c STR	X15, [SP, #1136]

(737) 0x45d040 LDR	X11, [SP, #584]

(737) 0x45d044 STR	X14, [SP, #1120]

(737) 0x45d048 LDR	X12, [SP, #1176]

(737) 0x45d04c STR	X16, [SP, #920]

(737) 0x45d050 STR	X7, [SP, #1144]

(737) 0x45d054 STR	X11, [SP, #848]

(737) 0x45d058 STR	X6, [SP, #1152]

(737) 0x45d05c STR	X12, [SP, #856]

(737) 0x45d060 LDR	X5, [SP, #592]

(737) 0x45d064 LDR	X13, [SP, #440]

(737) 0x45d068 LDR	X17, [SP, #448]

(737) 0x45d06c STR	X5, [SP, #864]

(737) 0x45d070 LDR	X18, [SP, #536]

(737) 0x45d074 STR	X13, [SP, #888]

(737) 0x45d078 LDR	X10, [SP, #600]

(737) 0x45d07c STR	X17, [SP, #904]

(737) 0x45d080 LDR	X8, [SP, #608]

(737) 0x45d084 STR	X18, [SP, #912]

(737) 0x45d088 LDR	X16, [SP, #616]

(737) 0x45d08c STR	X10, [SP, #872]

(737) 0x45d090 STR	X8, [SP, #880]

(737) 0x45d094 STR	X16, [SP, #896]

(737) 0x45d098 BL	4103b0

(737) 0x45d09c LDR	X2, [SP, #200]

(737) 0x45d0a0 LDR	X0, [X2, X23,LSL #3]

(737) 0x45d0a4 BL	524f40

(737) 0x45d0a8 LDR	X1, [SP, #200]

(737) 0x45d0ac LDR	X3, [SP, #816]

(737) 0x45d0b0 STR	XZR, [X1, X23,LSL #3]

(737) 0x45d0b4 CMP	X3, #1

(737) 0x45d0b8 B.LE	45d0dc

(737) 0x45d0bc LDR	X0, [SP, #192]

(737) 0x45d0c0 LDR	X0, [X0, X23,LSL #3]

(737) 0x45d0c4 BL	524f40

(737) 0x45d0c8 LDR	X9, [SP, #192]

(737) 0x45d0cc STR	XZR, [X9, X23,LSL #3]

(737) 0x45d0d0 LDR	X0, [X24, X23,LSL #3]

(737) 0x45d0d4 BL	524f40

(737) 0x45d0d8 STR	XZR, [X24, X23,LSL #3]

(737) 0x45d0dc LDR	X4, [SP, #328]

(737) 0x45d0e0 ADD	X23, X23, #1

(737) 0x45d0e4 ADD	X20, X20, #1

(737) 0x45d0e8 CMP	X4, X23

(737) 0x45d0ec B.EQ	45ee24

(737) 0x45d0f0 LDR	X12, [SP, #816]

(737) 0x45d0f4 CMP	X12, #1

(737) 0x45d0f8 B.LE	45cf50

(737) 0x45d0fc LDR	X2, [SP, #304]

(737) 0x45d100 LDR	X3, [SP, #280]

(737) 0x45d104 LDR	X5, [SP, #208]

(737) 0x45d108 LDR	X13, [X2, X23,LSL #3]

(737) 0x45d10c LDR	X0, [X13, X3]

(737) 0x45d110 STR	X0, [SP, #168]

(737) 0x45d114 CMP	X0, X5

(737) 0x45d118 B.GT	45ede4

(737) 0x45d11c LDR	X8, [SP, #152]

(737) 0x45d120 MOVZ	X5, #0

(737) 0x45d124 MOVZ	X2, #0

(737) 0x45d128 ORR	X10, XZR, X13

(737) 0x45d12c CMP	X8, #0

(737) 0x45d130 B.LE	45d604

  (738) 0x45d134 LDR	X13, [SP, #288]

  (738) 0x45d138 LDR	X17, [SP, #376]

  (738) 0x45d13c LDR	X1, [X13, X2,LSL #3]

  (738) 0x45d140 LDR	X8, [X17, X2,LSL #3]

  (738) 0x45d144 CMP	X1, X8

  (738) 0x45d148 B.GE	45d5f0

  (738) 0x45d14c ORR	X17, XZR, X10

  (738) 0x45d150 ORR	X16, XZR, X24

  (738) 0x45d154 B	45d164

    (739) 0x45d158 ADD	X1, X1, #1

    (739) 0x45d15c CMP	X1, X8

    (739) 0x45d160 B.EQ	45d5e8

    (739) 0x45d164 LDR	X24, [X25, X1,LSL #3]

    (739) 0x45d168 UBFM	X0, X24, #61, #60

    (739) 0x45d16c LDR	X9, [X22, X0]

    (739) 0x45d170 CMP	X9, X20

    (739) 0x45d174 B.NE	45d158

    (739) 0x45d178 ADD	X14, X0, #8

    (739) 0x45d17c LDR	X4, [X26, X0]

    (739) 0x45d180 LDR	X11, [X26, X14]

    (739) 0x45d184 CMP	X4, X11

    (739) 0x45d188 B.GE	45d3b4

    (739) 0x45d18c ADD	X3, X4, #1

    (739) 0x45d190 ADD	X6, X19, X5,LSL #3

    (739) 0x45d194 UBFM	X18, X5, #61, #60

    (739) 0x45d198 ADD	X10, X27, X3,LSL #3

    (739) 0x45d19c UBFM	X30, X3, #61, #60

    (739) 0x45d1a0 ORR	X15, XZR, X4

    (739) 0x45d1a4 SUB	X7, X6, X10

    (739) 0x45d1a8 CMP	X7, #16

    (739) 0x45d1ac B.LS	45ddb4

    (739) 0x45d1b0 SUB	X12, X11, X4

    (739) 0x45d1b4 SUB	X3, X12, #1

    (739) 0x45d1b8 CMP	X3, #2

    (739) 0x45d1bc B.LS	45dee0

    (739) 0x45d1c0 UBFM	X24, X12, #2, #63

    (739) 0x45d1c4 SUB	X30, X30, #8

    (739) 0x45d1c8 UBFM	X13, X24, #59, #58

    (739) 0x45d1cc ADD	X7, X27, X30

    (739) 0x45d1d0 SUB	X9, X13, #32

    (739) 0x45d1d4 MOVZ	X3, #0

    (739) 0x45d1d8 UBFM	X24, X9, #5, #63

    (739) 0x45d1dc ADD	X10, X7, #16

    (739) 0x45d1e0 ADD	X24, X24, #1

    (739) 0x45d1e4 ADD	X9, X6, #16

    (739) 0x45d1e8 ANDS	X24, X24, #0x7

    (739) 0x45d1ec B.EQ	45d2b4

    (739) 0x45d1f0 CMP	X24, #1

    (739) 0x45d1f4 B.EQ	45d298

    (739) 0x45d1f8 CMP	X24, #2

    (739) 0x45d1fc B.EQ	45d284

    (739) 0x45d200 CMP	X24, #3

    (739) 0x45d204 B.EQ	45d270

    (739) 0x45d208 CMP	X24, #4

    (739) 0x45d20c B.EQ	45d25c

    (739) 0x45d210 CMP	X24, #5

    (739) 0x45d214 B.EQ	45d248

    (739) 0x45d218 CMP	X24, #6

    (739) 0x45d21c B.EQ	45d234

    (739) 0x45d220 LDR	Q24, [X27, X30]

    (739) 0x45d224 MOVZ	X3, #32

    (739) 0x45d228 LDR	Q25, [X7, #16]

    (739) 0x45d22c STR	Q24, [X19, X18]

    (739) 0x45d230 STR	Q25, [X6, #16]

    (739) 0x45d234 LDR	Q0, [X7, X3]

    (739) 0x45d238 LDR	Q26, [X10, X3]

    (739) 0x45d23c STR	Q0, [X6, X3]

    (739) 0x45d240 STR	Q26, [X9, X3]

    (739) 0x45d244 ADD	X3, X3, #32

    (739) 0x45d248 LDR	Q27, [X7, X3]

    (739) 0x45d24c LDR	Q28, [X10, X3]

    (739) 0x45d250 STR	Q27, [X6, X3]

    (739) 0x45d254 STR	Q28, [X9, X3]

    (739) 0x45d258 ADD	X3, X3, #32

    (739) 0x45d25c LDR	Q1, [X7, X3]

    (739) 0x45d260 LDR	Q31, [X10, X3]

    (739) 0x45d264 STR	Q1, [X6, X3]

    (739) 0x45d268 STR	Q31, [X9, X3]

    (739) 0x45d26c ADD	X3, X3, #32

    (739) 0x45d270 LDR	Q30, [X7, X3]

    (739) 0x45d274 LDR	Q2, [X10, X3]

    (739) 0x45d278 STR	Q30, [X6, X3]

    (739) 0x45d27c STR	Q2, [X9, X3]

    (739) 0x45d280 ADD	X3, X3, #32

    (739) 0x45d284 LDR	Q3, [X7, X3]

    (739) 0x45d288 LDR	Q29, [X10, X3]

    (739) 0x45d28c STR	Q3, [X6, X3]

    (739) 0x45d290 STR	Q29, [X9, X3]

    (739) 0x45d294 ADD	X3, X3, #32

    (739) 0x45d298 LDR	Q4, [X7, X3]

    (739) 0x45d29c LDR	Q5, [X10, X3]

    (739) 0x45d2a0 STR	Q4, [X6, X3]

    (739) 0x45d2a4 STR	Q5, [X9, X3]

    (739) 0x45d2a8 ADD	X3, X3, #32

    (739) 0x45d2ac CMP	X3, X13

    (739) 0x45d2b0 B.EQ	45d36c

    (739) 0x45d2b4 STR	X25, [SP, #208]

    (739) 0x45d2b8 STR	X17, [SP, #224]

      (743) 0x45d2bc LDR	Q6, [X7, X3]

      (743) 0x45d2c0 ADD	X17, X3, #32

      (743) 0x45d2c4 ADD	X30, X3, #64

      (743) 0x45d2c8 ADD	X25, X3, #96

      (743) 0x45d2cc ADD	X24, X3, #128

      (743) 0x45d2d0 LDR	Q7, [X10, X3]

      (743) 0x45d2d4 ADD	X18, X3, #160

      (743) 0x45d2d8 STR	Q6, [X6, X3]

      (743) 0x45d2dc STR	Q7, [X9, X3]

      (743) 0x45d2e0 LDR	Q16, [X7, X17]

      (743) 0x45d2e4 LDR	Q17, [X10, X17]

      (743) 0x45d2e8 STR	Q16, [X6, X17]

      (743) 0x45d2ec STR	Q17, [X9, X17]

      (743) 0x45d2f0 ADD	X17, X3, #192

      (743) 0x45d2f4 LDR	Q18, [X7, X30]

      (743) 0x45d2f8 LDR	Q19, [X10, X30]

      (743) 0x45d2fc STR	Q18, [X6, X30]

      (743) 0x45d300 STR	Q19, [X9, X30]

      (743) 0x45d304 ADD	X30, X3, #224

      (743) 0x45d308 ADD	X3, X3, #256

      (743) 0x45d30c LDR	Q20, [X7, X25]

      (743) 0x45d310 LDR	Q21, [X10, X25]

      (743) 0x45d314 STR	Q20, [X6, X25]

      (743) 0x45d318 STR	Q21, [X9, X25]

      (743) 0x45d31c LDR	Q22, [X7, X24]

      (743) 0x45d320 LDR	Q23, [X10, X24]

      (743) 0x45d324 STR	Q22, [X6, X24]

      (743) 0x45d328 STR	Q23, [X9, X24]

      (743) 0x45d32c LDR	Q24, [X7, X18]

      (743) 0x45d330 LDR	Q25, [X10, X18]

      (743) 0x45d334 STR	Q24, [X6, X18]

      (743) 0x45d338 STR	Q25, [X9, X18]

      (743) 0x45d33c LDR	Q0, [X7, X17]

      (743) 0x45d340 LDR	Q26, [X10, X17]

      (743) 0x45d344 STR	Q0, [X6, X17]

      (743) 0x45d348 STR	Q26, [X9, X17]

      (743) 0x45d34c LDR	Q27, [X7, X30]

      (743) 0x45d350 LDR	Q28, [X10, X30]

      (743) 0x45d354 STR	Q27, [X6, X30]

      (743) 0x45d358 STR	Q28, [X9, X30]

      (743) 0x45d35c CMP	X3, X13

      (743) 0x45d360 B.NE	45d2bc

    (739) 0x45d364 LDR	X25, [SP, #208]

    (739) 0x45d368 LDR	X17, [SP, #224]

    (739) 0x45d36c AND	X13, X12, #0x0

    (739) 0x45d370 ANDS	XZR, X12, #0x3

    (739) 0x45d374 B.EQ	45d3ac

    (739) 0x45d378 ADD	X6, X13, X5

    (739) 0x45d37c SUB	X12, X12, X13

    (739) 0x45d380 WHILELO	P5.D, XZR, X12

    (739) 0x45d384 ADD	X13, X13, X4

    (739) 0x45d388 ADD	X4, X19, X6,LSL #3

    (739) 0x45d38c LD1D	{Z1.D}, P5/Z, [X27, X13,LSL #3]

    (739) 0x45d390 ST1D	{Z1.D}, P5, [X4, MUL VL]

    (739) 0x45d394 CNTD	X10, ALL

    (739) 0x45d398 ADD	X7, X27, X13,LSL #3

    (739) 0x45d39c WHILELO	P6.D, X10, X12

    (739) 0x45d3a0 B.EQ	45d3ac

    (739) 0x45d3a4 LD1D	{Z31.D}, P6/Z, [X7, #1, MUL VL]

    (739) 0x45d3a8 ST1D	{Z31.D}, P6, [X4, #1, MUL VL]

    (739) 0x45d3ac SUB	X11, X11, X15

    (739) 0x45d3b0 ADD	X5, X11, X5

    (739) 0x45d3b4 LDR	X3, [X21, X0]

    (739) 0x45d3b8 LDR	X12, [X21, X14]

    (739) 0x45d3bc CMP	X3, X12

    (739) 0x45d3c0 B.GE	45d158

    (739) 0x45d3c4 ADD	X0, X3, #1

    (739) 0x45d3c8 ADD	X6, X19, X5,LSL #3

    (739) 0x45d3cc UBFM	X24, X5, #61, #60

    (739) 0x45d3d0 ADD	X14, X28, X0,LSL #3

    (739) 0x45d3d4 UBFM	X18, X0, #61, #60

    (739) 0x45d3d8 ORR	X13, XZR, X3

    (739) 0x45d3dc SUB	X15, X6, X14

    (739) 0x45d3e0 CMP	X15, #16

    (739) 0x45d3e4 B.LS	45dc90

    (739) 0x45d3e8 SUB	X14, X12, X3

    (739) 0x45d3ec SUB	X0, X14, #1

    (739) 0x45d3f0 CMP	X0, #2

    (739) 0x45d3f4 B.LS	45ded8

    (739) 0x45d3f8 UBFM	X4, X14, #2, #63

    (739) 0x45d3fc SUB	X18, X18, #8

    (739) 0x45d400 UBFM	X15, X4, #59, #58

    (739) 0x45d404 ADD	X7, X28, X18

    (739) 0x45d408 SUB	X9, X15, #32

    (739) 0x45d40c MOVZ	X0, #0

    (739) 0x45d410 UBFM	X11, X9, #5, #63

    (739) 0x45d414 ADD	X10, X7, #16

    (739) 0x45d418 ADD	X30, X11, #1

    (739) 0x45d41c ADD	X9, X6, #16

    (739) 0x45d420 ANDS	X4, X30, #0x7

    (739) 0x45d424 B.EQ	45d4ec

    (739) 0x45d428 CMP	X4, #1

    (739) 0x45d42c B.EQ	45d4d0

    (739) 0x45d430 CMP	X4, #2

    (739) 0x45d434 B.EQ	45d4bc

    (739) 0x45d438 CMP	X4, #3

    (739) 0x45d43c B.EQ	45d4a8

    (739) 0x45d440 CMP	X4, #4

    (739) 0x45d444 B.EQ	45d494

    (739) 0x45d448 CMP	X4, #5

    (739) 0x45d44c B.EQ	45d480

    (739) 0x45d450 CMP	X4, #6

    (739) 0x45d454 B.EQ	45d46c

    (739) 0x45d458 LDR	Q16, [X28, X18]

    (739) 0x45d45c MOVZ	X0, #32

    (739) 0x45d460 LDR	Q17, [X7, #16]

    (739) 0x45d464 STR	Q16, [X19, X24]

    (739) 0x45d468 STR	Q17, [X6, #16]

    (739) 0x45d46c LDR	Q18, [X7, X0]

    (739) 0x45d470 LDR	Q19, [X10, X0]

    (739) 0x45d474 STR	Q18, [X6, X0]

    (739) 0x45d478 STR	Q19, [X9, X0]

    (739) 0x45d47c ADD	X0, X0, #32

    (739) 0x45d480 LDR	Q20, [X7, X0]

    (739) 0x45d484 LDR	Q21, [X10, X0]

    (739) 0x45d488 STR	Q20, [X6, X0]

    (739) 0x45d48c STR	Q21, [X9, X0]

    (739) 0x45d490 ADD	X0, X0, #32

    (739) 0x45d494 LDR	Q22, [X7, X0]

    (739) 0x45d498 LDR	Q23, [X10, X0]

    (739) 0x45d49c STR	Q22, [X6, X0]

    (739) 0x45d4a0 STR	Q23, [X9, X0]

    (739) 0x45d4a4 ADD	X0, X0, #32

    (739) 0x45d4a8 LDR	Q24, [X7, X0]

    (739) 0x45d4ac LDR	Q25, [X10, X0]

    (739) 0x45d4b0 STR	Q24, [X6, X0]

    (739) 0x45d4b4 STR	Q25, [X9, X0]

    (739) 0x45d4b8 ADD	X0, X0, #32

    (739) 0x45d4bc LDR	Q0, [X7, X0]

    (739) 0x45d4c0 LDR	Q26, [X10, X0]

    (739) 0x45d4c4 STR	Q0, [X6, X0]

    (739) 0x45d4c8 STR	Q26, [X9, X0]

    (739) 0x45d4cc ADD	X0, X0, #32

    (739) 0x45d4d0 LDR	Q27, [X7, X0]

    (739) 0x45d4d4 LDR	Q28, [X10, X0]

    (739) 0x45d4d8 STR	Q27, [X6, X0]

    (739) 0x45d4dc STR	Q28, [X9, X0]

    (739) 0x45d4e0 ADD	X0, X0, #32

    (739) 0x45d4e4 CMP	X0, X15

    (739) 0x45d4e8 B.EQ	45d594

      (741) 0x45d4ec LDR	Q1, [X7, X0]

      (741) 0x45d4f0 ADD	X4, X0, #32

      (741) 0x45d4f4 ADD	X30, X0, #64

      (741) 0x45d4f8 ADD	X24, X0, #96

      (741) 0x45d4fc ADD	X18, X0, #128

      (741) 0x45d500 LDR	Q31, [X10, X0]

      (741) 0x45d504 ADD	X11, X0, #160

      (741) 0x45d508 STR	Q1, [X6, X0]

      (741) 0x45d50c STR	Q31, [X9, X0]

      (741) 0x45d510 LDR	Q30, [X7, X4]

      (741) 0x45d514 LDR	Q2, [X10, X4]

      (741) 0x45d518 STR	Q30, [X6, X4]

      (741) 0x45d51c STR	Q2, [X9, X4]

      (741) 0x45d520 ADD	X4, X0, #192

      (741) 0x45d524 LDR	Q3, [X7, X30]

      (741) 0x45d528 LDR	Q29, [X10, X30]

      (741) 0x45d52c STR	Q3, [X6, X30]

      (741) 0x45d530 STR	Q29, [X9, X30]

      (741) 0x45d534 ADD	X30, X0, #224

      (741) 0x45d538 ADD	X0, X0, #256

      (741) 0x45d53c LDR	Q4, [X7, X24]

      (741) 0x45d540 LDR	Q5, [X10, X24]

      (741) 0x45d544 STR	Q4, [X6, X24]

      (741) 0x45d548 STR	Q5, [X9, X24]

      (741) 0x45d54c LDR	Q6, [X7, X18]

      (741) 0x45d550 LDR	Q7, [X10, X18]

      (741) 0x45d554 STR	Q6, [X6, X18]

      (741) 0x45d558 STR	Q7, [X9, X18]

      (741) 0x45d55c LDR	Q16, [X7, X11]

      (741) 0x45d560 LDR	Q17, [X10, X11]

      (741) 0x45d564 STR	Q16, [X6, X11]

      (741) 0x45d568 STR	Q17, [X9, X11]

      (741) 0x45d56c LDR	Q18, [X7, X4]

      (741) 0x45d570 LDR	Q19, [X10, X4]

      (741) 0x45d574 STR	Q18, [X6, X4]

      (741) 0x45d578 STR	Q19, [X9, X4]

      (741) 0x45d57c LDR	Q20, [X7, X30]

      (741) 0x45d580 LDR	Q21, [X10, X30]

      (741) 0x45d584 STR	Q20, [X6, X30]

      (741) 0x45d588 STR	Q21, [X9, X30]

      (741) 0x45d58c CMP	X0, X15

      (741) 0x45d590 B.NE	45d4ec

    (739) 0x45d594 AND	X30, X14, #0x0

    (739) 0x45d598 ANDS	XZR, X14, #0x3

    (739) 0x45d59c B.EQ	45d5d4

    (739) 0x45d5a0 ADD	X6, X30, X5

    (739) 0x45d5a4 ADD	X15, X3, X30

    (739) 0x45d5a8 SUB	X14, X14, X30

    (739) 0x45d5ac ADD	X3, X19, X6,LSL #3

    (739) 0x45d5b0 WHILELO	P7.D, XZR, X14

    (739) 0x45d5b4 LD1D	{Z22.D}, P7/Z, [X28, X15,LSL #3]

    (739) 0x45d5b8 ST1D	{Z22.D}, P7, [X3, MUL VL]

    (739) 0x45d5bc CNTD	X10, ALL

    (739) 0x45d5c0 ADD	X7, X28, X15,LSL #3

    (739) 0x45d5c4 WHILELO	P0.D, X10, X14

    (739) 0x45d5c8 B.EQ	45d5d4

    (739) 0x45d5cc LD1D	{Z23.D}, P0/Z, [X7, #1, MUL VL]

    (739) 0x45d5d0 ST1D	{Z23.D}, P0, [X3, #1, MUL VL]

    (739) 0x45d5d4 SUB	X12, X12, X13

    (739) 0x45d5d8 ADD	X1, X1, #1

    (739) 0x45d5dc ADD	X5, X12, X5

    (739) 0x45d5e0 CMP	X1, X8

    (739) 0x45d5e4 B.NE	45d164

  (738) 0x45d5e8 ORR	X10, XZR, X17

  (738) 0x45d5ec ORR	X24, XZR, X16

  (738) 0x45d5f0 LDR	X8, [SP, #152]

  (738) 0x45d5f4 ADD	X2, X2, #1

  (738) 0x45d5f8 CMP	X8, X2

  (738) 0x45d5fc B.NE	45d134

(737) 0x45d600 ORR	X13, XZR, X10

(737) 0x45d604 LDR	X16, [SP, #336]

(737) 0x45d608 LDR	X1, [SP, #368]

(737) 0x45d60c LDR	X9, [SP, #152]

(737) 0x45d610 LDR	X18, [SP, #176]

(737) 0x45d614 STR	X13, [X1, #24]

(737) 0x45d618 LDR	X17, [X16, X23,LSL #3]

(737) 0x45d61c STR	X9, [X1, #8]

(737) 0x45d620 LDR	X4, [SP, #344]

(737) 0x45d624 STR	X18, [X1, #40]

(737) 0x45d628 LDR	X30, [SP, #160]

(737) 0x45d62c LDR	X3, [X17, X4]

(737) 0x45d630 STR	X17, [X1, #56]

(737) 0x45d634 STR	X3, [SP, #208]

(737) 0x45d638 CMP	X3, X30

(737) 0x45d63c B.GT	45ee08

(737) 0x45d640 LDR	X3, [SP, #136]

(737) 0x45d644 ORR	X2, XZR, X19

(737) 0x45d648 MOVZ	X0, #1

(737) 0x45d64c LDR	X1, [SP, #368]

(737) 0x45d650 BL	4e0364

(737) 0x45d654 BL	4e0b6c

(737) 0x45d658 LDR	X11, [SP, #304]

(737) 0x45d65c LDR	X0, [X11, X23,LSL #3]

(737) 0x45d660 BL	524f40

(737) 0x45d664 LDR	X14, [SP, #304]

(737) 0x45d668 LDR	X15, [SP, #336]

(737) 0x45d66c STR	XZR, [X14, X23,LSL #3]

(737) 0x45d670 LDR	X0, [X15, X23,LSL #3]

(737) 0x45d674 BL	524f40

(737) 0x45d678 LDR	X12, [SP, #168]

(737) 0x45d67c LDR	X7, [SP, #208]

(737) 0x45d680 LDR	X6, [SP, #336]

(737) 0x45d684 STR	X12, [SP, #208]

(737) 0x45d688 STR	X7, [SP, #160]

(737) 0x45d68c STR	XZR, [X6, X23,LSL #3]

(737) 0x45d690 B	45cf50

      (754) 0x45d694 MOVZ	X11, #0

      (754) 0x45d698 HINT	#0

      (754) 0x45d69c HINT	#0

      (754) 0x45d6a0 UBFM	X8, X11, #61, #60

      (754) 0x45d6a4 LDR	X11, [X20, X8]

      (754) 0x45d6a8 LDR	X7, [X21, X8]

      (754) 0x45d6ac SUB	X28, X0, X11

      (754) 0x45d6b0 LDR	X4, [X7, X28,LSL #3]

      (754) 0x45d6b4 STR	X4, [X18, X3,LSL #3]

      (754) 0x45d6b8 ADD	X3, X3, #1

      (754) 0x45d6bc B	45c7f0

    (753) 0x45d6c0 LD1D	{Z24.D}, P0/Z, [X11, #1, MUL VL]

    (753) 0x45d6c4 ADD	Z25.D, Z21.D, Z24.D

    (753) 0x45d6c8 ST1D	{Z25.D}, P0, [X8, #1, MUL VL]

    (753) 0x45d6cc B	45c66c

        (748) 0x45d6d0 LDR	X5, [SP, #120]

        (748) 0x45d6d4 ADD	X28, X28, #8

        (748) 0x45d6d8 CMP	X19, X5

        (748) 0x45d6dc B.NE	45c934

      (747) 0x45d6e0 LDR	X10, [X23, X25,LSL #3]

      (747) 0x45d6e4 LDR	X7, [SP, #168]

      (747) 0x45d6e8 LDR	X8, [X21, X5,LSL #3]

      (747) 0x45d6ec LDR	X11, [X10, X20]

      (747) 0x45d6f0 UBFM	X12, X7, #61, #60

      (747) 0x45d6f4 ADD	X4, X7, #1

      (747) 0x45d6f8 LDR	X13, [SP, #208]

      (747) 0x45d6fc STR	X4, [SP, #168]

      (747) 0x45d700 STR	X11, [X8, X12]

      (747) 0x45d704 STR	X26, [X13, X12]

      (747) 0x45d708 B	45c8f8

  (757) 0x45d70c LDR	X14, [X12, X19]

  (757) 0x45d710 ADD	X17, X7, #1

  (757) 0x45d714 ADD	X9, X9, #1

  (757) 0x45d718 LDR	X16, [X11, #8]

  (757) 0x45d71c STR	X14, [X16, X7,LSL #3]

  (757) 0x45d720 ORR	X7, XZR, X17

  (757) 0x45d724 LDR	X1, [X20]

  (757) 0x45d728 CMP	X9, X1

  (757) 0x45d72c B.LT	45c240

(723) 0x45d730 LDR	X3, [X30, #16]

(723) 0x45d734 ADD	X5, X5, #1

(723) 0x45d738 CMP	X3, X5

(723) 0x45d73c B.GT	45c1d8

0x45d740 B	45c270

  (758) 0x45d744 LDR	X16, [X13, X9]

  (758) 0x45d748 ADD	X1, X4, #1

  (758) 0x45d74c ADD	X17, X17, #1

  (758) 0x45d750 LDR	X3, [X27, #8]

  (758) 0x45d754 STR	X16, [X3, X4,LSL #3]

  (758) 0x45d758 ORR	X4, XZR, X1

  (758) 0x45d75c LDR	X2, [X20]

  (758) 0x45d760 CMP	X17, X2

  (758) 0x45d764 B.LT	45c208

(723) 0x45d768 B	45c228

      (754) 0x45d76c MOVZ	X6, #0

      (754) 0x45d770 UBFM	X5, X6, #61, #60

      (754) 0x45d774 LDR	X10, [X20, X5]

      (754) 0x45d778 LDR	X8, [X21, X5]

      (754) 0x45d77c SUB	X7, X7, X10

      (754) 0x45d780 LDR	X4, [X8, X7,LSL #3]

      (754) 0x45d784 STR	X4, [X18, X3,LSL #3]

      (754) 0x45d788 ADD	X3, X3, #1

      (754) 0x45d78c B	45c750

      (754) 0x45d790 MOVZ	X11, #1

      (754) 0x45d794 B	45d6a0

    (753) 0x45d798 UBFM	X7, X3, #61, #60

    (753) 0x45d79c SUB	X5, X8, X2

    (753) 0x45d7a0 SUB	X28, X7, X4,LSL #3

    (753) 0x45d7a4 ANDS	X6, X5, #0x7

    (753) 0x45d7a8 ADD	X7, X18, X28

    (753) 0x45d7ac B.EQ	45d98c

    (753) 0x45d7b0 LDR	X28, [X11, X4,LSL #3]

    (753) 0x45d7b4 ADD	X5, X28, X17

    (753) 0x45d7b8 STR	X5, [X7, X4,LSL #3]

    (753) 0x45d7bc ORR	X4, XZR, X2

    (753) 0x45d7c0 ADD	X2, X2, #1

    (753) 0x45d7c4 CMP	X6, #1

    (753) 0x45d7c8 B.EQ	45d98c

    (753) 0x45d7cc CMP	X6, #2

    (753) 0x45d7d0 B.EQ	45d858

    (753) 0x45d7d4 CMP	X6, #3

    (753) 0x45d7d8 B.EQ	45d844

    (753) 0x45d7dc CMP	X6, #4

    (753) 0x45d7e0 B.EQ	45d830

    (753) 0x45d7e4 CMP	X6, #5

    (753) 0x45d7e8 B.EQ	45d81c

    (753) 0x45d7ec CMP	X6, #6

    (753) 0x45d7f0 B.EQ	45d808

    (753) 0x45d7f4 LDR	X6, [X11, X4,LSL #3]

    (753) 0x45d7f8 ADD	X28, X6, X17

    (753) 0x45d7fc STR	X28, [X7, X4,LSL #3]

    (753) 0x45d800 ORR	X4, XZR, X2

    (753) 0x45d804 ADD	X2, X2, #1

    (753) 0x45d808 LDR	X5, [X11, X4,LSL #3]

    (753) 0x45d80c ADD	X6, X5, X17

    (753) 0x45d810 STR	X6, [X7, X4,LSL #3]

    (753) 0x45d814 ORR	X4, XZR, X2

    (753) 0x45d818 ADD	X2, X2, #1

    (753) 0x45d81c LDR	X28, [X11, X4,LSL #3]

    (753) 0x45d820 ADD	X5, X28, X17

    (753) 0x45d824 STR	X5, [X7, X4,LSL #3]

    (753) 0x45d828 ORR	X4, XZR, X2

    (753) 0x45d82c ADD	X2, X2, #1

    (753) 0x45d830 LDR	X6, [X11, X4,LSL #3]

    (753) 0x45d834 ADD	X28, X6, X17

    (753) 0x45d838 STR	X28, [X7, X4,LSL #3]

    (753) 0x45d83c ORR	X4, XZR, X2

    (753) 0x45d840 ADD	X2, X2, #1

    (753) 0x45d844 LDR	X5, [X11, X4,LSL #3]

    (753) 0x45d848 ADD	X6, X5, X17

    (753) 0x45d84c STR	X6, [X7, X4,LSL #3]

    (753) 0x45d850 ORR	X4, XZR, X2

    (753) 0x45d854 ADD	X2, X2, #1

    (753) 0x45d858 LDR	X28, [X11, X4,LSL #3]

    (753) 0x45d85c STR	X9, [SP, #120]

    (753) 0x45d860 STR	X0, [SP, #136]

    (753) 0x45d864 ADD	X5, X28, X17

    (753) 0x45d868 STR	X5, [X7, X4,LSL #3]

    (753) 0x45d86c ORR	X4, XZR, X2

    (753) 0x45d870 ADD	X2, X2, #1

    (753) 0x45d874 STP	X12, X10, [SP, #160]

    (753) 0x45d878 B	45d8d4

      (755) 0x45d87c LDR	X0, [X11, X2,LSL #3]

      (755) 0x45d880 ADD	X0, X0, X17

      (755) 0x45d884 STR	X0, [X7, X2,LSL #3]

      (755) 0x45d888 ADD	X2, X2, #8

      (755) 0x45d88c LDR	X0, [X11, X28,LSL #3]

      (755) 0x45d890 ADD	X0, X0, X17

      (755) 0x45d894 STR	X0, [X7, X28,LSL #3]

      (755) 0x45d898 LDR	X28, [X11, X12,LSL #3]

      (755) 0x45d89c ADD	X0, X28, X17

      (755) 0x45d8a0 STR	X0, [X7, X12,LSL #3]

      (755) 0x45d8a4 LDR	X12, [X11, X10,LSL #3]

      (755) 0x45d8a8 ADD	X28, X12, X17

      (755) 0x45d8ac STR	X28, [X7, X10,LSL #3]

      (755) 0x45d8b0 LDR	X10, [X11, X9,LSL #3]

      (755) 0x45d8b4 ADD	X0, X10, X17

      (755) 0x45d8b8 STR	X0, [X7, X9,LSL #3]

      (755) 0x45d8bc LDR	X9, [X11, X6,LSL #3]

      (755) 0x45d8c0 ADD	X12, X9, X17

      (755) 0x45d8c4 STR	X12, [X7, X6,LSL #3]

      (755) 0x45d8c8 LDR	X6, [X11, X5,LSL #3]

      (755) 0x45d8cc ADD	X28, X6, X17

      (755) 0x45d8d0 STR	X28, [X7, X5,LSL #3]

      (755) 0x45d8d4 LDR	X0, [X11, X4,LSL #3]

      (755) 0x45d8d8 ADD	X28, X2, #1

      (755) 0x45d8dc ADD	X12, X2, #2

      (755) 0x45d8e0 ADD	X10, X2, #3

      (755) 0x45d8e4 ADD	X9, X2, #4

      (755) 0x45d8e8 ADD	X6, X2, #5

      (755) 0x45d8ec ADD	X5, X2, #6

      (755) 0x45d8f0 ADD	X0, X0, X17

      (755) 0x45d8f4 STR	X0, [X7, X4,LSL #3]

      (755) 0x45d8f8 ADD	X4, X2, #7

      (755) 0x45d8fc CMP	X8, X2

      (755) 0x45d900 B.NE	45d87c

    (753) 0x45d904 LDR	X9, [SP, #120]

    (753) 0x45d908 LDP	X12, X10, [SP, #160]

    (753) 0x45d90c LDR	X0, [SP, #136]

    (753) 0x45d910 B	45c66c

      (754) 0x45d914 MOVZ	X11, #2

      (754) 0x45d918 B	45d6a0

      (754) 0x45d91c MOVZ	X6, #1

      (754) 0x45d920 B	45d770

      (754) 0x45d924 MOVZ	X6, #2

      (754) 0x45d928 B	45d770

      (754) 0x45d92c MOVZ	X11, #3

      (754) 0x45d930 B	45d6a0

      (754) 0x45d934 MOVZ	X11, #4

      (754) 0x45d938 B	45d6a0

      (754) 0x45d93c MOVZ	X6, #3

      (754) 0x45d940 B	45d770

      (754) 0x45d944 MOVZ	X6, #4

      (754) 0x45d948 B	45d770

      (754) 0x45d94c MOVZ	X11, #5

      (754) 0x45d950 B	45d6a0

    (746) 0x45d954 ORR	X17, XZR, X2

    (746) 0x45d958 B	45c8a8

      (754) 0x45d95c MOVZ	X6, #5

      (754) 0x45d960 B	45d770

      (754) 0x45d964 MOVZ	X11, #6

      (754) 0x45d968 B	45d6a0

      (754) 0x45d96c MOVZ	X11, #7

      (754) 0x45d970 B	45d6a0

      (754) 0x45d974 MOVZ	X6, #6

      (754) 0x45d978 B	45d770

      (754) 0x45d97c MOVZ	X6, #7

      (754) 0x45d980 B	45d770

    (753) 0x45d984 MOVZ	X8, #0

    (753) 0x45d988 B	45c63c

    (753) 0x45d98c STR	X9, [SP, #120]

    (753) 0x45d990 STR	X0, [SP, #136]

    (753) 0x45d994 STP	X12, X10, [SP, #160]

    (753) 0x45d998 B	45d8d4

(725) 0x45d99c LDR	X17, [SP, #336]

(725) 0x45d9a0 LDR	X18, [SP, #176]

(725) 0x45d9a4 LDR	X16, [X17, X23,LSL #3]

(725) 0x45d9a8 STR	XZR, [X16]

(725) 0x45d9ac CMP	X18, #0

(725) 0x45d9b0 B.LE	45f5e0

(725) 0x45d9b4 LDR	X4, [SP, #664]

(725) 0x45d9b8 MOVZ	X22, #0

(725) 0x45d9bc MOVZ	X3, #8

(725) 0x45d9c0 LDR	X12, [SP, #456]

(725) 0x45d9c4 LDR	X30, [SP, #744]

(725) 0x45d9c8 SUB	X13, X4, #8

  (749) 0x45d9cc LDR	X14, [X13, X3]

  (749) 0x45d9d0 LDR	X2, [X4, X3]

  (749) 0x45d9d4 CMP	X14, X2

  (749) 0x45d9d8 B.GE	45d9f8

  (749) 0x45d9dc HINT	#0

    (750) 0x45d9e0 LDR	X1, [X26, X14,LSL #3]

    (750) 0x45d9e4 CMP	X19, X1

    (750) 0x45d9e8 B.EQ	45da90

    (750) 0x45d9ec ADD	X14, X14, #1

    (750) 0x45d9f0 CMP	X14, X2

    (750) 0x45d9f4 B.LT	45d9e0

  (749) 0x45d9f8 STR	X22, [X16, X3]

  (749) 0x45d9fc ADD	X3, X3, #8

  (749) 0x45da00 CMP	X3, X30

  (749) 0x45da04 B.NE	45d9cc

(725) 0x45da08 LDR	X24, [SP, #304]

(725) 0x45da0c LDR	X17, [SP, #368]

(725) 0x45da10 LDR	X16, [SP, #704]

(725) 0x45da14 LDR	X9, [SP, #336]

(725) 0x45da18 LDR	X18, [SP, #712]

(725) 0x45da1c STR	X16, [X17, #16]

(725) 0x45da20 LDR	X15, [X24, X23,LSL #3]

(725) 0x45da24 LDR	X10, [SP, #152]

(725) 0x45da28 STR	X18, [X17, #48]

(725) 0x45da2c LDR	X8, [SP, #176]

(725) 0x45da30 STR	X15, [X17, #24]

(725) 0x45da34 LDR	X0, [X9, X23,LSL #3]

(725) 0x45da38 STR	X10, [X17, #8]

(725) 0x45da3c LDR	X5, [SP, #400]

(725) 0x45da40 STR	X8, [X17, #40]

(725) 0x45da44 STR	X0, [X17, #56]

(725) 0x45da48 STR	X5, [X17]

(725) 0x45da4c CBNZ	X22, 45e1b8

(725) 0x45da50 LDR	X11, [SP, #568]

(725) 0x45da54 MOVZ	X0, #11

(725) 0x45da58 LDR	X1, [SP, #368]

(725) 0x45da5c LDR	X2, [SP, #384]

(725) 0x45da60 STR	XZR, [X11, X23,LSL #3]

(725) 0x45da64 STR	XZR, [X21, X19,LSL #3]

(725) 0x45da68 LDR	X3, [X11, W23,UXTW #3]

(725) 0x45da6c BL	4e0364

(725) 0x45da70 BL	4e0b6c

(725) 0x45da74 LDR	X28, [SP, #544]

(725) 0x45da78 TBNZ	X28, #63, 45e19c

(725) 0x45da7c LDR	X12, [SP, #176]

(725) 0x45da80 STR	XZR, [SP, #544]

(725) 0x45da84 CMP	X12, #0

(725) 0x45da88 B.GT	45c83c

(725) 0x45da8c B	45c9dc

    (750) 0x45da90 STR	X22, [X12, X14,LSL #3]

    (750) 0x45da94 LDR	X6, [X27, X14,LSL #3]

    (750) 0x45da98 ADD	X14, X14, #1

    (750) 0x45da9c LDR	X2, [X4, X3]

    (750) 0x45daa0 ADD	X22, X22, X6

    (750) 0x45daa4 CMP	X2, X14

    (750) 0x45daa8 B.GT	45d9e0

  (749) 0x45daac STR	X22, [X16, X3]

  (749) 0x45dab0 ADD	X3, X3, #8

  (749) 0x45dab4 CMP	X3, X30

  (749) 0x45dab8 B.NE	45d9cc

(725) 0x45dabc B	45da08

(725) 0x45dac0 LDR	X22, [SP, #152]

(725) 0x45dac4 MOVZ	X1, #8

(725) 0x45dac8 ADD	X0, X22, #1

(725) 0x45dacc BL	524ea8

(725) 0x45dad0 LDR	X24, [SP, #304]

(725) 0x45dad4 ORR	X18, XZR, X0

(725) 0x45dad8 MOVZ	X1, #8

(725) 0x45dadc LDR	X0, [SP, #552]

(725) 0x45dae0 STR	X18, [X24, X23,LSL #3]

(725) 0x45dae4 BL	524ea8

(725) 0x45dae8 LDR	X8, [SP, #336]

(725) 0x45daec STR	X0, [X8, X23,LSL #3]

(725) 0x45daf0 LDR	X15, [X24, X23,LSL #3]

(725) 0x45daf4 STR	XZR, [X15]

(725) 0x45daf8 CMP	X22, #0

(725) 0x45dafc B.LE	45f7dc

(725) 0x45db00 ADRP	X2,

(725) 0x45db04 MOVZ	X5, #0

(725) 0x45db08 ADD	X0, X2, #3552

(725) 0x45db0c MOVZ	X11, #0

(725) 0x45db10 STR	X0, [SP, #120]

(725) 0x45db14 TBZ	W22, #0, 45db84

(725) 0x45db18 LDP	X9, X4, [SP, #240]

(725) 0x45db1c ADD	X14, SP, #832

(725) 0x45db20 MOVZ	W3, #0

(725) 0x45db24 MOVZ	W2, #0

(725) 0x45db28 LDR	X1, [SP, #296]

(725) 0x45db2c STP	X9, X4, [X14]

(725) 0x45db30 STP	X23, X25, [X14, #40]

(725) 0x45db34 LDR	X7, [SP, #288]

(725) 0x45db38 STR	XZR, [SP, #888]

(725) 0x45db3c LDR	X16, [SP, #376]

(725) 0x45db40 STR	XZR, [SP, #896]

(725) 0x45db44 LDR	X17, [SP, #560]

(725) 0x45db48 STR	X7, [SP, #848]

(725) 0x45db4c LDR	X0, [SP, #120]

(725) 0x45db50 STR	X16, [SP, #864]

(725) 0x45db54 STR	X17, [SP, #856]

(725) 0x45db58 BL	4103b0

(725) 0x45db5c LDR	X1, [SP, #304]

(725) 0x45db60 MOVZ	X3, #1

(725) 0x45db64 ORR	X11, XZR, X3

(725) 0x45db68 LDR	X5, [SP, #896]

(725) 0x45db6c LDR	X6, [SP, #152]

(725) 0x45db70 LDR	X24, [X1, X23,LSL #3]

(725) 0x45db74 STR	X5, [X24, X3,LSL #3]

(725) 0x45db78 CMP	X6, X3

(725) 0x45db7c B.EQ	45dc5c

(725) 0x45db80 LDR	X24, [SP, #304]

(725) 0x45db84 ORR	X28, XZR, X19

(725) 0x45db88 ORR	X19, XZR, X20

(725) 0x45db8c STR	X27, [SP, #136]

(725) 0x45db90 ORR	X20, XZR, X26

(725) 0x45db94 ORR	X26, XZR, X25

(725) 0x45db98 LDR	X25, [SP, #560]

(725) 0x45db9c ORR	X22, XZR, X11

(725) 0x45dba0 ORR	X27, XZR, X21

  (751) 0x45dba4 LDP	X21, X30, [SP, #240]

  (751) 0x45dba8 ADD	X18, SP, #832

  (751) 0x45dbac ADD	X8, SP, #864

  (751) 0x45dbb0 MOVZ	W3, #0

  (751) 0x45dbb4 MOVZ	W2, #0

  (751) 0x45dbb8 LDP	X13, X1, [SP, #288]

  (751) 0x45dbbc LDR	X10, [SP, #376]

  (751) 0x45dbc0 LDR	X0, [SP, #120]

  (751) 0x45dbc4 STP	X21, X30, [X18]

  (751) 0x45dbc8 STP	X13, X25, [X18, #16]

  (751) 0x45dbcc STP	X10, X23, [X8]

  (751) 0x45dbd0 STP	X26, X22, [X8, #16]

  (751) 0x45dbd4 ADD	X22, X22, #1

  (751) 0x45dbd8 STR	X5, [SP, #896]

  (751) 0x45dbdc BL	4103b0

  (751) 0x45dbe0 LDR	X15, [X24, X23,LSL #3]

  (751) 0x45dbe4 ADD	X7, SP, #832

  (751) 0x45dbe8 ADD	X11, SP, #864

  (751) 0x45dbec LDP	X12, X1, [SP, #288]

  (751) 0x45dbf0 MOVZ	W3, #0

  (751) 0x45dbf4 MOVZ	W2, #0

  (751) 0x45dbf8 LDR	X4, [SP, #896]

  (751) 0x45dbfc LDR	X14, [SP, #248]

  (751) 0x45dc00 LDR	X9, [SP, #376]

  (751) 0x45dc04 STR	X4, [X15, X22,LSL #3]

  (751) 0x45dc08 LDR	X0, [SP, #120]

  (751) 0x45dc0c STP	X21, X14, [X7]

  (751) 0x45dc10 STP	X12, X25, [X7, #16]

  (751) 0x45dc14 STP	X9, X23, [X11]

  (751) 0x45dc18 STP	X26, X22, [X11, #16]

  (751) 0x45dc1c STR	X4, [SP, #896]

  (751) 0x45dc20 BL	4103b0

  (751) 0x45dc24 LDR	X0, [X24, X23,LSL #3]

  (751) 0x45dc28 ADD	X2, X22, #1

  (751) 0x45dc2c ORR	X22, XZR, X2

  (751) 0x45dc30 LDR	X5, [SP, #896]

  (751) 0x45dc34 LDR	X3, [SP, #152]

  (751) 0x45dc38 STR	X5, [X0, X2,LSL #3]

  (751) 0x45dc3c CMP	X3, X2

  (751) 0x45dc40 B.NE	45dba4

(725) 0x45dc44 ORR	X21, XZR, X27

(725) 0x45dc48 LDR	X27, [SP, #136]

(725) 0x45dc4c ORR	X25, XZR, X26

(725) 0x45dc50 ORR	X26, XZR, X20

(725) 0x45dc54 ORR	X20, XZR, X19

(725) 0x45dc58 ORR	X19, XZR, X28

(725) 0x45dc5c LDR	X1, [SP, #344]

(725) 0x45dc60 ORR	X3, XZR, X27

(725) 0x45dc64 MOVZ	X0, #11

(725) 0x45dc68 STR	X5, [SP, #120]

(725) 0x45dc6c LDR	X2, [SP, #376]

(725) 0x45dc70 BL	4e0364

(725) 0x45dc74 BL	4e0b6c

(725) 0x45dc78 LDR	X1, [SP, #120]

(725) 0x45dc7c LDR	X5, [SP, #528]

(725) 0x45dc80 CMP	X1, X5

(725) 0x45dc84 B.GT	45e240

(725) 0x45dc88 STR	X1, [SP, #528]

(725) 0x45dc8c B	45c32c

    (739) 0x45dc90 SUB	X9, X24, X3,LSL #3

    (739) 0x45dc94 SUB	X24, X12, X0

    (739) 0x45dc98 ANDS	X18, X24, #0x7

    (739) 0x45dc9c ADD	X4, X19, X9

    (739) 0x45dca0 B.EQ	45dd84

    (739) 0x45dca4 LDR	D24, [X28, X3,LSL #3]

    (739) 0x45dca8 STR	D24, [X4, X3,LSL #3]

    (739) 0x45dcac ORR	X3, XZR, X0

    (739) 0x45dcb0 ADD	X0, X0, #1

    (739) 0x45dcb4 CMP	X18, #1

    (739) 0x45dcb8 B.EQ	45dd84

    (739) 0x45dcbc CMP	X18, #2

    (739) 0x45dcc0 B.EQ	45dd34

    (739) 0x45dcc4 CMP	X18, #3

    (739) 0x45dcc8 B.EQ	45dd24

    (739) 0x45dccc CMP	X18, #4

    (739) 0x45dcd0 B.EQ	45dd14

    (739) 0x45dcd4 CMP	X18, #5

    (739) 0x45dcd8 B.EQ	45dd04

    (739) 0x45dcdc CMP	X18, #6

    (739) 0x45dce0 B.EQ	45dcf4

    (739) 0x45dce4 LDR	D25, [X28, X3,LSL #3]

    (739) 0x45dce8 STR	D25, [X4, X3,LSL #3]

    (739) 0x45dcec ORR	X3, XZR, X0

    (739) 0x45dcf0 ADD	X0, X0, #1

    (739) 0x45dcf4 LDR	D0, [X28, X3,LSL #3]

    (739) 0x45dcf8 STR	D0, [X4, X3,LSL #3]

    (739) 0x45dcfc ORR	X3, XZR, X0

    (739) 0x45dd00 ADD	X0, X0, #1

    (739) 0x45dd04 LDR	D26, [X28, X3,LSL #3]

    (739) 0x45dd08 STR	D26, [X4, X3,LSL #3]

    (739) 0x45dd0c ORR	X3, XZR, X0

    (739) 0x45dd10 ADD	X0, X0, #1

    (739) 0x45dd14 LDR	D27, [X28, X3,LSL #3]

    (739) 0x45dd18 STR	D27, [X4, X3,LSL #3]

    (739) 0x45dd1c ORR	X3, XZR, X0

    (739) 0x45dd20 ADD	X0, X0, #1

    (739) 0x45dd24 LDR	D28, [X28, X3,LSL #3]

    (739) 0x45dd28 STR	D28, [X4, X3,LSL #3]

    (739) 0x45dd2c ORR	X3, XZR, X0

    (739) 0x45dd30 ADD	X0, X0, #1

    (739) 0x45dd34 LDR	D1, [X28, X3,LSL #3]

    (739) 0x45dd38 STR	D1, [X4, X3,LSL #3]

    (739) 0x45dd3c ORR	X3, XZR, X0

    (739) 0x45dd40 ADD	X0, X0, #1

    (739) 0x45dd44 B	45dd84

      (740) 0x45dd48 LDR	D30, [X28, X0,LSL #3]

      (740) 0x45dd4c STR	D30, [X4, X0,LSL #3]

      (740) 0x45dd50 ADD	X0, X0, #8

      (740) 0x45dd54 LDR	D2, [X28, X30,LSL #3]

      (740) 0x45dd58 STR	D2, [X4, X30,LSL #3]

      (740) 0x45dd5c LDR	D3, [X28, X11,LSL #3]

      (740) 0x45dd60 STR	D3, [X4, X11,LSL #3]

      (740) 0x45dd64 LDR	D29, [X28, X14,LSL #3]

      (740) 0x45dd68 STR	D29, [X4, X14,LSL #3]

      (740) 0x45dd6c LDR	D4, [X28, X15,LSL #3]

      (740) 0x45dd70 STR	D4, [X4, X15,LSL #3]

      (740) 0x45dd74 LDR	D5, [X28, X7,LSL #3]

      (740) 0x45dd78 STR	D5, [X4, X7,LSL #3]

      (740) 0x45dd7c LDR	D6, [X28, X6,LSL #3]

      (740) 0x45dd80 STR	D6, [X4, X6,LSL #3]

      (740) 0x45dd84 LDR	D31, [X28, X3,LSL #3]

      (740) 0x45dd88 ADD	X30, X0, #1

      (740) 0x45dd8c ADD	X11, X0, #2

      (740) 0x45dd90 ADD	X14, X0, #3

      (740) 0x45dd94 ADD	X15, X0, #4

      (740) 0x45dd98 ADD	X7, X0, #5

      (740) 0x45dd9c ADD	X6, X0, #6

      (740) 0x45dda0 STR	D31, [X4, X3,LSL #3]

      (740) 0x45dda4 ADD	X3, X0, #7

      (740) 0x45dda8 CMP	X12, X0

      (740) 0x45ddac B.NE	45dd48

    (739) 0x45ddb0 B	45d5d4

    (739) 0x45ddb4 SUB	X9, X18, X4,LSL #3

    (739) 0x45ddb8 SUB	X24, X11, X3

    (739) 0x45ddbc ANDS	X18, X24, #0x7

    (739) 0x45ddc0 ADD	X30, X19, X9

    (739) 0x45ddc4 B.EQ	45dea8

    (739) 0x45ddc8 LDR	D30, [X27, X4,LSL #3]

    (739) 0x45ddcc STR	D30, [X30, X4,LSL #3]

    (739) 0x45ddd0 ORR	X4, XZR, X3

    (739) 0x45ddd4 ADD	X3, X3, #1

    (739) 0x45ddd8 CMP	X18, #1

    (739) 0x45dddc B.EQ	45dea8

    (739) 0x45dde0 CMP	X18, #2

    (739) 0x45dde4 B.EQ	45de58

    (739) 0x45dde8 CMP	X18, #3

    (739) 0x45ddec B.EQ	45de48

    (739) 0x45ddf0 CMP	X18, #4

    (739) 0x45ddf4 B.EQ	45de38

    (739) 0x45ddf8 CMP	X18, #5

    (739) 0x45ddfc B.EQ	45de28

    (739) 0x45de00 CMP	X18, #6

    (739) 0x45de04 B.EQ	45de18

    (739) 0x45de08 LDR	D2, [X27, X4,LSL #3]

    (739) 0x45de0c STR	D2, [X30, X4,LSL #3]

    (739) 0x45de10 ORR	X4, XZR, X3

    (739) 0x45de14 ADD	X3, X3, #1

    (739) 0x45de18 LDR	D3, [X27, X4,LSL #3]

    (739) 0x45de1c STR	D3, [X30, X4,LSL #3]

    (739) 0x45de20 ORR	X4, XZR, X3

    (739) 0x45de24 ADD	X3, X3, #1

    (739) 0x45de28 LDR	D29, [X27, X4,LSL #3]

    (739) 0x45de2c STR	D29, [X30, X4,LSL #3]

    (739) 0x45de30 ORR	X4, XZR, X3

    (739) 0x45de34 ADD	X3, X3, #1

    (739) 0x45de38 LDR	D4, [X27, X4,LSL #3]

    (739) 0x45de3c STR	D4, [X30, X4,LSL #3]

    (739) 0x45de40 ORR	X4, XZR, X3

    (739) 0x45de44 ADD	X3, X3, #1

    (739) 0x45de48 LDR	D5, [X27, X4,LSL #3]

    (739) 0x45de4c STR	D5, [X30, X4,LSL #3]

    (739) 0x45de50 ORR	X4, XZR, X3

    (739) 0x45de54 ADD	X3, X3, #1

    (739) 0x45de58 LDR	D6, [X27, X4,LSL #3]

    (739) 0x45de5c STR	D6, [X30, X4,LSL #3]

    (739) 0x45de60 ORR	X4, XZR, X3

    (739) 0x45de64 ADD	X3, X3, #1

    (739) 0x45de68 B	45dea8

      (742) 0x45de6c LDR	D7, [X27, X3,LSL #3]

      (742) 0x45de70 STR	D7, [X30, X3,LSL #3]

      (742) 0x45de74 ADD	X3, X3, #8

      (742) 0x45de78 LDR	D16, [X27, X6,LSL #3]

      (742) 0x45de7c STR	D16, [X30, X6,LSL #3]

      (742) 0x45de80 LDR	D17, [X27, X13,LSL #3]

      (742) 0x45de84 STR	D17, [X30, X13,LSL #3]

      (742) 0x45de88 LDR	D18, [X27, X12,LSL #3]

      (742) 0x45de8c STR	D18, [X30, X12,LSL #3]

      (742) 0x45de90 LDR	D19, [X27, X10,LSL #3]

      (742) 0x45de94 STR	D19, [X30, X10,LSL #3]

      (742) 0x45de98 LDR	D20, [X27, X9,LSL #3]

      (742) 0x45de9c STR	D20, [X30, X9,LSL #3]

      (742) 0x45dea0 LDR	D21, [X27, X7,LSL #3]

      (742) 0x45dea4 STR	D21, [X30, X7,LSL #3]

      (742) 0x45dea8 LDR	D7, [X27, X4,LSL #3]

      (742) 0x45deac ADD	X6, X3, #1

      (742) 0x45deb0 ADD	X13, X3, #2

      (742) 0x45deb4 ADD	X12, X3, #3

      (742) 0x45deb8 ADD	X10, X3, #4

      (742) 0x45debc ADD	X9, X3, #5

      (742) 0x45dec0 ADD	X7, X3, #6

      (742) 0x45dec4 STR	D7, [X30, X4,LSL #3]

      (742) 0x45dec8 ADD	X4, X3, #7

      (742) 0x45decc CMP	X11, X3

      (742) 0x45ded0 B.NE	45de6c

    (739) 0x45ded4 B	45d3ac

    (739) 0x45ded8 MOVZ	X30, #0

    (739) 0x45dedc B	45d5a0

    (739) 0x45dee0 MOVZ	X13, #0

    (739) 0x45dee4 B	45d378

(725) 0x45dee8 LDR	X24, [SP, #208]

(725) 0x45deec SUB	X3, X5, #1

(725) 0x45def0 MOVZ	X2, #0

(725) 0x45def4 STR	X5, [SP, #120]

(725) 0x45def8 LDR	X0, [X21, X22,LSL #3]

(725) 0x45defc ORR	X1, XZR, X24

(725) 0x45df00 BL	525ba0

(725) 0x45df04 LDR	X11, [SP, #568]

(725) 0x45df08 ORR	X8, XZR, X24

(725) 0x45df0c LDR	X6, [X20, X22,LSL #3]

(725) 0x45df10 LDR	X7, [X24]

(725) 0x45df14 LDR	X4, [X11, X23,LSL #3]

(725) 0x45df18 STR	X6, [SP, #576]

(725) 0x45df1c LDR	X12, [SP, #120]

(725) 0x45df20 STR	X6, [X4, X7,LSL #3]

(725) 0x45df24 CMP	X12, #1

(725) 0x45df28 B.EQ	45df78

(725) 0x45df2c LDR	X13, [X21, X22,LSL #3]

(725) 0x45df30 MOVZ	X2, #0

(725) 0x45df34 MOVZ	X1, #0

(725) 0x45df38 MOVZ	X3, #1

  (745) 0x45df3c LDR	X14, [X13, X3,LSL #3]

  (745) 0x45df40 ADD	X30, X13, X1

  (745) 0x45df44 LDR	X17, [X13, X1]

  (745) 0x45df48 CMP	X17, X14

  (745) 0x45df4c B.GE	45df88

  (745) 0x45df50 STR	X14, [X30, #8]

  (745) 0x45df54 ADD	X6, X6, #1

  (745) 0x45df58 ADD	X2, X2, #1

  (745) 0x45df5c LDR	X18, [X8, X3,LSL #3]

  (745) 0x45df60 ADD	X3, X3, #1

  (745) 0x45df64 UBFM	X1, X2, #61, #60

  (745) 0x45df68 STR	X6, [X4, X18,LSL #3]

  (745) 0x45df6c CMP	X12, X3

  (745) 0x45df70 B.NE	45df3c

(725) 0x45df74 STR	X6, [SP, #576]

(725) 0x45df78 LDR	X15, [SP, #576]

(725) 0x45df7c ADD	X9, X15, #1

(725) 0x45df80 STR	X9, [X20, X23,LSL #3]

(725) 0x45df84 B	45c9f0

  (745) 0x45df88 LDR	X16, [X8, X3,LSL #3]

  (745) 0x45df8c ADD	X3, X3, #1

  (745) 0x45df90 STR	X6, [X4, X16,LSL #3]

  (745) 0x45df94 CMP	X12, X3

  (745) 0x45df98 B.NE	45df3c

(725) 0x45df9c B	45df74

0x45dfa0 LDR	X27, [SP, #184]

0x45dfa4 MOVZ	X1, #8

0x45dfa8 STR	X6, [SP, #168]

0x45dfac ORR	X0, XZR, X27

0x45dfb0 BL	524ea8

0x45dfb4 MOVZ	X1, #8

0x45dfb8 ORR	X26, XZR, X0

0x45dfbc ORR	X0, XZR, X27

0x45dfc0 BL	524ea8

0x45dfc4 ORR	X9, XZR, X0

0x45dfc8 MOVZ	X1, #8

0x45dfcc ORR	X0, XZR, X27

0x45dfd0 STR	X9, [SP, #520]

0x45dfd4 BL	524ea8

0x45dfd8 ORR	X24, XZR, X0

0x45dfdc LDR	X0, [SP, #488]

0x45dfe0 MOVZ	X1, #8

0x45dfe4 BL	524ea8

0x45dfe8 LDR	X6, [SP, #168]

0x45dfec STR	X0, [SP, #136]

0x45dff0 B	45b25c

0x45dff4 MOVZ	X1, #8

0x45dff8 BL	524ea8

0x45dffc LDR	X28, [SP, #168]

0x45e000 STR	X0, [SP, #496]

0x45e004 B	45b588

0x45e008 MOVZ	X1, #112

0x45e00c MOVZ	X0, #1

0x45e010 STR	X6, [SP, #120]

0x45e014 STR	X7, [SP, #136]

0x45e018 BL	524ea8

0x45e01c ORR	X6, XZR, X0

0x45e020 MOVZ	X1, #8

0x45e024 ORR	X0, XZR, X24

0x45e028 STR	X6, [SP, #368]

0x45e02c BL	524ea8

0x45e030 ORR	X13, XZR, X0

0x45e034 MOVZ	X1, #8

0x45e038 ORR	X0, XZR, X24

0x45e03c STR	X13, [SP, #304]

0x45e040 BL	524ea8

0x45e044 ORR	X23, XZR, X0

0x45e048 MOVZ	X1, #8

0x45e04c ORR	X0, XZR, X24

0x45e050 STR	X23, [SP, #336]

0x45e054 BL	524ea8

0x45e058 LDR	X28, [SP, #184]

0x45e05c ORR	X24, XZR, X0

0x45e060 MOVZ	X1, #8

0x45e064 ADD	X0, X28, #1

0x45e068 BL	524ea8

0x45e06c STP	XZR, X0, [SP, #456]

0x45e070 LDR	X12, [SP, #120]

0x45e074 LDR	X4, [SP, #136]

0x45e078 CBNZ	X28, 45f7a4

0x45e07c STR	XZR, [SP, #376]

0x45e080 LDR	X8, [SP, #152]

0x45e084 LDR	X15, [SP, #288]

0x45e088 LDR	X0, [X15, X8,LSL #3]

0x45e08c CBNZ	X0, 45f784

0x45e090 LDR	X19, [SP, #296]

0x45e094 ADRP	X2,

0x45e098 MOVZ	W3, #0

0x45e09c ADD	X0, X2, #1736

0x45e0a0 MOVZ	W2, #0

0x45e0a4 STR	X12, [SP, #120]

0x45e0a8 LDR	X20, [SP, #184]

0x45e0ac STR	X4, [SP, #136]

0x45e0b0 LDR	X21, [SP, #464]

0x45e0b4 ORR	X1, XZR, X19

0x45e0b8 STR	X20, [SP, #832]

0x45e0bc STR	X21, [SP, #840]

0x45e0c0 BL	4103b0

0x45e0c4 LDR	X9, [SP, #152]

0x45e0c8 ADRP	X0,

0x45e0cc ORR	X1, XZR, X19

0x45e0d0 ADD	X0, X0, #1600

0x45e0d4 MOVZ	W3, #0

0x45e0d8 LDR	X7, [SP, #288]

0x45e0dc MOVZ	W2, #0

0x45e0e0 LDR	X14, [SP, #376]

0x45e0e4 STR	X9, [SP, #832]

0x45e0e8 STR	X7, [SP, #840]

0x45e0ec STR	X14, [SP, #848]

0x45e0f0 BL	4103b0

0x45e0f4 LDR	X17, [SP, #328]

0x45e0f8 LDR	X6, [SP, #120]

0x45e0fc LDR	X7, [SP, #136]

0x45e100 CMP	X17, #2

0x45e104 B.NE	45c2a8

0x45e108 MOVZ	X16, #0

0x45e10c STR	XZR, [SP, #208]

0x45e110 B	45cb30

0x45e114 MOVZ	X1, #8

0x45e118 ORR	X0, XZR, X24

0x45e11c BL	524ea8

0x45e120 STR	X0, [SP, #192]

0x45e124 MOVZ	X18, #0

0x45e128 LDR	X8, [SP, #120]

0x45e12c CBNZ	X28, 45f76c

0x45e130 MOVZ	X1, #8

0x45e134 ORR	X0, XZR, X24

0x45e138 STR	X8, [SP, #120]

0x45e13c LDR	X28, [SP, #192]

0x45e140 STR	X18, [X28, #8]

0x45e144 BL	524ea8

0x45e148 LDR	X9, [SP, #328]

0x45e14c ORR	X21, XZR, X0

0x45e150 MOVZ	X1, #8

0x45e154 STR	X21, [SP, #504]

0x45e158 ADD	X0, X9, #1

0x45e15c BL	524ea8

0x45e160 LDR	X14, [SP, #488]

0x45e164 MOVZ	X7, #0

0x45e168 LDR	X6, [SP, #120]

0x45e16c STP	XZR, X14, [X0]

0x45e170 LDR	X4, [SP, #136]

0x45e174 STR	X14, [SP, #472]

0x45e178 LDR	X30, [SP, #256]

0x45e17c STR	X0, [SP, #512]

0x45e180 STR	X4, [X21]

0x45e184 LDP	X5, X17, [X30, #8]

0x45e188 CMP	X5, X17

0x45e18c B.LT	45c1b0

0x45e190 LDR	X16, [SP, #128]

0x45e194 STR	X16, [SP, #624]

0x45e198 B	45c27c

(725) 0x45e19c LDR	X0, [SP, #208]

(725) 0x45e1a0 BL	524f40

(725) 0x45e1a4 MOVZ	X1, #8

(725) 0x45e1a8 MOVZ	X0, #0

(725) 0x45e1ac BL	524ea8

(725) 0x45e1b0 STR	X0, [SP, #208]

(725) 0x45e1b4 B	45da7c

(725) 0x45e1b8 MOVZ	X1, #8

(725) 0x45e1bc ORR	X0, XZR, X22

(725) 0x45e1c0 BL	524ea8

(725) 0x45e1c4 LDR	X24, [SP, #568]

(725) 0x45e1c8 ORR	X4, XZR, X0

(725) 0x45e1cc MOVZ	X1, #8

(725) 0x45e1d0 ORR	X0, XZR, X22

(725) 0x45e1d4 STR	X4, [X24, X23,LSL #3]

(725) 0x45e1d8 BL	524ea8

(725) 0x45e1dc ORR	X13, XZR, X0

(725) 0x45e1e0 LDR	X1, [SP, #368]

(725) 0x45e1e4 MOVZ	X0, #11

(725) 0x45e1e8 LDR	X2, [SP, #384]

(725) 0x45e1ec STR	X13, [X21, X19,LSL #3]

(725) 0x45e1f0 LDR	X3, [X24, W23,UXTW #3]

(725) 0x45e1f4 BL	4e0364

(725) 0x45e1f8 BL	4e0b6c

(725) 0x45e1fc LDR	X1, [SP, #544]

(725) 0x45e200 CMP	X22, X1

(725) 0x45e204 B.GT	45f5a0

(725) 0x45e208 STR	X22, [SP, #544]

(725) 0x45e20c B	45c83c

0x45e210 MOVZ	X1, #8

0x45e214 ORR	X0, XZR, X20

0x45e218 STR	X20, [SP, #120]

0x45e21c BL	524ea8

0x45e220 ORR	X19, XZR, X0

0x45e224 LDR	X0, [SP, #120]

0x45e228 MOVZ	X1, #8

0x45e22c STR	X19, [SP, #120]

0x45e230 BL	524ea8

0x45e234 LDR	X6, [SP, #136]

0x45e238 ORR	X28, XZR, X0

0x45e23c B	45cbb0

(725) 0x45e240 LDR	X0, [SP, #384]

(725) 0x45e244 BL	524f40

(725) 0x45e248 LDR	X0, [SP, #120]

(725) 0x45e24c MOVZ	X1, #8

(725) 0x45e250 BL	524ea8

(725) 0x45e254 LDR	X6, [SP, #120]

(725) 0x45e258 STR	X0, [SP, #384]

(725) 0x45e25c STR	X6, [SP, #528]

(725) 0x45e260 B	45c32c

0x45e264 LDR	X4, [SP, #144]

0x45e268 ADRP	X8,

0x45e26c MOVZ	W2, #0

0x45e270 ADD	X0, X8, #1900

0x45e274 STR	X23, [SP, #136]

0x45e278 MOVZ	W3, #0

0x45e27c LDR	X15, [SP, #184]

0x45e280 STR	X27, [SP, #920]

0x45e284 LDR	X7, [SP, #240]

0x45e288 STR	X4, [SP, #936]

0x45e28c LDR	X6, [SP, #248]

0x45e290 STR	X15, [SP, #912]

0x45e294 LDR	X12, [SP, #320]

0x45e298 STR	X7, [SP, #928]

0x45e29c LDR	X20, [SP, #432]

0x45e2a0 STR	X28, [SP, #944]

0x45e2a4 LDR	X17, [SP, #440]

0x45e2a8 STR	X12, [SP, #832]

0x45e2ac LDR	X18, [SP, #448]

0x45e2b0 STR	X20, [SP, #840]

0x45e2b4 LDR	X21, [SP, #584]

0x45e2b8 STR	X17, [SP, #888]

0x45e2bc LDR	X30, [SP, #592]

0x45e2c0 STR	X18, [SP, #904]

0x45e2c4 LDR	X13, [SP, #600]

0x45e2c8 STR	X21, [SP, #848]

0x45e2cc LDR	X14, [SP, #608]

0x45e2d0 STR	X30, [SP, #864]

0x45e2d4 LDR	X16, [SP, #616]

0x45e2d8 STR	X13, [SP, #872]

0x45e2dc LDR	X11, [SP, #1176]

0x45e2e0 STR	X14, [SP, #880]

0x45e2e4 LDR	X1, [SP, #296]

0x45e2e8 STR	X16, [SP, #896]

0x45e2ec STR	X6, [SP, #952]

0x45e2f0 STR	X11, [SP, #856]

0x45e2f4 LDR	X19, [SP, #120]

0x45e2f8 STR	X10, [SP, #1080]

0x45e2fc LDR	X30, [SP, #192]

0x45e300 LDR	X11, [SP, #200]

0x45e304 STR	X19, [SP, #960]

0x45e308 LDR	X16, [SP, #232]

0x45e30c STR	X30, [SP, #1040]

0x45e310 LDR	X12, [SP, #256]

0x45e314 STR	X11, [SP, #1032]

0x45e318 LDR	X14, [SP, #264]

0x45e31c STR	X16, [SP, #1072]

0x45e320 LDR	X8, [SP, #272]

0x45e324 STR	X12, [SP, #1008]

0x45e328 LDR	X17, [SP, #312]

0x45e32c STR	X14, [SP, #1056]

0x45e330 LDR	X9, [SP, #352]

0x45e334 STR	X8, [SP, #1000]

0x45e338 LDR	X10, [SP, #360]

0x45e33c STR	X17, [SP, #1064]

0x45e340 LDR	X21, [SP, #408]

0x45e344 STR	X9, [SP, #968]

0x45e348 LDR	X20, [SP, #416]

0x45e34c STR	X10, [SP, #984]

0x45e350 LDR	X23, [SP, #424]

0x45e354 STR	X21, [SP, #1016]

0x45e358 LDR	X5, [SP, #496]

0x45e35c STR	X20, [SP, #1024]

0x45e360 LDR	X13, [SP, #520]

0x45e364 STR	X23, [SP, #976]

0x45e368 STR	X5, [SP, #992]

0x45e36c STR	X13, [SP, #1048]

0x45e370 BL	4103b0

0x45e374 LDP	X0, X2, [SP, #128]

0x45e378 CBNZ	X0, 45f75c

0x45e37c STR	X2, [SP, #136]

0x45e380 LDR	X0, [SP, #496]

0x45e384 BL	524f40

0x45e388 LDR	X19, [SP, #200]

0x45e38c LDR	X0, [X19, #8]

0x45e390 BL	524f40

0x45e394 LDR	X3, [SP, #816]

0x45e398 STR	XZR, [X19, #8]

0x45e39c LDR	X15, [SP, #136]

0x45e3a0 CMP	X3, #1

0x45e3a4 B.LE	45e3bc

0x45e3a8 LDR	X23, [SP, #192]

0x45e3ac LDR	X0, [X23, #8]

0x45e3b0 BL	524f40

0x45e3b4 LDR	X15, [SP, #136]

0x45e3b8 STR	XZR, [X23, #8]

0x45e3bc LDR	X7, [SP, #328]

0x45e3c0 CMP	X7, #2

0x45e3c4 B.EQ	45f7c0

0x45e3c8 LDR	X10, [SP, #152]

0x45e3cc ADRP	X6,

0x45e3d0 MOVZ	X4, #0

0x45e3d4 ADD	X9, X6, #780

0x45e3d8 MOVZ	X19, #0

0x45e3dc STR	XZR, [SP, #136]

0x45e3e0 LDR	X8, [SP, #176]

0x45e3e4 MOVZ	X20, #1

0x45e3e8 MOVZ	X23, #2

0x45e3ec STR	XZR, [SP, #160]

0x45e3f0 LDR	X11, [SP, #256]

0x45e3f4 UBFM	X5, X10, #61, #60

0x45e3f8 STP	X4, X26, [SP, #208]

0x45e3fc UBFM	X12, X8, #61, #60

0x45e400 LDR	X13, [SP, #288]

0x45e404 ADD	X30, X11, #8

0x45e408 LDP	X26, X21, [SP, #240]

0x45e40c STR	X5, [SP, #280]

0x45e410 ADD	X14, X13, #8

0x45e414 STR	X12, [SP, #344]

0x45e418 STR	X9, [SP, #360]

0x45e41c STR	X14, [SP, #376]

0x45e420 STR	X30, [SP, #384]

0x45e424 STR	X15, [SP, #496]

0x45e428 B	45e5cc

(730) 0x45e42c LDR	X5, [SP, #256]

(730) 0x45e430 ADD	X18, SP, #952

(730) 0x45e434 MOVZ	W3, #0

(730) 0x45e438 MOVZ	W2, #0

(730) 0x45e43c LDR	X17, [SP, #384]

(730) 0x45e440 LDR	X8, [SP, #480]

(730) 0x45e444 LDR	X9, [SP, #144]

(730) 0x45e448 LDR	X13, [X17, X23,LSL #3]

(730) 0x45e44c LDR	X16, [X5, X23,LSL #3]

(730) 0x45e450 STR	X8, [SP, #928]

(730) 0x45e454 LDR	X1, [SP, #296]

(730) 0x45e458 LDR	X0, [SP, #360]

(730) 0x45e45c STP	X27, X26, [X18]

(730) 0x45e460 SUB	X10, X13, X16

(730) 0x45e464 STP	X9, X28, [X18, #16]

(730) 0x45e468 LDR	X4, [SP, #120]

(730) 0x45e46c STR	X5, [SP, #1032]

(730) 0x45e470 LDR	X14, [SP, #184]

(730) 0x45e474 STR	X21, [SP, #984]

(730) 0x45e478 LDR	X5, [SP, #272]

(730) 0x45e47c STR	X4, [SP, #992]

(730) 0x45e480 LDR	X6, [SP, #352]

(730) 0x45e484 STR	X14, [SP, #944]

(730) 0x45e488 LDR	X30, [SP, #392]

(730) 0x45e48c STR	X5, [SP, #1024]

(730) 0x45e490 LDR	X11, [SP, #408]

(730) 0x45e494 STR	X6, [SP, #1008]

(730) 0x45e498 LDR	X15, [SP, #416]

(730) 0x45e49c STR	X30, [SP, #936]

(730) 0x45e4a0 LDR	X12, [SP, #424]

(730) 0x45e4a4 STR	X11, [SP, #1040]

(730) 0x45e4a8 LDR	X7, [SP, #456]

(730) 0x45e4ac STR	X15, [SP, #1048]

(730) 0x45e4b0 STR	X24, [SP, #1072]

(730) 0x45e4b4 STR	X12, [SP, #1016]

(730) 0x45e4b8 STR	X7, [SP, #1000]

(730) 0x45e4bc STR	X23, [SP, #1096]

(730) 0x45e4c0 LDR	X30, [SP, #128]

(730) 0x45e4c4 LDP	X17, X8, [SP, #192]

(730) 0x45e4c8 STR	X10, [SP, #1160]

(730) 0x45e4cc LDR	X7, [SP, #136]

(730) 0x45e4d0 STR	X8, [SP, #1056]

(730) 0x45e4d4 LDR	X15, [SP, #216]

(730) 0x45e4d8 STR	X17, [SP, #1064]

(730) 0x45e4dc LDR	X10, [SP, #264]

(730) 0x45e4e0 STR	X30, [SP, #1112]

(730) 0x45e4e4 LDR	X18, [SP, #312]

(730) 0x45e4e8 STR	X22, [SP, #1128]

(730) 0x45e4ec LDR	X9, [SP, #320]

(730) 0x45e4f0 STR	X10, [SP, #1088]

(730) 0x45e4f4 LDR	X4, [SP, #432]

(730) 0x45e4f8 STR	X18, [SP, #1104]

(730) 0x45e4fc LDR	X13, [SP, #464]

(730) 0x45e500 STR	X9, [SP, #832]

(730) 0x45e504 LDR	X6, [SP, #472]

(730) 0x45e508 STR	X4, [SP, #840]

(730) 0x45e50c LDR	X14, [SP, #488]

(730) 0x45e510 STR	X13, [SP, #1080]

(730) 0x45e514 LDR	X16, [SP, #496]

(730) 0x45e518 STR	X15, [SP, #1136]

(730) 0x45e51c LDR	X11, [SP, #584]

(730) 0x45e520 STR	X14, [SP, #1120]

(730) 0x45e524 LDR	X12, [SP, #1176]

(730) 0x45e528 STR	X16, [SP, #920]

(730) 0x45e52c STR	X7, [SP, #1144]

(730) 0x45e530 STR	X11, [SP, #848]

(730) 0x45e534 STR	X6, [SP, #1152]

(730) 0x45e538 STR	X12, [SP, #856]

(730) 0x45e53c LDR	X5, [SP, #592]

(730) 0x45e540 LDR	X13, [SP, #440]

(730) 0x45e544 LDR	X10, [SP, #448]

(730) 0x45e548 STR	X5, [SP, #864]

(730) 0x45e54c LDR	X9, [SP, #536]

(730) 0x45e550 STR	X13, [SP, #888]

(730) 0x45e554 LDR	X17, [SP, #600]

(730) 0x45e558 STR	X10, [SP, #904]

(730) 0x45e55c LDR	X8, [SP, #608]

(730) 0x45e560 STR	X9, [SP, #912]

(730) 0x45e564 LDR	X16, [SP, #616]

(730) 0x45e568 STR	X17, [SP, #872]

(730) 0x45e56c STR	X8, [SP, #880]

(730) 0x45e570 STR	X16, [SP, #896]

(730) 0x45e574 BL	4103b0

(730) 0x45e578 LDR	X2, [SP, #200]

(730) 0x45e57c LDR	X0, [X2, X23,LSL #3]

(730) 0x45e580 BL	524f40

(730) 0x45e584 LDR	X1, [SP, #200]

(730) 0x45e588 LDR	X3, [SP, #816]

(730) 0x45e58c STR	XZR, [X1, X23,LSL #3]

(730) 0x45e590 CMP	X3, #1

(730) 0x45e594 B.LE	45e5b8

(730) 0x45e598 LDR	X0, [SP, #192]

(730) 0x45e59c LDR	X0, [X0, X23,LSL #3]

(730) 0x45e5a0 BL	524f40

(730) 0x45e5a4 LDR	X18, [SP, #192]

(730) 0x45e5a8 STR	XZR, [X18, X23,LSL #3]

(730) 0x45e5ac LDR	X0, [X24, X23,LSL #3]

(730) 0x45e5b0 BL	524f40

(730) 0x45e5b4 STR	XZR, [X24, X23,LSL #3]

(730) 0x45e5b8 LDR	X4, [SP, #328]

(730) 0x45e5bc ADD	X23, X23, #1

(730) 0x45e5c0 ADD	X20, X20, #1

(730) 0x45e5c4 CMP	X4, X23

(730) 0x45e5c8 B.EQ	45ee24

(730) 0x45e5cc LDR	X17, [SP, #816]

(730) 0x45e5d0 CMP	X17, #1

(730) 0x45e5d4 B.LE	45e42c

(730) 0x45e5d8 LDR	X0, [SP, #304]

(730) 0x45e5dc LDR	X2, [SP, #280]

(730) 0x45e5e0 LDR	X16, [SP, #208]

(730) 0x45e5e4 LDR	X13, [X0, X23,LSL #3]

(730) 0x45e5e8 LDR	X3, [X13, X2]

(730) 0x45e5ec STR	X3, [SP, #168]

(730) 0x45e5f0 CMP	X3, X16

(730) 0x45e5f4 B.GT	45edc0

(730) 0x45e5f8 LDR	X18, [SP, #152]

(730) 0x45e5fc MOVZ	X5, #0

(730) 0x45e600 MOVZ	X2, #0

(730) 0x45e604 ORR	X17, XZR, X13

(730) 0x45e608 CMP	X18, #0

(730) 0x45e60c B.LE	45ead8

  (731) 0x45e610 LDR	X15, [SP, #288]

  (731) 0x45e614 LDR	X7, [SP, #376]

  (731) 0x45e618 LDR	X1, [X15, X2,LSL #3]

  (731) 0x45e61c LDR	X8, [X7, X2,LSL #3]

  (731) 0x45e620 CMP	X1, X8

  (731) 0x45e624 B.GE	45eac4

  (731) 0x45e628 ORR	X16, XZR, X24

  (731) 0x45e62c B	45e63c

    (732) 0x45e630 ADD	X1, X1, #1

    (732) 0x45e634 CMP	X1, X8

    (732) 0x45e638 B.EQ	45eac0

    (732) 0x45e63c LDR	X24, [X25, X1,LSL #3]

    (732) 0x45e640 UBFM	X0, X24, #61, #60

    (732) 0x45e644 LDR	X4, [X22, X0]

    (732) 0x45e648 CMP	X4, X20

    (732) 0x45e64c B.NE	45e630

    (732) 0x45e650 ADD	X14, X0, #8

    (732) 0x45e654 LDR	X4, [X26, X0]

    (732) 0x45e658 LDR	X11, [X26, X14]

    (732) 0x45e65c CMP	X4, X11

    (732) 0x45e660 B.GE	45e88c

    (732) 0x45e664 ADD	X3, X4, #1

    (732) 0x45e668 ADD	X6, X19, X5,LSL #3

    (732) 0x45e66c UBFM	X18, X5, #61, #60

    (732) 0x45e670 ADD	X9, X27, X3,LSL #3

    (732) 0x45e674 UBFM	X10, X3, #61, #60

    (732) 0x45e678 ORR	X15, XZR, X4

    (732) 0x45e67c SUB	X12, X6, X9

    (732) 0x45e680 CMP	X12, #16

    (732) 0x45e684 B.LS	45ec8c

    (732) 0x45e688 SUB	X12, X11, X4

    (732) 0x45e68c SUB	X30, X12, #1

    (732) 0x45e690 CMP	X30, #2

    (732) 0x45e694 B.LS	45edb0

    (732) 0x45e698 UBFM	X7, X12, #2, #63

    (732) 0x45e69c SUB	X30, X10, #8

    (732) 0x45e6a0 UBFM	X13, X7, #59, #58

    (732) 0x45e6a4 ADD	X7, X27, X30

    (732) 0x45e6a8 SUB	X24, X13, #32

    (732) 0x45e6ac MOVZ	X3, #0

    (732) 0x45e6b0 UBFM	X24, X24, #5, #63

    (732) 0x45e6b4 ADD	X10, X7, #16

    (732) 0x45e6b8 ADD	X24, X24, #1

    (732) 0x45e6bc ADD	X9, X6, #16

    (732) 0x45e6c0 ANDS	X24, X24, #0x7

    (732) 0x45e6c4 B.EQ	45e78c

    (732) 0x45e6c8 CMP	X24, #1

    (732) 0x45e6cc B.EQ	45e770

    (732) 0x45e6d0 CMP	X24, #2

    (732) 0x45e6d4 B.EQ	45e75c

    (732) 0x45e6d8 CMP	X24, #3

    (732) 0x45e6dc B.EQ	45e748

    (732) 0x45e6e0 CMP	X24, #4

    (732) 0x45e6e4 B.EQ	45e734

    (732) 0x45e6e8 CMP	X24, #5

    (732) 0x45e6ec B.EQ	45e720

    (732) 0x45e6f0 CMP	X24, #6

    (732) 0x45e6f4 B.EQ	45e70c

    (732) 0x45e6f8 LDR	Q0, [X27, X30]

    (732) 0x45e6fc MOVZ	X3, #32

    (732) 0x45e700 LDR	Q26, [X7, #16]

    (732) 0x45e704 STR	Q0, [X19, X18]

    (732) 0x45e708 STR	Q26, [X6, #16]

    (732) 0x45e70c LDR	Q27, [X7, X3]

    (732) 0x45e710 LDR	Q28, [X10, X3]

    (732) 0x45e714 STR	Q27, [X6, X3]

    (732) 0x45e718 STR	Q28, [X9, X3]

    (732) 0x45e71c ADD	X3, X3, #32

    (732) 0x45e720 LDR	Q1, [X7, X3]

    (732) 0x45e724 LDR	Q31, [X10, X3]

    (732) 0x45e728 STR	Q1, [X6, X3]

    (732) 0x45e72c STR	Q31, [X9, X3]

    (732) 0x45e730 ADD	X3, X3, #32

    (732) 0x45e734 LDR	Q30, [X7, X3]

    (732) 0x45e738 LDR	Q2, [X10, X3]

    (732) 0x45e73c STR	Q30, [X6, X3]

    (732) 0x45e740 STR	Q2, [X9, X3]

    (732) 0x45e744 ADD	X3, X3, #32

    (732) 0x45e748 LDR	Q3, [X7, X3]

    (732) 0x45e74c LDR	Q29, [X10, X3]

    (732) 0x45e750 STR	Q3, [X6, X3]

    (732) 0x45e754 STR	Q29, [X9, X3]

    (732) 0x45e758 ADD	X3, X3, #32

    (732) 0x45e75c LDR	Q4, [X7, X3]

    (732) 0x45e760 LDR	Q5, [X10, X3]

    (732) 0x45e764 STR	Q4, [X6, X3]

    (732) 0x45e768 STR	Q5, [X9, X3]

    (732) 0x45e76c ADD	X3, X3, #32

    (732) 0x45e770 LDR	Q6, [X7, X3]

    (732) 0x45e774 LDR	Q7, [X10, X3]

    (732) 0x45e778 STR	Q6, [X6, X3]

    (732) 0x45e77c STR	Q7, [X9, X3]

    (732) 0x45e780 ADD	X3, X3, #32

    (732) 0x45e784 CMP	X13, X3

    (732) 0x45e788 B.EQ	45e844

    (732) 0x45e78c STR	X25, [SP, #208]

    (732) 0x45e790 STR	X17, [SP, #224]

      (736) 0x45e794 LDR	Q16, [X7, X3]

      (736) 0x45e798 ADD	X17, X3, #32

      (736) 0x45e79c ADD	X30, X3, #64

      (736) 0x45e7a0 ADD	X25, X3, #96

      (736) 0x45e7a4 ADD	X24, X3, #128

      (736) 0x45e7a8 LDR	Q17, [X10, X3]

      (736) 0x45e7ac ADD	X18, X3, #160

      (736) 0x45e7b0 STR	Q16, [X6, X3]

      (736) 0x45e7b4 STR	Q17, [X9, X3]

      (736) 0x45e7b8 LDR	Q18, [X7, X17]

      (736) 0x45e7bc LDR	Q19, [X10, X17]

      (736) 0x45e7c0 STR	Q18, [X6, X17]

      (736) 0x45e7c4 STR	Q19, [X9, X17]

      (736) 0x45e7c8 ADD	X17, X3, #192

      (736) 0x45e7cc LDR	Q20, [X7, X30]

      (736) 0x45e7d0 LDR	Q21, [X10, X30]

      (736) 0x45e7d4 STR	Q20, [X6, X30]

      (736) 0x45e7d8 STR	Q21, [X9, X30]

      (736) 0x45e7dc ADD	X30, X3, #224

      (736) 0x45e7e0 ADD	X3, X3, #256

      (736) 0x45e7e4 LDR	Q22, [X7, X25]

      (736) 0x45e7e8 LDR	Q23, [X10, X25]

      (736) 0x45e7ec STR	Q22, [X6, X25]

      (736) 0x45e7f0 STR	Q23, [X9, X25]

      (736) 0x45e7f4 LDR	Q24, [X7, X24]

      (736) 0x45e7f8 LDR	Q25, [X10, X24]

      (736) 0x45e7fc STR	Q24, [X6, X24]

      (736) 0x45e800 STR	Q25, [X9, X24]

      (736) 0x45e804 LDR	Q0, [X7, X18]

      (736) 0x45e808 LDR	Q26, [X10, X18]

      (736) 0x45e80c STR	Q0, [X6, X18]

      (736) 0x45e810 STR	Q26, [X9, X18]

      (736) 0x45e814 LDR	Q27, [X7, X17]

      (736) 0x45e818 LDR	Q28, [X10, X17]

      (736) 0x45e81c STR	Q27, [X6, X17]

      (736) 0x45e820 STR	Q28, [X9, X17]

      (736) 0x45e824 LDR	Q1, [X7, X30]

      (736) 0x45e828 LDR	Q31, [X10, X30]

      (736) 0x45e82c STR	Q1, [X6, X30]

      (736) 0x45e830 STR	Q31, [X9, X30]

      (736) 0x45e834 CMP	X13, X3

      (736) 0x45e838 B.NE	45e794

    (732) 0x45e83c LDR	X25, [SP, #208]

    (732) 0x45e840 LDR	X17, [SP, #224]

    (732) 0x45e844 AND	X13, X12, #0x0

    (732) 0x45e848 ANDS	XZR, X12, #0x3

    (732) 0x45e84c B.EQ	45e884

    (732) 0x45e850 ADD	X6, X13, X5

    (732) 0x45e854 SUB	X12, X12, X13

    (732) 0x45e858 WHILELO	P1.D, XZR, X12

    (732) 0x45e85c ADD	X13, X13, X4

    (732) 0x45e860 ADD	X4, X19, X6,LSL #3

    (732) 0x45e864 LD1D	{Z30.D}, P1/Z, [X27, X13,LSL #3]

    (732) 0x45e868 ST1D	{Z30.D}, P1, [X4, MUL VL]

    (732) 0x45e86c CNTD	X10, ALL

    (732) 0x45e870 ADD	X7, X27, X13,LSL #3

    (732) 0x45e874 WHILELO	P2.D, X10, X12

    (732) 0x45e878 B.EQ	45e884

    (732) 0x45e87c LD1D	{Z2.D}, P2/Z, [X7, #1, MUL VL]

    (732) 0x45e880 ST1D	{Z2.D}, P2, [X4, #1, MUL VL]

    (732) 0x45e884 SUB	X11, X11, X15

    (732) 0x45e888 ADD	X5, X11, X5

    (732) 0x45e88c LDR	X3, [X21, X0]

    (732) 0x45e890 LDR	X12, [X21, X14]

    (732) 0x45e894 CMP	X3, X12

    (732) 0x45e898 B.GE	45e630

    (732) 0x45e89c ADD	X0, X3, #1

    (732) 0x45e8a0 ADD	X6, X19, X5,LSL #3

    (732) 0x45e8a4 UBFM	X24, X5, #61, #60

    (732) 0x45e8a8 ADD	X14, X28, X0,LSL #3

    (732) 0x45e8ac UBFM	X18, X0, #61, #60

    (732) 0x45e8b0 ORR	X13, XZR, X3

    (732) 0x45e8b4 SUB	X15, X6, X14

    (732) 0x45e8b8 CMP	X15, #16

    (732) 0x45e8bc B.LS	45eb68

    (732) 0x45e8c0 SUB	X14, X12, X3

    (732) 0x45e8c4 SUB	X0, X14, #1

    (732) 0x45e8c8 CMP	X0, #2

    (732) 0x45e8cc B.LS	45edb8

    (732) 0x45e8d0 UBFM	X4, X14, #2, #63

    (732) 0x45e8d4 SUB	X18, X18, #8

    (732) 0x45e8d8 UBFM	X15, X4, #59, #58

    (732) 0x45e8dc ADD	X7, X28, X18

    (732) 0x45e8e0 SUB	X9, X15, #32

    (732) 0x45e8e4 MOVZ	X0, #0

    (732) 0x45e8e8 UBFM	X11, X9, #5, #63

    (732) 0x45e8ec ADD	X10, X7, #16

    (732) 0x45e8f0 ADD	X30, X11, #1

    (732) 0x45e8f4 ADD	X9, X6, #16

    (732) 0x45e8f8 ANDS	X4, X30, #0x7

    (732) 0x45e8fc B.EQ	45e9c4

    (732) 0x45e900 CMP	X4, #1

    (732) 0x45e904 B.EQ	45e9a8

    (732) 0x45e908 CMP	X4, #2

    (732) 0x45e90c B.EQ	45e994

    (732) 0x45e910 CMP	X4, #3

    (732) 0x45e914 B.EQ	45e980

    (732) 0x45e918 CMP	X4, #4

    (732) 0x45e91c B.EQ	45e96c

    (732) 0x45e920 CMP	X4, #5

    (732) 0x45e924 B.EQ	45e958

    (732) 0x45e928 CMP	X4, #6

    (732) 0x45e92c B.EQ	45e944

    (732) 0x45e930 LDR	Q18, [X28, X18]

    (732) 0x45e934 MOVZ	X0, #32

    (732) 0x45e938 LDR	Q19, [X7, #16]

    (732) 0x45e93c STR	Q18, [X19, X24]

    (732) 0x45e940 STR	Q19, [X6, #16]

    (732) 0x45e944 LDR	Q20, [X7, X0]

    (732) 0x45e948 LDR	Q21, [X10, X0]

    (732) 0x45e94c STR	Q20, [X6, X0]

    (732) 0x45e950 STR	Q21, [X9, X0]

    (732) 0x45e954 ADD	X0, X0, #32

    (732) 0x45e958 LDR	Q22, [X7, X0]

    (732) 0x45e95c LDR	Q23, [X10, X0]

    (732) 0x45e960 STR	Q22, [X6, X0]

    (732) 0x45e964 STR	Q23, [X9, X0]

    (732) 0x45e968 ADD	X0, X0, #32

    (732) 0x45e96c LDR	Q24, [X7, X0]

    (732) 0x45e970 LDR	Q25, [X10, X0]

    (732) 0x45e974 STR	Q24, [X6, X0]

    (732) 0x45e978 STR	Q25, [X9, X0]

    (732) 0x45e97c ADD	X0, X0, #32

    (732) 0x45e980 LDR	Q0, [X7, X0]

    (732) 0x45e984 LDR	Q26, [X10, X0]

    (732) 0x45e988 STR	Q0, [X6, X0]

    (732) 0x45e98c STR	Q26, [X9, X0]

    (732) 0x45e990 ADD	X0, X0, #32

    (732) 0x45e994 LDR	Q27, [X7, X0]

    (732) 0x45e998 LDR	Q28, [X10, X0]

    (732) 0x45e99c STR	Q27, [X6, X0]

    (732) 0x45e9a0 STR	Q28, [X9, X0]

    (732) 0x45e9a4 ADD	X0, X0, #32

    (732) 0x45e9a8 LDR	Q1, [X7, X0]

    (732) 0x45e9ac LDR	Q31, [X10, X0]

    (732) 0x45e9b0 STR	Q1, [X6, X0]

    (732) 0x45e9b4 STR	Q31, [X9, X0]

    (732) 0x45e9b8 ADD	X0, X0, #32

    (732) 0x45e9bc CMP	X0, X15

    (732) 0x45e9c0 B.EQ	45ea6c

      (734) 0x45e9c4 LDR	Q30, [X7, X0]

      (734) 0x45e9c8 ADD	X4, X0, #32

      (734) 0x45e9cc ADD	X30, X0, #64

      (734) 0x45e9d0 ADD	X24, X0, #96

      (734) 0x45e9d4 ADD	X18, X0, #128

      (734) 0x45e9d8 LDR	Q2, [X10, X0]

      (734) 0x45e9dc ADD	X11, X0, #160

      (734) 0x45e9e0 STR	Q30, [X6, X0]

      (734) 0x45e9e4 STR	Q2, [X9, X0]

      (734) 0x45e9e8 LDR	Q3, [X7, X4]

      (734) 0x45e9ec LDR	Q29, [X10, X4]

      (734) 0x45e9f0 STR	Q3, [X6, X4]

      (734) 0x45e9f4 STR	Q29, [X9, X4]

      (734) 0x45e9f8 ADD	X4, X0, #192

      (734) 0x45e9fc LDR	Q4, [X7, X30]

      (734) 0x45ea00 LDR	Q5, [X10, X30]

      (734) 0x45ea04 STR	Q4, [X6, X30]

      (734) 0x45ea08 STR	Q5, [X9, X30]

      (734) 0x45ea0c ADD	X30, X0, #224

      (734) 0x45ea10 ADD	X0, X0, #256

      (734) 0x45ea14 LDR	Q6, [X7, X24]

      (734) 0x45ea18 LDR	Q7, [X10, X24]

      (734) 0x45ea1c STR	Q6, [X6, X24]

      (734) 0x45ea20 STR	Q7, [X9, X24]

      (734) 0x45ea24 LDR	Q16, [X7, X18]

      (734) 0x45ea28 LDR	Q17, [X10, X18]

      (734) 0x45ea2c STR	Q16, [X6, X18]

      (734) 0x45ea30 STR	Q17, [X9, X18]

      (734) 0x45ea34 LDR	Q18, [X7, X11]

      (734) 0x45ea38 LDR	Q19, [X10, X11]

      (734) 0x45ea3c STR	Q18, [X6, X11]

      (734) 0x45ea40 STR	Q19, [X9, X11]

      (734) 0x45ea44 LDR	Q20, [X7, X4]

      (734) 0x45ea48 LDR	Q21, [X10, X4]

      (734) 0x45ea4c STR	Q20, [X6, X4]

      (734) 0x45ea50 STR	Q21, [X9, X4]

      (734) 0x45ea54 LDR	Q22, [X7, X30]

      (734) 0x45ea58 LDR	Q23, [X10, X30]

      (734) 0x45ea5c STR	Q22, [X6, X30]

      (734) 0x45ea60 STR	Q23, [X9, X30]

      (734) 0x45ea64 CMP	X0, X15

      (734) 0x45ea68 B.NE	45e9c4

    (732) 0x45ea6c AND	X30, X14, #0x0

    (732) 0x45ea70 ANDS	XZR, X14, #0x3

    (732) 0x45ea74 B.EQ	45eaac

    (732) 0x45ea78 ADD	X6, X30, X5

    (732) 0x45ea7c ADD	X15, X30, X3

    (732) 0x45ea80 SUB	X14, X14, X30

    (732) 0x45ea84 ADD	X3, X19, X6,LSL #3

    (732) 0x45ea88 WHILELO	P3.D, XZR, X14

    (732) 0x45ea8c LD1D	{Z24.D}, P3/Z, [X28, X15,LSL #3]

    (732) 0x45ea90 ST1D	{Z24.D}, P3, [X3, MUL VL]

    (732) 0x45ea94 CNTD	X10, ALL

    (732) 0x45ea98 ADD	X7, X28, X15,LSL #3

    (732) 0x45ea9c WHILELO	P4.D, X10, X14

    (732) 0x45eaa0 B.EQ	45eaac

    (732) 0x45eaa4 LD1D	{Z25.D}, P4/Z, [X7, #1, MUL VL]

    (732) 0x45eaa8 ST1D	{Z25.D}, P4, [X3, #1, MUL VL]

    (732) 0x45eaac SUB	X12, X12, X13

    (732) 0x45eab0 ADD	X1, X1, #1

    (732) 0x45eab4 ADD	X5, X12, X5

    (732) 0x45eab8 CMP	X1, X8

    (732) 0x45eabc B.NE	45e63c

  (731) 0x45eac0 ORR	X24, XZR, X16

  (731) 0x45eac4 LDR	X8, [SP, #152]

  (731) 0x45eac8 ADD	X2, X2, #1

  (731) 0x45eacc CMP	X8, X2

  (731) 0x45ead0 B.NE	45e610

(730) 0x45ead4 ORR	X13, XZR, X17

(730) 0x45ead8 LDR	X16, [SP, #336]

(730) 0x45eadc LDR	X1, [SP, #368]

(730) 0x45eae0 LDR	X9, [SP, #152]

(730) 0x45eae4 LDR	X18, [SP, #176]

(730) 0x45eae8 STR	X13, [X1, #24]

(730) 0x45eaec LDR	X10, [X16, X23,LSL #3]

(730) 0x45eaf0 STR	X9, [X1, #8]

(730) 0x45eaf4 LDR	X4, [SP, #344]

(730) 0x45eaf8 STR	X18, [X1, #40]

(730) 0x45eafc LDR	X30, [SP, #160]

(730) 0x45eb00 LDR	X3, [X10, X4]

(730) 0x45eb04 STR	X10, [X1, #56]

(730) 0x45eb08 STR	X3, [SP, #208]

(730) 0x45eb0c CMP	X3, X30

(730) 0x45eb10 B.GT	45f3f0

(730) 0x45eb14 LDR	X3, [SP, #136]

(730) 0x45eb18 ORR	X2, XZR, X19

(730) 0x45eb1c MOVZ	X0, #1

(730) 0x45eb20 LDR	X1, [SP, #368]

(730) 0x45eb24 BL	4e0364

(730) 0x45eb28 BL	4e0b6c

(730) 0x45eb2c LDR	X11, [SP, #304]

(730) 0x45eb30 LDR	X0, [X11, X23,LSL #3]

(730) 0x45eb34 BL	524f40

(730) 0x45eb38 LDR	X14, [SP, #304]

(730) 0x45eb3c LDR	X15, [SP, #336]

(730) 0x45eb40 STR	XZR, [X14, X23,LSL #3]

(730) 0x45eb44 LDR	X0, [X15, X23,LSL #3]

(730) 0x45eb48 BL	524f40

(730) 0x45eb4c LDR	X12, [SP, #168]

(730) 0x45eb50 LDR	X7, [SP, #208]

(730) 0x45eb54 LDR	X6, [SP, #336]

(730) 0x45eb58 STR	X12, [SP, #208]

(730) 0x45eb5c STR	X7, [SP, #160]

(730) 0x45eb60 STR	XZR, [X6, X23,LSL #3]

(730) 0x45eb64 B	45e42c

    (732) 0x45eb68 SUB	X9, X24, X3,LSL #3

    (732) 0x45eb6c SUB	X24, X12, X0

    (732) 0x45eb70 ANDS	X18, X24, #0x7

    (732) 0x45eb74 ADD	X4, X19, X9

    (732) 0x45eb78 B.EQ	45ec5c

    (732) 0x45eb7c LDR	D0, [X28, X3,LSL #3]

    (732) 0x45eb80 STR	D0, [X4, X3,LSL #3]

    (732) 0x45eb84 ORR	X3, XZR, X0

    (732) 0x45eb88 ADD	X0, X0, #1

    (732) 0x45eb8c CMP	X18, #1

    (732) 0x45eb90 B.EQ	45ec5c

    (732) 0x45eb94 CMP	X18, #2

    (732) 0x45eb98 B.EQ	45ec0c

    (732) 0x45eb9c CMP	X18, #3

    (732) 0x45eba0 B.EQ	45ebfc

    (732) 0x45eba4 CMP	X18, #4

    (732) 0x45eba8 B.EQ	45ebec

    (732) 0x45ebac CMP	X18, #5

    (732) 0x45ebb0 B.EQ	45ebdc

    (732) 0x45ebb4 CMP	X18, #6

    (732) 0x45ebb8 B.EQ	45ebcc

    (732) 0x45ebbc LDR	D26, [X28, X3,LSL #3]

    (732) 0x45ebc0 STR	D26, [X4, X3,LSL #3]

    (732) 0x45ebc4 ORR	X3, XZR, X0

    (732) 0x45ebc8 ADD	X0, X0, #1

    (732) 0x45ebcc LDR	D27, [X28, X3,LSL #3]

    (732) 0x45ebd0 STR	D27, [X4, X3,LSL #3]

    (732) 0x45ebd4 ORR	X3, XZR, X0

    (732) 0x45ebd8 ADD	X0, X0, #1

    (732) 0x45ebdc LDR	D28, [X28, X3,LSL #3]

    (732) 0x45ebe0 STR	D28, [X4, X3,LSL #3]

    (732) 0x45ebe4 ORR	X3, XZR, X0

    (732) 0x45ebe8 ADD	X0, X0, #1

    (732) 0x45ebec LDR	D1, [X28, X3,LSL #3]

    (732) 0x45ebf0 STR	D1, [X4, X3,LSL #3]

    (732) 0x45ebf4 ORR	X3, XZR, X0

    (732) 0x45ebf8 ADD	X0, X0, #1

    (732) 0x45ebfc LDR	D31, [X28, X3,LSL #3]

    (732) 0x45ec00 STR	D31, [X4, X3,LSL #3]

    (732) 0x45ec04 ORR	X3, XZR, X0

    (732) 0x45ec08 ADD	X0, X0, #1

    (732) 0x45ec0c LDR	D30, [X28, X3,LSL #3]

    (732) 0x45ec10 STR	D30, [X4, X3,LSL #3]

    (732) 0x45ec14 ORR	X3, XZR, X0

    (732) 0x45ec18 ADD	X0, X0, #1

    (732) 0x45ec1c B	45ec5c

      (733) 0x45ec20 LDR	D3, [X28, X0,LSL #3]

      (733) 0x45ec24 STR	D3, [X4, X0,LSL #3]

      (733) 0x45ec28 ADD	X0, X0, #8

      (733) 0x45ec2c LDR	D29, [X28, X30,LSL #3]

      (733) 0x45ec30 STR	D29, [X4, X30,LSL #3]

      (733) 0x45ec34 LDR	D4, [X28, X11,LSL #3]

      (733) 0x45ec38 STR	D4, [X4, X11,LSL #3]

      (733) 0x45ec3c LDR	D5, [X28, X14,LSL #3]

      (733) 0x45ec40 STR	D5, [X4, X14,LSL #3]

      (733) 0x45ec44 LDR	D6, [X28, X15,LSL #3]

      (733) 0x45ec48 STR	D6, [X4, X15,LSL #3]

      (733) 0x45ec4c LDR	D7, [X28, X7,LSL #3]

      (733) 0x45ec50 STR	D7, [X4, X7,LSL #3]

      (733) 0x45ec54 LDR	D16, [X28, X6,LSL #3]

      (733) 0x45ec58 STR	D16, [X4, X6,LSL #3]

      (733) 0x45ec5c LDR	D2, [X28, X3,LSL #3]

      (733) 0x45ec60 ADD	X30, X0, #1

      (733) 0x45ec64 ADD	X11, X0, #2

      (733) 0x45ec68 ADD	X14, X0, #3

      (733) 0x45ec6c ADD	X15, X0, #4

      (733) 0x45ec70 ADD	X7, X0, #5

      (733) 0x45ec74 ADD	X6, X0, #6

      (733) 0x45ec78 STR	D2, [X4, X3,LSL #3]

      (733) 0x45ec7c ADD	X3, X0, #7

      (733) 0x45ec80 CMP	X12, X0

      (733) 0x45ec84 B.NE	45ec20

    (732) 0x45ec88 B	45eaac

    (732) 0x45ec8c SUB	X9, X18, X4,LSL #3

    (732) 0x45ec90 SUB	X24, X11, X3

    (732) 0x45ec94 ANDS	X18, X24, #0x7

    (732) 0x45ec98 ADD	X30, X19, X9

    (732) 0x45ec9c B.EQ	45ed80

    (732) 0x45eca0 LDR	D3, [X27, X4,LSL #3]

    (732) 0x45eca4 STR	D3, [X30, X4,LSL #3]

    (732) 0x45eca8 ORR	X4, XZR, X3

    (732) 0x45ecac ADD	X3, X3, #1

    (732) 0x45ecb0 CMP	X18, #1

    (732) 0x45ecb4 B.EQ	45ed80

    (732) 0x45ecb8 CMP	X18, #2

    (732) 0x45ecbc B.EQ	45ed30

    (732) 0x45ecc0 CMP	X18, #3

    (732) 0x45ecc4 B.EQ	45ed20

    (732) 0x45ecc8 CMP	X18, #4

    (732) 0x45eccc B.EQ	45ed10

    (732) 0x45ecd0 CMP	X18, #5

    (732) 0x45ecd4 B.EQ	45ed00

    (732) 0x45ecd8 CMP	X18, #6

    (732) 0x45ecdc B.EQ	45ecf0

    (732) 0x45ece0 LDR	D29, [X27, X4,LSL #3]

    (732) 0x45ece4 STR	D29, [X30, X4,LSL #3]

    (732) 0x45ece8 ORR	X4, XZR, X3

    (732) 0x45ecec ADD	X3, X3, #1

    (732) 0x45ecf0 LDR	D4, [X27, X4,LSL #3]

    (732) 0x45ecf4 STR	D4, [X30, X4,LSL #3]

    (732) 0x45ecf8 ORR	X4, XZR, X3

    (732) 0x45ecfc ADD	X3, X3, #1

    (732) 0x45ed00 LDR	D5, [X27, X4,LSL #3]

    (732) 0x45ed04 STR	D5, [X30, X4,LSL #3]

    (732) 0x45ed08 ORR	X4, XZR, X3

    (732) 0x45ed0c ADD	X3, X3, #1

    (732) 0x45ed10 LDR	D6, [X27, X4,LSL #3]

    (732) 0x45ed14 STR	D6, [X30, X4,LSL #3]

    (732) 0x45ed18 ORR	X4, XZR, X3

    (732) 0x45ed1c ADD	X3, X3, #1

    (732) 0x45ed20 LDR	D7, [X27, X4,LSL #3]

    (732) 0x45ed24 STR	D7, [X30, X4,LSL #3]

    (732) 0x45ed28 ORR	X4, XZR, X3

    (732) 0x45ed2c ADD	X3, X3, #1

    (732) 0x45ed30 LDR	D16, [X27, X4,LSL #3]

    (732) 0x45ed34 STR	D16, [X30, X4,LSL #3]

    (732) 0x45ed38 ORR	X4, XZR, X3

    (732) 0x45ed3c ADD	X3, X3, #1

    (732) 0x45ed40 B	45ed80

      (735) 0x45ed44 LDR	D17, [X27, X3,LSL #3]

      (735) 0x45ed48 STR	D17, [X30, X3,LSL #3]

      (735) 0x45ed4c ADD	X3, X3, #8

      (735) 0x45ed50 LDR	D18, [X27, X6,LSL #3]

      (735) 0x45ed54 STR	D18, [X30, X6,LSL #3]

      (735) 0x45ed58 LDR	D19, [X27, X13,LSL #3]

      (735) 0x45ed5c STR	D19, [X30, X13,LSL #3]

      (735) 0x45ed60 LDR	D20, [X27, X12,LSL #3]

      (735) 0x45ed64 STR	D20, [X30, X12,LSL #3]

      (735) 0x45ed68 LDR	D21, [X27, X10,LSL #3]

      (735) 0x45ed6c STR	D21, [X30, X10,LSL #3]

      (735) 0x45ed70 LDR	D22, [X27, X9,LSL #3]

      (735) 0x45ed74 STR	D22, [X30, X9,LSL #3]

      (735) 0x45ed78 LDR	D23, [X27, X7,LSL #3]

      (735) 0x45ed7c STR	D23, [X30, X7,LSL #3]

      (735) 0x45ed80 LDR	D17, [X27, X4,LSL #3]

      (735) 0x45ed84 ADD	X6, X3, #1

      (735) 0x45ed88 ADD	X13, X3, #2

      (735) 0x45ed8c ADD	X12, X3, #3

      (735) 0x45ed90 ADD	X10, X3, #4

      (735) 0x45ed94 ADD	X9, X3, #5

      (735) 0x45ed98 ADD	X7, X3, #6

      (735) 0x45ed9c STR	D17, [X30, X4,LSL #3]

      (735) 0x45eda0 ADD	X4, X3, #7

      (735) 0x45eda4 CMP	X11, X3

      (735) 0x45eda8 B.NE	45ed44

    (732) 0x45edac B	45e884

    (732) 0x45edb0 MOVZ	X13, #0

    (732) 0x45edb4 B	45e850

    (732) 0x45edb8 MOVZ	X30, #0

    (732) 0x45edbc B	45ea78

(730) 0x45edc0 ORR	X0, XZR, X19

(730) 0x45edc4 BL	524f40

(730) 0x45edc8 LDR	X0, [SP, #168]

(730) 0x45edcc MOVZ	X1, #8

(730) 0x45edd0 BL	524ea8

(730) 0x45edd4 LDR	X1, [SP, #304]

(730) 0x45edd8 ORR	X19, XZR, X0

(730) 0x45eddc LDR	X13, [X1, X23,LSL #3]

(730) 0x45ede0 B	45e5f8

(737) 0x45ede4 ORR	X0, XZR, X19

(737) 0x45ede8 BL	524f40

(737) 0x45edec LDR	X0, [SP, #168]

(737) 0x45edf0 MOVZ	X1, #8

(737) 0x45edf4 BL	524ea8

(737) 0x45edf8 LDR	X1, [SP, #304]

(737) 0x45edfc ORR	X19, XZR, X0

(737) 0x45ee00 LDR	X13, [X1, X23,LSL #3]

(737) 0x45ee04 B	45d11c

(737) 0x45ee08 LDR	X0, [SP, #136]

(737) 0x45ee0c BL	524f40

(737) 0x45ee10 LDR	X0, [SP, #208]

(737) 0x45ee14 MOVZ	X1, #8

(737) 0x45ee18 BL	524ea8

(737) 0x45ee1c STR	X0, [SP, #136]

(737) 0x45ee20 B	45d640

0x45ee24 LDR	X26, [SP, #216]

0x45ee28 LDR	X0, [SP, #352]

0x45ee2c BL	524f40

0x45ee30 LDR	X0, [SP, #304]

0x45ee34 BL	524f40

0x45ee38 LDR	X0, [SP, #336]

0x45ee3c BL	524f40

0x45ee40 LDR	X0, [SP, #424]

0x45ee44 BL	524f40

0x45ee48 ORR	X0, XZR, X19

0x45ee4c BL	524f40

0x45ee50 LDR	X0, [SP, #136]

0x45ee54 BL	524f40

0x45ee58 LDR	X0, [SP, #200]

0x45ee5c BL	524f40

0x45ee60 LDR	X0, [SP, #192]

0x45ee64 BL	524f40

0x45ee68 ORR	X0, XZR, X24

0x45ee6c BL	524f40

0x45ee70 LDR	X0, [SP, #408]

0x45ee74 BL	524f40

0x45ee78 LDR	X0, [SP, #416]

0x45ee7c BL	524f40

0x45ee80 LDR	X0, [SP, #456]

0x45ee84 BL	524f40

0x45ee88 LDR	X0, [SP, #464]

0x45ee8c BL	524f40

0x45ee90 LDR	X0, [SP, #232]

0x45ee94 BL	524f40

0x45ee98 ORR	X0, XZR, X22

0x45ee9c BL	524f40

0x45eea0 ORR	X0, XZR, X26

0x45eea4 BL	524f40

0x45eea8 LDR	X0, [SP, #256]

0x45eeac BL	524f40

0x45eeb0 LDR	X0, [SP, #272]

0x45eeb4 BL	524f40

0x45eeb8 LDR	X0, [SP, #520]

0x45eebc BL	524f40

0x45eec0 LDR	X0, [SP, #264]

0x45eec4 BL	524f40

0x45eec8 LDR	X22, [SP, #816]

0x45eecc CMP	X22, #1

0x45eed0 B.LE	45eedc

0x45eed4 LDR	X0, [SP, #368]

0x45eed8 BL	524f40

0x45eedc LDR	X19, [SP, #312]

0x45eee0 MOVZ	X5, #0

0x45eee4 LDP	X21, X25, [SP, #240]

0x45eee8 LDR	X30, [SP, #680]

0x45eeec UBFM	X24, X19, #61, #60

0x45eef0 ADD	X23, X25, X19,LSL #3

0x45eef4 LDR	X7, [X25, X24]

0x45eef8 LDR	X6, [X21, X24]

0x45eefc LDR	X1, [X30, #8]

0x45ef00 LDR	X3, [X30, #104]

0x45ef04 LDR	X0, [SP, #400]

0x45ef08 LDR	X4, [SP, #688]

0x45ef0c LDR	X2, [SP, #824]

0x45ef10 BL	4f29e0

0x45ef14 LDR	X7, [SP, #144]

0x45ef18 FCMP	D15, #0

0x45ef1c ORR	X19, XZR, X0

0x45ef20 LDP	X14, X22, [X0, #56]

0x45ef24 LDR	X15, [SP, #728]

0x45ef28 STP	X21, X7, [X14]

0x45ef2c STR	X27, [X14, #48]

0x45ef30 LDR	X27, [SP, #120]

0x45ef34 CCMP	X15, #0, #0, #0

0x45ef38 STR	X28, [X22, #48]

0x45ef3c STP	X25, X27, [X22]

0x45ef40 STR	XZR, [X0, #136]

0x45ef44 B.NE	45f3d4

0x45ef48 LDR	X24, [X23]

0x45ef4c CBZ	X24, 45f348

0x45ef50 LDR	X10, [SP, #184]

0x45ef54 LDR	X0, [SP, #472]

0x45ef58 CMP	X10, X0

0x45ef5c B.LT	45ef64

0x45ef60 ORR	X0, XZR, X10

0x45ef64 MOVZ	X1, #8

0x45ef68 BL	524ea8

0x45ef6c LDR	X13, [SP, #472]

0x45ef70 ORR	X27, XZR, X0

0x45ef74 ADRP	X8,

0x45ef78 MOVZ	W3, #0

0x45ef7c ADD	X0, X8, #2400

0x45ef80 LDR	X1, [SP, #296]

0x45ef84 MOVZ	W2, #0

0x45ef88 STR	X27, [SP, #832]

0x45ef8c STR	X13, [SP, #840]

0x45ef90 BL	4103b0

0x45ef94 CMP	X24, #0

0x45ef98 B.LE	45f74c

0x45ef9c LDR	X2, [SP, #120]

0x45efa0 UBFM	X17, X24, #61, #60

0x45efa4 MOVZ	X9, #1

0x45efa8 SUB	X18, X17, #8

0x45efac MOVZ	X26, #0

0x45efb0 UBFM	X1, X18, #3, #63

0x45efb4 ADD	X20, X1, X9

0x45efb8 ANDS	X4, X20, #0x7

0x45efbc ADD	X3, X2, X24,LSL #3

0x45efc0 ORR	X0, XZR, X2

0x45efc4 B.EQ	45f0c4

0x45efc8 CMP	X4, X9

0x45efcc B.EQ	45f0a0

0x45efd0 CMP	X4, #2

0x45efd4 B.EQ	45f084

0x45efd8 CMP	X4, #3

0x45efdc B.EQ	45f068

0x45efe0 CMP	X4, #4

0x45efe4 B.EQ	45f04c

0x45efe8 CMP	X4, #5

0x45efec B.EQ	45f030

0x45eff0 CMP	X4, #6

0x45eff4 B.EQ	45f014

0x45eff8 LDR	X0, [SP, #120]

0x45effc LDR	X21, [X0]

0x45f000 ADD	X30, X27, X21,LSL #3

0x45f004 LDR	X11, [X30]

0x45f008 CBZ	X11, 45fa74

0x45f00c LDR	X14, [SP, #120]

0x45f010 ADD	X0, X14, #8

0x45f014 LDR	X15, [X0]

0x45f018 ADD	X7, X27, X15,LSL #3

0x45f01c LDR	X6, [X7]

0x45f020 CBNZ	X6, 45f02c

0x45f024 ADD	X26, X26, #1

0x45f028 STR	X9, [X7]

0x45f02c ADD	X0, X0, #8

0x45f030 LDR	X12, [X0]

0x45f034 ADD	X23, X27, X12,LSL #3

0x45f038 LDR	X25, [X23]

0x45f03c CBNZ	X25, 45f048

0x45f040 ADD	X26, X26, #1

0x45f044 STR	X9, [X23]

0x45f048 ADD	X0, X0, #8

0x45f04c LDR	X5, [X0]

0x45f050 ADD	X28, X27, X5,LSL #3

0x45f054 LDR	X10, [X28]

0x45f058 CBNZ	X10, 45f064

0x45f05c ADD	X26, X26, #1

0x45f060 STR	X9, [X28]

0x45f064 ADD	X0, X0, #8

0x45f068 LDR	X8, [X0]

0x45f06c ADD	X13, X27, X8,LSL #3

0x45f070 LDR	X16, [X13]

0x45f074 CBNZ	X16, 45f080

0x45f078 ADD	X26, X26, #1

0x45f07c STR	X9, [X13]

0x45f080 ADD	X0, X0, #8

0x45f084 LDR	X17, [X0]

0x45f088 ADD	X18, X27, X17,LSL #3

0x45f08c LDR	X1, [X18]

0x45f090 CBNZ	X1, 45f09c

0x45f094 ADD	X26, X26, #1

0x45f098 STR	X9, [X18]

0x45f09c ADD	X0, X0, #8

0x45f0a0 LDR	X2, [X0]

0x45f0a4 ADD	X20, X27, X2,LSL #3

0x45f0a8 LDR	X4, [X20]

0x45f0ac CBNZ	X4, 45f0b8

0x45f0b0 ADD	X26, X26, #1

0x45f0b4 STR	X9, [X20]

0x45f0b8 ADD	X0, X0, #8

0x45f0bc CMP	X0, X3

0x45f0c0 B.EQ	45f194

(729) 0x45f0c4 LDR	X21, [X0]

(729) 0x45f0c8 UBFM	X30, X21, #61, #60

(729) 0x45f0cc LDR	X11, [X27, X30]

(729) 0x45f0d0 CBNZ	X11, 45f0dc

(729) 0x45f0d4 ADD	X26, X26, #1

(729) 0x45f0d8 STR	X9, [X27, X30]

(729) 0x45f0dc LDR	X14, [X0, #8]

(729) 0x45f0e0 ADD	X0, X0, #8

(729) 0x45f0e4 UBFM	X15, X14, #61, #60

(729) 0x45f0e8 LDR	X7, [X27, X15]

(729) 0x45f0ec CBNZ	X7, 45f0f8

(729) 0x45f0f0 ADD	X26, X26, #1

(729) 0x45f0f4 STR	X9, [X27, X15]

(729) 0x45f0f8 LDR	X6, [X0, #8]

(729) 0x45f0fc UBFM	X12, X6, #61, #60

(729) 0x45f100 LDR	X23, [X27, X12]

(729) 0x45f104 CBNZ	X23, 45f110

(729) 0x45f108 ADD	X26, X26, #1

(729) 0x45f10c STR	X9, [X27, X12]

(729) 0x45f110 LDR	X25, [X0, #16]

(729) 0x45f114 UBFM	X5, X25, #61, #60

(729) 0x45f118 LDR	X28, [X27, X5]

(729) 0x45f11c CBNZ	X28, 45f128

(729) 0x45f120 ADD	X26, X26, #1

(729) 0x45f124 STR	X9, [X27, X5]

(729) 0x45f128 LDR	X10, [X0, #24]

(729) 0x45f12c UBFM	X8, X10, #61, #60

(729) 0x45f130 LDR	X13, [X27, X8]

(729) 0x45f134 CBNZ	X13, 45f140

(729) 0x45f138 ADD	X26, X26, #1

(729) 0x45f13c STR	X9, [X27, X8]

(729) 0x45f140 LDR	X16, [X0, #32]

(729) 0x45f144 UBFM	X17, X16, #61, #60

(729) 0x45f148 LDR	X18, [X27, X17]

(729) 0x45f14c CBNZ	X18, 45f158

(729) 0x45f150 ADD	X26, X26, #1

(729) 0x45f154 STR	X9, [X27, X17]

(729) 0x45f158 LDR	X1, [X0, #40]

(729) 0x45f15c UBFM	X2, X1, #61, #60

(729) 0x45f160 LDR	X20, [X27, X2]

(729) 0x45f164 CBNZ	X20, 45f170

(729) 0x45f168 ADD	X26, X26, #1

(729) 0x45f16c STR	X9, [X27, X2]

(729) 0x45f170 LDR	X4, [X0, #48]

(729) 0x45f174 UBFM	X21, X4, #61, #60

(729) 0x45f178 LDR	X30, [X27, X21]

(729) 0x45f17c CBNZ	X30, 45f188

(729) 0x45f180 ADD	X26, X26, #1

(729) 0x45f184 STR	X9, [X27, X21]

(729) 0x45f188 ADD	X0, X0, #56

(729) 0x45f18c CMP	X0, X3

(729) 0x45f190 B.NE	45f0c4

0x45f194 ORR	X0, XZR, X26

0x45f198 SUB	X16, X26, #1

0x45f19c MOVZ	X1, #8

0x45f1a0 STR	X16, [SP, #128]

0x45f1a4 BL	524ea8

0x45f1a8 LDR	X20, [SP, #512]

0x45f1ac MOVZ	X1, #8

0x45f1b0 ORR	X25, XZR, X0

0x45f1b4 LDR	X3, [SP, #632]

0x45f1b8 ADD	X9, X20, X3

0x45f1bc LDUR	X0, [X9, #504]

0x45f1c0 BL	524ea8

0x45f1c4 LDR	X14, [SP, #328]

0x45f1c8 ADRP	X11,

0x45f1cc ORR	X23, XZR, X0

0x45f1d0 MOVZ	W3, #0

0x45f1d4 ADD	X0, X11, #2252

0x45f1d8 STR	X20, [SP, #832]

0x45f1dc LDR	X1, [SP, #296]

0x45f1e0 MOVZ	W2, #0

0x45f1e4 STR	X23, [SP, #840]

0x45f1e8 SUB	X28, X14, #1

0x45f1ec STR	X14, [SP, #848]

0x45f1f0 BL	4103b0

0x45f1f4 LDR	X7, [SP, #128]

0x45f1f8 MOVZ	X1, #0

0x45f1fc MOVZ	X18, #0

0x45f200 ADD	X15, X20, #8

0x45f204 LDR	X6, [SP, #504]

(727) 0x45f208 LDR	X5, [X20, X1,LSL #3]

(727) 0x45f20c LDR	X17, [X15, X1,LSL #3]

(727) 0x45f210 CMP	X5, X17

(727) 0x45f214 B.GE	45f24c

  (728) 0x45f218 LDR	X12, [X27, X5,LSL #3]

  (728) 0x45f21c CBZ	X12, 45f3b8

  (728) 0x45f220 LDR	X10, [X20, X1,LSL #3]

  (728) 0x45f224 LDR	X8, [X6, X1,LSL #3]

  (728) 0x45f228 SUB	X13, X5, X10

  (728) 0x45f22c LDR	X16, [X8, X13,LSL #3]

  (728) 0x45f230 STR	X16, [X25, X18,LSL #3]

  (728) 0x45f234 ADD	X18, X18, #1

  (728) 0x45f238 STR	X16, [X23, X5,LSL #3]

  (728) 0x45f23c ADD	X5, X5, #1

  (728) 0x45f240 LDR	X17, [X15, X1,LSL #3]

  (728) 0x45f244 CMP	X5, X17

  (728) 0x45f248 B.LT	45f218

(727) 0x45f24c ADD	X1, X1, #1

(727) 0x45f250 CMP	X1, X28

(727) 0x45f254 B.NE	45f208

0x45f258 ORR	X2, XZR, X7

0x45f25c MOVZ	X1, #0

0x45f260 ORR	X0, XZR, X25

0x45f264 BL	525608

0x45f268 LDR	X21, [SP, #296]

0x45f26c ADD	X11, SP, #832

0x45f270 ADRP	X2,

0x45f274 ADD	X0, X2, #1064

0x45f278 MOVZ	W3, #0

0x45f27c LDR	X4, [SP, #328]

0x45f280 MOVZ	W2, #0

0x45f284 LDR	X9, [SP, #512]

0x45f288 ORR	X1, XZR, X21

0x45f28c STP	X23, X4, [X11, #16]

0x45f290 STP	X9, X25, [X11]

0x45f294 STR	X26, [SP, #864]

0x45f298 BL	4103b0

0x45f29c LDR	X14, [SP, #120]

0x45f2a0 ADRP	X0,

0x45f2a4 ORR	X1, XZR, X21

0x45f2a8 ADD	X0, X0, #1872

0x45f2ac MOVZ	W3, #0

0x45f2b0 STR	X23, [SP, #840]

0x45f2b4 MOVZ	W2, #0

0x45f2b8 STR	X24, [SP, #848]

0x45f2bc STR	X14, [SP, #832]

0x45f2c0 BL	4103b0

0x45f2c4 ORR	X0, XZR, X27

0x45f2c8 BL	524f40

0x45f2cc LDR	X24, [SP, #816]

0x45f2d0 CMP	X24, #1

0x45f2d4 B.GT	45f368

0x45f2d8 ORR	X0, XZR, X23

0x45f2dc BL	524f40

0x45f2e0 LDR	X0, [SP, #504]

0x45f2e4 BL	524f40

0x45f2e8 LDR	X0, [SP, #512]

0x45f2ec BL	524f40

0x45f2f0 CBZ	X26, 45f2fc

0x45f2f4 STR	X25, [X19, #88]

0x45f2f8 STR	X26, [X22, #24]

0x45f2fc LDR	X22, [SP, #720]

0x45f300 CBNZ	X22, 45f38c

0x45f304 LDR	X26, [SP, #816]

0x45f308 CMP	X26, #1

0x45f30c B.LE	45f318

0x45f310 ORR	X0, XZR, X19

0x45f314 BL	4e1f80

0x45f318 LDR	X3, [SP, #1184]

0x45f31c MOVZ	X0, #0

0x45f320 LDR	D15, [SP, #96]

0x45f324 STR	X19, [X3]

0x45f328 LDP	X29, X30, [SP]

0x45f32c LDP	X19, X20, [SP, #16]

0x45f330 LDP	X21, X22, [SP, #32]

0x45f334 LDP	X23, X24, [SP, #48]

0x45f338 LDP	X25, X26, [SP, #64]

0x45f33c LDP	X27, X28, [SP, #80]

0x45f340 ADD	SP, SP, #1168

0x45f344 RET

0x45f348 LDR	X12, [SP, #816]

0x45f34c CMP	X12, #1

0x45f350 B.LE	45f558

0x45f354 LDR	X5, [SP, #328]

0x45f358 MOVZ	X26, #0

0x45f35c MOVZ	X23, #0

0x45f360 MOVZ	X25, #0

0x45f364 SUB	X28, X5, #1

0x45f368 LDR	X27, [SP, #504]

0x45f36c ADD	X28, X27, W28,UXTW #3

0x45f370 ORR	X20, XZR, X27

(726) 0x45f374 LDR	X0, [X20]

(726) 0x45f378 BL	524f40

(726) 0x45f37c STR	XZR, [X20], #8

(726) 0x45f380 CMP	X20, X28

(726) 0x45f384 B.NE	45f374

0x45f388 B	45f2d8

0x45f38c LDR	X30, [SP, #312]

0x45f390 ADRP	X23,

0x45f394 MOVZ	W3, #0

0x45f398 ADD	X0, X23, #2532

0x45f39c MOVZ	W2, #0

0x45f3a0 LDR	X25, [SP, #320]

0x45f3a4 LDR	X1, [SP, #296]

0x45f3a8 STR	X30, [SP, #840]

0x45f3ac STR	X25, [SP, #832]

0x45f3b0 BL	4103b0

0x45f3b4 B	45f304

  (728) 0x45f3b8 ADD	X5, X5, #1

  (728) 0x45f3bc CMP	X5, X17

  (728) 0x45f3c0 B.LT	45f218

(727) 0x45f3c4 ADD	X1, X1, #1

(727) 0x45f3c8 CMP	X1, X28

(727) 0x45f3cc B.NE	45f208

0x45f3d0 B	45f258

0x45f3d4 LDR	X1, [SP, #728]

0x45f3d8 FMOV	D0, D15

0x45f3dc BL	44c660

0x45f3e0 LDP	X28, X6, [X22]

0x45f3e4 ADD	X23, X28, X24

0x45f3e8 STR	X6, [SP, #120]

0x45f3ec B	45ef48

(730) 0x45f3f0 LDR	X0, [SP, #136]

(730) 0x45f3f4 BL	524f40

(730) 0x45f3f8 LDR	X0, [SP, #208]

(730) 0x45f3fc MOVZ	X1, #8

(730) 0x45f400 BL	524ea8

(730) 0x45f404 STR	X0, [SP, #136]

(730) 0x45f408 B	45eb14

(777) 0x45f40c STR	X11, [X30, X3,LSL #3]

(777) 0x45f410 SUB	X3, X3, #1

(777) 0x45f414 STR	XZR, [X2, X11,LSL #3]

(777) 0x45f418 STR	XZR, [X4, X11,LSL #3]

(777) 0x45f41c STR	X12, [X22, X11,LSL #3]

(777) 0x45f420 STR	X12, [X15, X11,LSL #3]

(777) 0x45f424 B	45b400

(777) 0x45f428 STR	X7, [X30, X3,LSL #3]

(777) 0x45f42c SUB	X3, X3, #1

(777) 0x45f430 STR	XZR, [X2, X7,LSL #3]

(777) 0x45f434 STR	XZR, [X4, X7,LSL #3]

(777) 0x45f438 STR	X10, [X22, X7,LSL #3]

(777) 0x45f43c STR	X10, [X15, X7,LSL #3]

(777) 0x45f440 B	45b3d8

(777) 0x45f444 STR	X0, [X30, X3,LSL #3]

(777) 0x45f448 SUB	X3, X3, #1

(777) 0x45f44c STR	XZR, [X2, X0,LSL #3]

(777) 0x45f450 STR	XZR, [X4, X0,LSL #3]

(777) 0x45f454 STR	X8, [X22, X0,LSL #3]

(777) 0x45f458 STR	X8, [X15, X0,LSL #3]

(777) 0x45f45c B	45b3b0

(777) 0x45f460 STR	X0, [X30, X3,LSL #3]

(777) 0x45f464 SUB	X3, X3, #1

(777) 0x45f468 STR	XZR, [X2, X0,LSL #3]

(777) 0x45f46c STR	XZR, [X4, X0,LSL #3]

(777) 0x45f470 STR	X9, [X22, X0,LSL #3]

(777) 0x45f474 STR	X9, [X15, X0,LSL #3]

(777) 0x45f478 B	45b388

0x45f47c MOVZ	X1, #8

0x45f480 STR	X6, [SP, #136]

0x45f484 BL	524ea8

0x45f488 LDR	X26, [SP, #432]

0x45f48c STR	X0, [SP, #352]

0x45f490 LDR	X6, [SP, #136]

0x45f494 CMP	X26, #1

0x45f498 B.GT	45f6b0

0x45f49c LDR	X17, [SP, #816]

0x45f4a0 STR	XZR, [SP, #424]

0x45f4a4 CMP	X17, #1

0x45f4a8 B.GT	45b06c

0x45f4ac MOVZ	X8, #1

0x45f4b0 MOVZ	X20, #0

0x45f4b4 STR	XZR, [SP, #152]

0x45f4b8 STR	XZR, [SP, #176]

0x45f4bc STR	X8, [SP, #552]

0x45f4c0 B	45b20c

0x45f4c4 MOVZ	X1, #8

0x45f4c8 BL	524ea8

0x45f4cc LDR	X6, [SP, #136]

0x45f4d0 STR	X0, [SP, #360]

0x45f4d4 B	45b050

0x45f4d8 LDR	X5, [SP, #232]

0x45f4dc LDR	X28, [SP, #360]

0x45f4e0 STR	X1, [X5, X0,LSL #3]

0x45f4e4 STR	X0, [X28, X1,LSL #3]

0x45f4e8 ADD	X1, X1, #1

0x45f4ec STR	XZR, [X22, X0,LSL #3]

0x45f4f0 STR	X10, [X2, X0,LSL #3]

0x45f4f4 STR	XZR, [X4, X0,LSL #3]

0x45f4f8 B	45b34c

0x45f4fc MOVZ	X1, #8

0x45f500 STR	X9, [SP, #136]

0x45f504 MOVZ	X22, #0

0x45f508 BL	524ea8

0x45f50c ORR	X4, XZR, X0

0x45f510 MOVZ	X1, #8

0x45f514 MOVZ	X0, #11

0x45f518 STR	X4, [SP, #272]

0x45f51c BL	524ea8

0x45f520 LDR	X5, [SP, #136]

0x45f524 STR	XZR, [SP, #232]

0x45f528 STR	X0, [SP, #256]

0x45f52c B	45b010

0x45f530 STP	XZR, XZR, [SP, #440]

0x45f534 B	45af78

0x45f538 LDR	X16, [X24, #8]

0x45f53c ORR	X19, XZR, X21

0x45f540 STR	X23, [SP, #184]

0x45f544 LDR	X0, [X24, #48]

0x45f548 STR	XZR, [SP, #1176]

0x45f54c STR	X16, [SP, #448]

0x45f550 STR	X0, [SP, #440]

0x45f554 B	45af84

0x45f558 MOVZ	X0, #0

0x45f55c BL	524f40

0x45f560 LDR	X0, [SP, #504]

0x45f564 BL	524f40

0x45f568 LDR	X0, [SP, #512]

0x45f56c BL	524f40

0x45f570 B	45f2fc

0x45f574 LDR	X0, [SP, #432]

0x45f578 CMP	X0, #1

0x45f57c B.GT	45f4ac

0x45f580 MOVZ	X1, #1

0x45f584 MOVZ	X20, #0

0x45f588 STR	XZR, [SP, #152]

0x45f58c STR	XZR, [SP, #176]

0x45f590 STR	X1, [SP, #552]

0x45f594 B	45b20c

0x45f598 LDP	X1, X4, [SP, #240]

0x45f59c B	45cc90

(725) 0x45f5a0 LDR	X0, [SP, #208]

(725) 0x45f5a4 BL	524f40

(725) 0x45f5a8 MOVZ	X1, #8

(725) 0x45f5ac ORR	X0, XZR, X22

(725) 0x45f5b0 BL	524ea8

(725) 0x45f5b4 STR	X0, [SP, #208]

(725) 0x45f5b8 STR	X22, [SP, #544]

(725) 0x45f5bc B	45c83c

0x45f5c0 ORR	X21, XZR, X20

0x45f5c4 ORR	X20, XZR, X24

0x45f5c8 LDR	X28, [SP, #168]

0x45f5cc MOVZ	X24, #16

0x45f5d0 ADD	X11, X24, W19,UXTW #3

0x45f5d4 STR	X11, [SP, #632]

0x45f5d8 LDR	X24, [SP, #280]

0x45f5dc B	45c124

(725) 0x45f5e0 LDR	X5, [SP, #304]

(725) 0x45f5e4 LDR	X24, [SP, #368]

(725) 0x45f5e8 LDR	X15, [SP, #704]

(725) 0x45f5ec LDR	X10, [SP, #336]

(725) 0x45f5f0 LDR	X9, [SP, #712]

(725) 0x45f5f4 STR	X15, [X24, #16]

(725) 0x45f5f8 LDR	X0, [X5, X23,LSL #3]

(725) 0x45f5fc LDR	X7, [SP, #152]

(725) 0x45f600 STR	X9, [X24, #48]

(725) 0x45f604 LDR	X28, [SP, #176]

(725) 0x45f608 STR	X0, [X24, #24]

(725) 0x45f60c LDR	X11, [X10, X23,LSL #3]

(725) 0x45f610 STR	X7, [X24, #8]

(725) 0x45f614 LDR	X8, [SP, #400]

(725) 0x45f618 STR	X28, [X24, #40]

(725) 0x45f61c STR	X11, [X24, #56]

(725) 0x45f620 STR	X8, [X24]

(725) 0x45f624 B	45da50

0x45f628 MOVZ	X1, #8

0x45f62c STR	X6, [SP, #136]

0x45f630 BL	524ea8

0x45f634 LDR	X18, [SP, #176]

0x45f638 ORR	X20, XZR, X0

0x45f63c LDR	X15, [SP, #152]

0x45f640 LDR	X6, [SP, #136]

0x45f644 ADD	X28, X18, #1

0x45f648 CMP	X15, #0

0x45f64c STR	X28, [SP, #552]

0x45f650 B.GT	45b0c0

0x45f654 LDR	X30, [SP, #816]

0x45f658 CMP	X30, #1

0x45f65c B.LE	45b20c

0x45f660 B	45b144

0x45f664 LDR	X27, [SP, #680]

0x45f668 ORR	X0, XZR, X27

0x45f66c BL	4e1f80

0x45f670 LDR	X1, [X27, #112]

0x45f674 LDR	X18, [SP, #120]

0x45f678 STR	X1, [SP, #344]

0x45f67c CBZ	X23, 45b8c0

0x45f680 B	45f538

0x45f684 MOVZ	X1, #8

0x45f688 STR	X2, [SP, #136]

0x45f68c BL	524ea8

0x45f690 ORR	X15, XZR, X0

0x45f694 MOVZ	X1, #8

0x45f698 MOVZ	X0, #11

0x45f69c STR	X15, [SP, #272]

0x45f6a0 BL	524ea8

0x45f6a4 LDR	X18, [SP, #136]

0x45f6a8 STR	X0, [SP, #256]

0x45f6ac B	45b960

0x45f6b0 LDR	X0, [SP, #184]

0x45f6b4 MOVZ	X1, #8

0x45f6b8 STR	X6, [SP, #136]

0x45f6bc BL	524ea8

0x45f6c0 LDR	X9, [SP, #816]

0x45f6c4 STR	X0, [SP, #424]

0x45f6c8 LDR	X6, [SP, #136]

0x45f6cc CMP	X9, #1

0x45f6d0 B.GT	45b06c

0x45f6d4 B	45f4ac

0x45f6d8 LDR	X12, [SP, #272]

0x45f6dc LDR	X14, [SP, #232]

0x45f6e0 STR	X0, [X12, X3,LSL #3]

0x45f6e4 SUB	X3, X3, #1

0x45f6e8 STR	XZR, [X2, X0,LSL #3]

0x45f6ec STR	XZR, [X4, X0,LSL #3]

0x45f6f0 STR	X10, [X22, X0,LSL #3]

0x45f6f4 STR	X10, [X14, X0,LSL #3]

0x45f6f8 B	45b34c

0x45f6fc LDR	X30, [SP, #272]

0x45f700 LDR	X16, [SP, #232]

0x45f704 STR	X0, [X30, X3,LSL #3]

0x45f708 SUB	X3, X3, #1

0x45f70c STR	XZR, [X2, X0,LSL #3]

0x45f710 STR	XZR, [X4, X0,LSL #3]

0x45f714 STR	X15, [X22, X0,LSL #3]

0x45f718 STR	X15, [X16, X0,LSL #3]

0x45f71c ADD	X0, X0, #1

0x45f720 B	45b320

0x45f724 LDR	X17, [SP, #232]

0x45f728 LDR	X8, [SP, #360]

0x45f72c STR	X1, [X17, X0,LSL #3]

0x45f730 STR	X0, [X8, X1,LSL #3]

0x45f734 ADD	X1, X1, #1

0x45f738 STR	XZR, [X22, X0,LSL #3]

0x45f73c STR	X15, [X2, X0,LSL #3]

0x45f740 STR	XZR, [X4, X0,LSL #3]

0x45f744 ADD	X0, X0, #1

0x45f748 B	45b320

0x45f74c MOVZ	X0, #0

0x45f750 MOVZ	X26, #0

0x45f754 MOVN	X16, #0

0x45f758 B	45f19c

0x45f75c LDR	X0, [SP, #360]

0x45f760 BL	524f40

0x45f764 LDR	X2, [SP, #136]

0x45f768 B	45e37c

0x45f76c ORR	X0, XZR, X28

0x45f770 MOVZ	X1, #8

0x45f774 BL	524ea8

0x45f778 LDR	X8, [SP, #120]

0x45f77c ORR	X18, XZR, X0

0x45f780 B	45e130

0x45f784 MOVZ	X1, #8

0x45f788 STR	X12, [SP, #120]

0x45f78c STR	X4, [SP, #136]

0x45f790 BL	524ea8

0x45f794 LDR	X12, [SP, #120]

0x45f798 STR	X0, [SP, #376]

0x45f79c LDR	X4, [SP, #136]

0x45f7a0 B	45e090

0x45f7a4 LDR	X0, [SP, #184]

0x45f7a8 MOVZ	X1, #8

0x45f7ac BL	524ea8

0x45f7b0 LDR	X12, [SP, #120]

0x45f7b4 STR	X0, [SP, #456]

0x45f7b8 LDR	X4, [SP, #136]

0x45f7bc B	45e07c

0x45f7c0 MOVZ	X19, #0

0x45f7c4 STR	XZR, [SP, #136]

0x45f7c8 B	45ee28

0x45f7cc LDR	X0, [SP, #360]

0x45f7d0 BL	524f40

0x45f7d4 LDR	X1, [SP, #136]

0x45f7d8 B	45cea0

(725) 0x45f7dc LDR	X1, [SP, #344]

(725) 0x45f7e0 ORR	X3, XZR, X27

(725) 0x45f7e4 MOVZ	X0, #11

(725) 0x45f7e8 LDR	X2, [SP, #376]

(725) 0x45f7ec BL	4e0364

(725) 0x45f7f0 BL	4e0b6c

(725) 0x45f7f4 LDR	X12, [SP, #528]

(725) 0x45f7f8 TBNZ	X12, #63, 45f804

(725) 0x45f7fc STR	XZR, [SP, #528]

(725) 0x45f800 B	45c824

(725) 0x45f804 LDR	X0, [SP, #384]

(725) 0x45f808 BL	524f40

(725) 0x45f80c MOVZ	X1, #8

(725) 0x45f810 MOVZ	X0, #0

(725) 0x45f814 BL	524ea8

(725) 0x45f818 STR	X0, [SP, #384]

(725) 0x45f81c STR	XZR, [SP, #528]

(725) 0x45f820 B	45c824

0x45f824 MOVZ	X24, #2

0x45f828 MOVZ	X27, #16

0x45f82c STR	X24, [SP, #328]

0x45f830 STR	X27, [SP, #632]

0x45f834 B	45c124

0x45f838 LDR	X11, [X21, X1,LSL #3]

0x45f83c MOVN	X7, #0

0x45f840 LDR	X14, [X19, X0,LSL #3]

0x45f844 CMP	X11, X14

0x45f848 B.EQ	45fa48

0x45f84c LDR	X3, [SP, #264]

0x45f850 STR	X7, [X3, X1,LSL #3]

0x45f854 ADD	X1, X1, #1

0x45f858 LDR	X13, [SP, #184]

0x45f85c CMP	X13, X0

0x45f860 B.LE	45b7a0

0x45f864 LDR	X5, [X21, X1,LSL #3]

0x45f868 MOVN	X2, #0

0x45f86c LDR	X24, [X19, X0,LSL #3]

0x45f870 CMP	X5, X24

0x45f874 B.NE	45f880

0x45f878 ORR	X2, XZR, X0

0x45f87c ADD	X0, X0, #1

0x45f880 LDR	X28, [SP, #264]

0x45f884 STR	X2, [X28, X1,LSL #3]

0x45f888 ADD	X1, X1, #1

0x45f88c CMP	X23, X1

0x45f890 B.EQ	45b7dc

0x45f894 LDR	X15, [SP, #184]

0x45f898 ORR	X18, XZR, X28

0x45f89c B	45f8a8

0x45f8a0 LDR	X15, [SP, #184]

0x45f8a4 LDR	X18, [SP, #264]

(772) 0x45f8a8 CMP	X15, X0

(772) 0x45f8ac B.LE	45b7a0

(772) 0x45f8b0 LDR	X30, [X21, X1,LSL #3]

(772) 0x45f8b4 MOVN	X17, #0

(772) 0x45f8b8 LDR	X16, [X19, X0,LSL #3]

(772) 0x45f8bc CMP	X30, X16

(772) 0x45f8c0 B.NE	45f8cc

(772) 0x45f8c4 ORR	X17, XZR, X0

(772) 0x45f8c8 ADD	X0, X0, #1

(772) 0x45f8cc STR	X17, [X18, X1,LSL #3]

(772) 0x45f8d0 ADD	X1, X1, #1

(772) 0x45f8d4 ORR	X9, XZR, X1

(772) 0x45f8d8 CMP	X15, X0

(772) 0x45f8dc B.LE	45b7a0

(772) 0x45f8e0 LDR	X12, [X21, X1,LSL #3]

(772) 0x45f8e4 MOVN	X1, #0

(772) 0x45f8e8 LDR	X10, [X19, X0,LSL #3]

(772) 0x45f8ec CMP	X12, X10

(772) 0x45f8f0 B.NE	45f8fc

(772) 0x45f8f4 ORR	X1, XZR, X0

(772) 0x45f8f8 ADD	X0, X0, #1

(772) 0x45f8fc STR	X1, [X18, X9,LSL #3]

(772) 0x45f900 ADD	X1, X9, #1

(772) 0x45f904 CMP	X15, X0

(772) 0x45f908 B.LE	45b7a0

(772) 0x45f90c LDR	X8, [X21, X1,LSL #3]

(772) 0x45f910 MOVN	X11, #0

(772) 0x45f914 LDR	X4, [X19, X0,LSL #3]

(772) 0x45f918 CMP	X8, X4

(772) 0x45f91c B.NE	45f928

(772) 0x45f920 ORR	X11, XZR, X0

(772) 0x45f924 ADD	X0, X0, #1

(772) 0x45f928 STR	X11, [X18, X1,LSL #3]

(772) 0x45f92c ADD	X1, X9, #2

(772) 0x45f930 CMP	X15, X0

(772) 0x45f934 B.LE	45b7a0

(772) 0x45f938 LDR	X14, [X21, X1,LSL #3]

(772) 0x45f93c MOVN	X3, #0

(772) 0x45f940 LDR	X7, [X19, X0,LSL #3]

(772) 0x45f944 CMP	X14, X7

(772) 0x45f948 B.NE	45f954

(772) 0x45f94c ORR	X3, XZR, X0

(772) 0x45f950 ADD	X0, X0, #1

(772) 0x45f954 STR	X3, [X18, X1,LSL #3]

(772) 0x45f958 ADD	X1, X9, #3

(772) 0x45f95c CMP	X15, X0

(772) 0x45f960 B.LE	45b7a0

(772) 0x45f964 LDR	X13, [X21, X1,LSL #3]

(772) 0x45f968 MOVN	X5, #0

(772) 0x45f96c LDR	X24, [X19, X0,LSL #3]

(772) 0x45f970 CMP	X13, X24

(772) 0x45f974 B.NE	45f980

(772) 0x45f978 ORR	X5, XZR, X0

(772) 0x45f97c ADD	X0, X0, #1

(772) 0x45f980 STR	X5, [X18, X1,LSL #3]

(772) 0x45f984 ADD	X1, X9, #4

(772) 0x45f988 CMP	X15, X0

(772) 0x45f98c B.LE	45b7a0

(772) 0x45f990 LDR	X2, [X21, X1,LSL #3]

(772) 0x45f994 MOVN	X30, #0

(772) 0x45f998 LDR	X28, [X19, X0,LSL #3]

(772) 0x45f99c CMP	X2, X28

(772) 0x45f9a0 B.NE	45f9ac

(772) 0x45f9a4 ORR	X30, XZR, X0

(772) 0x45f9a8 ADD	X0, X0, #1

(772) 0x45f9ac STR	X30, [X18, X1,LSL #3]

(772) 0x45f9b0 ADD	X1, X9, #5

(772) 0x45f9b4 CMP	X15, X0

(772) 0x45f9b8 B.LE	45b7a0

(772) 0x45f9bc LDR	X16, [X21, X1,LSL #3]

(772) 0x45f9c0 MOVN	X12, #0

(772) 0x45f9c4 LDR	X17, [X19, X0,LSL #3]

(772) 0x45f9c8 CMP	X16, X17

(772) 0x45f9cc B.NE	45f9d8

(772) 0x45f9d0 ORR	X12, XZR, X0

(772) 0x45f9d4 ADD	X0, X0, #1

(772) 0x45f9d8 STR	X12, [X18, X1,LSL #3]

(772) 0x45f9dc ADD	X1, X9, #6

(772) 0x45f9e0 CMP	X15, X0

(772) 0x45f9e4 B.LE	45b7a0

(772) 0x45f9e8 LDR	X10, [X21, X1,LSL #3]

(772) 0x45f9ec MOVN	X4, #0

(772) 0x45f9f0 LDR	X8, [X19, X0,LSL #3]

(772) 0x45f9f4 CMP	X10, X8

(772) 0x45f9f8 B.EQ	45fa54

(772) 0x45f9fc STR	X4, [X18, X1,LSL #3]

(772) 0x45fa00 ADD	X1, X9, #7

(772) 0x45fa04 CMP	X23, X1

(772) 0x45fa08 B.NE	45f8a8

0x45fa0c B	45b7dc

0x45fa10 LDR	X1, [SP, #232]

0x45fa14 LDR	X28, [SP, #360]

0x45fa18 STR	XZR, [X1]

0x45fa1c ORR	X1, XZR, X0

0x45fa20 STR	XZR, [X28]

0x45fa24 STR	XZR, [X22]

0x45fa28 STR	X0, [X2]

0x45fa2c MOVZ	X0, #1

0x45fa30 STR	XZR, [X4]

0x45fa34 B	45b2f0

0x45fa38 LDR	X18, [SP, #432]

0x45fa3c CMP	X18, #1

0x45fa40 B.GT	45b180

0x45fa44 B	45b20c

0x45fa48 ORR	X7, XZR, X0

0x45fa4c ADD	X0, X0, #1

0x45fa50 B	45f84c

(772) 0x45fa54 ORR	X4, XZR, X0

(772) 0x45fa58 ADD	X0, X0, #1

(772) 0x45fa5c B	45f9fc

0x45fa60 UBFM	X27, X19, #61, #31

0x45fa64 ORR	X21, XZR, X23

0x45fa68 STR	X19, [SP, #328]

0x45fa6c STR	X27, [SP, #632]

0x45fa70 B	45c124

0x45fa74 ORR	X26, XZR, X9

0x45fa78 STR	X9, [X30]

0x45fa7c B	45f00c

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_multi_interp.c:41-2061
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:41-71,83-108,114-131,146-150,185-186,194,202-208,216-223,229-241,252-261,267-272,278-333,340,346-351,381-469,479-518,525-536,544-557,568-576,583-636,643-685,691-706,717-759,768-891,1140-1161,1167,1177-1184,1304-1369,1562-1566,1575,1669-1705,1711-1737,1884-1915,1921-1938,1944-1997,2007-2032,2038-2043,2061.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 298.17 to 24.13 cycles (12.36x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 26% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 298.17 to 76.71 cycles (3.89x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_BoomerAMGInterpTruncation: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1938
hypre_CAlloc: 46 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:194
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:203
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:204
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:280
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:282
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:283
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:433
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:465
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:267
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:280
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:281
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:608
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:611
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:613
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:617
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1148
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1149
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:348
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:349
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:350
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:351
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:436
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:671
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:672
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:673
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:674
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:675
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:621
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:628
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:630
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1154
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1155
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1954
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1972
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1973
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:288
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:284
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:279
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:280
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:302
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:279
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:280
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:289
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:624
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:678
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:676
hypre_Free: 45 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:461
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:604
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1140
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1141
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1142
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1143
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1144
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1145
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1146
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1305
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1306
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1307
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1670
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1671
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1672
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1893
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1894
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1895
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1896
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1897
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1898
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1899
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1900
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1901
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1902
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1903
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1904
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1905
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1906
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1907
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1908
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1909
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1910
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1911
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1912
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1913
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:2012
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:2019
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:2020
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:2021
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:2019
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:2020
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:2021
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1669
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1304
hypre_MPI_Allreduce: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:546
hypre_MPI_Bcast: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:223
hypre_MPI_Comm_rank: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:217
hypre_MPI_Comm_size: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:216
hypre_MatvecCommPkgCreate: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:2040
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:234
hypre_NumThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:202
hypre_ParCSRCommHandleCreate: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:315
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:331
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:428
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:534
hypre_ParCSRCommHandleDestroy: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:317
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:333
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:430
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:536
hypre_ParCSRMatrixCreate: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1915
hypre_qsort0: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1994
unknown: 14 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:272
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:340
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:469
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:272
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1167
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1184
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:680
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:685
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1575
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1956
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1976
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1997
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:2007
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:2032

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	1722
nb uops	1722
loop length	6888
used w registers	5
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	713

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	215.25 cycles
front end	215.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	147.50	147.50	163.25	163.25	163.25	163.25	1.00	1.00	1.00	1.00	298.17	297.83	298.00	194.00	194.00
cycles	147.50	147.50	163.25	163.25	163.25	163.25	1.00	1.00	1.00	1.00	298.17	297.83	298.00	194.00	194.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	215.25
Dispatch	298.17
Overall L1	298.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	26%
load	25%
store	26%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	26%
load	25%
store	26%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 298.17 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 45adc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #1168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X9, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X20, X24, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X6, X22, [X2, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X4, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #688]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D15, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
FMOV D15, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X10, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X5, [SP, #584]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #600]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #680]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X7, [SP, #728]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X5, X7, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X11, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [SP, #536]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X12, [SP, #608]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X7, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X19, [X2, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X13, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X2, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X14, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X23, [X24, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X21, [X9, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X0, [SP, #640]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 527b00 <hypre_NumThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X0, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X15, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X15, [SP, #648]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #656]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X18, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45aedc <hypre_BoomerAMGBuildMultipass+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #640]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X26, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, SP, #816	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X18, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X0, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 526dc0 <hypre_MPI_Comm_size>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X1, SP, #808	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 526df0 <hypre_MPI_Comm_rank>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #688]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [SP, #808]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X3, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.NE 45af2c <hypre_BoomerAMGBuildMultipass+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #688]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X30, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X5, [SP, #824]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADRP X7, <560f2c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X4, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X7, #1288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, SP, #824	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X2, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X10, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 5274a8 <hypre_MPI_Bcast>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X11, 45b8ac <hypre_BoomerAMGBuildMultipass+0xaec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #1176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X12, 45b8bc <hypre_BoomerAMGBuildMultipass+0xafc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X23, 45f530 <hypre_BoomerAMGBuildMultipass+0x4770>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X24, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X24, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X24, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBZ X13, 45af8c <hypre_BoomerAMGBuildMultipass+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X22, [X22, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X22, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X18, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBNZ X0, 45b8e4 <hypre_BoomerAMGBuildMultipass+0xb24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, SP, #832	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X26, SP, #832	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X17, 45afa8 <hypre_BoomerAMGBuildMultipass+0x1e8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X1, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X17, #2720	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP XZR, XZR, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, XZR, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #856]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #848]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X3, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUBS X0, X3, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
STR X8, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.NE 45f4fc <hypre_BoomerAMGBuildMultipass+0x473c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X0, [SP, #760]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X28, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X28, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X0, 45f4c4 <hypre_BoomerAMGBuildMultipass+0x4704>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X0, 45f47c <hypre_BoomerAMGBuildMultipass+0x46bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45f574 <hypre_BoomerAMGBuildMultipass+0x47b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X4, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X5, X3, [X4, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X7, X25, [X4, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
UBFM X24, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X11, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X7, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X3, [SP, #704]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X12, X2, [X4, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X0, [X7, X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #664]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X12, [SP, #712]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBNZ X0, 45f628 <hypre_BoomerAMGBuildMultipass+0x4868>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X27, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X14, [SP, #552]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b144 <hypre_BoomerAMGBuildMultipass+0x384>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X26, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X3, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X17, X1, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X15, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45fa38 <hypre_BoomerAMGBuildMultipass+0x4c78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X1, X3, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X2, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4e0364 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4e0b6c <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b20c <hypre_BoomerAMGBuildMultipass+0x44c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X30, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b1e0 <hypre_BoomerAMGBuildMultipass+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X26, [SP, #584]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X24, X1, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X1, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b20c <hypre_BoomerAMGBuildMultipass+0x44c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X2, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4e0364 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4e0b6c <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, SP, #832	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X27, <20045a210>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X28, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X27, #1920	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X18, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP XZR, XZR, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X18, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X1, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #856]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBNZ X28, 45dfa0 <hypre_BoomerAMGBuildMultipass+0x31e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X24, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #520]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X27, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b4bc <hypre_BoomerAMGBuildMultipass+0x6fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ANDS X7, X8, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ORR X3, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVN X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.EQ 45b35c <hypre_BoomerAMGBuildMultipass+0x59c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b320 <hypre_BoomerAMGBuildMultipass+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b2f0 <hypre_BoomerAMGBuildMultipass+0x530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45fa10 <hypre_BoomerAMGBuildMultipass+0x4c50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45b2d8 <hypre_BoomerAMGBuildMultipass+0x518>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X3, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [X14, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X18, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f724 <hypre_BoomerAMGBuildMultipass+0x4964>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f6fc <hypre_BoomerAMGBuildMultipass+0x493c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f4d8 <hypre_BoomerAMGBuildMultipass+0x4718>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f6d8 <hypre_BoomerAMGBuildMultipass+0x4918>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X18, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b4bc <hypre_BoomerAMGBuildMultipass+0x6fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 45b410 <hypre_BoomerAMGBuildMultipass+0x650>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X13, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X28, X14, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b538 <hypre_BoomerAMGBuildMultipass+0x778>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b564 <hypre_BoomerAMGBuildMultipass+0x7a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X3, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X2, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4e0364 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4e0b6c <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [SP, #552]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #672]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [SP, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X0, 45dff4 <hypre_BoomerAMGBuildMultipass+0x3234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #672]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b618 <hypre_BoomerAMGBuildMultipass+0x858>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #664]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X30, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X17, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X4, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #520]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X28, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [SP, #1176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X24, 45c0e4 <hypre_BoomerAMGBuildMultipass+0x1324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X23, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR X0, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B.LE 45b7dc <hypre_BoomerAMGBuildMultipass+0xa1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ANDS X28, X23, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.EQ 45f8a0 <hypre_BoomerAMGBuildMultipass+0x4ae0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f858 <hypre_BoomerAMGBuildMultipass+0x4a98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b794 <hypre_BoomerAMGBuildMultipass+0x9d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b760 <hypre_BoomerAMGBuildMultipass+0x9a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b72c <hypre_BoomerAMGBuildMultipass+0x96c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b6f8 <hypre_BoomerAMGBuildMultipass+0x938>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b6c4 <hypre_BoomerAMGBuildMultipass+0x904>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b7a0 <hypre_BoomerAMGBuildMultipass+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X30, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X12, X15, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSEL X0, X0, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b7a0 <hypre_BoomerAMGBuildMultipass+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X4, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45b6ec <hypre_BoomerAMGBuildMultipass+0x92c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X14, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X3, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X14, [X3, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X7, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X7, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b7a0 <hypre_BoomerAMGBuildMultipass+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45b720 <hypre_BoomerAMGBuildMultipass+0x960>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X24, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [X24, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X28, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X28, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b7a0 <hypre_BoomerAMGBuildMultipass+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X30, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X15, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X18, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45b754 <hypre_BoomerAMGBuildMultipass+0x994>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X30, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X30, [X16, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X17, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b7a0 <hypre_BoomerAMGBuildMultipass+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45b788 <hypre_BoomerAMGBuildMultipass+0x9c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X10, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X4, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X4, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 45f838 <hypre_BoomerAMGBuildMultipass+0x4a78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X19, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X21, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X23, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b7dc <hypre_BoomerAMGBuildMultipass+0xa1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X23, X23, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X18, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSEL X2, X18, X15, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410600 <@plt_start@+0x5e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP XZR, XZR, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
TBNZ X27, #63, 45c0f4 <hypre_BoomerAMGBuildMultipass+0x1334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X7, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X23, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X30, X13, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
UBFM X8, X27, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [SP, #536]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X19, [SP, #680]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X19, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X14, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBZ X14, 45f664 <hypre_BoomerAMGBuildMultipass+0x48a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ X23, 45f538 <hypre_BoomerAMGBuildMultipass+0x4778>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP XZR, XZR, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X18, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #1176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBZ X0, 45af9c <hypre_BoomerAMGBuildMultipass+0x1dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, SP, #832	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, SP, #832	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X12, <20045a8fc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X0, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X1, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X12, #2720	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP XZR, XZR, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X24, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #856]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #848]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X27, X24, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUBS X0, X27, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
STR X13, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.NE 45f684 <hypre_BoomerAMGBuildMultipass+0x48c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X18, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45b010 <hypre_BoomerAMGBuildMultipass+0x250>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 45b538 <hypre_BoomerAMGBuildMultipass+0x778>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 45b618 <hypre_BoomerAMGBuildMultipass+0x858>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X4, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X24, X30, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X13, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X23, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X4, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45baa8 <hypre_BoomerAMGBuildMultipass+0xce8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45bad4 <hypre_BoomerAMGBuildMultipass+0xd14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X3, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X2, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4e0364 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4e0b6c <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X19, <561ad4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, SP, #792	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X30, X19, #1288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X3, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X4, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, SP, #800	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X24, [SP, #800]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 5276d0 <hypre_MPI_Allreduce>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #792]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X12, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X21, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X12, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X15, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBZ X14, 45f824 <hypre_BoomerAMGBuildMultipass+0x4a64>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X11, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X20, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X28, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [SP, #536]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X27, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X23, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X19, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X21, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45c114 <hypre_BoomerAMGBuildMultipass+0x1354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP XZR, XZR, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
TBZ X27, #63, 45b7e8 <hypre_BoomerAMGBuildMultipass+0xa28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X23, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X24, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45ba30 <hypre_BoomerAMGBuildMultipass+0xc70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X21, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X24, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X23, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X24, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X23, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X21, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X19, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X20, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X15, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X15, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X2, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 45e114 <hypre_BoomerAMGBuildMultipass+0x3354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP XZR, XZR, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X5, X17, [X30, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP X5, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 45e190 <hypre_BoomerAMGBuildMultipass+0x33d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X11, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #520]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [SP, #536]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X11, X30, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X11, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X27, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 45e008 <hypre_BoomerAMGBuildMultipass+0x3248>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X24, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP XZR, XZR, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45e108 <hypre_BoomerAMGBuildMultipass+0x3348>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X1, <2004552a8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X3, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X23, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X21, X20, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X25, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X25, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVN X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X27, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X30, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X11, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X24, [SP, #568]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X24, X1, #524	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X13, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X6, [SP, #736]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X6, X27, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X27, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #544]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X22, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X7, [SP, #696]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X11, [SP, #744]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [SP, #752]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X24, [SP, #768]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [SP, #568]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [SP, #696]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [SP, #736]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ X28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X7, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #672]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #648]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #656]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #640]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X27, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X20, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X20, 45e210 <hypre_BoomerAMGBuildMultipass+0x3450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45cd28 <hypre_BoomerAMGBuildMultipass+0x1f68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #760]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X30, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X7, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X17, X7, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X16, X17, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X3, X30, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X15, X18, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB X2, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.EQ 45f598 <hypre_BoomerAMGBuildMultipass+0x47d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45cc54 <hypre_BoomerAMGBuildMultipass+0x1e94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45cc28 <hypre_BoomerAMGBuildMultipass+0x1e68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X23, [X3, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X5, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X10, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [X5, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [X2, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X11, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X4, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X1, [X11, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X21, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X19, [X20, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X19, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X13, [X20, X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [X2, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X14, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X16, X17, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X16, [X14, X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X15, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X15, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X23, X9, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X23, [X15, X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [X2, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X5, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X12, X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X12, [X5, X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X7, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45cd28 <hypre_BoomerAMGBuildMultipass+0x1f68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X4, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <200454d2c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3152	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X7, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X27, [SP, #832]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X19, [SP, #864]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [SP, #848]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [SP, #872]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X4, [SP, #840]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [SP, #856]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [SP, #1168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X3, X1, [X2, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
SUB X10, X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CBZ X5, 45e264 <hypre_BoomerAMGBuildMultipass+0x34a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X21, <200457d8c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X21, #2372	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X23, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X27, [SP, #920]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [SP, #936]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #912]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X19, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X13, [SP, #928]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X11, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X28, [SP, #944]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X19, [SP, #832]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X11, [SP, #840]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [SP, #584]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X12, [SP, #888]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X15, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X17, [SP, #904]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X7, [SP, #600]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X30, [SP, #848]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [SP, #608]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X15, [SP, #864]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [SP, #872]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [SP, #1176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X6, [SP, #880]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X5, [SP, #896]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X9, [SP, #952]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X14, [SP, #856]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X18, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #1080]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X15, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X18, [SP, #960]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X15, [SP, #1040]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X19, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X14, [SP, #1032]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X5, [SP, #1072]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X19, [SP, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X6, [SP, #1056]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [SP, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X12, [SP, #1064]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #968]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X11, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [SP, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X23, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X30, [SP, #1016]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X11, [SP, #1024]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X7, [SP, #520]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X23, [SP, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #992]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X7, [SP, #1048]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X2, X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CBNZ X2, 45f7cc <hypre_BoomerAMGBuildMultipass+0x4a0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45cee0 <hypre_BoomerAMGBuildMultipass+0x2120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X20, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f7c0 <hypre_BoomerAMGBuildMultipass+0x4a00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X9, <200456ef0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X9, #1824	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X23, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X4, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X16, X26, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
UBFM X11, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X7, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X26, X21, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X4, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X6, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X11, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X15, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45d0f0 <hypre_BoomerAMGBuildMultipass+0x2330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 45c270 <hypre_BoomerAMGBuildMultipass+0x14b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X27, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X0, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X9, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [SP, #520]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45b25c <hypre_BoomerAMGBuildMultipass+0x49c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45b588 <hypre_BoomerAMGBuildMultipass+0x7c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X7, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X6, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X13, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP XZR, X0, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X12, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X28, 45f7a4 <hypre_BoomerAMGBuildMultipass+0x49e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X15, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X0, 45f784 <hypre_BoomerAMGBuildMultipass+0x49c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X2, <200454094>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X2, #1736	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X12, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X1, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X20, [SP, #832]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X21, [SP, #840]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <2004540c8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X1, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1600	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X7, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [SP, #832]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X7, [SP, #840]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X14, [SP, #848]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45c2a8 <hypre_BoomerAMGBuildMultipass+0x14e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45cb30 <hypre_BoomerAMGBuildMultipass+0x1d70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ X18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X28, 45f76c <hypre_BoomerAMGBuildMultipass+0x49ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X28, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X18, [X28, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X21, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP XZR, X14, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X14, [SP, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X5, X17, [X30, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP X5, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 45c1b0 <hypre_BoomerAMGBuildMultipass+0x13f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45c27c <hypre_BoomerAMGBuildMultipass+0x14bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X20, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X19, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X28, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45cbb0 <hypre_BoomerAMGBuildMultipass+0x1df0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X8, <200459268>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X8, #1900	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X23, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X15, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X27, [SP, #920]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X7, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X4, [SP, #936]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X15, [SP, #912]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [SP, #928]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X28, [SP, #944]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X12, [SP, #832]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X18, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [SP, #840]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [SP, #584]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X17, [SP, #888]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X18, [SP, #904]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [SP, #600]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [SP, #848]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [SP, #608]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X30, [SP, #864]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X13, [SP, #872]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X11, [SP, #1176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X14, [SP, #880]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [SP, #896]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [SP, #952]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X11, [SP, #856]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X19, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #1080]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X19, [SP, #960]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X30, [SP, #1040]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X11, [SP, #1032]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [SP, #1072]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X12, [SP, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X14, [SP, #1056]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X17, [SP, #1064]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [SP, #968]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X23, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [SP, #1016]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [SP, #1024]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [SP, #520]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X23, [SP, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [SP, #992]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [SP, #1048]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X0, X2, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CBNZ X0, 45f75c <hypre_BoomerAMGBuildMultipass+0x499c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45e3bc <hypre_BoomerAMGBuildMultipass+0x35fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X7, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X7, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f7c0 <hypre_BoomerAMGBuildMultipass+0x4a00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X6, <2004583cc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X6, #780	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X23, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X11, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X5, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X4, X26, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
UBFM X12, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X13, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X30, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X26, X21, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X14, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X12, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X9, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X14, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X30, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X15, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45e5cc <hypre_BoomerAMGBuildMultipass+0x380c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X26, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #520]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X22, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45eedc <hypre_BoomerAMGBuildMultipass+0x411c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X21, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X30, [SP, #680]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X24, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X23, X25, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X7, [X25, X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X21, X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X30, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X30, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [SP, #688]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [SP, #824]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4f29e0 <hypre_ParCSRMatrixCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FCMP D15, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X14, X22, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X15, [SP, #728]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X21, X7, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X27, [X14, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X27, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CCMP X15, #0, #0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X28, [X22, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X25, X27, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X0, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.NE 45f3d4 <hypre_BoomerAMGBuildMultipass+0x4614>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X24, 45f348 <hypre_BoomerAMGBuildMultipass+0x4588>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [SP, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 45ef64 <hypre_BoomerAMGBuildMultipass+0x41a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X8, <200454f74>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X8, #2400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X1, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X27, [SP, #832]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [SP, #840]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X24, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45f74c <hypre_BoomerAMGBuildMultipass+0x498c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X17, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X18, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X1, X18, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X20, X1, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X4, X20, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD X3, X2, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.EQ 45f0c4 <hypre_BoomerAMGBuildMultipass+0x4304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f0a0 <hypre_BoomerAMGBuildMultipass+0x42e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f084 <hypre_BoomerAMGBuildMultipass+0x42c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f068 <hypre_BoomerAMGBuildMultipass+0x42a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f04c <hypre_BoomerAMGBuildMultipass+0x428c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f030 <hypre_BoomerAMGBuildMultipass+0x4270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f014 <hypre_BoomerAMGBuildMultipass+0x4254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X30, X27, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X11, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X11, 45fa74 <hypre_BoomerAMGBuildMultipass+0x4cb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X15, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X7, X27, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X6, 45f02c <hypre_BoomerAMGBuildMultipass+0x426c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X26, X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X23, X27, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X25, 45f048 <hypre_BoomerAMGBuildMultipass+0x4288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X26, X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X28, X27, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X10, 45f064 <hypre_BoomerAMGBuildMultipass+0x42a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X26, X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X27, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X16, 45f080 <hypre_BoomerAMGBuildMultipass+0x42c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X26, X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X17, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X18, X27, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X1, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X1, 45f09c <hypre_BoomerAMGBuildMultipass+0x42dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X26, X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X2, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X20, X27, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X4, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X4, 45f0b8 <hypre_BoomerAMGBuildMultipass+0x42f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X26, X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f194 <hypre_BoomerAMGBuildMultipass+0x43d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X16, X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X16, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X20, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X3, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X20, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X0, [X9, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X11, <2004541c8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X11, #2252	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X20, [SP, #832]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X23, [SP, #840]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X28, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X14, [SP, #848]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X20, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X2, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 525608 <hypre_qsort0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X11, SP, #832	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X2, <20045a270>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X2, #1064	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X4, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X23, X4, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X25, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X26, [SP, #864]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <2004542a0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1872	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X23, [SP, #840]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X24, [SP, #848]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X14, [SP, #832]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 45f368 <hypre_BoomerAMGBuildMultipass+0x45a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X26, 45f2fc <hypre_BoomerAMGBuildMultipass+0x453c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X25, [X19, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X26, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X22, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X22, 45f38c <hypre_BoomerAMGBuildMultipass+0x45cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X26, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45f318 <hypre_BoomerAMGBuildMultipass+0x4558>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4e1f80 <hypre_MatvecCommPkgCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #1184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR X19, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #1168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45f558 <hypre_BoomerAMGBuildMultipass+0x4798>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X23, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X25, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X28, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X27, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X28, X27, W28,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ORR X20, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45f2d8 <hypre_BoomerAMGBuildMultipass+0x4518>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X23, <200454390>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X23, #2532	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X30, [SP, #840]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X25, [SP, #832]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 45f304 <hypre_BoomerAMGBuildMultipass+0x4544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 45f258 <hypre_BoomerAMGBuildMultipass+0x4498>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #728]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D0, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
BL 44c660 <hypre_BoomerAMGInterpTruncation>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X28, X6, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X23, X28, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45ef48 <hypre_BoomerAMGBuildMultipass+0x4188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X26, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 45f6b0 <hypre_BoomerAMGBuildMultipass+0x48f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 45b06c <hypre_BoomerAMGBuildMultipass+0x2ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #552]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45b20c <hypre_BoomerAMGBuildMultipass+0x44c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45b050 <hypre_BoomerAMGBuildMultipass+0x290>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X1, [X5, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [X28, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45b34c <hypre_BoomerAMGBuildMultipass+0x58c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X4, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X4, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45b010 <hypre_BoomerAMGBuildMultipass+0x250>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP XZR, XZR, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 45af78 <hypre_BoomerAMGBuildMultipass+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X24, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X23, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X24, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #1176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X16, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45af84 <hypre_BoomerAMGBuildMultipass+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 45f2fc <hypre_BoomerAMGBuildMultipass+0x453c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 45f4ac <hypre_BoomerAMGBuildMultipass+0x46ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X1, [SP, #552]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45b20c <hypre_BoomerAMGBuildMultipass+0x44c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X1, X4, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
B 45cc90 <hypre_BoomerAMGBuildMultipass+0x1ed0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X28, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X24, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X24, W19,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STR X11, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X24, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 45c124 <hypre_BoomerAMGBuildMultipass+0x1364>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X15, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X28, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR X28, [SP, #552]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GT 45b0c0 <hypre_BoomerAMGBuildMultipass+0x300>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b20c <hypre_BoomerAMGBuildMultipass+0x44c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 45b144 <hypre_BoomerAMGBuildMultipass+0x384>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X27, [SP, #680]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4e1f80 <hypre_MatvecCommPkgCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X27, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X1, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBZ X23, 45b8c0 <hypre_BoomerAMGBuildMultipass+0xb00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 45f538 <hypre_BoomerAMGBuildMultipass+0x4778>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X15, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X15, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45b960 <hypre_BoomerAMGBuildMultipass+0xba0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 45b06c <hypre_BoomerAMGBuildMultipass+0x2ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 45f4ac <hypre_BoomerAMGBuildMultipass+0x46ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X12, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45b34c <hypre_BoomerAMGBuildMultipass+0x58c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X30, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X15, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X15, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45b320 <hypre_BoomerAMGBuildMultipass+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X1, [X17, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X15, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45b320 <hypre_BoomerAMGBuildMultipass+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVN X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45f19c <hypre_BoomerAMGBuildMultipass+0x43dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 45e37c <hypre_BoomerAMGBuildMultipass+0x35bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X18, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45e130 <hypre_BoomerAMGBuildMultipass+0x3370>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X12, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 45e090 <hypre_BoomerAMGBuildMultipass+0x32d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 45e07c <hypre_BoomerAMGBuildMultipass+0x32bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45ee28 <hypre_BoomerAMGBuildMultipass+0x4068>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 45cea0 <hypre_BoomerAMGBuildMultipass+0x20e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X24, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X27, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X24, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X27, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45c124 <hypre_BoomerAMGBuildMultipass+0x1364>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45fa48 <hypre_BoomerAMGBuildMultipass+0x4c88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [X3, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X13, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b7a0 <hypre_BoomerAMGBuildMultipass+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X24, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X5, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45f880 <hypre_BoomerAMGBuildMultipass+0x4ac0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X28, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [X28, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X23, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b7dc <hypre_BoomerAMGBuildMultipass+0xa1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X18, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45f8a8 <hypre_BoomerAMGBuildMultipass+0x4ae8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 45b7dc <hypre_BoomerAMGBuildMultipass+0xa1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X1, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45b2f0 <hypre_BoomerAMGBuildMultipass+0x530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 45b180 <hypre_BoomerAMGBuildMultipass+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 45b20c <hypre_BoomerAMGBuildMultipass+0x44c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X7, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45f84c <hypre_BoomerAMGBuildMultipass+0x4a8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X27, X19, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X19, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X27, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45c124 <hypre_BoomerAMGBuildMultipass+0x1364>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X26, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45f00c <hypre_BoomerAMGBuildMultipass+0x424c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_multi_interp.c:41-2061
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_BoomerAMGInterpTruncation: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1938
hypre_CAlloc: 46 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:194
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:203
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:204
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:280
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:282
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:283
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:433
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:465
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:267
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:280
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:281
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:608
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:611
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:613
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:617
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1148
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1149
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:348
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:349
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:350
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:351
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:436
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:671
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:672
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:673
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:674
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:675
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:621
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:628
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:630
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1154
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1155
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1954
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1972
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1973
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:288
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:284
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:279
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:280
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:302
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:279
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:280
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:289
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:624
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:678
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:676
hypre_Free: 45 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:461
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:604
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1140
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1141
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1142
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1143
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1144
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1145
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1146
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1305
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1306
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1307
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1670
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1671
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1672
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1893
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1894
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1895
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1896
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1897
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1898
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1899
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1900
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1901
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1902
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1903
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1904
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1905
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1906
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1907
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1908
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1909
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1910
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1911
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1912
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1913
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:2012
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:2019
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:2020
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:2021
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:2019
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:2020
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:2021
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1669
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1304
hypre_MPI_Allreduce: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:546
hypre_MPI_Bcast: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:223
hypre_MPI_Comm_rank: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:217
hypre_MPI_Comm_size: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:216
hypre_MatvecCommPkgCreate: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:2040
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:234
hypre_NumThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:202
hypre_ParCSRCommHandleCreate: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:315
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:331
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:428
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:534
hypre_ParCSRCommHandleDestroy: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:317
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:333
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:430
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:536
hypre_ParCSRMatrixCreate: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1915
hypre_qsort0: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1994
unknown: 14 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:272
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:340
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:469
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:272
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1167
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1184
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:680
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:685
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1575
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1956
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1976
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1997
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:2007
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:2032

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	1722
nb uops	1722
loop length	6888
used w registers	5
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	713

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	215.25 cycles
front end	215.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	147.50	147.50	163.25	163.25	163.25	163.25	1.00	1.00	1.00	1.00	298.17	297.83	298.00	194.00	194.00
cycles	147.50	147.50	163.25	163.25	163.25	163.25	1.00	1.00	1.00	1.00	298.17	297.83	298.00	194.00	194.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	215.25
Dispatch	298.17
Overall L1	298.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	26%
load	25%
store	26%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	26%
load	25%
store	26%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 298.17 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 45adc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #1168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X8, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X9, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X20, X24, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X6, X22, [X2, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X4, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #688]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D15, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
FMOV D15, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X10, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X5, [SP, #584]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #600]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #680]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X7, [SP, #728]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X5, X7, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X11, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [SP, #536]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X12, [SP, #608]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X7, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X19, [X2, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X13, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X2, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X14, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X23, [X24, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X21, [X9, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X0, [SP, #640]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 527b00 <hypre_NumThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X0, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X15, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X15, [SP, #648]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #656]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X18, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45aedc <hypre_BoomerAMGBuildMultipass+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #640]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X26, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, SP, #816	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X18, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X0, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 526dc0 <hypre_MPI_Comm_size>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X1, SP, #808	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 526df0 <hypre_MPI_Comm_rank>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #688]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [SP, #808]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X3, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.NE 45af2c <hypre_BoomerAMGBuildMultipass+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #688]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X30, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X5, [SP, #824]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADRP X7, <560f2c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X4, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X7, #1288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, SP, #824	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X2, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X10, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 5274a8 <hypre_MPI_Bcast>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X11, 45b8ac <hypre_BoomerAMGBuildMultipass+0xaec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #1176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X12, 45b8bc <hypre_BoomerAMGBuildMultipass+0xafc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X23, 45f530 <hypre_BoomerAMGBuildMultipass+0x4770>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X24, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X24, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X24, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBZ X13, 45af8c <hypre_BoomerAMGBuildMultipass+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X22, [X22, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X22, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X18, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBNZ X0, 45b8e4 <hypre_BoomerAMGBuildMultipass+0xb24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, SP, #832	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X26, SP, #832	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X17, 45afa8 <hypre_BoomerAMGBuildMultipass+0x1e8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X1, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X17, #2720	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP XZR, XZR, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, XZR, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #856]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #848]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X3, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUBS X0, X3, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
STR X8, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.NE 45f4fc <hypre_BoomerAMGBuildMultipass+0x473c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X0, [SP, #760]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X28, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X28, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X0, 45f4c4 <hypre_BoomerAMGBuildMultipass+0x4704>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X0, 45f47c <hypre_BoomerAMGBuildMultipass+0x46bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45f574 <hypre_BoomerAMGBuildMultipass+0x47b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X4, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X5, X3, [X4, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X7, X25, [X4, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
UBFM X24, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X11, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X7, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X3, [SP, #704]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X12, X2, [X4, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X0, [X7, X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #664]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X12, [SP, #712]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBNZ X0, 45f628 <hypre_BoomerAMGBuildMultipass+0x4868>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X27, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X14, [SP, #552]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b144 <hypre_BoomerAMGBuildMultipass+0x384>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X26, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X3, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X17, X1, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X15, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45fa38 <hypre_BoomerAMGBuildMultipass+0x4c78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X1, X3, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X2, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4e0364 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4e0b6c <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b20c <hypre_BoomerAMGBuildMultipass+0x44c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X30, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b1e0 <hypre_BoomerAMGBuildMultipass+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X26, [SP, #584]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X24, X1, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X1, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b20c <hypre_BoomerAMGBuildMultipass+0x44c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X2, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4e0364 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4e0b6c <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, SP, #832	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X27, <20045a210>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X28, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X27, #1920	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X18, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP XZR, XZR, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X18, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X1, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #856]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBNZ X28, 45dfa0 <hypre_BoomerAMGBuildMultipass+0x31e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X24, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #520]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X27, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b4bc <hypre_BoomerAMGBuildMultipass+0x6fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ANDS X7, X8, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ORR X3, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVN X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.EQ 45b35c <hypre_BoomerAMGBuildMultipass+0x59c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b320 <hypre_BoomerAMGBuildMultipass+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b2f0 <hypre_BoomerAMGBuildMultipass+0x530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45fa10 <hypre_BoomerAMGBuildMultipass+0x4c50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45b2d8 <hypre_BoomerAMGBuildMultipass+0x518>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X3, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [X14, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X18, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f724 <hypre_BoomerAMGBuildMultipass+0x4964>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f6fc <hypre_BoomerAMGBuildMultipass+0x493c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f4d8 <hypre_BoomerAMGBuildMultipass+0x4718>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f6d8 <hypre_BoomerAMGBuildMultipass+0x4918>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X18, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b4bc <hypre_BoomerAMGBuildMultipass+0x6fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 45b410 <hypre_BoomerAMGBuildMultipass+0x650>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X13, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X28, X14, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b538 <hypre_BoomerAMGBuildMultipass+0x778>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b564 <hypre_BoomerAMGBuildMultipass+0x7a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X3, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X2, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4e0364 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4e0b6c <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [SP, #552]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #672]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [SP, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X0, 45dff4 <hypre_BoomerAMGBuildMultipass+0x3234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #672]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b618 <hypre_BoomerAMGBuildMultipass+0x858>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #664]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X30, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X17, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X4, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #520]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X28, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [SP, #1176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X24, 45c0e4 <hypre_BoomerAMGBuildMultipass+0x1324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X23, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR X0, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B.LE 45b7dc <hypre_BoomerAMGBuildMultipass+0xa1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ANDS X28, X23, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.EQ 45f8a0 <hypre_BoomerAMGBuildMultipass+0x4ae0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f858 <hypre_BoomerAMGBuildMultipass+0x4a98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b794 <hypre_BoomerAMGBuildMultipass+0x9d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b760 <hypre_BoomerAMGBuildMultipass+0x9a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b72c <hypre_BoomerAMGBuildMultipass+0x96c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b6f8 <hypre_BoomerAMGBuildMultipass+0x938>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b6c4 <hypre_BoomerAMGBuildMultipass+0x904>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b7a0 <hypre_BoomerAMGBuildMultipass+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X30, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X12, X15, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSEL X0, X0, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b7a0 <hypre_BoomerAMGBuildMultipass+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X11, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X4, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45b6ec <hypre_BoomerAMGBuildMultipass+0x92c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X14, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X3, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X14, [X3, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X7, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X7, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b7a0 <hypre_BoomerAMGBuildMultipass+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45b720 <hypre_BoomerAMGBuildMultipass+0x960>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X24, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [X24, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X28, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X28, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b7a0 <hypre_BoomerAMGBuildMultipass+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X30, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X15, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X18, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45b754 <hypre_BoomerAMGBuildMultipass+0x994>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X30, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X30, [X16, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X17, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b7a0 <hypre_BoomerAMGBuildMultipass+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45b788 <hypre_BoomerAMGBuildMultipass+0x9c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X10, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X4, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X4, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 45f838 <hypre_BoomerAMGBuildMultipass+0x4a78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X19, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X21, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X23, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b7dc <hypre_BoomerAMGBuildMultipass+0xa1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X23, X23, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X18, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSEL X2, X18, X15, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410600 <@plt_start@+0x5e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP XZR, XZR, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
TBNZ X27, #63, 45c0f4 <hypre_BoomerAMGBuildMultipass+0x1334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X7, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X23, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X30, X13, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
UBFM X8, X27, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [SP, #536]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X19, [SP, #680]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X19, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X14, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBZ X14, 45f664 <hypre_BoomerAMGBuildMultipass+0x48a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ X23, 45f538 <hypre_BoomerAMGBuildMultipass+0x4778>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP XZR, XZR, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X18, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #1176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBZ X0, 45af9c <hypre_BoomerAMGBuildMultipass+0x1dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, SP, #832	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, SP, #832	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X12, <20045a8fc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X0, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X1, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X12, #2720	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP XZR, XZR, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X24, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #856]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #848]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X27, X24, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUBS X0, X27, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
STR X13, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.NE 45f684 <hypre_BoomerAMGBuildMultipass+0x48c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X18, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45b010 <hypre_BoomerAMGBuildMultipass+0x250>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 45b538 <hypre_BoomerAMGBuildMultipass+0x778>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 45b618 <hypre_BoomerAMGBuildMultipass+0x858>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X4, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X24, X30, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X13, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X23, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X4, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45baa8 <hypre_BoomerAMGBuildMultipass+0xce8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45bad4 <hypre_BoomerAMGBuildMultipass+0xd14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X3, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X2, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4e0364 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4e0b6c <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X19, <561ad4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, SP, #792	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X30, X19, #1288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X3, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X4, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, SP, #800	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X24, [SP, #800]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 5276d0 <hypre_MPI_Allreduce>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #792]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X12, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X21, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X12, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X15, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBZ X14, 45f824 <hypre_BoomerAMGBuildMultipass+0x4a64>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X11, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X20, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X28, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [SP, #536]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X27, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X23, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X19, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X21, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45c114 <hypre_BoomerAMGBuildMultipass+0x1354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP XZR, XZR, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
TBZ X27, #63, 45b7e8 <hypre_BoomerAMGBuildMultipass+0xa28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X23, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X24, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45ba30 <hypre_BoomerAMGBuildMultipass+0xc70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X21, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X24, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X23, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X24, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X23, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X21, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X19, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X20, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X15, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X15, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X2, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 45e114 <hypre_BoomerAMGBuildMultipass+0x3354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP XZR, XZR, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X5, X17, [X30, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP X5, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 45e190 <hypre_BoomerAMGBuildMultipass+0x33d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X11, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #520]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [SP, #536]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X11, X30, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X11, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X27, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 45e008 <hypre_BoomerAMGBuildMultipass+0x3248>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X24, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP XZR, XZR, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45e108 <hypre_BoomerAMGBuildMultipass+0x3348>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X1, <2004552a8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X3, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X23, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X21, X20, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X25, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X25, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVN X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X27, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X30, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X11, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X24, [SP, #568]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X24, X1, #524	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X13, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X6, [SP, #736]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X6, X27, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X5, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X27, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #544]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X22, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X7, [SP, #696]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X11, [SP, #744]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [SP, #752]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X24, [SP, #768]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [SP, #568]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [SP, #696]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [SP, #736]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ X28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X7, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #672]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #648]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #656]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #640]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X27, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X20, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X20, 45e210 <hypre_BoomerAMGBuildMultipass+0x3450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45cd28 <hypre_BoomerAMGBuildMultipass+0x1f68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #760]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X30, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X7, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X17, X7, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X16, X17, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X3, X30, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X15, X18, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB X2, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.EQ 45f598 <hypre_BoomerAMGBuildMultipass+0x47d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45cc54 <hypre_BoomerAMGBuildMultipass+0x1e94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45cc28 <hypre_BoomerAMGBuildMultipass+0x1e68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X23, [X3, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X5, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X10, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [X5, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [X2, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X11, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X4, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X1, [X11, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X21, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X19, [X20, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X19, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X13, [X20, X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [X2, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X14, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X16, X17, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X16, [X14, X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X15, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X15, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X23, X9, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X23, [X15, X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [X2, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X5, X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X12, X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X12, [X5, X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X7, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45cd28 <hypre_BoomerAMGBuildMultipass+0x1f68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X4, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <200454d2c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3152	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X7, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X27, [SP, #832]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X19, [SP, #864]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [SP, #848]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [SP, #872]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X4, [SP, #840]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [SP, #856]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [SP, #1168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X3, X1, [X2, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
SUB X10, X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CBZ X5, 45e264 <hypre_BoomerAMGBuildMultipass+0x34a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X21, <200457d8c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X21, #2372	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X23, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X27, [SP, #920]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [SP, #936]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #912]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X19, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X13, [SP, #928]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X11, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X28, [SP, #944]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X19, [SP, #832]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X11, [SP, #840]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [SP, #584]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X12, [SP, #888]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X15, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X17, [SP, #904]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X7, [SP, #600]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X30, [SP, #848]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [SP, #608]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X15, [SP, #864]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [SP, #872]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [SP, #1176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X6, [SP, #880]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X5, [SP, #896]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X9, [SP, #952]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X14, [SP, #856]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X18, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #1080]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X15, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X18, [SP, #960]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X15, [SP, #1040]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X19, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X14, [SP, #1032]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X5, [SP, #1072]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X19, [SP, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X6, [SP, #1056]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [SP, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X12, [SP, #1064]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #968]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X11, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [SP, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X23, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X30, [SP, #1016]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X11, [SP, #1024]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X7, [SP, #520]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X23, [SP, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #992]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X7, [SP, #1048]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X2, X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CBNZ X2, 45f7cc <hypre_BoomerAMGBuildMultipass+0x4a0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45cee0 <hypre_BoomerAMGBuildMultipass+0x2120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X20, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f7c0 <hypre_BoomerAMGBuildMultipass+0x4a00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X9, <200456ef0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X9, #1824	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X23, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X4, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X16, X26, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
UBFM X11, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X7, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X26, X21, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X4, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X6, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X11, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X15, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45d0f0 <hypre_BoomerAMGBuildMultipass+0x2330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 45c270 <hypre_BoomerAMGBuildMultipass+0x14b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X27, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X0, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X9, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [SP, #520]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45b25c <hypre_BoomerAMGBuildMultipass+0x49c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45b588 <hypre_BoomerAMGBuildMultipass+0x7c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X7, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X6, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X13, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP XZR, X0, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X12, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X28, 45f7a4 <hypre_BoomerAMGBuildMultipass+0x49e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X15, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X0, 45f784 <hypre_BoomerAMGBuildMultipass+0x49c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X2, <200454094>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X2, #1736	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X12, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X1, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X20, [SP, #832]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X21, [SP, #840]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <2004540c8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X1, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1600	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X7, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [SP, #832]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X7, [SP, #840]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X14, [SP, #848]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45c2a8 <hypre_BoomerAMGBuildMultipass+0x14e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45cb30 <hypre_BoomerAMGBuildMultipass+0x1d70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ X18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X28, 45f76c <hypre_BoomerAMGBuildMultipass+0x49ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X28, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X18, [X28, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X21, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP XZR, X14, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X14, [SP, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X5, X17, [X30, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP X5, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 45c1b0 <hypre_BoomerAMGBuildMultipass+0x13f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45c27c <hypre_BoomerAMGBuildMultipass+0x14bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X20, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X19, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X28, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45cbb0 <hypre_BoomerAMGBuildMultipass+0x1df0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X8, <200459268>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X8, #1900	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X23, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X15, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X27, [SP, #920]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X7, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X4, [SP, #936]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X15, [SP, #912]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [SP, #928]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X28, [SP, #944]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X12, [SP, #832]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X18, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [SP, #840]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [SP, #584]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X17, [SP, #888]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X18, [SP, #904]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [SP, #600]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [SP, #848]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [SP, #608]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X30, [SP, #864]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X13, [SP, #872]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X11, [SP, #1176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X14, [SP, #880]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [SP, #896]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [SP, #952]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X11, [SP, #856]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X19, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #1080]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X19, [SP, #960]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X30, [SP, #1040]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X11, [SP, #1032]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [SP, #1072]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X12, [SP, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X14, [SP, #1056]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X10, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X17, [SP, #1064]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [SP, #968]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X20, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X23, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [SP, #1016]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [SP, #1024]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X13, [SP, #520]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X23, [SP, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X5, [SP, #992]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [SP, #1048]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X0, X2, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CBNZ X0, 45f75c <hypre_BoomerAMGBuildMultipass+0x499c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45e3bc <hypre_BoomerAMGBuildMultipass+0x35fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X7, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X7, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f7c0 <hypre_BoomerAMGBuildMultipass+0x4a00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X6, <2004583cc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X6, #780	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X8, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X23, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X11, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X5, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X4, X26, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
UBFM X12, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X13, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X30, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X26, X21, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X14, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X12, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X9, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X14, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X30, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X15, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45e5cc <hypre_BoomerAMGBuildMultipass+0x380c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X26, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #520]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X22, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45eedc <hypre_BoomerAMGBuildMultipass+0x411c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X21, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X30, [SP, #680]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X24, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X23, X25, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X7, [X25, X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X21, X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X30, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X30, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [SP, #688]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [SP, #824]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4f29e0 <hypre_ParCSRMatrixCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FCMP D15, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X14, X22, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X15, [SP, #728]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X21, X7, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X27, [X14, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X27, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CCMP X15, #0, #0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X28, [X22, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X25, X27, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X0, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.NE 45f3d4 <hypre_BoomerAMGBuildMultipass+0x4614>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X24, 45f348 <hypre_BoomerAMGBuildMultipass+0x4588>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [SP, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 45ef64 <hypre_BoomerAMGBuildMultipass+0x41a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X8, <200454f74>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X8, #2400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X1, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X27, [SP, #832]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X13, [SP, #840]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X24, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45f74c <hypre_BoomerAMGBuildMultipass+0x498c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X17, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X18, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X1, X18, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X20, X1, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X4, X20, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD X3, X2, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.EQ 45f0c4 <hypre_BoomerAMGBuildMultipass+0x4304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f0a0 <hypre_BoomerAMGBuildMultipass+0x42e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f084 <hypre_BoomerAMGBuildMultipass+0x42c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f068 <hypre_BoomerAMGBuildMultipass+0x42a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f04c <hypre_BoomerAMGBuildMultipass+0x428c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f030 <hypre_BoomerAMGBuildMultipass+0x4270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f014 <hypre_BoomerAMGBuildMultipass+0x4254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X30, X27, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X11, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X11, 45fa74 <hypre_BoomerAMGBuildMultipass+0x4cb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X15, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X7, X27, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X6, 45f02c <hypre_BoomerAMGBuildMultipass+0x426c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X26, X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X12, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X23, X27, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X25, 45f048 <hypre_BoomerAMGBuildMultipass+0x4288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X26, X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X28, X27, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X10, 45f064 <hypre_BoomerAMGBuildMultipass+0x42a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X26, X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X27, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X16, 45f080 <hypre_BoomerAMGBuildMultipass+0x42c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X26, X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X17, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X18, X27, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X1, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X1, 45f09c <hypre_BoomerAMGBuildMultipass+0x42dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X26, X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X2, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X20, X27, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X4, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X4, 45f0b8 <hypre_BoomerAMGBuildMultipass+0x42f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X26, X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45f194 <hypre_BoomerAMGBuildMultipass+0x43d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X16, X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X16, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X20, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X3, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X20, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR X0, [X9, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X11, <2004541c8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X11, #2252	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X20, [SP, #832]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X23, [SP, #840]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X28, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X14, [SP, #848]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X20, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X2, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 525608 <hypre_qsort0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X11, SP, #832	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X2, <20045a270>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X2, #1064	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X4, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X23, X4, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X25, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X26, [SP, #864]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <2004542a0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1872	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X23, [SP, #840]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X24, [SP, #848]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X14, [SP, #832]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X24, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 45f368 <hypre_BoomerAMGBuildMultipass+0x45a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X26, 45f2fc <hypre_BoomerAMGBuildMultipass+0x453c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X25, [X19, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X26, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X22, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X22, 45f38c <hypre_BoomerAMGBuildMultipass+0x45cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X26, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45f318 <hypre_BoomerAMGBuildMultipass+0x4558>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4e1f80 <hypre_MatvecCommPkgCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #1184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR X19, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #1168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45f558 <hypre_BoomerAMGBuildMultipass+0x4798>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X23, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X25, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X28, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X27, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X28, X27, W28,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ORR X20, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45f2d8 <hypre_BoomerAMGBuildMultipass+0x4518>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X23, <200454390>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X23, #2532	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X30, [SP, #840]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X25, [SP, #832]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4103b0 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 45f304 <hypre_BoomerAMGBuildMultipass+0x4544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 45f258 <hypre_BoomerAMGBuildMultipass+0x4498>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #728]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D0, D15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
BL 44c660 <hypre_BoomerAMGInterpTruncation>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X28, X6, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X23, X28, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45ef48 <hypre_BoomerAMGBuildMultipass+0x4188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X26, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 45f6b0 <hypre_BoomerAMGBuildMultipass+0x48f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 45b06c <hypre_BoomerAMGBuildMultipass+0x2ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #552]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45b20c <hypre_BoomerAMGBuildMultipass+0x44c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45b050 <hypre_BoomerAMGBuildMultipass+0x290>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X1, [X5, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [X28, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45b34c <hypre_BoomerAMGBuildMultipass+0x58c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X4, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X4, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45b010 <hypre_BoomerAMGBuildMultipass+0x250>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP XZR, XZR, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 45af78 <hypre_BoomerAMGBuildMultipass+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X24, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X19, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X23, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X24, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #1176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X16, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45af84 <hypre_BoomerAMGBuildMultipass+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 45f2fc <hypre_BoomerAMGBuildMultipass+0x453c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 45f4ac <hypre_BoomerAMGBuildMultipass+0x46ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X1, [SP, #552]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45b20c <hypre_BoomerAMGBuildMultipass+0x44c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X1, X4, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
B 45cc90 <hypre_BoomerAMGBuildMultipass+0x1ed0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X28, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X24, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X24, W19,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STR X11, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X24, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 45c124 <hypre_BoomerAMGBuildMultipass+0x1364>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X15, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X28, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR X28, [SP, #552]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GT 45b0c0 <hypre_BoomerAMGBuildMultipass+0x300>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b20c <hypre_BoomerAMGBuildMultipass+0x44c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 45b144 <hypre_BoomerAMGBuildMultipass+0x384>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X27, [SP, #680]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4e1f80 <hypre_MatvecCommPkgCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X27, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X1, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBZ X23, 45b8c0 <hypre_BoomerAMGBuildMultipass+0xb00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 45f538 <hypre_BoomerAMGBuildMultipass+0x4778>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X15, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X15, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45b960 <hypre_BoomerAMGBuildMultipass+0xba0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #816]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 45b06c <hypre_BoomerAMGBuildMultipass+0x2ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 45f4ac <hypre_BoomerAMGBuildMultipass+0x46ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X12, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45b34c <hypre_BoomerAMGBuildMultipass+0x58c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X30, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X15, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X15, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45b320 <hypre_BoomerAMGBuildMultipass+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X1, [X17, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X15, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45b320 <hypre_BoomerAMGBuildMultipass+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVN X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45f19c <hypre_BoomerAMGBuildMultipass+0x43dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 45e37c <hypre_BoomerAMGBuildMultipass+0x35bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X18, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45e130 <hypre_BoomerAMGBuildMultipass+0x3370>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X12, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 45e090 <hypre_BoomerAMGBuildMultipass+0x32d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 524ea8 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 45e07c <hypre_BoomerAMGBuildMultipass+0x32bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45ee28 <hypre_BoomerAMGBuildMultipass+0x4068>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 524f40 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 45cea0 <hypre_BoomerAMGBuildMultipass+0x20e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X24, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X27, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X24, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X27, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45c124 <hypre_BoomerAMGBuildMultipass+0x1364>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45fa48 <hypre_BoomerAMGBuildMultipass+0x4c88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [X3, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X13, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b7a0 <hypre_BoomerAMGBuildMultipass+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X24, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X5, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45f880 <hypre_BoomerAMGBuildMultipass+0x4ac0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X28, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [X28, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X23, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b7dc <hypre_BoomerAMGBuildMultipass+0xa1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X18, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45f8a8 <hypre_BoomerAMGBuildMultipass+0x4ae8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 45b7dc <hypre_BoomerAMGBuildMultipass+0xa1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR X1, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR XZR, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR XZR, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45b2f0 <hypre_BoomerAMGBuildMultipass+0x530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 45b180 <hypre_BoomerAMGBuildMultipass+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 45b20c <hypre_BoomerAMGBuildMultipass+0x44c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X7, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45f84c <hypre_BoomerAMGBuildMultipass+0x4a8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X27, X19, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X19, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X27, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45c124 <hypre_BoomerAMGBuildMultipass+0x1364>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X26, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X9, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 45f00c <hypre_BoomerAMGBuildMultipass+0x424c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass–	0.22	0.09
○Loop 777 - par_multi_interp.c:385-410 - exec	0.01	0.21
▼Loop 722 - par_multi_interp.c:488-514 - exec–	0.01	0.14
○Loop 771 - par_multi_interp.c:491-498 - exec	0.06	1.29
○Loop 770 - par_multi_interp.c:501-508 - exec	0.00	0.00
○Loop 744 - par_multi_interp.c:1158-1161 - exec	0.01	0.13
▼Loop 723 - par_multi_interp.c:646-661 - exec–	0.00	0.03
○Loop 758 - par_multi_interp.c:651-655 - exec	0.07	1.34
○Loop 757 - par_multi_interp.c:657-661 - exec	0.00	0.00
▼Loop 727 - par_multi_interp.c:1982-1989 - exec–	0.00	0.00
○Loop 728 - par_multi_interp.c:1984-1989 - exec	0.00	0.00
○Loop 726 - par_multi_interp.c:2016-2017 - exec	0.00	0.00
○Loop 780 - par_multi_interp.c:205-208 - exec	0.00	0.00
○Loop 772 - par_multi_interp.c:466-469 - exec	0.00	0.00
▼Loop 773 - par_multi_interp.c:440-457 - exec–	0.00	0.00
○Loop 774 - par_multi_interp.c:442-454 - exec	0.00	0.00
▼Loop 768 - par_multi_interp.c:526-530 - exec–	0.00	0.00
○Loop 769 - par_multi_interp.c:529-530 - exec	0.00	0.00
▼Loop 737 - par_multi_interp.c:729-1566 - exec–	0.00	0.00
▼Loop 738 - par_multi_interp.c:729-1338 - exec–	0.00	0.00
▼Loop 739 - par_multi_interp.c:729-1338 - exec–	0.00	0.00
○Loop 741 - par_multi_interp.c:1337-1338 - exec	0.00	0.00
○Loop 742 - par_multi_interp.c:1333-1334 - exec	0.00	0.00
○Loop 743 - par_multi_interp.c:1333-1334 - exec	0.00	0.00
○Loop 740 - par_multi_interp.c:1337-1338 - exec	0.00	0.00
▼Loop 760 - par_multi_interp.c:548-600 - exec–	0.00	0.00
▼Loop 761 - par_multi_interp.c:590-594 - exec–	0.00	0.00
○Loop 762 - par_multi_interp.c:593-594 - exec	0.00	0.00
○Loop 729 - par_multi_interp.c:1962-1968 - exec	0.00	0.00
▼Loop 720 - par_multi_interp.c:307-311 - exec–	0.00	0.00
○Loop 779 - par_multi_interp.c:310-311 - exec	0.00	0.00
▼Loop 730 - par_multi_interp.c:1674-1888 - exec–	0.00	0.00
▼Loop 731 - par_multi_interp.c:1688-1732 - exec–	0.00	0.00
▼Loop 732 - par_multi_interp.c:1690-1732 - exec–	0.00	0.00
○Loop 735 - par_multi_interp.c:1697-1699 - exec	0.00	0.00
○Loop 734 - par_multi_interp.c:1703-1705 - exec	0.00	0.00
○Loop 733 - par_multi_interp.c:1703-1705 - exec	0.00	0.00
○Loop 736 - par_multi_interp.c:1697-1699 - exec	0.00	0.00
▼Loop 725 - par_multi_interp.c:693-891 - exec–	0.00	0.00
▼Loop 749 - par_multi_interp.c:773-784 - exec–	0.00	0.00
○Loop 750 - par_multi_interp.c:775-780 - exec	0.00	0.00
▼Loop 752 - par_multi_interp.c:733-759 - exec–	0.00	0.00
▼Loop 753 - par_multi_interp.c:735-759 - exec–	0.00	0.00
○Loop 754 - par_multi_interp.c:749-759 - exec	0.00	0.00
○Loop 755 - par_multi_interp.c:742-745 - exec	0.00	0.00
○Loop 756 - par_multi_interp.c:742-745 - exec	0.00	0.00
○Loop 745 - par_multi_interp.c:872-879 - exec	0.00	0.00
○Loop 751 - par_multi_interp.c:703-717 - exec	0.00	0.00
▼Loop 724 - par_multi_interp.c:823-860 - exec–	0.00	0.00
▼Loop 746 - par_multi_interp.c:825-860 - exec–	0.00	0.00
▼Loop 747 - par_multi_interp.c:829-856 - exec–	0.00	0.00
○Loop 748 - par_multi_interp.c:839-850 - exec	0.00	0.00
▼Loop 759 - par_multi_interp.c:548-600 - exec–	0.00	0.00
▼Loop 765 - par_multi_interp.c:550-576 - exec–	0.05	0.96
○Loop 767 - par_multi_interp.c:554-557 - exec	0.01	0.28
○Loop 766 - par_multi_interp.c:568-571 - exec	0.00	0.00
▼Loop 763 - par_multi_interp.c:590-594 - exec–	0.00	0.00
○Loop 764 - par_multi_interp.c:593-594 - exec	0.00	0.00
▼Loop 775 - par_multi_interp.c:415-423 - exec–	0.00	0.00
○Loop 776 - par_multi_interp.c:418-423 - exec	0.00	0.00
▼Loop 721 - par_multi_interp.c:323-327 - exec–	0.00	0.00
○Loop 778 - par_multi_interp.c:326-327 - exec	0.00	0.00

Report Configuration

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Matching between your function (in the source code) and the binary function

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Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code