OV - exec - Function hypre_BoomerAMGCreateS._omp

	Function: hypre_BoomerAMGCreateS._omp_fn.1	Module: exec	Source: par_strength.c:246-513 [...]	Coverage (incl. loops): 0.29% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 246 - 513

--------------------------------------------------------------------------------

246: #pragma omp parallel private(i,diag,row_scale,row_sum,jA,jS)

247: #endif

248:    {

249:    HYPRE_Int start, stop;

250:    hypre_GetSimpleThreadPartition(&start, &stop, num_variables);

251:    HYPRE_Int jS_diag = 0, jS_offd = 0;

252:

253:    for (i = start; i < stop; i++)

254:    {

255:       S_diag_i[i] = jS_diag;

256:       if (num_cols_offd)

257:       {

258:          S_offd_i[i] = jS_offd;

259:       }

260:

261:       diag = A_diag_data[A_diag_i[i]];

262:

263:       /* compute scaling factor and row sum */

264:       row_scale = 0.0;

265:       row_sum = diag;

266:       if (num_functions > 1)

267:       {

268:          if (diag < 0)

269:          {

270:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

271:             {

272:                if (dof_func[i] == dof_func[A_diag_j[jA]])

273:                {

274:                   row_scale = hypre_max(row_scale, A_diag_data[jA]);

275:                   row_sum += A_diag_data[jA];

276:                }

277:             }

278:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

279:             {

280:                if (dof_func[i] == dof_func_offd[A_offd_j[jA]])

281:                {

282:                   row_scale = hypre_max(row_scale, A_offd_data[jA]);

283:                   row_sum += A_offd_data[jA];

[...]

289:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

290:             {

291:                if (dof_func[i] == dof_func[A_diag_j[jA]])

292:                {

293:                   row_scale = hypre_min(row_scale, A_diag_data[jA]);

294:                   row_sum += A_diag_data[jA];

295:                }

296:             }

297:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

298:             {

299:                if (dof_func[i] == dof_func_offd[A_offd_j[jA]])

300:                {

301:                   row_scale = hypre_min(row_scale, A_offd_data[jA]);

302:                   row_sum += A_offd_data[jA];

[...]

309:          if (diag < 0)

310:          {

311:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

312:             {

313:                row_scale = hypre_max(row_scale, A_diag_data[jA]);

314:                row_sum += A_diag_data[jA];

315:             }

316:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

317:             {

318:                row_scale = hypre_max(row_scale, A_offd_data[jA]);

319:                row_sum += A_offd_data[jA];

320:             }

321:          }

322:          else

323:          {

324:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

325:             {

326:                row_scale = hypre_min(row_scale, A_diag_data[jA]);

327:                row_sum += A_diag_data[jA];

328:             }

329:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

330:             {

331:                row_scale = hypre_min(row_scale, A_offd_data[jA]);

332:                row_sum += A_offd_data[jA];

333:             }

334:          } /* diag >= 0*/

335:       } /* num_functions <= 1 */

336:

337:       jS_diag += A_diag_i[i + 1] - A_diag_i[i] - 1;

338:       jS_offd += A_offd_i[i + 1] - A_offd_i[i];

339:

340:       /* compute row entries of S */

341:       S_temp_diag_j[A_diag_i[i]] = -1;

342:       if ((fabs(row_sum) > fabs(diag)*max_row_sum) && (max_row_sum < 1.0))

343:       {

344:          /* make all dependencies weak */

345:          for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

346:          {

347:             S_temp_diag_j[jA] = -1;

348:          }

349:          jS_diag -= A_diag_i[i + 1] - (A_diag_i[i] + 1);

350:

351:          for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

352:          {

353:             S_temp_offd_j[jA] = -1;

354:          }

355:          jS_offd -= A_offd_i[i + 1] - A_offd_i[i];

[...]

363:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

364:                {

365:                   if (A_diag_data[jA] <= strength_threshold * row_scale

366:                       || dof_func[i] != dof_func[A_diag_j[jA]])

367:                   {

368:                      S_temp_diag_j[jA] = -1;

369:                      --jS_diag;

[...]

376:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

377:                {

378:                   if (A_offd_data[jA] <= strength_threshold * row_scale

379:                       || dof_func[i] != dof_func_offd[A_offd_j[jA]])

380:                   {

381:                      S_temp_offd_j[jA] = -1;

382:                      --jS_offd;

[...]

392:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

393:                {

394:                   if (A_diag_data[jA] >= strength_threshold * row_scale

395:                       || dof_func[i] != dof_func[A_diag_j[jA]])

396:                   {

397:                      S_temp_diag_j[jA] = -1;

398:                      --jS_diag;

[...]

405:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

406:                {

407:                   if (A_offd_data[jA] >= strength_threshold * row_scale

408:                       || dof_func[i] != dof_func_offd[A_offd_j[jA]])

409:                   {

410:                      S_temp_offd_j[jA] = -1;

411:                      --jS_offd;

[...]

424:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

425:                {

426:                   if (A_diag_data[jA] <= strength_threshold * row_scale)

427:                   {

428:                      S_temp_diag_j[jA] = -1;

429:                      --jS_diag;

430:                   }

431:                   else

432:                   {

433:                      S_temp_diag_j[jA] = A_diag_j[jA];

434:                   }

435:                }

436:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

437:                {

438:                   if (A_offd_data[jA] <= strength_threshold * row_scale)

439:                   {

440:                      S_temp_offd_j[jA] = -1;

441:                      --jS_offd;

442:                   }

443:                   else

444:                   {

445:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

451:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

452:                {

453:                   if (A_diag_data[jA] >= strength_threshold * row_scale)

454:                   {

455:                      S_temp_diag_j[jA] = -1;

456:                      --jS_diag;

457:                   }

458:                   else

459:                   {

460:                      S_temp_diag_j[jA] = A_diag_j[jA];

461:                   }

462:                }

463:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

464:                {

465:                   if (A_offd_data[jA] >= strength_threshold * row_scale)

466:                   {

467:                      S_temp_offd_j[jA] = -1;

468:                      --jS_offd;

469:                   }

470:                   else

471:                   {

472:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

480:    hypre_prefix_sum_pair(&jS_diag, S_diag_i + num_variables, &jS_offd, S_offd_i + num_variables, prefix_sum_workspace);

[...]

492:    for (i = start; i < stop; i++)

493:    {

494:       S_diag_i[i] += jS_diag;

495:       S_offd_i[i] += jS_offd;

496:

497:       jS = S_diag_i[i];

498:       for (jA = A_diag_i[i]; jA < A_diag_i[i+1]; jA++)

499:       {

500:          if (S_temp_diag_j[jA] > -1)

501:          {

502:             S_diag_j[jS]    = S_temp_diag_j[jA];

503:             jS++;

504:          }

505:       }

506:

507:       jS = S_offd_i[i];

508:       for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

509:       {

510:          if (S_temp_offd_j[jA] > -1)

511:          {

512:             S_offd_j[jS]    = S_temp_offd_j[jA];

513:             jS++;

0x4ae004 STP	X29, X30, [SP, #816]!

0x4ae008 ORR	X3, XZR, X0

0x4ae00c ADD	X29, SP, #0

0x4ae010 ADD	X1, SP, #184

0x4ae014 ADD	X0, SP, #176

0x4ae018 STP	X19, X20, [SP, #16]

0x4ae01c STP	X21, X22, [SP, #32]

0x4ae020 STP	X23, X24, [SP, #48]

0x4ae024 STP	X25, X26, [SP, #64]

0x4ae028 STP	X27, X28, [SP, #80]

0x4ae02c STP	D14, D15, [SP, #96]

0x4ae030 LDR	X8, [X3, #112]

0x4ae034 LDP	X10, X22, [X3, #32]

0x4ae038 LDP	X7, X28, [X3, #96]

0x4ae03c LDP	X9, X23, [X3, #48]

0x4ae040 LDP	X4, X21, [X3, #16]

0x4ae044 LDP	X25, X24, [X3, #64]

0x4ae048 LDR	X5, [X3, #80]

0x4ae04c LDP	D14, D15, [X3]

0x4ae050 STP	X8, X7, [SP, #120]

0x4ae054 ORR	X2, XZR, X5

0x4ae058 STP	X9, X10, [SP, #136]

0x4ae05c LDR	X6, [X3, #88]

0x4ae060 STR	X5, [SP, #152]

0x4ae064 STR	X4, [SP, #168]

0x4ae068 STR	X6, [SP, #160]

0x4ae06c LDP	X27, X26, [X3, #120]

0x4ae070 LDP	X11, X19, [X3, #136]

0x4ae074 LDR	X20, [X3, #152]

0x4ae078 STR	X11, [SP, #112]

0x4ae07c BL	527b60

0x4ae080 LDP	X4, X30, [SP, #176]

0x4ae084 STP	XZR, XZR, [SP, #192]

0x4ae088 CMP	X4, X30

0x4ae08c LDR	X18, [SP, #152]

0x4ae090 LDP	X8, X7, [SP, #120]

0x4ae094 LDP	X15, X10, [SP, #136]

0x4ae098 B.GE	4ae630

0x4ae09c UBFM	X0, X4, #61, #60

0x4ae0a0 FMOV	D31, #1.0000000

0x4ae0a4 ADD	X12, X15, X4,LSL #3

0x4ae0a8 ADD	X13, X0, #8

0x4ae0ac MOVZ	X2, #0

0x4ae0b0 LDP	X16, X17, [SP, #160]

0x4ae0b4 ADD	X3, X15, X13

0x4ae0b8 ADD	X0, X10, X13

0x4ae0bc MOVZ	X1, #0

0x4ae0c0 MOVN	X13, #0

0x4ae0c4 STP	X27, X28, [SP, #120]

0x4ae0c8 STP	X18, X15, [SP, #136]

(1912) 0x4ae0cc STR	X1, [X7, X4,LSL #3]

(1912) 0x4ae0d0 CBZ	X16, 4ae0d8

(1912) 0x4ae0d4 STR	X2, [X8, X4,LSL #3]

(1912) 0x4ae0d8 LDP	X6, X9, [X0, #1016]

(1912) 0x4ae0dc UBFM	X14, X6, #61, #60

(1912) 0x4ae0e0 ADD	X5, X6, #1

(1912) 0x4ae0e4 LDR	D4, [X22, X14]

(1912) 0x4ae0e8 CMP	X17, #1

(1912) 0x4ae0ec B.LE	4ae77c

(1912) 0x4ae0f0 FCMPE	D4, #0

(1912) 0x4ae0f4 B.MI	4aeb70

(1912) 0x4ae0f8 CMP	X5, X9

(1912) 0x4ae0fc B.GE	4af614

(1912) 0x4ae100 SUB	X18, X9, X5

(1912) 0x4ae104 LDR	X11, [X21, X4,LSL #3]

(1912) 0x4ae108 FMOV	D23, D4

(1912) 0x4ae10c ANDS	X15, X18, #0x7

(1912) 0x4ae110 MOVI	D22, #0

(1912) 0x4ae114 B.EQ	4ae1ec

(1912) 0x4ae118 CMP	X15, #1

(1912) 0x4ae11c B.EQ	4ae1c0

(1912) 0x4ae120 CMP	X15, #2

(1912) 0x4ae124 B.EQ	4ae1ac

(1912) 0x4ae128 CMP	X15, #3

(1912) 0x4ae12c B.EQ	4ae198

(1912) 0x4ae130 CMP	X15, #4

(1912) 0x4ae134 B.EQ	4ae184

(1912) 0x4ae138 CMP	X15, #5

(1912) 0x4ae13c B.EQ	4ae170

(1912) 0x4ae140 CMP	X15, #6

(1912) 0x4ae144 B.EQ	4ae15c

(1912) 0x4ae148 LDR	X27, [X25, X5,LSL #3]

(1912) 0x4ae14c LDR	X28, [X21, X27,LSL #3]

(1912) 0x4ae150 CMP	X11, X28

(1912) 0x4ae154 B.EQ	4af698

(1912) 0x4ae158 ADD	X5, X5, #1

(1912) 0x4ae15c LDR	X18, [X25, X5,LSL #3]

(1912) 0x4ae160 LDR	X15, [X21, X18,LSL #3]

(1912) 0x4ae164 CMP	X11, X15

(1912) 0x4ae168 B.EQ	4af600

(1912) 0x4ae16c ADD	X5, X5, #1

(1912) 0x4ae170 LDR	X27, [X25, X5,LSL #3]

(1912) 0x4ae174 LDR	X28, [X21, X27,LSL #3]

(1912) 0x4ae178 CMP	X11, X28

(1912) 0x4ae17c B.EQ	4af588

(1912) 0x4ae180 ADD	X5, X5, #1

(1912) 0x4ae184 LDR	X18, [X25, X5,LSL #3]

(1912) 0x4ae188 LDR	X15, [X21, X18,LSL #3]

(1912) 0x4ae18c CMP	X11, X15

(1912) 0x4ae190 B.EQ	4af524

(1912) 0x4ae194 ADD	X5, X5, #1

(1912) 0x4ae198 LDR	X27, [X25, X5,LSL #3]

(1912) 0x4ae19c LDR	X28, [X21, X27,LSL #3]

(1912) 0x4ae1a0 CMP	X11, X28

(1912) 0x4ae1a4 B.EQ	4ae734

(1912) 0x4ae1a8 ADD	X5, X5, #1

(1912) 0x4ae1ac LDR	X18, [X25, X5,LSL #3]

(1912) 0x4ae1b0 LDR	X15, [X21, X18,LSL #3]

(1912) 0x4ae1b4 CMP	X11, X15

(1912) 0x4ae1b8 B.EQ	4ae720

(1912) 0x4ae1bc ADD	X5, X5, #1

(1912) 0x4ae1c0 LDR	X27, [X25, X5,LSL #3]

(1912) 0x4ae1c4 LDR	X28, [X21, X27,LSL #3]

(1912) 0x4ae1c8 CMP	X11, X28

(1912) 0x4ae1cc B.NE	4ae1e0

(1912) 0x4ae1d0 LDR	D21, [X22, X5,LSL #3]

(1912) 0x4ae1d4 FCMPE	D21, D22

(1912) 0x4ae1d8 FADD	D23, D23, D21

(1912) 0x4ae1dc FCSEL	D22, D22, D21, #12

(1912) 0x4ae1e0 ADD	X5, X5, #1

(1912) 0x4ae1e4 CMP	X5, X9

(1912) 0x4ae1e8 B.EQ	4ae314

  (1930) 0x4ae1ec LDR	X18, [X25, X5,LSL #3]

  (1930) 0x4ae1f0 LDR	X15, [X21, X18,LSL #3]

  (1930) 0x4ae1f4 CMP	X11, X15

  (1930) 0x4ae1f8 B.NE	4ae20c

  (1930) 0x4ae1fc LDR	D1, [X22, X5,LSL #3]

  (1930) 0x4ae200 FCMPE	D1, D22

  (1930) 0x4ae204 FADD	D23, D23, D1

  (1930) 0x4ae208 FCSEL	D22, D22, D1, #12

  (1930) 0x4ae20c ADD	X5, X5, #1

  (1930) 0x4ae210 LDR	X27, [X25, X5,LSL #3]

  (1930) 0x4ae214 LDR	X28, [X21, X27,LSL #3]

  (1930) 0x4ae218 CMP	X11, X28

  (1930) 0x4ae21c B.NE	4ae230

  (1930) 0x4ae220 LDR	D0, [X22, X5,LSL #3]

  (1930) 0x4ae224 FCMPE	D0, D22

  (1930) 0x4ae228 FADD	D23, D23, D0

  (1930) 0x4ae22c FCSEL	D22, D22, D0, #12

  (1930) 0x4ae230 ADD	X15, X5, #1

  (1930) 0x4ae234 LDR	X18, [X25, X15,LSL #3]

  (1930) 0x4ae238 LDR	X27, [X21, X18,LSL #3]

  (1930) 0x4ae23c CMP	X11, X27

  (1930) 0x4ae240 B.NE	4ae254

  (1930) 0x4ae244 LDR	D20, [X22, X15,LSL #3]

  (1930) 0x4ae248 FCMPE	D20, D22

  (1930) 0x4ae24c FADD	D23, D23, D20

  (1930) 0x4ae250 FCSEL	D22, D22, D20, #12

  (1930) 0x4ae254 ADD	X28, X5, #2

  (1930) 0x4ae258 LDR	X15, [X25, X28,LSL #3]

  (1930) 0x4ae25c LDR	X18, [X21, X15,LSL #3]

  (1930) 0x4ae260 CMP	X11, X18

  (1930) 0x4ae264 B.NE	4ae278

  (1930) 0x4ae268 LDR	D19, [X22, X28,LSL #3]

  (1930) 0x4ae26c FCMPE	D19, D22

  (1930) 0x4ae270 FADD	D23, D23, D19

  (1930) 0x4ae274 FCSEL	D22, D22, D19, #12

  (1930) 0x4ae278 ADD	X27, X5, #3

  (1930) 0x4ae27c LDR	X28, [X25, X27,LSL #3]

  (1930) 0x4ae280 LDR	X15, [X21, X28,LSL #3]

  (1930) 0x4ae284 CMP	X11, X15

  (1930) 0x4ae288 B.NE	4ae29c

  (1930) 0x4ae28c LDR	D24, [X22, X27,LSL #3]

  (1930) 0x4ae290 FCMPE	D24, D22

  (1930) 0x4ae294 FADD	D23, D23, D24

  (1930) 0x4ae298 FCSEL	D22, D22, D24, #12

  (1930) 0x4ae29c ADD	X27, X5, #4

  (1930) 0x4ae2a0 LDR	X18, [X25, X27,LSL #3]

  (1930) 0x4ae2a4 LDR	X28, [X21, X18,LSL #3]

  (1930) 0x4ae2a8 CMP	X11, X28

  (1930) 0x4ae2ac B.NE	4ae2c0

  (1930) 0x4ae2b0 LDR	D25, [X22, X27,LSL #3]

  (1930) 0x4ae2b4 FCMPE	D25, D22

  (1930) 0x4ae2b8 FADD	D23, D23, D25

  (1930) 0x4ae2bc FCSEL	D22, D22, D25, #12

  (1930) 0x4ae2c0 ADD	X15, X5, #5

  (1930) 0x4ae2c4 LDR	X27, [X25, X15,LSL #3]

  (1930) 0x4ae2c8 LDR	X18, [X21, X27,LSL #3]

  (1930) 0x4ae2cc CMP	X11, X18

  (1930) 0x4ae2d0 B.NE	4ae2e4

  (1930) 0x4ae2d4 LDR	D28, [X22, X15,LSL #3]

  (1930) 0x4ae2d8 FCMPE	D28, D22

  (1930) 0x4ae2dc FADD	D23, D23, D28

  (1930) 0x4ae2e0 FCSEL	D22, D22, D28, #12

  (1930) 0x4ae2e4 ADD	X28, X5, #6

  (1930) 0x4ae2e8 LDR	X15, [X25, X28,LSL #3]

  (1930) 0x4ae2ec LDR	X27, [X21, X15,LSL #3]

  (1930) 0x4ae2f0 CMP	X11, X27

  (1930) 0x4ae2f4 B.NE	4ae308

  (1930) 0x4ae2f8 LDR	D29, [X22, X28,LSL #3]

  (1930) 0x4ae2fc FCMPE	D29, D22

  (1930) 0x4ae300 FADD	D23, D23, D29

  (1930) 0x4ae304 FCSEL	D22, D22, D29, #12

  (1930) 0x4ae308 ADD	X5, X5, #7

  (1930) 0x4ae30c CMP	X5, X9

  (1930) 0x4ae310 B.NE	4ae1ec

(1912) 0x4ae314 LDR	X18, [X3]

(1912) 0x4ae318 LDR	X15, [X12]

(1912) 0x4ae31c CMP	X15, X18

(1912) 0x4ae320 B.GE	4ae534

(1912) 0x4ae324 SUB	X28, X18, X15

(1912) 0x4ae328 LDR	X11, [X21, X4,LSL #3]

(1912) 0x4ae32c ORR	X5, XZR, X15

(1912) 0x4ae330 ANDS	X27, X28, #0x7

(1912) 0x4ae334 B.EQ	4ae40c

(1912) 0x4ae338 CMP	X27, #1

(1912) 0x4ae33c B.EQ	4ae3e0

(1912) 0x4ae340 CMP	X27, #2

(1912) 0x4ae344 B.EQ	4ae3cc

(1912) 0x4ae348 CMP	X27, #3

(1912) 0x4ae34c B.EQ	4ae3b8

(1912) 0x4ae350 CMP	X27, #4

(1912) 0x4ae354 B.EQ	4ae3a4

(1912) 0x4ae358 CMP	X27, #5

(1912) 0x4ae35c B.EQ	4ae390

(1912) 0x4ae360 CMP	X27, #6

(1912) 0x4ae364 B.EQ	4ae37c

(1912) 0x4ae368 LDR	X5, [X24, X15,LSL #3]

(1912) 0x4ae36c LDR	X28, [X26, X5,LSL #3]

(1912) 0x4ae370 CMP	X11, X28

(1912) 0x4ae374 B.EQ	4af6b0

(1912) 0x4ae378 ADD	X5, X15, #1

(1912) 0x4ae37c LDR	X27, [X24, X5,LSL #3]

(1912) 0x4ae380 LDR	X28, [X26, X27,LSL #3]

(1912) 0x4ae384 CMP	X11, X28

(1912) 0x4ae388 B.EQ	4af5ec

(1912) 0x4ae38c ADD	X5, X5, #1

(1912) 0x4ae390 LDR	X27, [X24, X5,LSL #3]

(1912) 0x4ae394 LDR	X28, [X26, X27,LSL #3]

(1912) 0x4ae398 CMP	X11, X28

(1912) 0x4ae39c B.EQ	4af574

(1912) 0x4ae3a0 ADD	X5, X5, #1

(1912) 0x4ae3a4 LDR	X27, [X24, X5,LSL #3]

(1912) 0x4ae3a8 LDR	X28, [X26, X27,LSL #3]

(1912) 0x4ae3ac CMP	X11, X28

(1912) 0x4ae3b0 B.EQ	4af538

(1912) 0x4ae3b4 ADD	X5, X5, #1

(1912) 0x4ae3b8 LDR	X27, [X24, X5,LSL #3]

(1912) 0x4ae3bc LDR	X28, [X26, X27,LSL #3]

(1912) 0x4ae3c0 CMP	X11, X28

(1912) 0x4ae3c4 B.EQ	4ae75c

(1912) 0x4ae3c8 ADD	X5, X5, #1

(1912) 0x4ae3cc LDR	X27, [X24, X5,LSL #3]

(1912) 0x4ae3d0 LDR	X28, [X26, X27,LSL #3]

(1912) 0x4ae3d4 CMP	X11, X28

(1912) 0x4ae3d8 B.EQ	4ae748

(1912) 0x4ae3dc ADD	X5, X5, #1

(1912) 0x4ae3e0 LDR	X27, [X24, X5,LSL #3]

(1912) 0x4ae3e4 LDR	X28, [X26, X27,LSL #3]

(1912) 0x4ae3e8 CMP	X11, X28

(1912) 0x4ae3ec B.NE	4ae400

(1912) 0x4ae3f0 LDR	D5, [X23, X5,LSL #3]

(1912) 0x4ae3f4 FCMPE	D5, D22

(1912) 0x4ae3f8 FADD	D23, D23, D5

(1912) 0x4ae3fc FCSEL	D22, D22, D5, #12

(1912) 0x4ae400 ADD	X5, X5, #1

(1912) 0x4ae404 CMP	X5, X18

(1912) 0x4ae408 B.EQ	4ae534

  (1929) 0x4ae40c LDR	X27, [X24, X5,LSL #3]

  (1929) 0x4ae410 LDR	X28, [X26, X27,LSL #3]

  (1929) 0x4ae414 CMP	X11, X28

  (1929) 0x4ae418 B.NE	4ae42c

  (1929) 0x4ae41c LDR	D27, [X23, X5,LSL #3]

  (1929) 0x4ae420 FCMPE	D27, D22

  (1929) 0x4ae424 FADD	D23, D23, D27

  (1929) 0x4ae428 FCSEL	D22, D22, D27, #12

  (1929) 0x4ae42c ADD	X5, X5, #1

  (1929) 0x4ae430 LDR	X27, [X24, X5,LSL #3]

  (1929) 0x4ae434 LDR	X28, [X26, X27,LSL #3]

  (1929) 0x4ae438 CMP	X11, X28

  (1929) 0x4ae43c B.NE	4ae450

  (1929) 0x4ae440 LDR	D18, [X23, X5,LSL #3]

  (1929) 0x4ae444 FCMPE	D18, D22

  (1929) 0x4ae448 FADD	D23, D23, D18

  (1929) 0x4ae44c FCSEL	D22, D22, D18, #12

  (1929) 0x4ae450 ADD	X27, X5, #1

  (1929) 0x4ae454 LDR	X28, [X24, X27,LSL #3]

  (1929) 0x4ae458 LDR	X28, [X26, X28,LSL #3]

  (1929) 0x4ae45c CMP	X11, X28

  (1929) 0x4ae460 B.NE	4ae474

  (1929) 0x4ae464 LDR	D17, [X23, X27,LSL #3]

  (1929) 0x4ae468 FCMPE	D17, D22

  (1929) 0x4ae46c FADD	D23, D23, D17

  (1929) 0x4ae470 FCSEL	D22, D22, D17, #12

  (1929) 0x4ae474 ADD	X27, X5, #2

  (1929) 0x4ae478 LDR	X28, [X24, X27,LSL #3]

  (1929) 0x4ae47c LDR	X28, [X26, X28,LSL #3]

  (1929) 0x4ae480 CMP	X11, X28

  (1929) 0x4ae484 B.NE	4ae498

  (1929) 0x4ae488 LDR	D2, [X23, X27,LSL #3]

  (1929) 0x4ae48c FCMPE	D2, D22

  (1929) 0x4ae490 FADD	D23, D23, D2

  (1929) 0x4ae494 FCSEL	D22, D22, D2, #12

  (1929) 0x4ae498 ADD	X27, X5, #3

  (1929) 0x4ae49c LDR	X28, [X24, X27,LSL #3]

  (1929) 0x4ae4a0 LDR	X28, [X26, X28,LSL #3]

  (1929) 0x4ae4a4 CMP	X11, X28

  (1929) 0x4ae4a8 B.NE	4ae4bc

  (1929) 0x4ae4ac LDR	D21, [X23, X27,LSL #3]

  (1929) 0x4ae4b0 FCMPE	D21, D22

  (1929) 0x4ae4b4 FADD	D23, D23, D21

  (1929) 0x4ae4b8 FCSEL	D22, D22, D21, #12

  (1929) 0x4ae4bc ADD	X27, X5, #4

  (1929) 0x4ae4c0 LDR	X28, [X24, X27,LSL #3]

  (1929) 0x4ae4c4 LDR	X28, [X26, X28,LSL #3]

  (1929) 0x4ae4c8 CMP	X11, X28

  (1929) 0x4ae4cc B.NE	4ae4e0

  (1929) 0x4ae4d0 LDR	D1, [X23, X27,LSL #3]

  (1929) 0x4ae4d4 FCMPE	D1, D22

  (1929) 0x4ae4d8 FADD	D23, D23, D1

  (1929) 0x4ae4dc FCSEL	D22, D22, D1, #12

  (1929) 0x4ae4e0 ADD	X27, X5, #5

  (1929) 0x4ae4e4 LDR	X28, [X24, X27,LSL #3]

  (1929) 0x4ae4e8 LDR	X28, [X26, X28,LSL #3]

  (1929) 0x4ae4ec CMP	X11, X28

  (1929) 0x4ae4f0 B.NE	4ae504

  (1929) 0x4ae4f4 LDR	D0, [X23, X27,LSL #3]

  (1929) 0x4ae4f8 FCMPE	D0, D22

  (1929) 0x4ae4fc FADD	D23, D23, D0

  (1929) 0x4ae500 FCSEL	D22, D22, D0, #12

  (1929) 0x4ae504 ADD	X27, X5, #6

  (1929) 0x4ae508 LDR	X28, [X24, X27,LSL #3]

  (1929) 0x4ae50c LDR	X28, [X26, X28,LSL #3]

  (1929) 0x4ae510 CMP	X11, X28

  (1929) 0x4ae514 B.NE	4ae528

  (1929) 0x4ae518 LDR	D20, [X23, X27,LSL #3]

  (1929) 0x4ae51c FCMPE	D20, D22

  (1929) 0x4ae520 FADD	D23, D23, D20

  (1929) 0x4ae524 FCSEL	D22, D22, D20, #12

  (1929) 0x4ae528 ADD	X5, X5, #7

  (1929) 0x4ae52c CMP	X5, X18

  (1929) 0x4ae530 B.NE	4ae40c

(1912) 0x4ae534 FABS	D4, D4

(1912) 0x4ae538 SUB	X6, X9, X6

(1912) 0x4ae53c FABS	D24, D23

(1912) 0x4ae540 SUB	X9, X18, X15

(1912) 0x4ae544 STR	X13, [X19, X14]

(1912) 0x4ae548 SUB	X14, X6, #1

(1912) 0x4ae54c LDP	X18, X15, [X0, #1016]

(1912) 0x4ae550 ADD	X2, X2, X9

(1912) 0x4ae554 ADD	X1, X1, X14

(1912) 0x4ae558 FMUL	D19, D4, D15

(1912) 0x4ae55c ADD	X27, X18, #1

(1912) 0x4ae560 FCMPE	D19, D24

(1912) 0x4ae564 B.MI	4af098

(1912) 0x4ae568 CMP	X27, X15

(1912) 0x4ae56c B.GE	4ae5bc

(1912) 0x4ae570 FMUL	D25, D14, D22

(1912) 0x4ae574 HINT	#0

(1912) 0x4ae578 HINT	#0

(1912) 0x4ae57c HINT	#0

  (1928) 0x4ae580 LDR	D28, [X22, X27,LSL #3]

  (1928) 0x4ae584 FCMPE	D25, D28

  (1928) 0x4ae588 B.LS	4ae5a0

  (1928) 0x4ae58c LDR	X28, [X25, X27,LSL #3]

  (1928) 0x4ae590 LDR	X15, [X21, X4,LSL #3]

  (1928) 0x4ae594 LDR	X11, [X21, X28,LSL #3]

  (1928) 0x4ae598 CMP	X11, X15

  (1928) 0x4ae59c B.EQ	4ae5a8

  (1928) 0x4ae5a0 SUB	X1, X1, #1

  (1928) 0x4ae5a4 MOVN	X28, #0

  (1928) 0x4ae5a8 STR	X28, [X19, X27,LSL #3]

  (1928) 0x4ae5ac ADD	X27, X27, #1

  (1928) 0x4ae5b0 LDR	X5, [X0]

  (1928) 0x4ae5b4 CMP	X5, X27

  (1928) 0x4ae5b8 B.GT	4ae580

(1912) 0x4ae5bc LDR	X27, [X3]

(1912) 0x4ae5c0 LDR	X18, [X12]

(1912) 0x4ae5c4 CMP	X18, X27

(1912) 0x4ae5c8 B.GE	4ae60c

(1912) 0x4ae5cc FMUL	D29, D14, D22

  (1927) 0x4ae5d0 LDR	D23, [X23, X18,LSL #3]

  (1927) 0x4ae5d4 FCMPE	D29, D23

  (1927) 0x4ae5d8 B.LS	4ae5f0

  (1927) 0x4ae5dc LDR	X6, [X24, X18,LSL #3]

  (1927) 0x4ae5e0 LDR	X9, [X21, X4,LSL #3]

  (1927) 0x4ae5e4 LDR	X14, [X26, X6,LSL #3]

  (1927) 0x4ae5e8 CMP	X14, X9

  (1927) 0x4ae5ec B.EQ	4ae5f8

  (1927) 0x4ae5f0 SUB	X2, X2, #1

  (1927) 0x4ae5f4 MOVN	X6, #0

  (1927) 0x4ae5f8 STR	X6, [X20, X18,LSL #3]

  (1927) 0x4ae5fc ADD	X18, X18, #1

  (1927) 0x4ae600 LDR	X15, [X3]

  (1927) 0x4ae604 CMP	X15, X18

  (1927) 0x4ae608 B.GT	4ae5d0

(1912) 0x4ae60c ADD	X4, X4, #1

(1912) 0x4ae610 ADD	X12, X12, #8

(1912) 0x4ae614 ADD	X3, X3, #8

(1912) 0x4ae618 ADD	X0, X0, #8

(1912) 0x4ae61c CMP	X4, X30

(1912) 0x4ae620 B.NE	4ae0cc

0x4ae624 LDP	X27, X28, [SP, #120]

0x4ae628 LDP	X18, X15, [SP, #136]

0x4ae62c STP	X1, X2, [SP, #192]

0x4ae630 ADD	X1, X7, X18,LSL #3

0x4ae634 ADD	X2, SP, #200

0x4ae638 ADD	X0, SP, #192

0x4ae63c ADD	X3, X8, X18,LSL #3

0x4ae640 LDR	X4, [SP, #112]

0x4ae644 STP	X7, X8, [SP, #112]

0x4ae648 STP	X15, X10, [SP, #128]

0x4ae64c BL	528d08

0x4ae650 LDP	X1, X21, [SP, #176]

0x4ae654 CMP	X1, X21

0x4ae658 B.GE	4ae700

0x4ae65c LDP	X16, X10, [SP, #128]

0x4ae660 LDP	X7, X8, [SP, #112]

0x4ae664 ADD	X22, X10, #8

0x4ae668 ADD	X23, X16, #8

0x4ae66c LDP	X17, X13, [SP, #192]

(1908) 0x4ae670 LDR	X2, [X7, X1,LSL #3]

(1908) 0x4ae674 ADD	X24, X2, X17

(1908) 0x4ae678 STR	X24, [X7, X1,LSL #3]

(1908) 0x4ae67c LDR	X25, [X8, X1,LSL #3]

(1908) 0x4ae680 ADD	X9, X13, X25

(1908) 0x4ae684 STR	X9, [X8, X1,LSL #3]

(1908) 0x4ae688 LDR	X30, [X10, X1,LSL #3]

(1908) 0x4ae68c LDR	X5, [X22, X1,LSL #3]

(1908) 0x4ae690 LDR	X11, [X7, X1,LSL #3]

(1908) 0x4ae694 CMP	X30, X5

(1908) 0x4ae698 B.GE	4ae6c4

(1908) 0x4ae69c HINT	#0

  (1911) 0x4ae6a0 LDR	X26, [X19, X30,LSL #3]

  (1911) 0x4ae6a4 ADD	X30, X30, #1

  (1911) 0x4ae6a8 TBNZ	X26, #63, 4ae770

  (1911) 0x4ae6ac STR	X26, [X28, X11,LSL #3]

  (1911) 0x4ae6b0 ADD	X11, X11, #1

  (1911) 0x4ae6b4 LDR	X5, [X22, X1,LSL #3]

  (1911) 0x4ae6b8 CMP	X5, X30

  (1911) 0x4ae6bc B.GT	4ae6a0

(1908) 0x4ae6c0 LDR	X9, [X8, X1,LSL #3]

(1908) 0x4ae6c4 LDR	X6, [X16, X1,LSL #3]

(1908) 0x4ae6c8 LDR	X4, [X23, X1,LSL #3]

  (1909) 0x4ae6cc CMP	X6, X4

  (1909) 0x4ae6d0 B.GE	4ae6f4

    (1910) 0x4ae6d4 LDR	X14, [X20, X6,LSL #3]

    (1910) 0x4ae6d8 ADD	X6, X6, #1

    (1910) 0x4ae6dc TBNZ	X14, #63, 4ae6cc

    (1910) 0x4ae6e0 STR	X14, [X27, X9,LSL #3]

    (1910) 0x4ae6e4 ADD	X9, X9, #1

    (1910) 0x4ae6e8 LDR	X4, [X23, X1,LSL #3]

    (1910) 0x4ae6ec CMP	X4, X6

    (1910) 0x4ae6f0 B.GT	4ae6d4

(1908) 0x4ae6f4 ADD	X1, X1, #1

(1908) 0x4ae6f8 CMP	X1, X21

(1908) 0x4ae6fc B.NE	4ae670

0x4ae700 LDP	D14, D15, [SP, #96]

0x4ae704 LDP	X19, X20, [SP, #16]

0x4ae708 LDP	X21, X22, [SP, #32]

0x4ae70c LDP	X23, X24, [SP, #48]

0x4ae710 LDP	X25, X26, [SP, #64]

0x4ae714 LDP	X27, X28, [SP, #80]

0x4ae718 LDP	X29, X30, [SP], #208

0x4ae71c RET

(1912) 0x4ae720 LDR	D2, [X22, X5,LSL #3]

(1912) 0x4ae724 FCMPE	D2, D22

(1912) 0x4ae728 FADD	D23, D23, D2

(1912) 0x4ae72c FCSEL	D22, D22, D2, #12

(1912) 0x4ae730 B	4ae1bc

(1912) 0x4ae734 LDR	D17, [X22, X5,LSL #3]

(1912) 0x4ae738 FCMPE	D17, D22

(1912) 0x4ae73c FADD	D23, D23, D17

(1912) 0x4ae740 FCSEL	D22, D22, D17, #12

(1912) 0x4ae744 B	4ae1a8

(1912) 0x4ae748 LDR	D6, [X23, X5,LSL #3]

(1912) 0x4ae74c FCMPE	D6, D22

(1912) 0x4ae750 FADD	D23, D23, D6

(1912) 0x4ae754 FCSEL	D22, D22, D6, #12

(1912) 0x4ae758 B	4ae3dc

(1912) 0x4ae75c LDR	D7, [X23, X5,LSL #3]

(1912) 0x4ae760 FCMPE	D7, D22

(1912) 0x4ae764 FADD	D23, D23, D7

(1912) 0x4ae768 FCSEL	D22, D22, D7, #12

(1912) 0x4ae76c B	4ae3c8

  (1911) 0x4ae770 CMP	X30, X5

  (1911) 0x4ae774 B.LT	4ae6a0

(1908) 0x4ae778 B	4ae6c0

(1912) 0x4ae77c FCMPE	D4, #0

(1912) 0x4ae780 B.MI	4af124

(1912) 0x4ae784 CMP	X5, X9

(1912) 0x4ae788 B.GE	4af62c

(1912) 0x4ae78c ADD	X15, X22, X9,LSL #3

(1912) 0x4ae790 ADD	X18, X14, #8

(1912) 0x4ae794 FMOV	D3, D4

(1912) 0x4ae798 ADD	X5, X22, X18

(1912) 0x4ae79c MOVI	D23, #0

(1912) 0x4ae7a0 SUB	X27, X15, X5

(1912) 0x4ae7a4 SUB	X28, X27, #8

(1912) 0x4ae7a8 UBFM	X11, X28, #3, #63

(1912) 0x4ae7ac ADD	X27, X11, #1

(1912) 0x4ae7b0 ANDS	X28, X27, #0x7

(1912) 0x4ae7b4 B.EQ	4ae864

(1912) 0x4ae7b8 CMP	X28, #1

(1912) 0x4ae7bc B.EQ	4ae84c

(1912) 0x4ae7c0 CMP	X28, #2

(1912) 0x4ae7c4 B.EQ	4ae83c

(1912) 0x4ae7c8 CMP	X28, #3

(1912) 0x4ae7cc B.EQ	4ae82c

(1912) 0x4ae7d0 CMP	X28, #4

(1912) 0x4ae7d4 B.EQ	4ae81c

(1912) 0x4ae7d8 CMP	X28, #5

(1912) 0x4ae7dc B.EQ	4ae80c

(1912) 0x4ae7e0 CMP	X28, #6

(1912) 0x4ae7e4 B.EQ	4ae7fc

(1912) 0x4ae7e8 LDR	D18, [X22, X18]

(1912) 0x4ae7ec ADD	X5, X5, #8

(1912) 0x4ae7f0 FCMPE	D18, #0

(1912) 0x4ae7f4 FADD	D3, D4, D18

(1912) 0x4ae7f8 FCSEL	D23, D23, D18, #12

(1912) 0x4ae7fc LDR	D17, [X5], #8

(1912) 0x4ae800 FCMPE	D17, D23

(1912) 0x4ae804 FADD	D3, D3, D17

(1912) 0x4ae808 FCSEL	D23, D23, D17, #12

(1912) 0x4ae80c LDR	D16, [X5], #8

(1912) 0x4ae810 FCMPE	D16, D23

(1912) 0x4ae814 FADD	D3, D3, D16

(1912) 0x4ae818 FCSEL	D23, D23, D16, #12

(1912) 0x4ae81c LDR	D7, [X5], #8

(1912) 0x4ae820 FCMPE	D7, D23

(1912) 0x4ae824 FADD	D3, D3, D7

(1912) 0x4ae828 FCSEL	D23, D23, D7, #12

(1912) 0x4ae82c LDR	D6, [X5], #8

(1912) 0x4ae830 FCMPE	D6, D23

(1912) 0x4ae834 FADD	D3, D3, D6

(1912) 0x4ae838 FCSEL	D23, D23, D6, #12

(1912) 0x4ae83c LDR	D5, [X5], #8

(1912) 0x4ae840 FCMPE	D5, D23

(1912) 0x4ae844 FADD	D3, D3, D5

(1912) 0x4ae848 FCSEL	D23, D23, D5, #12

(1912) 0x4ae84c LDR	D2, [X5], #8

(1912) 0x4ae850 FCMPE	D2, D23

(1912) 0x4ae854 FADD	D3, D3, D2

(1912) 0x4ae858 FCSEL	D23, D23, D2, #12

(1912) 0x4ae85c CMP	X5, X15

(1912) 0x4ae860 B.EQ	4ae8ec

  (1922) 0x4ae864 ORR	X18, XZR, X5

  (1922) 0x4ae868 LDR	D27, [X5, #8]

  (1922) 0x4ae86c LDR	D1, [X18], #8

  (1922) 0x4ae870 LDP	D20, D19, [X5, #24]

  (1922) 0x4ae874 LDP	D22, D24, [X5, #40]

  (1922) 0x4ae878 ADD	X5, X5, #64

  (1922) 0x4ae87c FCMPE	D1, D23

  (1922) 0x4ae880 LDR	D29, [X18, #8]

  (1922) 0x4ae884 FADD	D0, D3, D1

  (1922) 0x4ae888 LDUR	D25, [X5, #504]

  (1922) 0x4ae88c FADD	D26, D0, D27

  (1922) 0x4ae890 FCSEL	D21, D23, D1, #12

  (1922) 0x4ae894 FCMPE	D27, D21

  (1922) 0x4ae898 FADD	D30, D26, D29

  (1922) 0x4ae89c FCSEL	D28, D21, D27, #12

  (1922) 0x4ae8a0 FADD	D18, D30, D20

  (1922) 0x4ae8a4 FCMPE	D29, D28

  (1922) 0x4ae8a8 FADD	D17, D18, D19

  (1922) 0x4ae8ac FCSEL	D16, D28, D29, #12

  (1922) 0x4ae8b0 FADD	D7, D17, D22

  (1922) 0x4ae8b4 FCMPE	D20, D16

  (1922) 0x4ae8b8 FADD	D6, D7, D24

  (1922) 0x4ae8bc FCSEL	D5, D16, D20, #12

  (1922) 0x4ae8c0 FADD	D3, D6, D25

  (1922) 0x4ae8c4 FCMPE	D19, D5

  (1922) 0x4ae8c8 FCSEL	D2, D5, D19, #12

  (1922) 0x4ae8cc FCMPE	D22, D2

  (1922) 0x4ae8d0 FCSEL	D23, D2, D22, #12

  (1922) 0x4ae8d4 FCMPE	D24, D23

  (1922) 0x4ae8d8 FCSEL	D1, D23, D24, #12

  (1922) 0x4ae8dc FCMPE	D25, D1

  (1922) 0x4ae8e0 FCSEL	D23, D1, D25, #12

  (1922) 0x4ae8e4 CMP	X5, X15

  (1922) 0x4ae8e8 B.NE	4ae864

(1912) 0x4ae8ec LDR	X18, [X3]

(1912) 0x4ae8f0 LDR	X15, [X12]

(1912) 0x4ae8f4 CMP	X15, X18

(1912) 0x4ae8f8 B.GE	4aea54

(1912) 0x4ae8fc ADD	X5, X23, X15,LSL #3

(1912) 0x4ae900 UBFM	X28, X15, #61, #60

(1912) 0x4ae904 ADD	X27, X23, X18,LSL #3

(1912) 0x4ae908 SUB	X11, X27, X5

(1912) 0x4ae90c SUB	X11, X11, #8

(1912) 0x4ae910 UBFM	X11, X11, #3, #63

(1912) 0x4ae914 ADD	X11, X11, #1

(1912) 0x4ae918 ANDS	X11, X11, #0x7

(1912) 0x4ae91c B.EQ	4ae9cc

(1912) 0x4ae920 CMP	X11, #1

(1912) 0x4ae924 B.EQ	4ae9b4

(1912) 0x4ae928 CMP	X11, #2

(1912) 0x4ae92c B.EQ	4ae9a4

(1912) 0x4ae930 CMP	X11, #3

(1912) 0x4ae934 B.EQ	4ae994

(1912) 0x4ae938 CMP	X11, #4

(1912) 0x4ae93c B.EQ	4ae984

(1912) 0x4ae940 CMP	X11, #5

(1912) 0x4ae944 B.EQ	4ae974

(1912) 0x4ae948 CMP	X11, #6

(1912) 0x4ae94c B.EQ	4ae964

(1912) 0x4ae950 LDR	D0, [X23, X28]

(1912) 0x4ae954 ADD	X5, X5, #8

(1912) 0x4ae958 FCMPE	D0, D23

(1912) 0x4ae95c FADD	D3, D3, D0

(1912) 0x4ae960 FCSEL	D23, D23, D0, #12

(1912) 0x4ae964 LDR	D21, [X5], #8

(1912) 0x4ae968 FCMPE	D21, D23

(1912) 0x4ae96c FADD	D3, D3, D21

(1912) 0x4ae970 FCSEL	D23, D23, D21, #12

(1912) 0x4ae974 LDR	D27, [X5], #8

(1912) 0x4ae978 FCMPE	D27, D23

(1912) 0x4ae97c FADD	D3, D3, D27

(1912) 0x4ae980 FCSEL	D23, D23, D27, #12

(1912) 0x4ae984 LDR	D20, [X5], #8

(1912) 0x4ae988 FCMPE	D20, D23

(1912) 0x4ae98c FADD	D3, D3, D20

(1912) 0x4ae990 FCSEL	D23, D23, D20, #12

(1912) 0x4ae994 LDR	D19, [X5], #8

(1912) 0x4ae998 FCMPE	D19, D23

(1912) 0x4ae99c FADD	D3, D3, D19

(1912) 0x4ae9a0 FCSEL	D23, D23, D19, #12

(1912) 0x4ae9a4 LDR	D22, [X5], #8

(1912) 0x4ae9a8 FCMPE	D22, D23

(1912) 0x4ae9ac FADD	D3, D3, D22

(1912) 0x4ae9b0 FCSEL	D23, D23, D22, #12

(1912) 0x4ae9b4 LDR	D24, [X5], #8

(1912) 0x4ae9b8 FCMPE	D24, D23

(1912) 0x4ae9bc FADD	D3, D3, D24

(1912) 0x4ae9c0 FCSEL	D23, D23, D24, #12

(1912) 0x4ae9c4 CMP	X27, X5

(1912) 0x4ae9c8 B.EQ	4aea54

  (1921) 0x4ae9cc ORR	X28, XZR, X5

  (1921) 0x4ae9d0 LDR	D28, [X5, #8]

  (1921) 0x4ae9d4 LDR	D25, [X28], #8

  (1921) 0x4ae9d8 LDP	D29, D30, [X5, #24]

  (1921) 0x4ae9dc LDP	D17, D16, [X5, #40]

  (1921) 0x4ae9e0 ADD	X5, X5, #64

  (1921) 0x4ae9e4 FCMPE	D25, D23

  (1921) 0x4ae9e8 LDR	D18, [X28, #8]

  (1921) 0x4ae9ec FADD	D3, D3, D25

  (1921) 0x4ae9f0 LDUR	D7, [X5, #504]

  (1921) 0x4ae9f4 FADD	D6, D3, D28

  (1921) 0x4ae9f8 FCSEL	D26, D23, D25, #12

  (1921) 0x4ae9fc FCMPE	D28, D26

  (1921) 0x4aea00 FADD	D2, D6, D18

  (1921) 0x4aea04 FCSEL	D5, D26, D28, #12

  (1921) 0x4aea08 FADD	D23, D2, D29

  (1921) 0x4aea0c FCMPE	D18, D5

  (1921) 0x4aea10 FADD	D1, D23, D30

  (1921) 0x4aea14 FCSEL	D0, D5, D18, #12

  (1921) 0x4aea18 FADD	D21, D1, D17

  (1921) 0x4aea1c FCMPE	D29, D0

  (1921) 0x4aea20 FADD	D27, D21, D16

  (1921) 0x4aea24 FCSEL	D20, D0, D29, #12

  (1921) 0x4aea28 FADD	D3, D27, D7

  (1921) 0x4aea2c FCMPE	D30, D20

  (1921) 0x4aea30 FCSEL	D19, D20, D30, #12

  (1921) 0x4aea34 FCMPE	D17, D19

  (1921) 0x4aea38 FCSEL	D22, D19, D17, #12

  (1921) 0x4aea3c FCMPE	D16, D22

  (1921) 0x4aea40 FCSEL	D24, D22, D16, #12

  (1921) 0x4aea44 FCMPE	D7, D24

  (1921) 0x4aea48 FCSEL	D23, D24, D7, #12

  (1921) 0x4aea4c CMP	X27, X5

  (1921) 0x4aea50 B.NE	4ae9cc

(1912) 0x4aea54 FABS	D4, D4

(1912) 0x4aea58 FABS	D25, D3

(1912) 0x4aea5c SUB	X6, X9, X6

(1912) 0x4aea60 SUB	X9, X18, X15

(1912) 0x4aea64 STR	X13, [X19, X14]

(1912) 0x4aea68 SUB	X14, X6, #1

(1912) 0x4aea6c LDP	X18, X15, [X0, #1016]

(1912) 0x4aea70 ADD	X2, X2, X9

(1912) 0x4aea74 ADD	X1, X1, X14

(1912) 0x4aea78 FMUL	D3, D4, D15

(1912) 0x4aea7c ADD	X27, X18, #1

(1912) 0x4aea80 FCMPE	D3, D25

(1912) 0x4aea84 B.MI	4af4e0

(1912) 0x4aea88 CMP	X27, X15

(1912) 0x4aea8c B.GE	4aeac4

(1912) 0x4aea90 FMUL	D26, D14, D23

(1912) 0x4aea94 HINT	#0

(1912) 0x4aea98 HINT	#0

(1912) 0x4aea9c HINT	#0

  (1920) 0x4aeaa0 LDR	D28, [X22, X27,LSL #3]

  (1920) 0x4aeaa4 FCMPE	D28, D26

  (1920) 0x4aeaa8 B.GE	4aeb20

  (1920) 0x4aeaac LDR	X11, [X25, X27,LSL #3]

  (1920) 0x4aeab0 STR	X11, [X19, X27,LSL #3]

  (1920) 0x4aeab4 ADD	X27, X27, #1

  (1920) 0x4aeab8 LDR	X5, [X0]

  (1920) 0x4aeabc CMP	X5, X27

  (1920) 0x4aeac0 B.GT	4aeaa0

(1912) 0x4aeac4 LDR	X6, [X3]

(1912) 0x4aeac8 LDR	X18, [X12]

(1912) 0x4aeacc CMP	X18, X6

(1912) 0x4aead0 B.GE	4ae60c

(1912) 0x4aead4 FMUL	D29, D14, D23

(1912) 0x4aead8 HINT	#0

(1912) 0x4aeadc HINT	#0

  (1919) 0x4aeae0 LDR	D30, [X23, X18,LSL #3]

  (1919) 0x4aeae4 FCMPE	D29, D30

  (1919) 0x4aeae8 B.LS	4aeb3c

  (1919) 0x4aeaec LDR	X9, [X24, X18,LSL #3]

  (1919) 0x4aeaf0 STR	X9, [X20, X18,LSL #3]

  (1919) 0x4aeaf4 ADD	X18, X18, #1

  (1919) 0x4aeaf8 LDR	X14, [X3]

  (1919) 0x4aeafc CMP	X14, X18

  (1919) 0x4aeb00 B.GT	4aeae0

(1912) 0x4aeb04 ADD	X4, X4, #1

(1912) 0x4aeb08 ADD	X12, X12, #8

(1912) 0x4aeb0c ADD	X3, X3, #8

(1912) 0x4aeb10 ADD	X0, X0, #8

(1912) 0x4aeb14 CMP	X4, X30

(1912) 0x4aeb18 B.NE	4ae0cc

0x4aeb1c B	4ae624

  (1920) 0x4aeb20 STR	X13, [X19, X27,LSL #3]

  (1920) 0x4aeb24 ADD	X27, X27, #1

  (1920) 0x4aeb28 SUB	X1, X1, #1

  (1920) 0x4aeb2c LDR	X28, [X0]

  (1920) 0x4aeb30 CMP	X27, X28

  (1920) 0x4aeb34 B.LT	4aeaa0

(1912) 0x4aeb38 B	4aeac4

  (1919) 0x4aeb3c STR	X13, [X20, X18,LSL #3]

  (1919) 0x4aeb40 ADD	X18, X18, #1

  (1919) 0x4aeb44 SUB	X2, X2, #1

  (1919) 0x4aeb48 LDR	X15, [X3]

  (1919) 0x4aeb4c CMP	X18, X15

  (1919) 0x4aeb50 B.LT	4aeae0

(1912) 0x4aeb54 ADD	X4, X4, #1

(1912) 0x4aeb58 ADD	X12, X12, #8

(1912) 0x4aeb5c ADD	X3, X3, #8

(1912) 0x4aeb60 ADD	X0, X0, #8

(1912) 0x4aeb64 CMP	X4, X30

(1912) 0x4aeb68 B.NE	4ae0cc

0x4aeb6c B	4ae624

(1912) 0x4aeb70 CMP	X5, X9

(1912) 0x4aeb74 B.GE	4af620

(1912) 0x4aeb78 SUB	X28, X9, X5

(1912) 0x4aeb7c LDR	X11, [X21, X4,LSL #3]

(1912) 0x4aeb80 FMOV	D18, D4

(1912) 0x4aeb84 ANDS	X27, X28, #0x7

(1912) 0x4aeb88 MOVI	D24, #0

(1912) 0x4aeb8c B.EQ	4aec64

(1912) 0x4aeb90 CMP	X27, #1

(1912) 0x4aeb94 B.EQ	4aec38

(1912) 0x4aeb98 CMP	X27, #2

(1912) 0x4aeb9c B.EQ	4aec24

(1912) 0x4aeba0 CMP	X27, #3

(1912) 0x4aeba4 B.EQ	4aec10

(1912) 0x4aeba8 CMP	X27, #4

(1912) 0x4aebac B.EQ	4aebfc

(1912) 0x4aebb0 CMP	X27, #5

(1912) 0x4aebb4 B.EQ	4aebe8

(1912) 0x4aebb8 CMP	X27, #6

(1912) 0x4aebbc B.EQ	4aebd4

(1912) 0x4aebc0 LDR	X18, [X25, X5,LSL #3]

(1912) 0x4aebc4 LDR	X15, [X21, X18,LSL #3]

(1912) 0x4aebc8 CMP	X11, X15

(1912) 0x4aebcc B.EQ	4af6c8

(1912) 0x4aebd0 ADD	X5, X5, #1

(1912) 0x4aebd4 LDR	X28, [X25, X5,LSL #3]

(1912) 0x4aebd8 LDR	X27, [X21, X28,LSL #3]

(1912) 0x4aebdc CMP	X11, X27

(1912) 0x4aebe0 B.EQ	4af680

(1912) 0x4aebe4 ADD	X5, X5, #1

(1912) 0x4aebe8 LDR	X18, [X25, X5,LSL #3]

(1912) 0x4aebec LDR	X15, [X21, X18,LSL #3]

(1912) 0x4aebf0 CMP	X11, X15

(1912) 0x4aebf4 B.EQ	4af5c4

(1912) 0x4aebf8 ADD	X5, X5, #1

(1912) 0x4aebfc LDR	X28, [X25, X5,LSL #3]

(1912) 0x4aec00 LDR	X27, [X21, X28,LSL #3]

(1912) 0x4aec04 CMP	X11, X27

(1912) 0x4aec08 B.EQ	4af5b0

(1912) 0x4aec0c ADD	X5, X5, #1

(1912) 0x4aec10 LDR	X18, [X25, X5,LSL #3]

(1912) 0x4aec14 LDR	X15, [X21, X18,LSL #3]

(1912) 0x4aec18 CMP	X11, X15

(1912) 0x4aec1c B.EQ	4af54c

(1912) 0x4aec20 ADD	X5, X5, #1

(1912) 0x4aec24 LDR	X28, [X25, X5,LSL #3]

(1912) 0x4aec28 LDR	X27, [X21, X28,LSL #3]

(1912) 0x4aec2c CMP	X11, X27

(1912) 0x4aec30 B.EQ	4af510

(1912) 0x4aec34 ADD	X5, X5, #1

(1912) 0x4aec38 LDR	X18, [X25, X5,LSL #3]

(1912) 0x4aec3c LDR	X15, [X21, X18,LSL #3]

(1912) 0x4aec40 CMP	X11, X15

(1912) 0x4aec44 B.NE	4aec58

(1912) 0x4aec48 LDR	D6, [X22, X5,LSL #3]

(1912) 0x4aec4c FCMPE	D6, D24

(1912) 0x4aec50 FADD	D18, D18, D6

(1912) 0x4aec54 FCSEL	D24, D6, D24, #12

(1912) 0x4aec58 ADD	X5, X5, #1

(1912) 0x4aec5c CMP	X5, X9

(1912) 0x4aec60 B.EQ	4aed8c

  (1926) 0x4aec64 LDR	X28, [X25, X5,LSL #3]

  (1926) 0x4aec68 LDR	X27, [X21, X28,LSL #3]

  (1926) 0x4aec6c CMP	X11, X27

  (1926) 0x4aec70 B.NE	4aec84

  (1926) 0x4aec74 LDR	D5, [X22, X5,LSL #3]

  (1926) 0x4aec78 FCMPE	D5, D24

  (1926) 0x4aec7c FADD	D18, D18, D5

  (1926) 0x4aec80 FCSEL	D24, D5, D24, #12

  (1926) 0x4aec84 ADD	X5, X5, #1

  (1926) 0x4aec88 LDR	X18, [X25, X5,LSL #3]

  (1926) 0x4aec8c LDR	X15, [X21, X18,LSL #3]

  (1926) 0x4aec90 CMP	X11, X15

  (1926) 0x4aec94 B.NE	4aeca8

  (1926) 0x4aec98 LDR	D27, [X22, X5,LSL #3]

  (1926) 0x4aec9c FCMPE	D27, D24

  (1926) 0x4aeca0 FADD	D18, D18, D27

  (1926) 0x4aeca4 FCSEL	D24, D27, D24, #12

  (1926) 0x4aeca8 ADD	X28, X5, #1

  (1926) 0x4aecac LDR	X27, [X25, X28,LSL #3]

  (1926) 0x4aecb0 LDR	X18, [X21, X27,LSL #3]

  (1926) 0x4aecb4 CMP	X11, X18

  (1926) 0x4aecb8 B.NE	4aeccc

  (1926) 0x4aecbc LDR	D17, [X22, X28,LSL #3]

  (1926) 0x4aecc0 FCMPE	D17, D24

  (1926) 0x4aecc4 FADD	D18, D18, D17

  (1926) 0x4aecc8 FCSEL	D24, D17, D24, #12

  (1926) 0x4aeccc ADD	X15, X5, #2

  (1926) 0x4aecd0 LDR	X28, [X25, X15,LSL #3]

  (1926) 0x4aecd4 LDR	X27, [X21, X28,LSL #3]

  (1926) 0x4aecd8 CMP	X11, X27

  (1926) 0x4aecdc B.NE	4aecf0

  (1926) 0x4aece0 LDR	D2, [X22, X15,LSL #3]

  (1926) 0x4aece4 FCMPE	D2, D24

  (1926) 0x4aece8 FADD	D18, D18, D2

  (1926) 0x4aecec FCSEL	D24, D2, D24, #12

  (1926) 0x4aecf0 ADD	X15, X5, #3

  (1926) 0x4aecf4 LDR	X18, [X25, X15,LSL #3]

  (1926) 0x4aecf8 LDR	X28, [X21, X18,LSL #3]

  (1926) 0x4aecfc CMP	X11, X28

  (1926) 0x4aed00 B.NE	4aed14

  (1926) 0x4aed04 LDR	D21, [X22, X15,LSL #3]

  (1926) 0x4aed08 FCMPE	D21, D24

  (1926) 0x4aed0c FADD	D18, D18, D21

  (1926) 0x4aed10 FCSEL	D24, D21, D24, #12

  (1926) 0x4aed14 ADD	X27, X5, #4

  (1926) 0x4aed18 LDR	X15, [X25, X27,LSL #3]

  (1926) 0x4aed1c LDR	X18, [X21, X15,LSL #3]

  (1926) 0x4aed20 CMP	X11, X18

  (1926) 0x4aed24 B.NE	4aed38

  (1926) 0x4aed28 LDR	D1, [X22, X27,LSL #3]

  (1926) 0x4aed2c FCMPE	D1, D24

  (1926) 0x4aed30 FADD	D18, D18, D1

  (1926) 0x4aed34 FCSEL	D24, D1, D24, #12

  (1926) 0x4aed38 ADD	X28, X5, #5

  (1926) 0x4aed3c LDR	X27, [X25, X28,LSL #3]

  (1926) 0x4aed40 LDR	X15, [X21, X27,LSL #3]

  (1926) 0x4aed44 CMP	X11, X15

  (1926) 0x4aed48 B.NE	4aed5c

  (1926) 0x4aed4c LDR	D0, [X22, X28,LSL #3]

  (1926) 0x4aed50 FCMPE	D0, D24

  (1926) 0x4aed54 FADD	D18, D18, D0

  (1926) 0x4aed58 FCSEL	D24, D0, D24, #12

  (1926) 0x4aed5c ADD	X28, X5, #6

  (1926) 0x4aed60 LDR	X18, [X25, X28,LSL #3]

  (1926) 0x4aed64 LDR	X27, [X21, X18,LSL #3]

  (1926) 0x4aed68 CMP	X11, X27

  (1926) 0x4aed6c B.NE	4aed80

  (1926) 0x4aed70 LDR	D20, [X22, X28,LSL #3]

  (1926) 0x4aed74 FCMPE	D20, D24

  (1926) 0x4aed78 FADD	D18, D18, D20

  (1926) 0x4aed7c FCSEL	D24, D20, D24, #12

  (1926) 0x4aed80 ADD	X5, X5, #7

  (1926) 0x4aed84 CMP	X5, X9

  (1926) 0x4aed88 B.NE	4aec64

(1912) 0x4aed8c LDR	X18, [X3]

(1912) 0x4aed90 LDR	X15, [X12]

(1912) 0x4aed94 CMP	X15, X18

(1912) 0x4aed98 B.GE	4aefac

(1912) 0x4aed9c SUB	X28, X18, X15

(1912) 0x4aeda0 LDR	X11, [X21, X4,LSL #3]

(1912) 0x4aeda4 ORR	X5, XZR, X15

(1912) 0x4aeda8 ANDS	X27, X28, #0x7

(1912) 0x4aedac B.EQ	4aee84

(1912) 0x4aedb0 CMP	X27, #1

(1912) 0x4aedb4 B.EQ	4aee58

(1912) 0x4aedb8 CMP	X27, #2

(1912) 0x4aedbc B.EQ	4aee44

(1912) 0x4aedc0 CMP	X27, #3

(1912) 0x4aedc4 B.EQ	4aee30

(1912) 0x4aedc8 CMP	X27, #4

(1912) 0x4aedcc B.EQ	4aee1c

(1912) 0x4aedd0 CMP	X27, #5

(1912) 0x4aedd4 B.EQ	4aee08

(1912) 0x4aedd8 CMP	X27, #6

(1912) 0x4aeddc B.EQ	4aedf4

(1912) 0x4aede0 LDR	X5, [X24, X15,LSL #3]

(1912) 0x4aede4 LDR	X28, [X26, X5,LSL #3]

(1912) 0x4aede8 CMP	X11, X28

(1912) 0x4aedec B.EQ	4af6dc

(1912) 0x4aedf0 ADD	X5, X15, #1

(1912) 0x4aedf4 LDR	X27, [X24, X5,LSL #3]

(1912) 0x4aedf8 LDR	X28, [X26, X27,LSL #3]

(1912) 0x4aedfc CMP	X11, X28

(1912) 0x4aee00 B.EQ	4af668

(1912) 0x4aee04 ADD	X5, X5, #1

(1912) 0x4aee08 LDR	X27, [X24, X5,LSL #3]

(1912) 0x4aee0c LDR	X28, [X26, X27,LSL #3]

(1912) 0x4aee10 CMP	X11, X28

(1912) 0x4aee14 B.EQ	4af5d8

(1912) 0x4aee18 ADD	X5, X5, #1

(1912) 0x4aee1c LDR	X27, [X24, X5,LSL #3]

(1912) 0x4aee20 LDR	X28, [X26, X27,LSL #3]

(1912) 0x4aee24 CMP	X11, X28

(1912) 0x4aee28 B.EQ	4af59c

(1912) 0x4aee2c ADD	X5, X5, #1

(1912) 0x4aee30 LDR	X27, [X24, X5,LSL #3]

(1912) 0x4aee34 LDR	X28, [X26, X27,LSL #3]

(1912) 0x4aee38 CMP	X11, X28

(1912) 0x4aee3c B.EQ	4af560

(1912) 0x4aee40 ADD	X5, X5, #1

(1912) 0x4aee44 LDR	X27, [X24, X5,LSL #3]

(1912) 0x4aee48 LDR	X28, [X26, X27,LSL #3]

(1912) 0x4aee4c CMP	X11, X28

(1912) 0x4aee50 B.EQ	4af4fc

(1912) 0x4aee54 ADD	X5, X5, #1

(1912) 0x4aee58 LDR	X27, [X24, X5,LSL #3]

(1912) 0x4aee5c LDR	X28, [X26, X27,LSL #3]

(1912) 0x4aee60 CMP	X11, X28

(1912) 0x4aee64 B.NE	4aee78

(1912) 0x4aee68 LDR	D26, [X23, X5,LSL #3]

(1912) 0x4aee6c FCMPE	D26, D24

(1912) 0x4aee70 FADD	D18, D18, D26

(1912) 0x4aee74 FCSEL	D24, D26, D24, #12

(1912) 0x4aee78 ADD	X5, X5, #1

(1912) 0x4aee7c CMP	X5, X18

(1912) 0x4aee80 B.EQ	4aefac

  (1925) 0x4aee84 LDR	X27, [X24, X5,LSL #3]

  (1925) 0x4aee88 LDR	X28, [X26, X27,LSL #3]

  (1925) 0x4aee8c CMP	X11, X28

  (1925) 0x4aee90 B.NE	4aeea4

  (1925) 0x4aee94 LDR	D3, [X23, X5,LSL #3]

  (1925) 0x4aee98 FCMPE	D3, D24

  (1925) 0x4aee9c FADD	D18, D18, D3

  (1925) 0x4aeea0 FCSEL	D24, D3, D24, #12

  (1925) 0x4aeea4 ADD	X5, X5, #1

  (1925) 0x4aeea8 LDR	X27, [X24, X5,LSL #3]

  (1925) 0x4aeeac LDR	X28, [X26, X27,LSL #3]

  (1925) 0x4aeeb0 CMP	X11, X28

  (1925) 0x4aeeb4 B.NE	4aeec8

  (1925) 0x4aeeb8 LDR	D30, [X23, X5,LSL #3]

  (1925) 0x4aeebc FCMPE	D30, D24

  (1925) 0x4aeec0 FADD	D18, D18, D30

  (1925) 0x4aeec4 FCSEL	D24, D30, D24, #12

  (1925) 0x4aeec8 ADD	X27, X5, #1

  (1925) 0x4aeecc LDR	X28, [X24, X27,LSL #3]

  (1925) 0x4aeed0 LDR	X28, [X26, X28,LSL #3]

  (1925) 0x4aeed4 CMP	X11, X28

  (1925) 0x4aeed8 B.NE	4aeeec

  (1925) 0x4aeedc LDR	D16, [X23, X27,LSL #3]

  (1925) 0x4aeee0 FCMPE	D16, D24

  (1925) 0x4aeee4 FADD	D18, D18, D16

  (1925) 0x4aeee8 FCSEL	D24, D16, D24, #12

  (1925) 0x4aeeec ADD	X27, X5, #2

  (1925) 0x4aeef0 LDR	X28, [X24, X27,LSL #3]

  (1925) 0x4aeef4 LDR	X28, [X26, X28,LSL #3]

  (1925) 0x4aeef8 CMP	X11, X28

  (1925) 0x4aeefc B.NE	4aef10

  (1925) 0x4aef00 LDR	D7, [X23, X27,LSL #3]

  (1925) 0x4aef04 FCMPE	D7, D24

  (1925) 0x4aef08 FADD	D18, D18, D7

  (1925) 0x4aef0c FCSEL	D24, D7, D24, #12

  (1925) 0x4aef10 ADD	X27, X5, #3

  (1925) 0x4aef14 LDR	X28, [X24, X27,LSL #3]

  (1925) 0x4aef18 LDR	X28, [X26, X28,LSL #3]

  (1925) 0x4aef1c CMP	X11, X28

  (1925) 0x4aef20 B.NE	4aef34

  (1925) 0x4aef24 LDR	D6, [X23, X27,LSL #3]

  (1925) 0x4aef28 FCMPE	D6, D24

  (1925) 0x4aef2c FADD	D18, D18, D6

  (1925) 0x4aef30 FCSEL	D24, D6, D24, #12

  (1925) 0x4aef34 ADD	X27, X5, #4

  (1925) 0x4aef38 LDR	X28, [X24, X27,LSL #3]

  (1925) 0x4aef3c LDR	X28, [X26, X28,LSL #3]

  (1925) 0x4aef40 CMP	X11, X28

  (1925) 0x4aef44 B.NE	4aef58

  (1925) 0x4aef48 LDR	D5, [X23, X27,LSL #3]

  (1925) 0x4aef4c FCMPE	D5, D24

  (1925) 0x4aef50 FADD	D18, D18, D5

  (1925) 0x4aef54 FCSEL	D24, D5, D24, #12

  (1925) 0x4aef58 ADD	X27, X5, #5

  (1925) 0x4aef5c LDR	X28, [X24, X27,LSL #3]

  (1925) 0x4aef60 LDR	X28, [X26, X28,LSL #3]

  (1925) 0x4aef64 CMP	X11, X28

  (1925) 0x4aef68 B.NE	4aef7c

  (1925) 0x4aef6c LDR	D27, [X23, X27,LSL #3]

  (1925) 0x4aef70 FCMPE	D27, D24

  (1925) 0x4aef74 FADD	D18, D18, D27

  (1925) 0x4aef78 FCSEL	D24, D27, D24, #12

  (1925) 0x4aef7c ADD	X27, X5, #6

  (1925) 0x4aef80 LDR	X28, [X24, X27,LSL #3]

  (1925) 0x4aef84 LDR	X28, [X26, X28,LSL #3]

  (1925) 0x4aef88 CMP	X11, X28

  (1925) 0x4aef8c B.NE	4aefa0

  (1925) 0x4aef90 LDR	D17, [X23, X27,LSL #3]

  (1925) 0x4aef94 FCMPE	D17, D24

  (1925) 0x4aef98 FADD	D18, D18, D17

  (1925) 0x4aef9c FCSEL	D24, D17, D24, #12

  (1925) 0x4aefa0 ADD	X5, X5, #7

  (1925) 0x4aefa4 CMP	X5, X18

  (1925) 0x4aefa8 B.NE	4aee84

(1912) 0x4aefac FABS	D4, D4

(1912) 0x4aefb0 FABS	D2, D18

(1912) 0x4aefb4 STR	X13, [X19, X14]

(1912) 0x4aefb8 SUB	X14, X18, X15

(1912) 0x4aefbc LDP	X18, X15, [X0, #1016]

(1912) 0x4aefc0 SUB	X9, X9, X6

(1912) 0x4aefc4 SUB	X6, X9, #1

(1912) 0x4aefc8 ADD	X2, X2, X14

(1912) 0x4aefcc ADD	X1, X1, X6

(1912) 0x4aefd0 FMUL	D21, D4, D15

(1912) 0x4aefd4 ADD	X27, X18, #1

(1912) 0x4aefd8 FCMPE	D21, D2

(1912) 0x4aefdc B.MI	4af4d4

(1912) 0x4aefe0 CMP	X15, X27

(1912) 0x4aefe4 B.LE	4af028

(1912) 0x4aefe8 FMUL	D1, D14, D24

  (1924) 0x4aefec LDR	D0, [X22, X27,LSL #3]

  (1924) 0x4aeff0 FCMPE	D1, D0

  (1924) 0x4aeff4 B.GE	4af00c

  (1924) 0x4aeff8 LDR	X28, [X25, X27,LSL #3]

  (1924) 0x4aeffc LDR	X15, [X21, X4,LSL #3]

  (1924) 0x4af000 LDR	X11, [X21, X28,LSL #3]

  (1924) 0x4af004 CMP	X11, X15

  (1924) 0x4af008 B.EQ	4af014

  (1924) 0x4af00c SUB	X1, X1, #1

  (1924) 0x4af010 MOVN	X28, #0

  (1924) 0x4af014 STR	X28, [X19, X27,LSL #3]

  (1924) 0x4af018 ADD	X27, X27, #1

  (1924) 0x4af01c LDR	X5, [X0]

  (1924) 0x4af020 CMP	X5, X27

  (1924) 0x4af024 B.GT	4aefec

(1912) 0x4af028 LDR	X27, [X3]

(1912) 0x4af02c LDR	X18, [X12]

(1912) 0x4af030 CMP	X18, X27

(1912) 0x4af034 B.GE	4ae60c

(1912) 0x4af038 FMUL	D20, D14, D24

(1912) 0x4af03c HINT	#0

  (1923) 0x4af040 LDR	D18, [X23, X18,LSL #3]

  (1923) 0x4af044 FCMPE	D20, D18

  (1923) 0x4af048 B.GE	4af060

  (1923) 0x4af04c LDR	X6, [X24, X18,LSL #3]

  (1923) 0x4af050 LDR	X9, [X21, X4,LSL #3]

  (1923) 0x4af054 LDR	X14, [X26, X6,LSL #3]

  (1923) 0x4af058 CMP	X14, X9

  (1923) 0x4af05c B.EQ	4af068

  (1923) 0x4af060 SUB	X2, X2, #1

  (1923) 0x4af064 MOVN	X6, #0

  (1923) 0x4af068 STR	X6, [X20, X18,LSL #3]

  (1923) 0x4af06c ADD	X18, X18, #1

  (1923) 0x4af070 LDR	X15, [X3]

  (1923) 0x4af074 CMP	X15, X18

  (1923) 0x4af078 B.GT	4af040

(1912) 0x4af07c ADD	X4, X4, #1

(1912) 0x4af080 ADD	X12, X12, #8

(1912) 0x4af084 ADD	X3, X3, #8

(1912) 0x4af088 ADD	X0, X0, #8

(1912) 0x4af08c CMP	X4, X30

(1912) 0x4af090 B.NE	4ae0cc

0x4af094 B	4ae624

(1912) 0x4af098 FCMPE	D15, D31

(1912) 0x4af09c B.MI	4af0a4

(1912) 0x4af0a0 B	4ae568

(1912) 0x4af0a4 MOVN	X11, #0

(1912) 0x4af0a8 CMP	X27, X15

(1912) 0x4af0ac B.GE	4af0cc

  (1914) 0x4af0b0 STR	X11, [X19, X27,LSL #3]

  (1914) 0x4af0b4 ADD	X27, X27, #1

  (1914) 0x4af0b8 LDR	X15, [X0]

  (1914) 0x4af0bc CMP	X15, X27

  (1914) 0x4af0c0 B.GT	4af0b0

(1912) 0x4af0c4 LDUR	X28, [X0, #504]

(1912) 0x4af0c8 ADD	X27, X28, #1

(1912) 0x4af0cc LDR	X9, [X3]

(1912) 0x4af0d0 SUB	X5, X15, X27

(1912) 0x4af0d4 MOVN	X27, #0

(1912) 0x4af0d8 SUB	X1, X1, X5

(1912) 0x4af0dc LDR	X14, [X12]

(1912) 0x4af0e0 CMP	X14, X9

(1912) 0x4af0e4 B.GE	4af100

  (1913) 0x4af0e8 STR	X27, [X20, X14,LSL #3]

  (1913) 0x4af0ec ADD	X14, X14, #1

  (1913) 0x4af0f0 LDR	X9, [X3]

  (1913) 0x4af0f4 CMP	X9, X14

  (1913) 0x4af0f8 B.GT	4af0e8

(1912) 0x4af0fc LDR	X14, [X12]

(1912) 0x4af100 SUB	X6, X9, X14

(1912) 0x4af104 ADD	X4, X4, #1

(1912) 0x4af108 SUB	X2, X2, X6

(1912) 0x4af10c ADD	X12, X12, #8

(1912) 0x4af110 ADD	X3, X3, #8

(1912) 0x4af114 ADD	X0, X0, #8

(1912) 0x4af118 CMP	X4, X30

(1912) 0x4af11c B.NE	4ae0cc

0x4af120 B	4ae624

(1912) 0x4af124 CMP	X5, X9

(1912) 0x4af128 B.GE	4af6f0

(1912) 0x4af12c ADD	X28, X22, X9,LSL #3

(1912) 0x4af130 ADD	X27, X14, #8

(1912) 0x4af134 FMOV	D23, D4

(1912) 0x4af138 ADD	X5, X22, X27

(1912) 0x4af13c MOVI	D21, #0

(1912) 0x4af140 SUB	X11, X28, X5

(1912) 0x4af144 SUB	X18, X11, #8

(1912) 0x4af148 UBFM	X15, X18, #3, #63

(1912) 0x4af14c ADD	X11, X15, #1

(1912) 0x4af150 ANDS	X18, X11, #0x7

(1912) 0x4af154 B.EQ	4af1f0

(1912) 0x4af158 CMP	X18, #1

(1912) 0x4af15c B.EQ	4af1d8

(1912) 0x4af160 CMP	X18, #2

(1912) 0x4af164 B.EQ	4af1c8

(1912) 0x4af168 CMP	X18, #3

(1912) 0x4af16c B.EQ	4af1b8

(1912) 0x4af170 CMP	X18, #4

(1912) 0x4af174 B.EQ	4af1a8

(1912) 0x4af178 CMP	X18, #5

(1912) 0x4af17c B.EQ	4af198

(1912) 0x4af180 CMP	X18, #6

(1912) 0x4af184 B.NE	4af638

(1912) 0x4af188 LDR	D16, [X5], #8

(1912) 0x4af18c FCMPE	D16, D21

(1912) 0x4af190 FADD	D23, D23, D16

(1912) 0x4af194 FCSEL	D21, D16, D21, #12

(1912) 0x4af198 LDR	D7, [X5], #8

(1912) 0x4af19c FCMPE	D7, D21

(1912) 0x4af1a0 FADD	D23, D23, D7

(1912) 0x4af1a4 FCSEL	D21, D7, D21, #12

(1912) 0x4af1a8 LDR	D6, [X5], #8

(1912) 0x4af1ac FCMPE	D6, D21

(1912) 0x4af1b0 FADD	D23, D23, D6

(1912) 0x4af1b4 FCSEL	D21, D6, D21, #12

(1912) 0x4af1b8 LDR	D5, [X5], #8

(1912) 0x4af1bc FCMPE	D5, D21

(1912) 0x4af1c0 FADD	D23, D23, D5

(1912) 0x4af1c4 FCSEL	D21, D5, D21, #12

(1912) 0x4af1c8 LDR	D18, [X5], #8

(1912) 0x4af1cc FCMPE	D18, D21

(1912) 0x4af1d0 FADD	D23, D23, D18

(1912) 0x4af1d4 FCSEL	D21, D18, D21, #12

(1912) 0x4af1d8 LDR	D2, [X5], #8

(1912) 0x4af1dc FCMPE	D2, D21

(1912) 0x4af1e0 FADD	D23, D23, D2

(1912) 0x4af1e4 FCSEL	D21, D2, D21, #12

(1912) 0x4af1e8 CMP	X5, X28

(1912) 0x4af1ec B.EQ	4af278

  (1918) 0x4af1f0 ORR	X27, XZR, X5

  (1918) 0x4af1f4 LDR	D19, [X5, #8]

  (1918) 0x4af1f8 LDR	D1, [X27], #8

  (1918) 0x4af1fc LDP	D22, D24, [X5, #24]

  (1918) 0x4af200 LDP	D25, D28, [X5, #40]

  (1918) 0x4af204 ADD	X5, X5, #64

  (1918) 0x4af208 FCMPE	D1, D21

  (1918) 0x4af20c LDR	D3, [X27, #8]

  (1918) 0x4af210 FADD	D0, D23, D1

  (1918) 0x4af214 LDUR	D29, [X5, #504]

  (1918) 0x4af218 FADD	D27, D0, D19

  (1918) 0x4af21c FCSEL	D20, D1, D21, #12

  (1918) 0x4af220 FCMPE	D19, D20

  (1918) 0x4af224 FADD	D30, D27, D3

  (1918) 0x4af228 FCSEL	D26, D19, D20, #12

  (1918) 0x4af22c FADD	D17, D30, D22

  (1918) 0x4af230 FCMPE	D3, D26

  (1918) 0x4af234 FADD	D16, D17, D24

  (1918) 0x4af238 FCSEL	D7, D3, D26, #12

  (1918) 0x4af23c FADD	D6, D16, D25

  (1918) 0x4af240 FCMPE	D22, D7

  (1918) 0x4af244 FADD	D5, D6, D28

  (1918) 0x4af248 FCSEL	D18, D22, D7, #12

  (1918) 0x4af24c FADD	D23, D5, D29

  (1918) 0x4af250 FCMPE	D24, D18

  (1918) 0x4af254 FCSEL	D2, D24, D18, #12

  (1918) 0x4af258 FCMPE	D25, D2

  (1918) 0x4af25c FCSEL	D21, D25, D2, #12

  (1918) 0x4af260 FCMPE	D28, D21

  (1918) 0x4af264 FCSEL	D1, D28, D21, #12

  (1918) 0x4af268 FCMPE	D29, D1

  (1918) 0x4af26c FCSEL	D21, D29, D1, #12

  (1918) 0x4af270 CMP	X5, X28

  (1918) 0x4af274 B.NE	4af1f0

(1912) 0x4af278 LDR	X18, [X3]

(1912) 0x4af27c LDR	X15, [X12]

(1912) 0x4af280 CMP	X15, X18

(1912) 0x4af284 B.GE	4af3cc

(1912) 0x4af288 ADD	X5, X23, X15,LSL #3

(1912) 0x4af28c UBFM	X28, X15, #61, #60

(1912) 0x4af290 ADD	X27, X23, X18,LSL #3

(1912) 0x4af294 SUB	X11, X27, X5

(1912) 0x4af298 SUB	X11, X11, #8

(1912) 0x4af29c UBFM	X11, X11, #3, #63

(1912) 0x4af2a0 ADD	X11, X11, #1

(1912) 0x4af2a4 ANDS	X11, X11, #0x7

(1912) 0x4af2a8 B.EQ	4af344

(1912) 0x4af2ac CMP	X11, #1

(1912) 0x4af2b0 B.EQ	4af32c

(1912) 0x4af2b4 CMP	X11, #2

(1912) 0x4af2b8 B.EQ	4af31c

(1912) 0x4af2bc CMP	X11, #3

(1912) 0x4af2c0 B.EQ	4af30c

(1912) 0x4af2c4 CMP	X11, #4

(1912) 0x4af2c8 B.EQ	4af2fc

(1912) 0x4af2cc CMP	X11, #5

(1912) 0x4af2d0 B.EQ	4af2ec

(1912) 0x4af2d4 CMP	X11, #6

(1912) 0x4af2d8 B.NE	4af650

(1912) 0x4af2dc LDR	D20, [X5], #8

(1912) 0x4af2e0 FCMPE	D20, D21

(1912) 0x4af2e4 FADD	D23, D23, D20

(1912) 0x4af2e8 FCSEL	D21, D20, D21, #12

(1912) 0x4af2ec LDR	D19, [X5], #8

(1912) 0x4af2f0 FCMPE	D19, D21

(1912) 0x4af2f4 FADD	D23, D23, D19

(1912) 0x4af2f8 FCSEL	D21, D19, D21, #12

(1912) 0x4af2fc LDR	D22, [X5], #8

(1912) 0x4af300 FCMPE	D22, D21

(1912) 0x4af304 FADD	D23, D23, D22

(1912) 0x4af308 FCSEL	D21, D22, D21, #12

(1912) 0x4af30c LDR	D24, [X5], #8

(1912) 0x4af310 FCMPE	D24, D21

(1912) 0x4af314 FADD	D23, D23, D24

(1912) 0x4af318 FCSEL	D21, D24, D21, #12

(1912) 0x4af31c LDR	D25, [X5], #8

(1912) 0x4af320 FCMPE	D25, D21

(1912) 0x4af324 FADD	D23, D23, D25

(1912) 0x4af328 FCSEL	D21, D25, D21, #12

(1912) 0x4af32c LDR	D28, [X5], #8

(1912) 0x4af330 FCMPE	D28, D21

(1912) 0x4af334 FADD	D23, D23, D28

(1912) 0x4af338 FCSEL	D21, D28, D21, #12

(1912) 0x4af33c CMP	X27, X5

(1912) 0x4af340 B.EQ	4af3cc

  (1917) 0x4af344 ORR	X28, XZR, X5

  (1917) 0x4af348 LDR	D3, [X5, #8]

  (1917) 0x4af34c LDR	D29, [X28], #8

  (1917) 0x4af350 LDP	D30, D16, [X5, #24]

  (1917) 0x4af354 LDP	D7, D6, [X5, #40]

  (1917) 0x4af358 ADD	X5, X5, #64

  (1917) 0x4af35c FCMPE	D29, D21

  (1917) 0x4af360 LDR	D17, [X28, #8]

  (1917) 0x4af364 FADD	D23, D23, D29

  (1917) 0x4af368 LDUR	D5, [X5, #504]

  (1917) 0x4af36c FADD	D27, D23, D3

  (1917) 0x4af370 FCSEL	D26, D29, D21, #12

  (1917) 0x4af374 FCMPE	D3, D26

  (1917) 0x4af378 FADD	D2, D27, D17

  (1917) 0x4af37c FCSEL	D18, D3, D26, #12

  (1917) 0x4af380 FADD	D21, D2, D30

  (1917) 0x4af384 FCMPE	D17, D18

  (1917) 0x4af388 FADD	D1, D21, D16

  (1917) 0x4af38c FCSEL	D0, D17, D18, #12

  (1917) 0x4af390 FADD	D20, D1, D7

  (1917) 0x4af394 FCMPE	D30, D0

  (1917) 0x4af398 FADD	D19, D20, D6

  (1917) 0x4af39c FCSEL	D22, D30, D0, #12

  (1917) 0x4af3a0 FADD	D23, D19, D5

  (1917) 0x4af3a4 FCMPE	D16, D22

  (1917) 0x4af3a8 FCSEL	D24, D16, D22, #12

  (1917) 0x4af3ac FCMPE	D7, D24

  (1917) 0x4af3b0 FCSEL	D25, D7, D24, #12

  (1917) 0x4af3b4 FCMPE	D6, D25

  (1917) 0x4af3b8 FCSEL	D28, D6, D25, #12

  (1917) 0x4af3bc FCMPE	D5, D28

  (1917) 0x4af3c0 FCSEL	D21, D5, D28, #12

  (1917) 0x4af3c4 CMP	X27, X5

  (1917) 0x4af3c8 B.NE	4af344

(1912) 0x4af3cc FABS	D4, D4

(1912) 0x4af3d0 FABS	D29, D23

(1912) 0x4af3d4 SUB	X6, X9, X6

(1912) 0x4af3d8 SUB	X9, X18, X15

(1912) 0x4af3dc STR	X13, [X19, X14]

(1912) 0x4af3e0 SUB	X14, X6, #1

(1912) 0x4af3e4 LDP	X18, X15, [X0, #1016]

(1912) 0x4af3e8 ADD	X2, X2, X9

(1912) 0x4af3ec ADD	X1, X1, X14

(1912) 0x4af3f0 FMUL	D23, D4, D15

(1912) 0x4af3f4 ADD	X27, X18, #1

(1912) 0x4af3f8 FCMPE	D29, D23

(1912) 0x4af3fc B.GT	4af4ec

(1912) 0x4af400 CMP	X27, X15

(1912) 0x4af404 B.GE	4af430

(1912) 0x4af408 FMUL	D3, D14, D21

  (1916) 0x4af40c LDR	D30, [X22, X27,LSL #3]

  (1916) 0x4af410 FCMPE	D3, D30

  (1916) 0x4af414 B.GE	4af484

  (1916) 0x4af418 LDR	X15, [X25, X27,LSL #3]

  (1916) 0x4af41c STR	X15, [X19, X27,LSL #3]

  (1916) 0x4af420 ADD	X27, X27, #1

  (1916) 0x4af424 LDR	X11, [X0]

  (1916) 0x4af428 CMP	X11, X27

  (1916) 0x4af42c B.GT	4af40c

(1912) 0x4af430 LDR	X27, [X3]

(1912) 0x4af434 LDR	X9, [X12]

(1912) 0x4af438 CMP	X9, X27

(1912) 0x4af43c B.GE	4ae60c

(1912) 0x4af440 FMUL	D16, D14, D21

  (1915) 0x4af444 LDR	D7, [X23, X9,LSL #3]

  (1915) 0x4af448 FCMPE	D16, D7

  (1915) 0x4af44c B.GE	4af4a0

  (1915) 0x4af450 LDR	X28, [X24, X9,LSL #3]

  (1915) 0x4af454 STR	X28, [X20, X9,LSL #3]

  (1915) 0x4af458 ADD	X9, X9, #1

  (1915) 0x4af45c LDR	X6, [X3]

  (1915) 0x4af460 CMP	X6, X9

  (1915) 0x4af464 B.GT	4af444

(1912) 0x4af468 ADD	X4, X4, #1

(1912) 0x4af46c ADD	X12, X12, #8

(1912) 0x4af470 ADD	X3, X3, #8

(1912) 0x4af474 ADD	X0, X0, #8

(1912) 0x4af478 CMP	X4, X30

(1912) 0x4af47c B.NE	4ae0cc

0x4af480 B	4ae624

  (1916) 0x4af484 STR	X13, [X19, X27,LSL #3]

  (1916) 0x4af488 ADD	X27, X27, #1

  (1916) 0x4af48c SUB	X1, X1, #1

  (1916) 0x4af490 LDR	X5, [X0]

  (1916) 0x4af494 CMP	X5, X27

  (1916) 0x4af498 B.GT	4af40c

(1912) 0x4af49c B	4af430

  (1915) 0x4af4a0 STR	X13, [X20, X9,LSL #3]

  (1915) 0x4af4a4 ADD	X9, X9, #1

  (1915) 0x4af4a8 SUB	X2, X2, #1

  (1915) 0x4af4ac LDR	X14, [X3]

  (1915) 0x4af4b0 CMP	X14, X9

  (1915) 0x4af4b4 B.GT	4af444

(1912) 0x4af4b8 ADD	X4, X4, #1

(1912) 0x4af4bc ADD	X12, X12, #8

(1912) 0x4af4c0 ADD	X3, X3, #8

(1912) 0x4af4c4 ADD	X0, X0, #8

(1912) 0x4af4c8 CMP	X4, X30

(1912) 0x4af4cc B.NE	4ae0cc

0x4af4d0 B	4ae624

(1912) 0x4af4d4 FCMPE	D15, D31

(1912) 0x4af4d8 B.MI	4af0a4

(1912) 0x4af4dc B	4aefe0

(1912) 0x4af4e0 FCMPE	D15, D31

(1912) 0x4af4e4 B.MI	4af0a4

(1912) 0x4af4e8 B	4aea88

(1912) 0x4af4ec FMOV	D26, #1.0000000

(1912) 0x4af4f0 FCMPE	D15, D26

(1912) 0x4af4f4 B.MI	4af0a4

(1912) 0x4af4f8 B	4af400

(1912) 0x4af4fc LDR	D22, [X23, X5,LSL #3]

(1912) 0x4af500 FCMPE	D22, D24

(1912) 0x4af504 FADD	D18, D18, D22

(1912) 0x4af508 FCSEL	D24, D22, D24, #12

(1912) 0x4af50c B	4aee54

(1912) 0x4af510 LDR	D7, [X22, X5,LSL #3]

(1912) 0x4af514 FCMPE	D7, D24

(1912) 0x4af518 FADD	D18, D18, D7

(1912) 0x4af51c FCSEL	D24, D7, D24, #12

(1912) 0x4af520 B	4aec34

(1912) 0x4af524 LDR	D18, [X22, X5,LSL #3]

(1912) 0x4af528 FCMPE	D18, D22

(1912) 0x4af52c FADD	D23, D23, D18

(1912) 0x4af530 FCSEL	D22, D22, D18, #12

(1912) 0x4af534 B	4ae194

(1912) 0x4af538 LDR	D16, [X23, X5,LSL #3]

(1912) 0x4af53c FCMPE	D16, D22

(1912) 0x4af540 FADD	D23, D23, D16

(1912) 0x4af544 FCSEL	D22, D22, D16, #12

(1912) 0x4af548 B	4ae3b4

(1912) 0x4af54c LDR	D16, [X22, X5,LSL #3]

(1912) 0x4af550 FCMPE	D16, D24

(1912) 0x4af554 FADD	D18, D18, D16

(1912) 0x4af558 FCSEL	D24, D16, D24, #12

(1912) 0x4af55c B	4aec20

(1912) 0x4af560 LDR	D23, [X23, X5,LSL #3]

(1912) 0x4af564 FCMPE	D23, D24

(1912) 0x4af568 FADD	D18, D18, D23

(1912) 0x4af56c FCSEL	D24, D23, D24, #12

(1912) 0x4af570 B	4aee40

(1912) 0x4af574 LDR	D30, [X23, X5,LSL #3]

(1912) 0x4af578 FCMPE	D30, D22

(1912) 0x4af57c FADD	D23, D23, D30

(1912) 0x4af580 FCSEL	D22, D22, D30, #12

(1912) 0x4af584 B	4ae3a0

(1912) 0x4af588 LDR	D27, [X22, X5,LSL #3]

(1912) 0x4af58c FCMPE	D27, D22

(1912) 0x4af590 FADD	D23, D23, D27

(1912) 0x4af594 FCSEL	D22, D22, D27, #12

(1912) 0x4af598 B	4ae180

(1912) 0x4af59c LDR	D29, [X23, X5,LSL #3]

(1912) 0x4af5a0 FCMPE	D29, D24

(1912) 0x4af5a4 FADD	D18, D18, D29

(1912) 0x4af5a8 FCSEL	D24, D29, D24, #12

(1912) 0x4af5ac B	4aee2c

(1912) 0x4af5b0 LDR	D30, [X22, X5,LSL #3]

(1912) 0x4af5b4 FCMPE	D30, D24

(1912) 0x4af5b8 FADD	D18, D18, D30

(1912) 0x4af5bc FCSEL	D24, D30, D24, #12

(1912) 0x4af5c0 B	4aec0c

(1912) 0x4af5c4 LDR	D3, [X22, X5,LSL #3]

(1912) 0x4af5c8 FCMPE	D3, D24

(1912) 0x4af5cc FADD	D18, D18, D3

(1912) 0x4af5d0 FCSEL	D24, D3, D24, #12

(1912) 0x4af5d4 B	4aebf8

(1912) 0x4af5d8 LDR	D28, [X23, X5,LSL #3]

(1912) 0x4af5dc FCMPE	D28, D24

(1912) 0x4af5e0 FADD	D18, D18, D28

(1912) 0x4af5e4 FCSEL	D24, D28, D24, #12

(1912) 0x4af5e8 B	4aee18

(1912) 0x4af5ec LDR	D3, [X23, X5,LSL #3]

(1912) 0x4af5f0 FCMPE	D3, D22

(1912) 0x4af5f4 FADD	D23, D23, D3

(1912) 0x4af5f8 FCSEL	D22, D22, D3, #12

(1912) 0x4af5fc B	4ae38c

(1912) 0x4af600 LDR	D5, [X22, X5,LSL #3]

(1912) 0x4af604 FCMPE	D5, D22

(1912) 0x4af608 FADD	D23, D23, D5

(1912) 0x4af60c FCSEL	D22, D22, D5, #12

(1912) 0x4af610 B	4ae16c

(1912) 0x4af614 FMOV	D23, D4

(1912) 0x4af618 MOVI	D22, #0

(1912) 0x4af61c B	4ae314

(1912) 0x4af620 FMOV	D18, D4

(1912) 0x4af624 MOVI	D24, #0

(1912) 0x4af628 B	4aed8c

(1912) 0x4af62c FMOV	D3, D4

(1912) 0x4af630 MOVI	D23, #0

(1912) 0x4af634 B	4ae8ec

(1912) 0x4af638 LDR	D17, [X22, X27]

(1912) 0x4af63c ADD	X5, X5, #8

(1912) 0x4af640 FCMPE	D17, #0

(1912) 0x4af644 FADD	D23, D4, D17

(1912) 0x4af648 FCSEL	D21, D17, D21, #12

(1912) 0x4af64c B	4af188

(1912) 0x4af650 LDR	D0, [X23, X28]

(1912) 0x4af654 ADD	X5, X5, #8

(1912) 0x4af658 FCMPE	D0, D21

(1912) 0x4af65c FADD	D23, D23, D0

(1912) 0x4af660 FCSEL	D21, D0, D21, #12

(1912) 0x4af664 B	4af2dc

(1912) 0x4af668 LDR	D25, [X23, X5,LSL #3]

(1912) 0x4af66c ADD	X5, X5, #1

(1912) 0x4af670 FCMPE	D25, D24

(1912) 0x4af674 FADD	D18, D18, D25

(1912) 0x4af678 FCSEL	D24, D25, D24, #12

(1912) 0x4af67c B	4aee08

(1912) 0x4af680 LDR	D26, [X22, X5,LSL #3]

(1912) 0x4af684 ADD	X5, X5, #1

(1912) 0x4af688 FCMPE	D26, D24

(1912) 0x4af68c FADD	D18, D18, D26

(1912) 0x4af690 FCSEL	D24, D26, D24, #12

(1912) 0x4af694 B	4aebe8

(1912) 0x4af698 LDR	D6, [X22, X5,LSL #3]

(1912) 0x4af69c ADD	X5, X5, #1

(1912) 0x4af6a0 FCMPE	D6, #0

(1912) 0x4af6a4 FADD	D23, D4, D6

(1912) 0x4af6a8 FCSEL	D22, D22, D6, #12

(1912) 0x4af6ac B	4ae15c

(1912) 0x4af6b0 LDR	D26, [X23, X15,LSL #3]

(1912) 0x4af6b4 ADD	X5, X15, #1

(1912) 0x4af6b8 FCMPE	D26, D22

(1912) 0x4af6bc FADD	D23, D23, D26

(1912) 0x4af6c0 FCSEL	D22, D22, D26, #12

(1912) 0x4af6c4 B	4ae37c

(1912) 0x4af6c8 LDR	D22, [X22, X5,LSL #3]

(1912) 0x4af6cc FCMPE	D22, #0

(1912) 0x4af6d0 FADD	D18, D4, D22

(1912) 0x4af6d4 FCSEL	D24, D22, D24, #12

(1912) 0x4af6d8 B	4aebd0

(1912) 0x4af6dc LDR	D19, [X23, X15,LSL #3]

(1912) 0x4af6e0 FCMPE	D19, D24

(1912) 0x4af6e4 FADD	D18, D18, D19

(1912) 0x4af6e8 FCSEL	D24, D19, D24, #12

(1912) 0x4af6ec B	4aedf0

(1912) 0x4af6f0 FMOV	D23, D4

(1912) 0x4af6f4 MOVI	D21, #0

(1912) 0x4af6f8 B	4af278

0x4af6fc HINT	#0

Coverage (%)	Name	Source Location	Module
►98.59+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.41+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGCreateS	par_strength.c:520	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:581	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_strength.c:246-513
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:246-283,289-302,309-355,363-369,376-382,392-398,405-411,424-445,451-472,480,492-513.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.83 to 2.50 cycles (6.73x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 39% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 16.83 to 7.17 cycles (2.35x speedup).

Details

4% of VPU instructions are used in vector version (process two or more data elements in vector registers):

7% of VPU loads are used in vector version.
5% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_GetSimpleThreadPartition: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:250
hypre_prefix_sum_pair: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:480

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	84
nb uops	83
loop length	336
used w registers	0
used x registers	31
used b registers	0
used h registers	0
used s registers	1
used d registers	3
used q registers	0
used v registers	0
used z registers	0
nb stack references	38

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.38 cycles
front end	10.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	6.00	6.00	6.00	6.00	0.50	0.50	0.50	0.50	16.83	16.50	16.67	9.00	9.00
cycles	5.50	5.50	6.00	6.00	6.00	6.00	0.50	0.50	0.50	0.50	16.83	16.50	16.67	9.00	9.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.38
Dispatch	16.83
Overall L1	16.83

Vectorization ratios

INT

all	4%
load	7%
store	5%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	4%
load	7%
store	5%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	39%
load	44%
store	44%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	39%
load	44%
store	44%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.83 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4ae004

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #816]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X3, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, SP, #184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDR X8, [X3, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X10, X22, [X3, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X7, X28, [X3, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X23, [X3, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X4, X21, [X3, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X24, [X3, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X5, [X3, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP D14, D15, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
STP X8, X7, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X2, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X9, X10, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X6, [X3, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X5, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X27, X26, [X3, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X19, [X3, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X20, [X3, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X11, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 527b60 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X4, X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP XZR, XZR, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X4, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X18, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X8, X7, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X15, X10, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B.GE 4ae630 <hypre_BoomerAMGCreateS._omp_fn.1+0x62c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X0, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FMOV D31, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD X12, X15, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X16, X17, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X3, X15, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X10, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVN X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X27, X28, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X27, X28, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X18, X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X1, X2, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X7, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X2, SP, #200	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X8, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X7, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X15, X10, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 528d08 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X1, X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X1, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4ae700 <hypre_BoomerAMGCreateS._omp_fn.1+0x6fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X16, X10, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X7, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ADD X22, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X23, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X17, X13, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #208	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4ae624 <hypre_BoomerAMGCreateS._omp_fn.1+0x620>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4ae624 <hypre_BoomerAMGCreateS._omp_fn.1+0x620>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4ae624 <hypre_BoomerAMGCreateS._omp_fn.1+0x620>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4ae624 <hypre_BoomerAMGCreateS._omp_fn.1+0x620>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4ae624 <hypre_BoomerAMGCreateS._omp_fn.1+0x620>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4ae624 <hypre_BoomerAMGCreateS._omp_fn.1+0x620>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_strength.c:246-513
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.83 to 2.50 cycles (6.73x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

4% of VPU instructions are used in vector version (process two or more data elements in vector registers):

7% of VPU loads are used in vector version.
5% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_GetSimpleThreadPartition: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:250
hypre_prefix_sum_pair: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:480

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	84
nb uops	83
loop length	336
used w registers	0
used x registers	31
used b registers	0
used h registers	0
used s registers	1
used d registers	3
used q registers	0
used v registers	0
used z registers	0
nb stack references	38

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.38 cycles
front end	10.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	6.00	6.00	6.00	6.00	0.50	0.50	0.50	0.50	16.83	16.50	16.67	9.00	9.00
cycles	5.50	5.50	6.00	6.00	6.00	6.00	0.50	0.50	0.50	0.50	16.83	16.50	16.67	9.00	9.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.38
Dispatch	16.83
Overall L1	16.83

Vectorization ratios

INT

all	4%
load	7%
store	5%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	4%
load	7%
store	5%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	39%
load	44%
store	44%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	39%
load	44%
store	44%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.83 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4ae004

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #816]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X3, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, SP, #184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDR X8, [X3, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X10, X22, [X3, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X7, X28, [X3, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X23, [X3, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X4, X21, [X3, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X24, [X3, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X5, [X3, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP D14, D15, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
STP X8, X7, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X2, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X9, X10, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X6, [X3, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X5, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X6, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X27, X26, [X3, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X19, [X3, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X20, [X3, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X11, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 527b60 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X4, X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP XZR, XZR, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X4, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X18, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X8, X7, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X15, X10, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B.GE 4ae630 <hypre_BoomerAMGCreateS._omp_fn.1+0x62c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X0, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FMOV D31, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD X12, X15, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X13, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X16, X17, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X3, X15, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X10, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVN X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X27, X28, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X27, X28, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X18, X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
STP X1, X2, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X7, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X2, SP, #200	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X8, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STP X7, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X15, X10, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 528d08 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X1, X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X1, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4ae700 <hypre_BoomerAMGCreateS._omp_fn.1+0x6fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X16, X10, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X7, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ADD X22, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X23, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X17, X13, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #208	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4ae624 <hypre_BoomerAMGCreateS._omp_fn.1+0x620>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4ae624 <hypre_BoomerAMGCreateS._omp_fn.1+0x620>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4ae624 <hypre_BoomerAMGCreateS._omp_fn.1+0x620>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4ae624 <hypre_BoomerAMGCreateS._omp_fn.1+0x620>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4ae624 <hypre_BoomerAMGCreateS._omp_fn.1+0x620>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4ae624 <hypre_BoomerAMGCreateS._omp_fn.1+0x620>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCreateS._omp_fn.1–	0.29	0.12
▼Loop 1912 - par_strength.c:253-472 - exec–	0.06	0.02
○Loop 1920 - par_strength.c:451-460 - exec	0.11	0.03
○Loop 1922 - par_strength.c:324-327 - exec	0.04	0.01
○Loop 1928 - par_strength.c:392-398 - exec	0.00	0.00
○Loop 1923 - par_strength.c:376-382 - exec	0.00	0.00
○Loop 1924 - par_strength.c:363-369 - exec	0.00	0.00
○Loop 1917 - par_strength.c:316-319 - exec	0.00	0.00
○Loop 1916 - par_strength.c:424-433 - exec	0.00	0.00
○Loop 1913 - par_strength.c:351-353 - exec	0.00	0.00
○Loop 1918 - par_strength.c:311-314 - exec	0.00	0.00
○Loop 1919 - par_strength.c:463-472 - exec	0.00	0.00
○Loop 1929 - par_strength.c:297-302 - exec	0.00	0.00
○Loop 1925 - par_strength.c:278-283 - exec	0.00	0.00
○Loop 1921 - par_strength.c:329-332 - exec	0.00	0.00
○Loop 1926 - par_strength.c:270-275 - exec	0.00	0.00
○Loop 1914 - par_strength.c:345-347 - exec	0.00	0.00
○Loop 1915 - par_strength.c:436-445 - exec	0.00	0.00
○Loop 1930 - par_strength.c:289-294 - exec	0.00	0.00
○Loop 1927 - par_strength.c:405-411 - exec	0.00	0.00
▼Loop 1908 - par_strength.c:492-513 - exec–	0.01	0.01
○Loop 1911 - par_strength.c:498-503 - exec	0.07	0.02
▼Loop 1909 - par_strength.c:508-513 - exec–	0.00	0.00
○Loop 1910 - par_strength.c:508-513 - exec	0.00	0.00

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Matching between your function (in the source code) and the binary function

General properties

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Front-end bottlenecks

ASM code