OV - exec - Function hypre_BoomerAMGCreate2ndS._omp

	Function: hypre_BoomerAMGCreate2ndS._omp_fn.0	Module: exec	Source: par_strength.c:1253-1278	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 1253 - 1278

--------------------------------------------------------------------------------

1253: #pragma omp parallel private(i)

1254: #endif

1255:    {

1256:       HYPRE_Int num_coarse_private = 0;

1257:

1258:       HYPRE_Int i_begin, i_end;

1259:       hypre_GetSimpleThreadPartition(&i_begin, &i_end, num_cols_diag_S);

1260:

1261:       for (i = i_begin; i < i_end; i++)

1262:       {

1263:          if (CF_marker[i] > 0) num_coarse_private++;

1264:       }

1265:

1266:       hypre_prefix_sum(&num_coarse_private, &num_coarse, num_coarse_prefix_sum);

1267:

1268:       for (i = i_begin; i < i_end; i++)

1269:       {

1270:          if (CF_marker[i] > 0)

1271:          {

1272:             fine_to_coarse[i] = num_coarse_private;

1273:             coarse_to_fine[num_coarse_private] = i;

1274:             num_coarse_private++;

1275:          }

1276:          else

1277:          {

1278:             fine_to_coarse[i] = -1;

0x4b2560 STP	X29, X30, [SP, #928]!

0x4b2564 ADD	X29, SP, #0

0x4b2568 ADD	X1, SP, #88

0x4b256c STP	X21, X22, [SP, #32]

0x4b2570 ORR	X22, XZR, X0

0x4b2574 ADD	X0, SP, #80

0x4b2578 STP	X19, X20, [SP, #16]

0x4b257c LDP	X19, X2, [X22]

0x4b2580 STR	XZR, [SP, #72]

0x4b2584 LDR	X21, [X22, #16]

0x4b2588 LDR	X20, [X22, #32]

0x4b258c STR	X23, [SP, #48]

0x4b2590 LDR	X23, [X22, #40]

0x4b2594 BL	527b60

0x4b2598 LDP	X1, X4, [SP, #80]

0x4b259c CMP	X1, X4

0x4b25a0 B.GE	4b2764

0x4b25a4 ADD	X18, X19, X1,LSL #3

0x4b25a8 MOVZ	W0, #0

0x4b25ac ADD	X5, X19, X4,LSL #3

0x4b25b0 SUB	X3, X5, X18

0x4b25b4 SUB	X2, X3, #8

0x4b25b8 UBFM	X6, X2, #3, #63

0x4b25bc LDR	X2, [SP, #72]

0x4b25c0 ADD	X7, X6, #1

0x4b25c4 ANDS	X8, X7, #0x7

0x4b25c8 B.EQ	4b26ac

0x4b25cc CMP	X8, #1

0x4b25d0 B.EQ	4b268c

0x4b25d4 CMP	X8, #2

0x4b25d8 B.EQ	4b2674

0x4b25dc CMP	X8, #3

0x4b25e0 B.EQ	4b265c

0x4b25e4 CMP	X8, #4

0x4b25e8 B.EQ	4b2644

0x4b25ec CMP	X8, #5

0x4b25f0 B.EQ	4b262c

0x4b25f4 CMP	X8, #6

0x4b25f8 B.EQ	4b2614

0x4b25fc LDR	X9, [X18]

0x4b2600 CMP	X9, #0

0x4b2604 B.LE	4b2610

0x4b2608 ADD	X2, X2, #1

0x4b260c MOVZ	W0, #1

0x4b2610 ADD	X18, X18, #8

0x4b2614 LDR	X10, [X18]

0x4b2618 CMP	X10, #0

0x4b261c B.LE	4b2628

0x4b2620 ADD	X2, X2, #1

0x4b2624 MOVZ	W0, #1

0x4b2628 ADD	X18, X18, #8

0x4b262c LDR	X11, [X18]

0x4b2630 CMP	X11, #0

0x4b2634 B.LE	4b2640

0x4b2638 ADD	X2, X2, #1

0x4b263c MOVZ	W0, #1

0x4b2640 ADD	X18, X18, #8

0x4b2644 LDR	X12, [X18]

0x4b2648 CMP	X12, #0

0x4b264c B.LE	4b2658

0x4b2650 ADD	X2, X2, #1

0x4b2654 MOVZ	W0, #1

0x4b2658 ADD	X18, X18, #8

0x4b265c LDR	X13, [X18]

0x4b2660 CMP	X13, #0

0x4b2664 B.LE	4b2670

0x4b2668 ADD	X2, X2, #1

0x4b266c MOVZ	W0, #1

0x4b2670 ADD	X18, X18, #8

0x4b2674 LDR	X14, [X18]

0x4b2678 CMP	X14, #0

0x4b267c B.LE	4b2688

0x4b2680 ADD	X2, X2, #1

0x4b2684 MOVZ	W0, #1

0x4b2688 ADD	X18, X18, #8

0x4b268c LDR	X15, [X18]

0x4b2690 CMP	X15, #0

0x4b2694 B.LE	4b26a0

0x4b2698 ADD	X2, X2, #1

0x4b269c MOVZ	W0, #1

0x4b26a0 ADD	X18, X18, #8

0x4b26a4 CMP	X18, X5

0x4b26a8 B.EQ	4b275c

(1989) 0x4b26ac LDR	X16, [X18]

(1989) 0x4b26b0 CMP	X16, #0

(1989) 0x4b26b4 B.LE	4b26c0

(1989) 0x4b26b8 ADD	X2, X2, #1

(1989) 0x4b26bc MOVZ	W0, #1

(1989) 0x4b26c0 LDR	X17, [X18, #8]

(1989) 0x4b26c4 ADD	X18, X18, #8

(1989) 0x4b26c8 CMP	X17, #0

(1989) 0x4b26cc B.LE	4b26d8

(1989) 0x4b26d0 ADD	X2, X2, #1

(1989) 0x4b26d4 MOVZ	W0, #1

(1989) 0x4b26d8 LDR	X30, [X18, #8]

(1989) 0x4b26dc CMP	X30, #0

(1989) 0x4b26e0 B.LE	4b26ec

(1989) 0x4b26e4 ADD	X2, X2, #1

(1989) 0x4b26e8 MOVZ	W0, #1

(1989) 0x4b26ec LDR	X1, [X18, #16]

(1989) 0x4b26f0 CMP	X1, #0

(1989) 0x4b26f4 B.LE	4b2700

(1989) 0x4b26f8 ADD	X2, X2, #1

(1989) 0x4b26fc MOVZ	W0, #1

(1989) 0x4b2700 LDR	X4, [X18, #24]

(1989) 0x4b2704 CMP	X4, #0

(1989) 0x4b2708 B.LE	4b2714

(1989) 0x4b270c ADD	X2, X2, #1

(1989) 0x4b2710 MOVZ	W0, #1

(1989) 0x4b2714 LDR	X3, [X18, #32]

(1989) 0x4b2718 CMP	X3, #0

(1989) 0x4b271c B.LE	4b2728

(1989) 0x4b2720 ADD	X2, X2, #1

(1989) 0x4b2724 MOVZ	W0, #1

(1989) 0x4b2728 LDR	X6, [X18, #40]

(1989) 0x4b272c CMP	X6, #0

(1989) 0x4b2730 B.LE	4b273c

(1989) 0x4b2734 ADD	X2, X2, #1

(1989) 0x4b2738 MOVZ	W0, #1

(1989) 0x4b273c LDR	X7, [X18, #48]

(1989) 0x4b2740 CMP	X7, #0

(1989) 0x4b2744 B.LE	4b2750

(1989) 0x4b2748 ADD	X2, X2, #1

(1989) 0x4b274c MOVZ	W0, #1

(1989) 0x4b2750 ADD	X18, X18, #56

(1989) 0x4b2754 CMP	X18, X5

(1989) 0x4b2758 B.NE	4b26ac

0x4b275c CBZ	W0, 4b2764

0x4b2760 STR	X2, [SP, #72]

0x4b2764 LDR	X1, [X22, #24]

0x4b2768 ORR	X2, XZR, X20

0x4b276c ADD	X0, SP, #72

0x4b2770 BL	528b00

0x4b2774 LDP	X4, X8, [SP, #80]

0x4b2778 CMP	X4, X8

0x4b277c B.GE	4b2890

0x4b2780 SUB	X5, X8, X4

0x4b2784 LDR	X1, [SP, #72]

0x4b2788 MOVN	X9, #0

0x4b278c ANDS	X10, X5, #0x7

0x4b2790 B.EQ	4b2980

0x4b2794 CMP	X10, #1

0x4b2798 B.EQ	4b286c

0x4b279c CMP	X10, #2

0x4b27a0 B.EQ	4b2850

0x4b27a4 CMP	X10, #3

0x4b27a8 B.EQ	4b2834

0x4b27ac CMP	X10, #4

0x4b27b0 B.EQ	4b2818

0x4b27b4 CMP	X10, #5

0x4b27b8 B.EQ	4b27fc

0x4b27bc CMP	X10, #6

0x4b27c0 B.EQ	4b27e0

0x4b27c4 LDR	X11, [X19, X4,LSL #3]

0x4b27c8 CMP	X11, #0

0x4b27cc B.LE	4b2a64

0x4b27d0 STR	X1, [X21, X4,LSL #3]

0x4b27d4 STR	X4, [X23, X1,LSL #3]

0x4b27d8 ADD	X1, X1, #1

0x4b27dc ADD	X4, X4, #1

0x4b27e0 LDR	X12, [X19, X4,LSL #3]

0x4b27e4 CMP	X12, #0

0x4b27e8 B.LE	4b2a4c

0x4b27ec STR	X1, [X21, X4,LSL #3]

0x4b27f0 STR	X4, [X23, X1,LSL #3]

0x4b27f4 ADD	X1, X1, #1

0x4b27f8 ADD	X4, X4, #1

0x4b27fc LDR	X13, [X19, X4,LSL #3]

0x4b2800 CMP	X13, #0

0x4b2804 B.LE	4b2a40

0x4b2808 STR	X1, [X21, X4,LSL #3]

0x4b280c STR	X4, [X23, X1,LSL #3]

0x4b2810 ADD	X1, X1, #1

0x4b2814 ADD	X4, X4, #1

0x4b2818 LDR	X14, [X19, X4,LSL #3]

0x4b281c CMP	X14, #0

0x4b2820 B.LE	4b2a58

0x4b2824 STR	X1, [X21, X4,LSL #3]

0x4b2828 STR	X4, [X23, X1,LSL #3]

0x4b282c ADD	X1, X1, #1

0x4b2830 ADD	X4, X4, #1

0x4b2834 LDR	X15, [X19, X4,LSL #3]

0x4b2838 CMP	X15, #0

0x4b283c B.LE	4b2a34

0x4b2840 STR	X1, [X21, X4,LSL #3]

0x4b2844 STR	X4, [X23, X1,LSL #3]

0x4b2848 ADD	X1, X1, #1

0x4b284c ADD	X4, X4, #1

0x4b2850 LDR	X16, [X19, X4,LSL #3]

0x4b2854 CMP	X16, #0

0x4b2858 B.LE	4b2a28

0x4b285c STR	X1, [X21, X4,LSL #3]

0x4b2860 STR	X4, [X23, X1,LSL #3]

0x4b2864 ADD	X1, X1, #1

0x4b2868 ADD	X4, X4, #1

0x4b286c LDR	X17, [X19, X4,LSL #3]

0x4b2870 CMP	X17, #0

0x4b2874 B.LE	4b2a20

0x4b2878 STR	X1, [X21, X4,LSL #3]

0x4b287c STR	X4, [X23, X1,LSL #3]

0x4b2880 ADD	X1, X1, #1

0x4b2884 ADD	X4, X4, #1

0x4b2888 CMP	X8, X4

0x4b288c B.NE	4b2980

0x4b2890 LDR	X23, [SP, #48]

0x4b2894 LDP	X19, X20, [SP, #16]

0x4b2898 LDP	X21, X22, [SP, #32]

0x4b289c LDP	X29, X30, [SP], #96

0x4b28a0 RET

(1988) 0x4b28a4 STR	X1, [X21, X4,LSL #3]

(1988) 0x4b28a8 STR	X4, [X23, X1,LSL #3]

(1988) 0x4b28ac ADD	X4, X4, #1

(1988) 0x4b28b0 ADD	X1, X1, #1

(1988) 0x4b28b4 LDR	X3, [X19, X4,LSL #3]

(1988) 0x4b28b8 CMP	X3, #0

(1988) 0x4b28bc B.LE	4b29a0

(1988) 0x4b28c0 ADD	X6, X4, #1

(1988) 0x4b28c4 STR	X1, [X21, X4,LSL #3]

(1988) 0x4b28c8 STR	X4, [X23, X1,LSL #3]

(1988) 0x4b28cc ADD	X1, X1, #1

(1988) 0x4b28d0 LDR	X7, [X19, X6,LSL #3]

(1988) 0x4b28d4 CMP	X7, #0

(1988) 0x4b28d8 B.LE	4b29b4

(1988) 0x4b28dc ADD	X2, X4, #2

(1988) 0x4b28e0 STR	X1, [X21, X6,LSL #3]

(1988) 0x4b28e4 STR	X6, [X23, X1,LSL #3]

(1988) 0x4b28e8 ADD	X1, X1, #1

(1988) 0x4b28ec LDR	X0, [X19, X2,LSL #3]

(1988) 0x4b28f0 CMP	X0, #0

(1988) 0x4b28f4 B.LE	4b29c8

(1988) 0x4b28f8 ADD	X18, X4, #3

(1988) 0x4b28fc STR	X1, [X21, X2,LSL #3]

(1988) 0x4b2900 STR	X2, [X23, X1,LSL #3]

(1988) 0x4b2904 ADD	X1, X1, #1

(1988) 0x4b2908 LDR	X20, [X19, X18,LSL #3]

(1988) 0x4b290c CMP	X20, #0

(1988) 0x4b2910 B.LE	4b29dc

(1988) 0x4b2914 ADD	X22, X4, #4

(1988) 0x4b2918 STR	X1, [X21, X18,LSL #3]

(1988) 0x4b291c STR	X18, [X23, X1,LSL #3]

(1988) 0x4b2920 ADD	X1, X1, #1

(1988) 0x4b2924 LDR	X5, [X19, X22,LSL #3]

(1988) 0x4b2928 CMP	X5, #0

(1988) 0x4b292c B.LE	4b29f0

(1988) 0x4b2930 ADD	X10, X4, #5

(1988) 0x4b2934 STR	X1, [X21, X22,LSL #3]

(1988) 0x4b2938 STR	X22, [X23, X1,LSL #3]

(1988) 0x4b293c ADD	X1, X1, #1

(1988) 0x4b2940 LDR	X11, [X19, X10,LSL #3]

(1988) 0x4b2944 CMP	X11, #0

(1988) 0x4b2948 B.LE	4b2a04

(1988) 0x4b294c ADD	X12, X4, #6

(1988) 0x4b2950 STR	X1, [X21, X10,LSL #3]

(1988) 0x4b2954 STR	X10, [X23, X1,LSL #3]

(1988) 0x4b2958 ADD	X1, X1, #1

(1988) 0x4b295c LDR	X13, [X19, X12,LSL #3]

(1988) 0x4b2960 CMP	X13, #0

(1988) 0x4b2964 B.LE	4b2a18

(1988) 0x4b2968 STR	X1, [X21, X12,LSL #3]

(1988) 0x4b296c STR	X12, [X23, X1,LSL #3]

(1988) 0x4b2970 ADD	X1, X1, #1

(1988) 0x4b2974 ADD	X4, X4, #7

(1988) 0x4b2978 CMP	X8, X4

(1988) 0x4b297c B.EQ	4b2890

(1988) 0x4b2980 LDR	X30, [X19, X4,LSL #3]

(1988) 0x4b2984 CMP	X30, #0

(1988) 0x4b2988 B.GT	4b28a4

(1988) 0x4b298c STR	X9, [X21, X4,LSL #3]

(1988) 0x4b2990 ADD	X4, X4, #1

(1988) 0x4b2994 LDR	X3, [X19, X4,LSL #3]

(1988) 0x4b2998 CMP	X3, #0

(1988) 0x4b299c B.GT	4b28c0

(1988) 0x4b29a0 ADD	X6, X4, #1

(1988) 0x4b29a4 STR	X9, [X21, X4,LSL #3]

(1988) 0x4b29a8 LDR	X7, [X19, X6,LSL #3]

(1988) 0x4b29ac CMP	X7, #0

(1988) 0x4b29b0 B.GT	4b28dc

(1988) 0x4b29b4 ADD	X2, X4, #2

(1988) 0x4b29b8 STR	X9, [X21, X6,LSL #3]

(1988) 0x4b29bc LDR	X0, [X19, X2,LSL #3]

(1988) 0x4b29c0 CMP	X0, #0

(1988) 0x4b29c4 B.GT	4b28f8

(1988) 0x4b29c8 ADD	X18, X4, #3

(1988) 0x4b29cc STR	X9, [X21, X2,LSL #3]

(1988) 0x4b29d0 LDR	X20, [X19, X18,LSL #3]

(1988) 0x4b29d4 CMP	X20, #0

(1988) 0x4b29d8 B.GT	4b2914

(1988) 0x4b29dc ADD	X22, X4, #4

(1988) 0x4b29e0 STR	X9, [X21, X18,LSL #3]

(1988) 0x4b29e4 LDR	X5, [X19, X22,LSL #3]

(1988) 0x4b29e8 CMP	X5, #0

(1988) 0x4b29ec B.GT	4b2930

(1988) 0x4b29f0 ADD	X10, X4, #5

(1988) 0x4b29f4 STR	X9, [X21, X22,LSL #3]

(1988) 0x4b29f8 LDR	X11, [X19, X10,LSL #3]

(1988) 0x4b29fc CMP	X11, #0

(1988) 0x4b2a00 B.GT	4b294c

(1988) 0x4b2a04 ADD	X12, X4, #6

(1988) 0x4b2a08 STR	X9, [X21, X10,LSL #3]

(1988) 0x4b2a0c LDR	X13, [X19, X12,LSL #3]

(1988) 0x4b2a10 CMP	X13, #0

(1988) 0x4b2a14 B.GT	4b2968

(1988) 0x4b2a18 STR	X9, [X21, X12,LSL #3]

(1988) 0x4b2a1c B	4b2974

0x4b2a20 STR	X9, [X21, X4,LSL #3]

0x4b2a24 B	4b2884

0x4b2a28 STR	X9, [X21, X4,LSL #3]

0x4b2a2c ADD	X4, X4, #1

0x4b2a30 B	4b286c

0x4b2a34 STR	X9, [X21, X4,LSL #3]

0x4b2a38 ADD	X4, X4, #1

0x4b2a3c B	4b2850

0x4b2a40 STR	X9, [X21, X4,LSL #3]

0x4b2a44 ADD	X4, X4, #1

0x4b2a48 B	4b2818

0x4b2a4c STR	X9, [X21, X4,LSL #3]

0x4b2a50 ADD	X4, X4, #1

0x4b2a54 B	4b27fc

0x4b2a58 STR	X9, [X21, X4,LSL #3]

0x4b2a5c ADD	X4, X4, #1

0x4b2a60 B	4b2834

0x4b2a64 STR	X9, [X21, X4,LSL #3]

0x4b2a68 ADD	X4, X4, #1

0x4b2a6c B	4b27e0

Coverage (%)	Name	Source Location	Module
►96.08+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►3.92+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGCreate2ndS	par_strength.c:1283	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:622	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_strength.c:1253-1278
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1253-1278.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 23.13 to 4.47 cycles (5.17x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_GetSimpleThreadPartition: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1259
hypre_prefix_sum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1266

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	185
nb uops	185
loop length	740
used w registers	1
used x registers	27
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.13 cycles
front end	23.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	21.50	21.50	22.75	22.75	22.75	22.75	0.00	0.00	0.00	0.00	18.17	17.83	18.00	13.50	13.50
cycles	21.50	21.50	22.75	22.75	22.75	22.75	0.00	0.00	0.00	0.00	18.17	17.83	18.00	13.50	13.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.13
Dispatch	22.75
Overall L1	23.13

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	26%
store	27%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.13 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 4b2560

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, SP, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X19, X2, [X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR XZR, [SP, #72]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [X22, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X22, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X23, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X23, [X22, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 527b60 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP X1, X4, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP X1, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4b2764 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X18, X19, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X5, X19, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X5, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X2, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X6, X2, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X2, [SP, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X7, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X8, X7, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b26ac <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b268c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b2674 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b265c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b2644 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b262c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b2614 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b2610 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X10, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b2628 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X11, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b2640 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X12, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b2658 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b2670 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X14, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b2688 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X15, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b26a0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X18, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b275c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W0, 4b2764 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X2, [SP, #72]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [X22, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X2, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, SP, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
BL 528b00 <hypre_prefix_sum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP X4, X8, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP X4, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4b2890 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X5, X8, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X1, [SP, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X10, X5, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b2980 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b286c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x30c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b2850 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b2834 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b2818 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b27fc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b27e0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b2a64 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X12, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b2a4c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b2a40 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X14, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b2a58 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X15, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b2a34 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X16, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b2a28 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X17, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b2a20 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X8, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 4b2980 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 4b2884 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4b286c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x30c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4b2850 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4b2818 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4b27fc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4b2834 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4b27e0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_strength.c:1253-1278
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1253-1278.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_GetSimpleThreadPartition: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1259
hypre_prefix_sum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1266

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	185
nb uops	185
loop length	740
used w registers	1
used x registers	27
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.13 cycles
front end	23.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	21.50	21.50	22.75	22.75	22.75	22.75	0.00	0.00	0.00	0.00	18.17	17.83	18.00	13.50	13.50
cycles	21.50	21.50	22.75	22.75	22.75	22.75	0.00	0.00	0.00	0.00	18.17	17.83	18.00	13.50	13.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.13
Dispatch	22.75
Overall L1	23.13

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	26%
store	27%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.13 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 4b2560

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X1, SP, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X19, X2, [X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR XZR, [SP, #72]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [X22, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X22, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X23, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X23, [X22, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 527b60 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP X1, X4, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP X1, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4b2764 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X18, X19, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X5, X19, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X5, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X2, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X6, X2, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X2, [SP, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X7, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X8, X7, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b26ac <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b268c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b2674 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b265c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b2644 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b262c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b2614 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b2610 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X10, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b2628 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X11, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b2640 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X12, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b2658 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b2670 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X14, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b2688 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X15, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b26a0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X18, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b275c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W0, 4b2764 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X2, [SP, #72]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [X22, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X2, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, SP, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
BL 528b00 <hypre_prefix_sum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
LDP X4, X8, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP X4, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4b2890 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X5, X8, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X1, [SP, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X10, X5, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b2980 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b286c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x30c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b2850 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b2834 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b2818 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b27fc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4b27e0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b2a64 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X12, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b2a4c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b2a40 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X14, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b2a58 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X15, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b2a34 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X16, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b2a28 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X17, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4b2a20 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X8, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 4b2980 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B 4b2884 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4b286c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x30c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4b2850 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4b2818 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4b27fc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4b2834 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4b27e0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCreate2ndS._omp_fn.0–	0.01	0.01
○Loop 1989 - par_strength.c:1261-1263 - exec	0.01	0.00
○Loop 1988 - par_strength.c:1268-1278 - exec	0.01	0.01

Report Configuration

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code