OV - exec - Function hypre_ParCSRRelaxThreads._omp

	Function: hypre_ParCSRRelaxThreads._omp_fn.1	Module: exec	Source: ams.c:3662-3682 [...]	Coverage (incl. loops): 35.85% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3662 - 3682

--------------------------------------------------------------------------------

3662: #pragma omp parallel for private(i,ii,jj,res) HYPRE_SMP_SCHEDULE

[...]

3669:          if (A_diag_data[A_diag_i[i]] != zero)

3670:          {

3671:             res = f_data[i];

3672:             for (jj = A_diag_i[i]; jj < A_diag_i[i+1]; jj++)

3673:             {

3674:                ii = A_diag_j[jj];

3675:                res -= A_diag_data[jj] * Vtemp_data[ii];

3676:             }

3677:             for (jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++)

3678:             {

3679:                ii = A_offd_j[jj];

3680:                res -= A_offd_data[jj] * Vext_data[ii];

3681:             }

3682:             u_data[i] += (relax_weight*res)/l1_norms[i];

0x4c4c4c STP	X29, X30, [SP, #976]!

0x4c4c50 ADD	X29, SP, #0

0x4c4c54 STP	X19, X20, [SP, #16]

0x4c4c58 ORR	X19, XZR, X0

0x4c4c5c STR	X21, [SP, #32]

0x4c4c60 LDR	X21, [X0, #64]

0x4c4c64 BL	4100b0

0x4c4c68 SBFM	X20, X0, #0, #31

0x4c4c6c BL	410200

0x4c4c70 SBFM	X1, X0, #0, #31

0x4c4c74 SDIV	X7, X21, X20

0x4c4c78 MSUB	X0, X7, X20, X21

0x4c4c7c CMP	X1, X0

0x4c4c80 B.LT	4c4db8

0x4c4c84 MADD	X1, X7, X1, X0

0x4c4c88 ADD	X30, X7, X1

0x4c4c8c CMP	X1, X30

0x4c4c90 B.GE	4c4da8

0x4c4c94 LDP	X10, X11, [X19, #16]

0x4c4c98 CNTD	X4, ALL

0x4c4c9c PTRUE	P6.B, ALL

0x4c4ca0 LDP	X21, X13, [X19, #32]

0x4c4ca4 ADD	X17, X11, #8

0x4c4ca8 LDP	X20, X18, [X19, #48]

0x4c4cac ADD	X16, X13, #8

0x4c4cb0 LDP	X12, X14, [X19, #72]

0x4c4cb4 LDP	X9, X8, [X19, #88]

0x4c4cb8 LDR	X15, [X19]

0x4c4cbc LDR	D30, [X19, #8]

0x4c4cc0 LDR	D31, [X19, #104]

0x4c4cc4 B	4c4cd4

(2214) 0x4c4cc8 ADD	X1, X1, #1

(2214) 0x4c4ccc CMP	X30, X1

(2214) 0x4c4cd0 B.EQ	4c4da8

(2214) 0x4c4cd4 LDR	X5, [X11, X1,LSL #3]

(2214) 0x4c4cd8 UBFM	X3, X5, #61, #60

(2214) 0x4c4cdc ADD	X6, X10, X5,LSL #3

(2214) 0x4c4ce0 LDR	D5, [X10, X3]

(2214) 0x4c4ce4 FCMP	D31, D5

(2214) 0x4c4ce8 B.EQ	4c4cc8

(2214) 0x4c4cec LDR	X2, [X17, X1,LSL #3]

(2214) 0x4c4cf0 LDR	D0, [X14, X1,LSL #3]

(2214) 0x4c4cf4 CMP	X5, X2

(2214) 0x4c4cf8 B.GE	4c4d30

(2214) 0x4c4cfc MOVZ	X0, #0

(2214) 0x4c4d00 ADD	X19, X21, X3

(2214) 0x4c4d04 SUB	X7, X2, X5

(2214) 0x4c4d08 WHILELO	P7.D, XZR, X7

  (2216) 0x4c4d0c LD1D	{Z4.D}, P7/Z, [X19, X0,LSL #3]

  (2216) 0x4c4d10 LD1D	{Z2.D}, P7/Z, [X6, X0,LSL #3]

  (2216) 0x4c4d14 LD1D	{Z3.D}, P7/Z, [X9, Z4.D,LSL #3]

  (2216) 0x4c4d18 ADD	X0, X0, X4

  (2216) 0x4c4d1c FMUL	Z2.D, P7/M, Z2.D, Z3.D

  (2216) 0x4c4d20 FNEG	Z2.D, P6/M, Z2.D

  (2216) 0x4c4d24 FADDA	D0, P7, D0, Z2.D

  (2216) 0x4c4d28 WHILELO	P7.D, X0, X7

  (2216) 0x4c4d2c B.NE	4c4d0c

(2214) 0x4c4d30 LDR	X3, [X13, X1,LSL #3]

(2214) 0x4c4d34 LDR	X6, [X16, X1,LSL #3]

(2214) 0x4c4d38 CMP	X3, X6

(2214) 0x4c4d3c B.GE	4c4d84

(2214) 0x4c4d40 ADD	X5, X18, X3,LSL #3

(2214) 0x4c4d44 MOVZ	X7, #0

(2214) 0x4c4d48 SUB	X2, X6, X3

(2214) 0x4c4d4c ADD	X19, X20, X3,LSL #3

(2214) 0x4c4d50 WHILELO	P0.D, XZR, X2

(2214) 0x4c4d54 HINT	#0

(2214) 0x4c4d58 HINT	#0

(2214) 0x4c4d5c HINT	#0

  (2215) 0x4c4d60 LD1D	{Z27.D}, P0/Z, [X5, X7,LSL #3]

  (2215) 0x4c4d64 LD1D	{Z1.D}, P0/Z, [X19, X7,LSL #3]

  (2215) 0x4c4d68 LD1D	{Z26.D}, P0/Z, [X8, Z27.D,LSL #3]

  (2215) 0x4c4d6c ADD	X7, X7, X4

  (2215) 0x4c4d70 FMUL	Z1.D, P0/M, Z1.D, Z26.D

  (2215) 0x4c4d74 FNEG	Z1.D, P6/M, Z1.D

  (2215) 0x4c4d78 FADDA	D0, P0, D0, Z1.D

  (2215) 0x4c4d7c WHILELO	P0.D, X7, X2

  (2215) 0x4c4d80 B.NE	4c4d60

(2214) 0x4c4d84 LDR	D29, [X15, X1,LSL #3]

(2214) 0x4c4d88 FMUL	D6, D30, D0

(2214) 0x4c4d8c LDR	D28, [X12, X1,LSL #3]

(2214) 0x4c4d90 FDIV	D7, D6, D29

(2214) 0x4c4d94 FADD	D16, D28, D7

(2214) 0x4c4d98 STR	D16, [X12, X1,LSL #3]

(2214) 0x4c4d9c ADD	X1, X1, #1

(2214) 0x4c4da0 CMP	X30, X1

(2214) 0x4c4da4 B.NE	4c4cd4

0x4c4da8 LDR	X21, [SP, #32]

0x4c4dac LDP	X19, X20, [SP, #16]

0x4c4db0 LDP	X29, X30, [SP], #48

0x4c4db4 RET

0x4c4db8 ADD	X7, X7, #1

0x4c4dbc MOVZ	X0, #0

0x4c4dc0 B	4c4c84

Coverage (%)	Name	Source Location	Module
►98.49+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.44+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_ParCSRRelaxThreads	ams.c:3662	exec
○	hypre_BoomerAMGCycle	par_cycle.c:394	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:235	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	ams.c:3662-3682
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662,3669-3682.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 42% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 5.17 cycles (3.87x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	38
nb uops	38
loop length	152
used w registers	0
used x registers	21
used b registers	0
used h registers	0
used s registers	1
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.75 cycles
front end	4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	4.75	4.75	5.00	4.50	0.00	0.00	0.00	0.00	5.17	4.83	5.00	1.50	1.50
cycles	3.50	3.50	4.75	4.75	5.00	4.50	0.00	0.00	0.00	0.00	5.17	4.83	5.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	4.75
Dispatch	5.17
DIV/SQRT	5.00-20.00
Overall L1	5.17-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	42%
load	38%
store	41%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	62%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4c4c4c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [X0, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4100b0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X20, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
BL 410200 <@plt_start@+0x1e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
SDIV X7, X21, X20	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X0, X7, X20, X21	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4c4db8 <hypre_ParCSRRelaxThreads._omp_fn.1+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X1, X7, X1, X0	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X30, X7, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X1, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4c4da8 <hypre_ParCSRRelaxThreads._omp_fn.1+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X11, [X19, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CNTD X4, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (100.0%)
LDP X21, X13, [X19, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ADD X17, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X20, X18, [X19, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ADD X16, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X12, X14, [X19, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X8, [X19, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X15, [X19]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D30, [X19, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D31, [X19, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
B 4c4cd4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4c4c84 <hypre_ParCSRRelaxThreads._omp_fn.1+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	ams.c:3662-3682
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662,3669-3682.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 42% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 5.17 cycles (3.87x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	38
nb uops	38
loop length	152
used w registers	0
used x registers	21
used b registers	0
used h registers	0
used s registers	1
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.75 cycles
front end	4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	4.75	4.75	5.00	4.50	0.00	0.00	0.00	0.00	5.17	4.83	5.00	1.50	1.50
cycles	3.50	3.50	4.75	4.75	5.00	4.50	0.00	0.00	0.00	0.00	5.17	4.83	5.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	4.75
Dispatch	5.17
DIV/SQRT	5.00-20.00
Overall L1	5.17-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	42%
load	38%
store	41%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	62%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4c4c4c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [X0, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4100b0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X20, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
BL 410200 <@plt_start@+0x1e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
SDIV X7, X21, X20	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X0, X7, X20, X21	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4c4db8 <hypre_ParCSRRelaxThreads._omp_fn.1+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X1, X7, X1, X0	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X30, X7, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X1, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4c4da8 <hypre_ParCSRRelaxThreads._omp_fn.1+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X11, [X19, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CNTD X4, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (100.0%)
LDP X21, X13, [X19, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ADD X17, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X20, X18, [X19, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ADD X16, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X12, X14, [X19, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X9, X8, [X19, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X15, [X19]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D30, [X19, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D31, [X19, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
B 4c4cd4 <hypre_ParCSRRelaxThreads._omp_fn.1+0x88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 4c4c84 <hypre_ParCSRRelaxThreads._omp_fn.1+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_ParCSRRelaxThreads._omp_fn.1–	35.85	14.97
▼Loop 2214 - ams.c:3662-3682 - exec–	1.31	0.41
○Loop 2216 - ams.c:3672-3675 - exec	34.54	10.74
○Loop 2215 - ams.c:3677-3680 - exec	0.00	0.00

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Matching between your function (in the source code) and the binary function

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ASM code

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code