OV - exec - Function hypre_IJMatrixAssembleParCSR._omp

	Function: hypre_IJMatrixAssembleParCSR._omp_fn.1	Module: exec	Source: IJMatrix_parcsr.c:2798-2812	Coverage (incl. loops): 0.47% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 2798 - 2812

--------------------------------------------------------------------------------

2798: #pragma omp parallel for private (i,j,j0,temp)

2799: #endif

2800:          for (i=0; i < num_rows; i++)

2801:          {

2802:    	    j0 = diag_i[i];

2803:    	    for (j=j0; j < diag_i[i+1]; j++)

2804:    	    {

2805:    	       diag_j[j] -= col_0;

2806:    	       if (diag_j[j] == i)

2807:    	       {

2808:    	          temp = diag_data[j0];

2809:    	          diag_data[j0] = diag_data[j];

2810:    	          diag_data[j] = temp;

2811:    	          diag_j[j] = diag_j[j0];

2812:    	          diag_j[j0] = i;

0x4ff820 STP	X29, X30, [SP, #976]!

0x4ff824 ADD	X29, SP, #0

0x4ff828 STP	X19, X20, [SP, #16]

0x4ff82c ORR	X20, XZR, X0

0x4ff830 STR	X21, [SP, #32]

0x4ff834 LDR	X21, [X0, #24]

0x4ff838 BL	4100b0

0x4ff83c SBFM	X19, X0, #0, #31

0x4ff840 BL	410200

0x4ff844 SBFM	X2, X0, #0, #31

0x4ff848 SDIV	X9, X21, X19

0x4ff84c MSUB	X1, X9, X19, X21

0x4ff850 CMP	X2, X1

0x4ff854 B.LT	4ff91c

0x4ff858 MADD	X18, X9, X2, X1

0x4ff85c ADD	X11, X9, X18

0x4ff860 CMP	X18, X11

0x4ff864 B.GE	4ff8d0

0x4ff868 LDP	X10, X3, [X20]

0x4ff86c LDR	X6, [X20, #16]

0x4ff870 ADD	X4, X10, #8

0x4ff874 LDR	X5, [X20, #32]

0x4ff878 HINT	#0

0x4ff87c HINT	#0

(2925) 0x4ff880 LDR	X0, [X10, X18,LSL #3]

(2925) 0x4ff884 LDR	X12, [X4, X18,LSL #3]

(2925) 0x4ff888 ADD	X8, X6, X0,LSL #3

(2925) 0x4ff88c ADD	X7, X3, X0,LSL #3

(2925) 0x4ff890 CMP	X0, X12

(2925) 0x4ff894 B.GE	4ff8c4

(2925) 0x4ff898 HINT	#0

(2925) 0x4ff89c HINT	#0

  (2926) 0x4ff8a0 LDR	X13, [X3, X0,LSL #3]

  (2926) 0x4ff8a4 SUB	X14, X13, X5

  (2926) 0x4ff8a8 STR	X14, [X3, X0,LSL #3]

  (2926) 0x4ff8ac CMP	X18, X14

  (2926) 0x4ff8b0 B.EQ	4ff8e0

  (2926) 0x4ff8b4 LDR	X15, [X4, X18,LSL #3]

  (2926) 0x4ff8b8 ADD	X0, X0, #1

  (2926) 0x4ff8bc CMP	X15, X0

  (2926) 0x4ff8c0 B.GT	4ff8a0

(2925) 0x4ff8c4 ADD	X18, X18, #1

(2925) 0x4ff8c8 CMP	X11, X18

(2925) 0x4ff8cc B.NE	4ff880

0x4ff8d0 LDR	X21, [SP, #32]

0x4ff8d4 LDP	X19, X20, [SP, #16]

0x4ff8d8 LDP	X29, X30, [SP], #48

0x4ff8dc RET

  (2926) 0x4ff8e0 LDR	D30, [X6, X0,LSL #3]

  (2926) 0x4ff8e4 LDR	D31, [X8]

  (2926) 0x4ff8e8 LDR	X16, [X7]

  (2926) 0x4ff8ec STR	D30, [X8]

  (2926) 0x4ff8f0 STR	D31, [X6, X0,LSL #3]

  (2926) 0x4ff8f4 STR	X16, [X3, X0,LSL #3]

  (2926) 0x4ff8f8 ADD	X0, X0, #1

  (2926) 0x4ff8fc STR	X18, [X7]

  (2926) 0x4ff900 LDR	X17, [X4, X18,LSL #3]

  (2926) 0x4ff904 CMP	X17, X0

  (2926) 0x4ff908 B.GT	4ff8a0

(2925) 0x4ff90c ADD	X18, X18, #1

(2925) 0x4ff910 CMP	X11, X18

(2925) 0x4ff914 B.NE	4ff880

0x4ff918 B	4ff8d0

0x4ff91c ADD	X9, X9, #1

0x4ff920 MOVZ	X1, #0

0x4ff924 B	4ff858

Coverage (%)	Name	Source Location	Module
►98.49+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.51+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_IJMatrixAssembleParCSR	IJMatrix_parcsr.c:2798	exec
○	BuildIJLaplacian27pt	amg.c:2272	exec
○	main	amg.c:274	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	IJMatrix_parcsr.c:2798-2812
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:2798-2812.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 38% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 3.75 cycles (5.33x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:2798
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:2798

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	32
nb uops	30
loop length	128
used w registers	0
used x registers	17
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.75 cycles
front end	3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	3.50	3.17	3.33	1.50	1.50
cycles	3.50	3.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	3.50	3.17	3.33	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	3.75
Dispatch	4.00
DIV/SQRT	5.00-20.00
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	38%
load	33%
store	41%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	55%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4ff820

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4100b0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
BL 410200 <@plt_start@+0x1e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X2, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
SDIV X9, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X1, X9, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4ff91c <hypre_IJMatrixAssembleParCSR._omp_fn.1+0xfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X18, X9, X2, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X11, X9, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X18, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4ff8d0 <hypre_IJMatrixAssembleParCSR._omp_fn.1+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X3, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X6, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X4, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X5, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4ff8d0 <hypre_IJMatrixAssembleParCSR._omp_fn.1+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4ff858 <hypre_IJMatrixAssembleParCSR._omp_fn.1+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	IJMatrix_parcsr.c:2798-2812
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:2798-2812.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 38% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 3.75 cycles (5.33x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:2798
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:2798

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	32
nb uops	30
loop length	128
used w registers	0
used x registers	17
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.75 cycles
front end	3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	3.50	3.17	3.33	1.50	1.50
cycles	3.50	3.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	3.50	3.17	3.33	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	3.75
Dispatch	4.00
DIV/SQRT	5.00-20.00
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	38%
load	33%
store	41%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	55%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4ff820

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4100b0 <@plt_start@+0x90>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
BL 410200 <@plt_start@+0x1e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X2, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
SDIV X9, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X1, X9, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4ff91c <hypre_IJMatrixAssembleParCSR._omp_fn.1+0xfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X18, X9, X2, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X11, X9, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X18, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4ff8d0 <hypre_IJMatrixAssembleParCSR._omp_fn.1+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X3, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X6, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X4, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X5, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4ff8d0 <hypre_IJMatrixAssembleParCSR._omp_fn.1+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 4ff858 <hypre_IJMatrixAssembleParCSR._omp_fn.1+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_IJMatrixAssembleParCSR._omp_fn.1–	0.47	0.19
▼Loop 2925 - IJMatrix_parcsr.c:2802-2812 - exec–	0.00	0.00
○Loop 2926 - IJMatrix_parcsr.c:2803-2812 - exec	0.47	0.14

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ASM code

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code